1/* 2 * Copyright (C) 2015 Cavium Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28#ifndef NICVF_QUEUES_H 29#define NICVF_QUEUES_H 30 31#include "q_struct.h" 32 33#define MAX_QUEUE_SET 128 34#define MAX_RCV_QUEUES_PER_QS 8 35#define MAX_RCV_BUF_DESC_RINGS_PER_QS 2 36#define MAX_SND_QUEUES_PER_QS 8 37#define MAX_CMP_QUEUES_PER_QS 8 38 39/* VF's queue interrupt ranges */ 40#define NICVF_INTR_ID_CQ 0 41#define NICVF_INTR_ID_SQ 8 42#define NICVF_INTR_ID_RBDR 16 43#define NICVF_INTR_ID_MISC 18 44#define NICVF_INTR_ID_QS_ERR 19 45 46#define for_each_cq_irq(irq) \ 47 for ((irq) = NICVF_INTR_ID_CQ; (irq) < NICVF_INTR_ID_SQ; (irq)++) 48#define for_each_sq_irq(irq) \ 49 for ((irq) = NICVF_INTR_ID_SQ; (irq) < NICVF_INTR_ID_RBDR; (irq)++) 50#define for_each_rbdr_irq(irq) \ 51 for ((irq) = NICVF_INTR_ID_RBDR; (irq) < NICVF_INTR_ID_MISC; (irq)++) 52 53#define RBDR_SIZE0 0UL /* 8K entries */ 54#define RBDR_SIZE1 1UL /* 16K entries */ 55#define RBDR_SIZE2 2UL /* 32K entries */ 56#define RBDR_SIZE3 3UL /* 64K entries */ 57#define RBDR_SIZE4 4UL /* 126K entries */ 58#define RBDR_SIZE5 5UL /* 256K entries */ 59#define RBDR_SIZE6 6UL /* 512K entries */ 60 61#define SND_QUEUE_SIZE0 0UL /* 1K entries */ 62#define SND_QUEUE_SIZE1 1UL /* 2K entries */ 63#define SND_QUEUE_SIZE2 2UL /* 4K entries */ 64#define SND_QUEUE_SIZE3 3UL /* 8K entries */ 65#define SND_QUEUE_SIZE4 4UL /* 16K entries */ 66#define SND_QUEUE_SIZE5 5UL /* 32K entries */ 67#define SND_QUEUE_SIZE6 6UL /* 64K entries */ 68 69#define CMP_QUEUE_SIZE0 0UL /* 1K entries */ 70#define CMP_QUEUE_SIZE1 1UL /* 2K entries */ 71#define CMP_QUEUE_SIZE2 2UL /* 4K entries */ 72#define CMP_QUEUE_SIZE3 3UL /* 8K entries */ 73#define CMP_QUEUE_SIZE4 4UL /* 16K entries */ 74#define CMP_QUEUE_SIZE5 5UL /* 32K entries */ 75#define CMP_QUEUE_SIZE6 6UL /* 64K entries */ 76 77/* Default queue count per QS, its lengths and threshold values */ 78#define RBDR_CNT 1 79#define RCV_QUEUE_CNT 8 80#define SND_QUEUE_CNT 8 81#define CMP_QUEUE_CNT 8 /* Max of RCV and SND qcount */ 82 83#define SND_QSIZE SND_QUEUE_SIZE2 84#define SND_QUEUE_LEN (1UL << (SND_QSIZE + 10)) 85#define MAX_SND_QUEUE_LEN (1UL << (SND_QUEUE_SIZE6 + 10)) 86#define SND_QUEUE_THRESH 2UL 87#define MIN_SQ_DESC_PER_PKT_XMIT 2 88/* Since timestamp not enabled, otherwise 2 */ 89#define MAX_CQE_PER_PKT_XMIT 1 90 91/* 92 * Keep CQ and SQ sizes same, if timestamping 93 * is enabled this equation will change. 94 */ 95#define CMP_QSIZE CMP_QUEUE_SIZE2 96#define CMP_QUEUE_LEN (1UL << (CMP_QSIZE + 10)) 97#define CMP_QUEUE_CQE_THRESH 32 98#define CMP_QUEUE_TIMER_THRESH 220 /* 10usec */ 99 100#define RBDR_SIZE RBDR_SIZE0 101#define RCV_BUF_COUNT (1UL << (RBDR_SIZE + 13)) 102#define MAX_RCV_BUF_COUNT (1UL << (RBDR_SIZE6 + 13)) 103#define RBDR_THRESH (RCV_BUF_COUNT / 2) 104#define DMA_BUFFER_LEN 2048 /* In multiples of 128bytes */ 105 106#define MAX_CQES_FOR_TX \ 107 ((SND_QUEUE_LEN / MIN_SQ_DESC_PER_PKT_XMIT) * MAX_CQE_PER_PKT_XMIT) 108/* Calculate number of CQEs to reserve for all SQEs. 109 * Its 1/256th level of CQ size. 110 * '+ 1' to account for pipelining 111 */ 112#define RQ_CQ_DROP \ 113 ((256 / (CMP_QUEUE_LEN / (CMP_QUEUE_LEN - MAX_CQES_FOR_TX))) + 1) 114 115/* Descriptor size in bytes */ 116#define SND_QUEUE_DESC_SIZE 16 117#define CMP_QUEUE_DESC_SIZE 512 118 119/* Buffer / descriptor alignments */ 120#define NICVF_RCV_BUF_ALIGN 7 121#define NICVF_RCV_BUF_ALIGN_BYTES (1UL << NICVF_RCV_BUF_ALIGN) 122#define NICVF_CQ_BASE_ALIGN_BYTES 512 /* 9 bits */ 123#define NICVF_SQ_BASE_ALIGN_BYTES 128 /* 7 bits */ 124 125#define NICVF_ALIGNED_ADDR(addr, align_bytes) \ 126 roundup2((addr), (align_bytes)) 127#define NICVF_ADDR_ALIGN_LEN(addr, bytes) \ 128 (NICVF_ALIGNED_ADDR((addr), (bytes)) - (bytes)) 129#define NICVF_RCV_BUF_ALIGN_LEN(addr) \ 130 (NICVF_ALIGNED_ADDR((addr), NICVF_RCV_BUF_ALIGN_BYTES) - (addr)) 131 132#define NICVF_TXBUF_MAXSIZE NIC_HW_MAX_FRS /* Total max payload without TSO */ 133#define NICVF_TXBUF_NSEGS 256 /* Single command is at most 256 buffers 134 (hdr + 255 subcmds) */ 135/* TSO-related definitions */ 136#define NICVF_TSO_MAXSIZE IP_MAXPACKET 137#define NICVF_TSO_NSEGS NICVF_TXBUF_NSEGS 138#define NICVF_TSO_HEADER_SIZE 128 139 140/* Queue enable/disable */ 141#define NICVF_SQ_EN (1UL << 19) 142 143/* Queue reset */ 144#define NICVF_CQ_RESET (1UL << 41) 145#define NICVF_SQ_RESET (1UL << 17) 146#define NICVF_RBDR_RESET (1UL << 43) 147 148enum CQ_RX_ERRLVL_E { 149 CQ_ERRLVL_MAC, 150 CQ_ERRLVL_L2, 151 CQ_ERRLVL_L3, 152 CQ_ERRLVL_L4, 153}; 154 155enum CQ_RX_ERROP_E { 156 CQ_RX_ERROP_RE_NONE = 0x0, 157 CQ_RX_ERROP_RE_PARTIAL = 0x1, 158 CQ_RX_ERROP_RE_JABBER = 0x2, 159 CQ_RX_ERROP_RE_FCS = 0x7, 160 CQ_RX_ERROP_RE_TERMINATE = 0x9, 161 CQ_RX_ERROP_RE_RX_CTL = 0xb, 162 CQ_RX_ERROP_PREL2_ERR = 0x1f, 163 CQ_RX_ERROP_L2_FRAGMENT = 0x20, 164 CQ_RX_ERROP_L2_OVERRUN = 0x21, 165 CQ_RX_ERROP_L2_PFCS = 0x22, 166 CQ_RX_ERROP_L2_PUNY = 0x23, 167 CQ_RX_ERROP_L2_MAL = 0x24, 168 CQ_RX_ERROP_L2_OVERSIZE = 0x25, 169 CQ_RX_ERROP_L2_UNDERSIZE = 0x26, 170 CQ_RX_ERROP_L2_LENMISM = 0x27, 171 CQ_RX_ERROP_L2_PCLP = 0x28, 172 CQ_RX_ERROP_IP_NOT = 0x41, 173 CQ_RX_ERROP_IP_CSUM_ERR = 0x42, 174 CQ_RX_ERROP_IP_MAL = 0x43, 175 CQ_RX_ERROP_IP_MALD = 0x44, 176 CQ_RX_ERROP_IP_HOP = 0x45, 177 CQ_RX_ERROP_L3_ICRC = 0x46, 178 CQ_RX_ERROP_L3_PCLP = 0x47, 179 CQ_RX_ERROP_L4_MAL = 0x61, 180 CQ_RX_ERROP_L4_CHK = 0x62, 181 CQ_RX_ERROP_UDP_LEN = 0x63, 182 CQ_RX_ERROP_L4_PORT = 0x64, 183 CQ_RX_ERROP_TCP_FLAG = 0x65, 184 CQ_RX_ERROP_TCP_OFFSET = 0x66, 185 CQ_RX_ERROP_L4_PCLP = 0x67, 186 CQ_RX_ERROP_RBDR_TRUNC = 0x70, 187}; 188 189enum CQ_TX_ERROP_E { 190 CQ_TX_ERROP_GOOD = 0x0, 191 CQ_TX_ERROP_DESC_FAULT = 0x10, 192 CQ_TX_ERROP_HDR_CONS_ERR = 0x11, 193 CQ_TX_ERROP_SUBDC_ERR = 0x12, 194 CQ_TX_ERROP_IMM_SIZE_OFLOW = 0x80, 195 CQ_TX_ERROP_DATA_SEQUENCE_ERR = 0x81, 196 CQ_TX_ERROP_MEM_SEQUENCE_ERR = 0x82, 197 CQ_TX_ERROP_LOCK_VIOL = 0x83, 198 CQ_TX_ERROP_DATA_FAULT = 0x84, 199 CQ_TX_ERROP_TSTMP_CONFLICT = 0x85, 200 CQ_TX_ERROP_TSTMP_TIMEOUT = 0x86, 201 CQ_TX_ERROP_MEM_FAULT = 0x87, 202 CQ_TX_ERROP_CK_OVERLAP = 0x88, 203 CQ_TX_ERROP_CK_OFLOW = 0x89, 204 CQ_TX_ERROP_ENUM_LAST = 0x8a, 205}; 206 207struct cmp_queue_stats { 208 struct tx_stats { 209 uint64_t good; 210 uint64_t desc_fault; 211 uint64_t hdr_cons_err; 212 uint64_t subdesc_err; 213 uint64_t imm_size_oflow; 214 uint64_t data_seq_err; 215 uint64_t mem_seq_err; 216 uint64_t lock_viol; 217 uint64_t data_fault; 218 uint64_t tstmp_conflict; 219 uint64_t tstmp_timeout; 220 uint64_t mem_fault; 221 uint64_t csum_overlap; 222 uint64_t csum_overflow; 223 } tx; 224} __aligned(CACHE_LINE_SIZE); 225 226enum RQ_SQ_STATS { 227 RQ_SQ_STATS_OCTS, 228 RQ_SQ_STATS_PKTS, 229}; 230 231struct rx_tx_queue_stats { 232 uint64_t bytes; 233 uint64_t pkts; 234} __aligned(CACHE_LINE_SIZE); 235 236struct q_desc_mem { 237 bus_dma_tag_t dmat; 238 bus_dmamap_t dmap; 239 void *base; 240 bus_addr_t phys_base; 241 uint64_t size; 242 uint16_t q_len; 243}; 244 245struct rbdr { 246 boolean_t enable; 247 uint32_t dma_size; 248 uint32_t frag_len; 249 uint32_t thresh; /* Threshold level for interrupt */ 250 void *desc; 251 uint32_t head; 252 uint32_t tail; 253 struct q_desc_mem dmem; 254 255 struct nicvf *nic; 256 int idx; 257 258 struct task rbdr_task; 259 struct task rbdr_task_nowait; 260 struct taskqueue *rbdr_taskq; 261 262 bus_dma_tag_t rbdr_buff_dmat; 263 bus_dmamap_t *rbdr_buff_dmaps; 264} __aligned(CACHE_LINE_SIZE); 265 266struct rcv_queue { 267 boolean_t enable; 268 struct rbdr *rbdr_start; 269 struct rbdr *rbdr_cont; 270 boolean_t en_tcp_reassembly; 271 uint8_t cq_qs; /* CQ's QS to which this RQ is assigned */ 272 uint8_t cq_idx; /* CQ index (0 to 7) in the QS */ 273 uint8_t cont_rbdr_qs; /* Continue buffer ptrs - QS num */ 274 uint8_t cont_qs_rbdr_idx; /* RBDR idx in the cont QS */ 275 uint8_t start_rbdr_qs; /* First buffer ptrs - QS num */ 276 uint8_t start_qs_rbdr_idx; /* RBDR idx in the above QS */ 277 uint8_t caching; 278 struct rx_tx_queue_stats stats; 279 280 boolean_t lro_enabled; 281 struct lro_ctrl lro; 282} __aligned(CACHE_LINE_SIZE); 283 284struct cmp_queue { 285 boolean_t enable; 286 uint16_t thresh; 287 288 struct nicvf *nic; 289 int idx; /* This queue index */ 290 291 struct buf_ring *rx_br; /* Reception buf ring */ 292 struct mtx mtx; /* lock to serialize processing CQEs */ 293 char mtx_name[32]; 294 295 struct task cmp_task; 296 struct taskqueue *cmp_taskq; 297 u_int cmp_cpuid; /* CPU to which bind the CQ task */ 298 299 void *desc; 300 struct q_desc_mem dmem; 301 struct cmp_queue_stats stats; 302 int irq; 303} __aligned(CACHE_LINE_SIZE); 304 305struct snd_buff { 306 bus_dmamap_t dmap; 307 struct mbuf *mbuf; 308}; 309 310struct snd_queue { 311 boolean_t enable; 312 uint8_t cq_qs; /* CQ's QS to which this SQ is pointing */ 313 uint8_t cq_idx; /* CQ index (0 to 7) in the above QS */ 314 uint16_t thresh; 315 volatile int free_cnt; 316 uint32_t head; 317 uint32_t tail; 318 uint64_t *skbuff; 319 void *desc; 320 321 struct nicvf *nic; 322 int idx; /* This queue index */ 323 324 bus_dma_tag_t snd_buff_dmat; 325 struct snd_buff *snd_buff; 326 327 struct buf_ring *br; /* Transmission buf ring */ 328 struct mtx mtx; 329 char mtx_name[32]; 330 331 struct task snd_task; 332 struct taskqueue *snd_taskq; 333 334 struct q_desc_mem dmem; 335 struct rx_tx_queue_stats stats; 336} __aligned(CACHE_LINE_SIZE); 337 338struct queue_set { 339 boolean_t enable; 340 boolean_t be_en; 341 uint8_t vnic_id; 342 uint8_t rq_cnt; 343 uint8_t cq_cnt; 344 uint64_t cq_len; 345 uint8_t sq_cnt; 346 uint64_t sq_len; 347 uint8_t rbdr_cnt; 348 uint64_t rbdr_len; 349 struct rcv_queue rq[MAX_RCV_QUEUES_PER_QS]; 350 struct cmp_queue cq[MAX_CMP_QUEUES_PER_QS]; 351 struct snd_queue sq[MAX_SND_QUEUES_PER_QS]; 352 struct rbdr rbdr[MAX_RCV_BUF_DESC_RINGS_PER_QS]; 353 354 struct task qs_err_task; 355 struct taskqueue *qs_err_taskq; 356} __aligned(CACHE_LINE_SIZE); 357 358#define GET_RBDR_DESC(RING, idx) \ 359 (&(((struct rbdr_entry_t *)((RING)->desc))[(idx)])) 360#define GET_SQ_DESC(RING, idx) \ 361 (&(((struct sq_hdr_subdesc *)((RING)->desc))[(idx)])) 362#define GET_CQ_DESC(RING, idx) \ 363 (&(((union cq_desc_t *)((RING)->desc))[(idx)])) 364 365/* CQ status bits */ 366#define CQ_WR_FUL (1UL << 26) 367#define CQ_WR_DISABLE (1UL << 25) 368#define CQ_WR_FAULT (1UL << 24) 369#define CQ_CQE_COUNT (0xFFFF << 0) 370 371#define CQ_ERR_MASK (CQ_WR_FUL | CQ_WR_DISABLE | CQ_WR_FAULT) 372 373#define NICVF_TX_LOCK(sq) mtx_lock(&(sq)->mtx) 374#define NICVF_TX_TRYLOCK(sq) mtx_trylock(&(sq)->mtx) 375#define NICVF_TX_UNLOCK(sq) mtx_unlock(&(sq)->mtx) 376#define NICVF_TX_LOCK_ASSERT(sq) mtx_assert(&(sq)->mtx, MA_OWNED) 377 378#define NICVF_CMP_LOCK(cq) mtx_lock(&(cq)->mtx) 379#define NICVF_CMP_UNLOCK(cq) mtx_unlock(&(cq)->mtx) 380 381int nicvf_set_qset_resources(struct nicvf *); 382int nicvf_config_data_transfer(struct nicvf *, boolean_t); 383void nicvf_qset_config(struct nicvf *, boolean_t); 384 385void nicvf_enable_intr(struct nicvf *, int, int); 386void nicvf_disable_intr(struct nicvf *, int, int); 387void nicvf_clear_intr(struct nicvf *, int, int); 388int nicvf_is_intr_enabled(struct nicvf *, int, int); 389 390int nicvf_xmit_locked(struct snd_queue *sq); 391 392/* Register access APIs */ 393void nicvf_reg_write(struct nicvf *, uint64_t, uint64_t); 394uint64_t nicvf_reg_read(struct nicvf *, uint64_t); 395void nicvf_qset_reg_write(struct nicvf *, uint64_t, uint64_t); 396uint64_t nicvf_qset_reg_read(struct nicvf *, uint64_t); 397void nicvf_queue_reg_write(struct nicvf *, uint64_t, uint64_t, uint64_t); 398uint64_t nicvf_queue_reg_read(struct nicvf *, uint64_t, uint64_t); 399 400/* Stats */ 401void nicvf_update_rq_stats(struct nicvf *, int); 402void nicvf_update_sq_stats(struct nicvf *, int); 403int nicvf_check_cqe_rx_errs(struct nicvf *, struct cmp_queue *, 404 struct cqe_rx_t *); 405int nicvf_check_cqe_tx_errs(struct nicvf *,struct cmp_queue *, 406 struct cqe_send_t *); 407#endif /* NICVF_QUEUES_H */ 408