1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2013-2014 Kevin Lo
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#define	AXGE_ACCESS_MAC			0x01
30#define	AXGE_ACCESS_PHY			0x02
31#define	AXGE_ACCESS_WAKEUP		0x03
32#define	AXGE_ACCESS_EEPROM		0x04
33#define	AXGE_ACCESS_EFUSE		0x05
34#define	AXGE_RELOAD_EEPROM_EFUSE	0x06
35#define	AXGE_FW_MODE			0x08
36#define	AXGE_WRITE_EFUSE_EN		0x09
37#define	AXGE_WRITE_EFUSE_DIS		0x0A
38#define	AXGE_ACCESS_MFAB		0x10
39
40#define	AXGE_FW_MODE_178A179		0x0000
41#define	AXGE_FW_MODE_179A		0x0001
42
43/* Physical link status register */
44#define	AXGE_PLSR			0x02
45#define	PLSR_USB_FS			0x01
46#define	PLSR_USB_HS			0x02
47#define	PLSR_USB_SS			0x04
48
49/* EEPROM address register */
50#define	AXGE_EAR			0x07
51
52/* EEPROM data low register */
53#define	AXGE_EDLR			0x08
54
55/* EEPROM data high register */
56#define	AXGE_EDHR			0x09
57
58/* EEPROM command register */
59#define	AXGE_ECR			0x0a
60
61/* Rx control register */
62#define	AXGE_RCR			0x0b
63#define	RCR_STOP			0x0000
64#define	RCR_PROMISC			0x0001
65#define	RCR_ACPT_ALL_MCAST		0x0002
66#define	RCR_AUTOPAD_BNDRY		0x0004
67#define	RCR_ACPT_BCAST			0x0008
68#define	RCR_ACPT_MCAST			0x0010
69#define	RCR_ACPT_PHY_MCAST		0x0020
70#define	RCR_START			0x0080
71#define	RCR_DROP_CRCERR			0x0100
72#define	RCR_IPE				0x0200
73#define	RCR_TX_CRC_PAD			0x0400
74
75/* Node id register */
76#define	AXGE_NIDR			0x10
77
78/* Multicast filter array */
79#define	AXGE_MFA			0x16
80
81/* Medium status register */
82#define	AXGE_MSR			0x22
83#define	MSR_GM				0x0001
84#define	MSR_FD				0x0002
85#define	MSR_EN_125MHZ			0x0008
86#define	MSR_RFC				0x0010
87#define	MSR_TFC				0x0020
88#define	MSR_RE				0x0100
89#define	MSR_PS				0x0200
90
91/* Monitor mode status register */
92#define	AXGE_MMSR			0x24
93#define	MMSR_RWLC			0x02
94#define	MMSR_RWMP			0x04
95#define	MMSR_RWWF			0x08
96#define	MMSR_RW_FLAG			0x10
97#define	MMSR_PME_POL			0x20
98#define	MMSR_PME_TYPE			0x40
99#define	MMSR_PME_IND			0x80
100
101/* GPIO control/status register */
102#define	AXGE_GPIOCR			0x25
103
104/* Ethernet PHY power & reset control register */
105#define	AXGE_EPPRCR			0x26
106#define	EPPRCR_BZ			0x0010
107#define	EPPRCR_IPRL			0x0020
108#define	EPPRCR_AUTODETACH		0x1000
109
110#define	AXGE_RX_BULKIN_QCTRL		0x2e
111
112#define	AXGE_CLK_SELECT			0x33
113#define	AXGE_CLK_SELECT_BCS		0x01
114#define	AXGE_CLK_SELECT_ACS		0x02
115#define	AXGE_CLK_SELECT_ACSREQ		0x10
116#define	AXGE_CLK_SELECT_ULR		0x08
117
118/* COE Rx control register */
119#define	AXGE_CRCR			0x34
120#define	CRCR_IP				0x01
121#define	CRCR_TCP			0x02
122#define	CRCR_UDP			0x04
123#define	CRCR_ICMP			0x08
124#define	CRCR_IGMP			0x10
125#define	CRCR_TCPV6			0x20
126#define	CRCR_UDPV6			0x40
127#define	CRCR_ICMPV6			0x80
128
129/* COE Tx control register */
130#define	AXGE_CTCR			0x35
131#define	CTCR_IP				0x01
132#define	CTCR_TCP			0x02
133#define	CTCR_UDP			0x04
134#define	CTCR_ICMP			0x08
135#define	CTCR_IGMP			0x10
136#define	CTCR_TCPV6			0x20
137#define	CTCR_UDPV6			0x40
138#define	CTCR_ICMPV6			0x80
139
140/* Pause water level high register */
141#define	AXGE_PWLHR			0x54
142
143/* Pause water level low register */
144#define	AXGE_PWLLR			0x55
145
146#define	AXGE_CONFIG_IDX			0	/* config number 1 */
147#define	AXGE_IFACE_IDX			0
148
149#define	GET_MII(sc)		uether_getmii(&(sc)->sc_ue)
150
151/* The interrupt endpoint is currently unused by the ASIX part. */
152enum {
153	AXGE_BULK_DT_WR,
154	AXGE_BULK_DT_RD,
155	AXGE_N_TRANSFER,
156};
157
158#define	AXGE_N_FRAMES	16
159
160struct axge_frame_txhdr {
161	uint32_t		len;
162#define	AXGE_TXLEN_MASK		0x0001FFFF
163#define	AXGE_VLAN_INSERT	0x20000000
164#define	AXGE_CSUM_DISABLE	0x80000000
165	uint32_t		mss;
166#define	AXGE_MSS_MASK		0x00003FFF
167#define	AXGE_PADDING		0x80008000
168#define	AXGE_VLAN_TAG_MASK	0xFFFF0000
169} __packed;
170
171#define	AXGE_TXBYTES(x)		((x) & AXGE_TXLEN_MASK)
172
173#define	AXGE_PHY_ADDR		3
174
175struct axge_frame_rxhdr {
176	uint32_t		status;
177#define	AXGE_RX_L4_CSUM_ERR	0x00000001
178#define	AXGE_RX_L3_CSUM_ERR	0x00000002
179#define	AXGE_RX_L4_TYPE_UDP	0x00000004
180#define	AXGE_RX_L4_TYPE_ICMP	0x00000008
181#define	AXGE_RX_L4_TYPE_IGMP	0x0000000C
182#define	AXGE_RX_L4_TYPE_TCP	0x00000010
183#define	AXGE_RX_L4_TYPE_MASK	0x0000001C
184#define	AXGE_RX_L3_TYPE_IPV4	0x00000020
185#define	AXGE_RX_L3_TYPE_IPV6	0x00000040
186#define	AXGE_RX_L3_TYPE_MASK	0x00000060
187#define	AXGE_RX_VLAN_IND_MASK	0x00000700
188#define	AXGE_RX_GOOD_PKT	0x00000800
189#define	AXGE_RX_VLAN_PRI_MASK	0x00007000
190#define	AXGE_RX_MBCAST		0x00008000
191#define	AXGE_RX_LEN_MASK	0x1FFF0000
192#define	AXGE_RX_CRC_ERR		0x20000000
193#define	AXGE_RX_MII_ERR		0x40000000
194#define	AXGE_RX_DROP_PKT	0x80000000
195#define	AXGE_RX_LEN_SHIFT	16
196} __packed;
197
198#define	AXGE_RXBYTES(x)		(((x) & AXGE_RX_LEN_MASK) >> AXGE_RX_LEN_SHIFT)
199#define	AXGE_RX_ERR(x)		\
200	    ((x) & (AXGE_RX_CRC_ERR | AXGE_RX_MII_ERR | AXGE_RX_DROP_PKT))
201
202struct axge_softc {
203	struct usb_ether	sc_ue;
204	struct mtx		sc_mtx;
205	struct usb_xfer		*sc_xfer[AXGE_N_TRANSFER];
206
207	int			sc_flags;
208#define	AXGE_FLAG_LINK		0x0001	/* got a link */
209#define	AXGE_FLAG_178A		0x1000	/* AX88178A */
210#define	AXGE_FLAG_179		0x2000	/* AX88179 */
211#define	AXGE_FLAG_179A		0x4000	/* AX88179A */
212};
213
214#define	AXGE_LOCK(_sc)			mtx_lock(&(_sc)->sc_mtx)
215#define	AXGE_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_mtx)
216#define	AXGE_LOCK_ASSERT(_sc, t)	mtx_assert(&(_sc)->sc_mtx, t)
217