1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 5 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved. 6 * Copyright (c) 2004 Lennart Augustsson. All rights reserved. 7 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31/* 32 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 33 * 34 * The EHCI 0.96 spec can be found at 35 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 36 * The EHCI 1.0 spec can be found at 37 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 38 * and the USB 2.0 spec at 39 * http://www.usb.org/developers/docs/usb_20.zip 40 * 41 */ 42 43/* 44 * TODO: 45 * 1) command failures are not recovered correctly 46 */ 47 48#ifdef USB_GLOBAL_INCLUDE_FILE 49#include USB_GLOBAL_INCLUDE_FILE 50#else 51#include <sys/stdint.h> 52#include <sys/stddef.h> 53#include <sys/param.h> 54#include <sys/queue.h> 55#include <sys/types.h> 56#include <sys/systm.h> 57#include <sys/kernel.h> 58#include <sys/bus.h> 59#include <sys/module.h> 60#include <sys/lock.h> 61#include <sys/mutex.h> 62#include <sys/condvar.h> 63#include <sys/sysctl.h> 64#include <sys/sx.h> 65#include <sys/unistd.h> 66#include <sys/callout.h> 67#include <sys/malloc.h> 68#include <sys/priv.h> 69 70#include <dev/usb/usb.h> 71#include <dev/usb/usbdi.h> 72 73#define USB_DEBUG_VAR ehcidebug 74 75#include <dev/usb/usb_core.h> 76#include <dev/usb/usb_debug.h> 77#include <dev/usb/usb_busdma.h> 78#include <dev/usb/usb_process.h> 79#include <dev/usb/usb_transfer.h> 80#include <dev/usb/usb_device.h> 81#include <dev/usb/usb_hub.h> 82#include <dev/usb/usb_util.h> 83 84#include <dev/usb/usb_controller.h> 85#include <dev/usb/usb_bus.h> 86#endif /* USB_GLOBAL_INCLUDE_FILE */ 87 88#include <dev/usb/controller/ehci.h> 89#include <dev/usb/controller/ehcireg.h> 90 91#define EHCI_BUS2SC(bus) \ 92 __containerof(bus, ehci_softc_t, sc_bus) 93 94#ifdef USB_DEBUG 95static int ehcidebug = 0; 96static int ehcinohighspeed = 0; 97static int ehciiaadbug = 0; 98static int ehcilostintrbug = 0; 99 100static SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 101 "USB ehci"); 102SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RWTUN, 103 &ehcidebug, 0, "Debug level"); 104SYSCTL_INT(_hw_usb_ehci, OID_AUTO, no_hs, CTLFLAG_RWTUN, 105 &ehcinohighspeed, 0, "Disable High Speed USB"); 106SYSCTL_INT(_hw_usb_ehci, OID_AUTO, iaadbug, CTLFLAG_RWTUN, 107 &ehciiaadbug, 0, "Enable doorbell bug workaround"); 108SYSCTL_INT(_hw_usb_ehci, OID_AUTO, lostintrbug, CTLFLAG_RWTUN, 109 &ehcilostintrbug, 0, "Enable lost interrupt bug workaround"); 110 111static void ehci_dump_regs(ehci_softc_t *sc); 112static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh); 113 114#endif 115 116#define EHCI_INTR_ENDPT 1 117 118static const struct usb_bus_methods ehci_bus_methods; 119static const struct usb_pipe_methods ehci_device_bulk_methods; 120static const struct usb_pipe_methods ehci_device_ctrl_methods; 121static const struct usb_pipe_methods ehci_device_intr_methods; 122static const struct usb_pipe_methods ehci_device_isoc_fs_methods; 123static const struct usb_pipe_methods ehci_device_isoc_hs_methods; 124 125static void ehci_do_poll(struct usb_bus *); 126static void ehci_device_done(struct usb_xfer *, usb_error_t); 127static uint8_t ehci_check_transfer(struct usb_xfer *); 128static void ehci_timeout(void *); 129static void ehci_poll_timeout(void *); 130 131static void ehci_root_intr(ehci_softc_t *sc); 132 133struct ehci_std_temp { 134 ehci_softc_t *sc; 135 struct usb_page_cache *pc; 136 ehci_qtd_t *td; 137 ehci_qtd_t *td_next; 138 uint32_t average; 139 uint32_t qtd_status; 140 uint32_t len; 141 uint16_t max_frame_size; 142 uint8_t shortpkt; 143 uint8_t auto_data_toggle; 144 uint8_t setup_alt_next; 145 uint8_t last_frame; 146}; 147 148void 149ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 150{ 151 ehci_softc_t *sc = EHCI_BUS2SC(bus); 152 uint32_t i; 153 154 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 155 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN); 156 157 cb(bus, &sc->sc_hw.terminate_pc, &sc->sc_hw.terminate_pg, 158 sizeof(struct ehci_qh_sub), EHCI_QH_ALIGN); 159 160 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg, 161 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 162 163 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 164 cb(bus, sc->sc_hw.intr_start_pc + i, 165 sc->sc_hw.intr_start_pg + i, 166 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 167 } 168 169 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 170 cb(bus, sc->sc_hw.isoc_hs_start_pc + i, 171 sc->sc_hw.isoc_hs_start_pg + i, 172 sizeof(ehci_itd_t), EHCI_ITD_ALIGN); 173 } 174 175 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 176 cb(bus, sc->sc_hw.isoc_fs_start_pc + i, 177 sc->sc_hw.isoc_fs_start_pg + i, 178 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN); 179 } 180} 181 182usb_error_t 183ehci_reset(ehci_softc_t *sc) 184{ 185 uint32_t hcr; 186 int i; 187 188 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 189 for (i = 0; i < 100; i++) { 190 usb_pause_mtx(NULL, hz / 128); 191 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 192 if (!hcr) { 193 if (sc->sc_vendor_post_reset != NULL) 194 sc->sc_vendor_post_reset(sc); 195 return (0); 196 } 197 } 198 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 199 return (USB_ERR_IOERROR); 200} 201 202static usb_error_t 203ehci_hcreset(ehci_softc_t *sc) 204{ 205 uint32_t hcr; 206 int i; 207 208 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 209 for (i = 0; i < 100; i++) { 210 usb_pause_mtx(NULL, hz / 128); 211 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 212 if (hcr) 213 break; 214 } 215 if (!hcr) 216 /* 217 * Fall through and try reset anyway even though 218 * Table 2-9 in the EHCI spec says this will result 219 * in undefined behavior. 220 */ 221 device_printf(sc->sc_bus.bdev, "stop timeout\n"); 222 223 return (ehci_reset(sc)); 224} 225 226static int 227ehci_init_sub(struct ehci_softc *sc) 228{ 229 struct usb_page_search buf_res; 230 uint32_t cparams; 231 uint32_t hcr; 232 uint8_t i; 233 234 cparams = EREAD4(sc, EHCI_HCCPARAMS); 235 236 DPRINTF("cparams=0x%x\n", cparams); 237 238 if (EHCI_HCC_64BIT(cparams)) { 239 DPRINTF("HCC uses 64-bit structures\n"); 240 241 /* MUST clear segment register if 64 bit capable */ 242 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 243 } 244 245 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 246 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 247 248 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 249 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 250 251 /* enable interrupts */ 252 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 253 254 /* turn on controller */ 255 EOWRITE4(sc, EHCI_USBCMD, 256 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */ 257 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 258 EHCI_CMD_ASE | 259 EHCI_CMD_PSE | 260 EHCI_CMD_RS); 261 262 /* Take over port ownership */ 263 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 264 265 for (i = 0; i < 100; i++) { 266 usb_pause_mtx(NULL, hz / 128); 267 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 268 if (!hcr) { 269 break; 270 } 271 } 272 if (hcr) { 273 device_printf(sc->sc_bus.bdev, "run timeout\n"); 274 return (USB_ERR_IOERROR); 275 } 276 return (USB_ERR_NORMAL_COMPLETION); 277} 278 279usb_error_t 280ehci_init(ehci_softc_t *sc) 281{ 282 struct usb_page_search buf_res; 283 uint32_t version; 284 uint32_t sparams; 285 uint16_t i; 286 uint16_t x; 287 uint16_t y; 288 uint16_t bit; 289 usb_error_t err = 0; 290 291 DPRINTF("start\n"); 292 293 usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0); 294 usb_callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_mtx, 0); 295 296 sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 297 298#ifdef USB_DEBUG 299 if (ehciiaadbug) 300 sc->sc_flags |= EHCI_SCFLG_IAADBUG; 301 if (ehcilostintrbug) 302 sc->sc_flags |= EHCI_SCFLG_LOSTINTRBUG; 303 if (ehcidebug > 2) { 304 ehci_dump_regs(sc); 305 } 306#endif 307 308 version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 309 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n", 310 version >> 8, version & 0xff); 311 312 sparams = EREAD4(sc, EHCI_HCSPARAMS); 313 DPRINTF("sparams=0x%x\n", sparams); 314 315 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 316 sc->sc_bus.usbrev = USB_REV_2_0; 317 318 if (!(sc->sc_flags & EHCI_SCFLG_DONTRESET)) { 319 /* Reset the controller */ 320 DPRINTF("%s: resetting\n", 321 device_get_nameunit(sc->sc_bus.bdev)); 322 323 err = ehci_hcreset(sc); 324 if (err) { 325 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 326 return (err); 327 } 328 } 329 330 /* 331 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4 332 * bytes 2: 256*4 bytes 3: unknown 333 */ 334 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) { 335 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n"); 336 return (USB_ERR_IOERROR); 337 } 338 /* set up the bus struct */ 339 sc->sc_bus.methods = &ehci_bus_methods; 340 341 sc->sc_eintrs = EHCI_NORMAL_INTRS; 342 343 if (1) { 344 struct ehci_qh_sub *qh; 345 346 usbd_get_page(&sc->sc_hw.terminate_pc, 0, &buf_res); 347 348 qh = buf_res.buffer; 349 350 sc->sc_terminate_self = htohc32(sc, buf_res.physaddr); 351 352 /* init terminate TD */ 353 qh->qtd_next = 354 htohc32(sc, EHCI_LINK_TERMINATE); 355 qh->qtd_altnext = 356 htohc32(sc, EHCI_LINK_TERMINATE); 357 qh->qtd_status = 358 htohc32(sc, EHCI_QTD_HALTED); 359 } 360 361 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 362 ehci_qh_t *qh; 363 364 usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res); 365 366 qh = buf_res.buffer; 367 368 /* initialize page cache pointer */ 369 370 qh->page_cache = sc->sc_hw.intr_start_pc + i; 371 372 /* store a pointer to queue head */ 373 374 sc->sc_intr_p_last[i] = qh; 375 376 qh->qh_self = 377 htohc32(sc, buf_res.physaddr) | 378 htohc32(sc, EHCI_LINK_QH); 379 380 qh->qh_endp = 381 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 382 qh->qh_endphub = 383 htohc32(sc, EHCI_QH_SET_MULT(1)); 384 qh->qh_curqtd = 0; 385 386 qh->qh_qtd.qtd_next = 387 htohc32(sc, EHCI_LINK_TERMINATE); 388 qh->qh_qtd.qtd_altnext = 389 htohc32(sc, EHCI_LINK_TERMINATE); 390 qh->qh_qtd.qtd_status = 391 htohc32(sc, EHCI_QTD_HALTED); 392 } 393 394 /* 395 * the QHs are arranged to give poll intervals that are 396 * powers of 2 times 1ms 397 */ 398 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 399 while (bit) { 400 x = bit; 401 while (x & bit) { 402 ehci_qh_t *qh_x; 403 ehci_qh_t *qh_y; 404 405 y = (x ^ bit) | (bit / 2); 406 407 qh_x = sc->sc_intr_p_last[x]; 408 qh_y = sc->sc_intr_p_last[y]; 409 410 /* 411 * the next QH has half the poll interval 412 */ 413 qh_x->qh_link = qh_y->qh_self; 414 415 x++; 416 } 417 bit >>= 1; 418 } 419 420 if (1) { 421 ehci_qh_t *qh; 422 423 qh = sc->sc_intr_p_last[0]; 424 425 /* the last (1ms) QH terminates */ 426 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE); 427 } 428 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 429 ehci_sitd_t *sitd; 430 ehci_itd_t *itd; 431 432 usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res); 433 434 sitd = buf_res.buffer; 435 436 /* initialize page cache pointer */ 437 438 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i; 439 440 /* store a pointer to the transfer descriptor */ 441 442 sc->sc_isoc_fs_p_last[i] = sitd; 443 444 /* initialize full speed isochronous */ 445 446 sitd->sitd_self = 447 htohc32(sc, buf_res.physaddr) | 448 htohc32(sc, EHCI_LINK_SITD); 449 450 sitd->sitd_back = 451 htohc32(sc, EHCI_LINK_TERMINATE); 452 453 sitd->sitd_next = 454 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self; 455 456 usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res); 457 458 itd = buf_res.buffer; 459 460 /* initialize page cache pointer */ 461 462 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i; 463 464 /* store a pointer to the transfer descriptor */ 465 466 sc->sc_isoc_hs_p_last[i] = itd; 467 468 /* initialize high speed isochronous */ 469 470 itd->itd_self = 471 htohc32(sc, buf_res.physaddr) | 472 htohc32(sc, EHCI_LINK_ITD); 473 474 itd->itd_next = 475 sitd->sitd_self; 476 } 477 478 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 479 480 if (1) { 481 uint32_t *pframes; 482 483 pframes = buf_res.buffer; 484 485 /* 486 * execution order: 487 * pframes -> high speed isochronous -> 488 * full speed isochronous -> interrupt QH's 489 */ 490 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) { 491 pframes[i] = sc->sc_isoc_hs_p_last 492 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self; 493 } 494 } 495 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 496 497 if (1) { 498 ehci_qh_t *qh; 499 500 qh = buf_res.buffer; 501 502 /* initialize page cache pointer */ 503 504 qh->page_cache = &sc->sc_hw.async_start_pc; 505 506 /* store a pointer to the queue head */ 507 508 sc->sc_async_p_last = qh; 509 510 /* init dummy QH that starts the async list */ 511 512 qh->qh_self = 513 htohc32(sc, buf_res.physaddr) | 514 htohc32(sc, EHCI_LINK_QH); 515 516 /* fill the QH */ 517 qh->qh_endp = 518 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 519 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1)); 520 qh->qh_link = qh->qh_self; 521 qh->qh_curqtd = 0; 522 523 /* fill the overlay qTD */ 524 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE); 525 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE); 526 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED); 527 } 528 /* flush all cache into memory */ 529 530 usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc); 531 532#ifdef USB_DEBUG 533 if (ehcidebug) { 534 ehci_dump_sqh(sc, sc->sc_async_p_last); 535 } 536#endif 537 538 /* finial setup */ 539 err = ehci_init_sub(sc); 540 541 if (!err) { 542 /* catch any lost interrupts */ 543 ehci_do_poll(&sc->sc_bus); 544 } 545 return (err); 546} 547 548/* 549 * shut down the controller when the system is going down 550 */ 551void 552ehci_detach(ehci_softc_t *sc) 553{ 554 USB_BUS_LOCK(&sc->sc_bus); 555 556 usb_callout_stop(&sc->sc_tmo_pcd); 557 usb_callout_stop(&sc->sc_tmo_poll); 558 559 EOWRITE4(sc, EHCI_USBINTR, 0); 560 USB_BUS_UNLOCK(&sc->sc_bus); 561 562 if (ehci_hcreset(sc)) { 563 DPRINTF("reset failed!\n"); 564 } 565 566 /* XXX let stray task complete */ 567 usb_pause_mtx(NULL, hz / 20); 568 569 usb_callout_drain(&sc->sc_tmo_pcd); 570 usb_callout_drain(&sc->sc_tmo_poll); 571} 572 573static void 574ehci_suspend(ehci_softc_t *sc) 575{ 576 DPRINTF("stopping the HC\n"); 577 578 /* reset HC */ 579 ehci_hcreset(sc); 580} 581 582static void 583ehci_resume(ehci_softc_t *sc) 584{ 585 /* reset HC */ 586 ehci_hcreset(sc); 587 588 /* setup HC */ 589 ehci_init_sub(sc); 590 591 /* catch any lost interrupts */ 592 ehci_do_poll(&sc->sc_bus); 593} 594 595#ifdef USB_DEBUG 596static void 597ehci_dump_regs(ehci_softc_t *sc) 598{ 599 uint32_t i; 600 601 i = EOREAD4(sc, EHCI_USBCMD); 602 printf("cmd=0x%08x\n", i); 603 604 if (i & EHCI_CMD_ITC_1) 605 printf(" EHCI_CMD_ITC_1\n"); 606 if (i & EHCI_CMD_ITC_2) 607 printf(" EHCI_CMD_ITC_2\n"); 608 if (i & EHCI_CMD_ITC_4) 609 printf(" EHCI_CMD_ITC_4\n"); 610 if (i & EHCI_CMD_ITC_8) 611 printf(" EHCI_CMD_ITC_8\n"); 612 if (i & EHCI_CMD_ITC_16) 613 printf(" EHCI_CMD_ITC_16\n"); 614 if (i & EHCI_CMD_ITC_32) 615 printf(" EHCI_CMD_ITC_32\n"); 616 if (i & EHCI_CMD_ITC_64) 617 printf(" EHCI_CMD_ITC_64\n"); 618 if (i & EHCI_CMD_ASPME) 619 printf(" EHCI_CMD_ASPME\n"); 620 if (i & EHCI_CMD_ASPMC) 621 printf(" EHCI_CMD_ASPMC\n"); 622 if (i & EHCI_CMD_LHCR) 623 printf(" EHCI_CMD_LHCR\n"); 624 if (i & EHCI_CMD_IAAD) 625 printf(" EHCI_CMD_IAAD\n"); 626 if (i & EHCI_CMD_ASE) 627 printf(" EHCI_CMD_ASE\n"); 628 if (i & EHCI_CMD_PSE) 629 printf(" EHCI_CMD_PSE\n"); 630 if (i & EHCI_CMD_FLS_M) 631 printf(" EHCI_CMD_FLS_M\n"); 632 if (i & EHCI_CMD_HCRESET) 633 printf(" EHCI_CMD_HCRESET\n"); 634 if (i & EHCI_CMD_RS) 635 printf(" EHCI_CMD_RS\n"); 636 637 i = EOREAD4(sc, EHCI_USBSTS); 638 639 printf("sts=0x%08x\n", i); 640 641 if (i & EHCI_STS_ASS) 642 printf(" EHCI_STS_ASS\n"); 643 if (i & EHCI_STS_PSS) 644 printf(" EHCI_STS_PSS\n"); 645 if (i & EHCI_STS_REC) 646 printf(" EHCI_STS_REC\n"); 647 if (i & EHCI_STS_HCH) 648 printf(" EHCI_STS_HCH\n"); 649 if (i & EHCI_STS_IAA) 650 printf(" EHCI_STS_IAA\n"); 651 if (i & EHCI_STS_HSE) 652 printf(" EHCI_STS_HSE\n"); 653 if (i & EHCI_STS_FLR) 654 printf(" EHCI_STS_FLR\n"); 655 if (i & EHCI_STS_PCD) 656 printf(" EHCI_STS_PCD\n"); 657 if (i & EHCI_STS_ERRINT) 658 printf(" EHCI_STS_ERRINT\n"); 659 if (i & EHCI_STS_INT) 660 printf(" EHCI_STS_INT\n"); 661 662 printf("ien=0x%08x\n", 663 EOREAD4(sc, EHCI_USBINTR)); 664 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 665 EOREAD4(sc, EHCI_FRINDEX), 666 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 667 EOREAD4(sc, EHCI_PERIODICLISTBASE), 668 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 669 for (i = 1; i <= sc->sc_noport; i++) { 670 printf("port %d status=0x%08x\n", i, 671 EOREAD4(sc, EHCI_PORTSC(i))); 672 } 673} 674 675static void 676ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type) 677{ 678 link = hc32toh(sc, link); 679 printf("0x%08x", link); 680 if (link & EHCI_LINK_TERMINATE) 681 printf("<T>"); 682 else { 683 printf("<"); 684 if (type) { 685 switch (EHCI_LINK_TYPE(link)) { 686 case EHCI_LINK_ITD: 687 printf("ITD"); 688 break; 689 case EHCI_LINK_QH: 690 printf("QH"); 691 break; 692 case EHCI_LINK_SITD: 693 printf("SITD"); 694 break; 695 case EHCI_LINK_FSTN: 696 printf("FSTN"); 697 break; 698 } 699 } 700 printf(">"); 701 } 702} 703 704static void 705ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd) 706{ 707 uint32_t s; 708 709 printf(" next="); 710 ehci_dump_link(sc, qtd->qtd_next, 0); 711 printf(" altnext="); 712 ehci_dump_link(sc, qtd->qtd_altnext, 0); 713 printf("\n"); 714 s = hc32toh(sc, qtd->qtd_status); 715 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 716 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 717 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 718 printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n", 719 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), 720 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE", 721 (s & EHCI_QTD_HALTED) ? "-HALTED" : "", 722 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "", 723 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "", 724 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "", 725 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "", 726 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "", 727 (s & EHCI_QTD_PINGSTATE) ? "-PING" : ""); 728 729 for (s = 0; s < 5; s++) { 730 printf(" buffer[%d]=0x%08x\n", s, 731 hc32toh(sc, qtd->qtd_buffer[s])); 732 } 733 for (s = 0; s < 5; s++) { 734 printf(" buffer_hi[%d]=0x%08x\n", s, 735 hc32toh(sc, qtd->qtd_buffer_hi[s])); 736 } 737} 738 739static uint8_t 740ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd) 741{ 742 uint8_t temp; 743 744 usb_pc_cpu_invalidate(sqtd->page_cache); 745 printf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self)); 746 ehci_dump_qtd(sc, sqtd); 747 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0; 748 return (temp); 749} 750 751static void 752ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd) 753{ 754 uint16_t i; 755 uint8_t stop; 756 757 stop = 0; 758 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) { 759 stop = ehci_dump_sqtd(sc, sqtd); 760 } 761 if (sqtd) { 762 printf("dump aborted, too many TDs\n"); 763 } 764} 765 766static void 767ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh) 768{ 769 uint32_t endp; 770 uint32_t endphub; 771 772 usb_pc_cpu_invalidate(qh->page_cache); 773 printf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F); 774 printf(" link="); 775 ehci_dump_link(sc, qh->qh_link, 1); 776 printf("\n"); 777 endp = hc32toh(sc, qh->qh_endp); 778 printf(" endp=0x%08x\n", endp); 779 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 780 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 781 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 782 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 783 printf(" mpl=0x%x ctl=%d nrl=%d\n", 784 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 785 EHCI_QH_GET_NRL(endp)); 786 endphub = hc32toh(sc, qh->qh_endphub); 787 printf(" endphub=0x%08x\n", endphub); 788 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 789 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 790 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 791 EHCI_QH_GET_MULT(endphub)); 792 printf(" curqtd="); 793 ehci_dump_link(sc, qh->qh_curqtd, 0); 794 printf("\n"); 795 printf("Overlay qTD:\n"); 796 ehci_dump_qtd(sc, (void *)&qh->qh_qtd); 797} 798 799static void 800ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd) 801{ 802 usb_pc_cpu_invalidate(sitd->page_cache); 803 printf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F); 804 printf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next)); 805 printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n", 806 hc32toh(sc, sitd->sitd_portaddr), 807 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN)) 808 ? "in" : "out", 809 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)), 810 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)), 811 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)), 812 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr))); 813 printf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask)); 814 printf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status), 815 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "", 816 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status))); 817 printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n", 818 hc32toh(sc, sitd->sitd_back), 819 hc32toh(sc, sitd->sitd_bp[0]), 820 hc32toh(sc, sitd->sitd_bp[1]), 821 hc32toh(sc, sitd->sitd_bp_hi[0]), 822 hc32toh(sc, sitd->sitd_bp_hi[1])); 823} 824 825static void 826ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd) 827{ 828 usb_pc_cpu_invalidate(itd->page_cache); 829 printf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F); 830 printf(" next=0x%08x\n", hc32toh(sc, itd->itd_next)); 831 printf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]), 832 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 833 printf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]), 834 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 835 printf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]), 836 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 837 printf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]), 838 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 839 printf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]), 840 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 841 printf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]), 842 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 843 printf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]), 844 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 845 printf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]), 846 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 847 printf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0])); 848 printf(" addr=0x%02x; endpt=0x%01x\n", 849 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])), 850 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0]))); 851 printf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1])); 852 printf(" dir=%s; mpl=0x%02x\n", 853 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out", 854 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1]))); 855 printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n", 856 hc32toh(sc, itd->itd_bp[2]), 857 hc32toh(sc, itd->itd_bp[3]), 858 hc32toh(sc, itd->itd_bp[4]), 859 hc32toh(sc, itd->itd_bp[5]), 860 hc32toh(sc, itd->itd_bp[6])); 861 printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n" 862 " 0x%08x,0x%08x,0x%08x\n", 863 hc32toh(sc, itd->itd_bp_hi[0]), 864 hc32toh(sc, itd->itd_bp_hi[1]), 865 hc32toh(sc, itd->itd_bp_hi[2]), 866 hc32toh(sc, itd->itd_bp_hi[3]), 867 hc32toh(sc, itd->itd_bp_hi[4]), 868 hc32toh(sc, itd->itd_bp_hi[5]), 869 hc32toh(sc, itd->itd_bp_hi[6])); 870} 871 872static void 873ehci_dump_isoc(ehci_softc_t *sc) 874{ 875 ehci_itd_t *itd; 876 ehci_sitd_t *sitd; 877 uint16_t max = 1000; 878 uint16_t pos; 879 880 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) & 881 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 882 883 printf("%s: isochronous dump from frame 0x%03x:\n", 884 __FUNCTION__, pos); 885 886 itd = sc->sc_isoc_hs_p_last[pos]; 887 sitd = sc->sc_isoc_fs_p_last[pos]; 888 889 while (itd && max && max--) { 890 ehci_dump_itd(sc, itd); 891 itd = itd->prev; 892 } 893 894 while (sitd && max && max--) { 895 ehci_dump_sitd(sc, sitd); 896 sitd = sitd->prev; 897 } 898} 899 900#endif 901 902static void 903ehci_transfer_intr_enqueue(struct usb_xfer *xfer) 904{ 905 /* check for early completion */ 906 if (ehci_check_transfer(xfer)) { 907 return; 908 } 909 /* put transfer on interrupt queue */ 910 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 911 912 /* start timeout, if any */ 913 if (xfer->timeout != 0) { 914 usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout); 915 } 916} 917 918#define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last) 919static ehci_sitd_t * 920_ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 921{ 922 DPRINTFN(11, "%p to %p\n", std, last); 923 924 /* (sc->sc_bus.mtx) must be locked */ 925 926 std->next = last->next; 927 std->sitd_next = last->sitd_next; 928 929 std->prev = last; 930 931 usb_pc_cpu_flush(std->page_cache); 932 933 /* 934 * the last->next->prev is never followed: std->next->prev = std; 935 */ 936 last->next = std; 937 last->sitd_next = std->sitd_self; 938 939 usb_pc_cpu_flush(last->page_cache); 940 941 return (std); 942} 943 944#define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last) 945static ehci_itd_t * 946_ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last) 947{ 948 DPRINTFN(11, "%p to %p\n", std, last); 949 950 /* (sc->sc_bus.mtx) must be locked */ 951 952 std->next = last->next; 953 std->itd_next = last->itd_next; 954 955 std->prev = last; 956 957 usb_pc_cpu_flush(std->page_cache); 958 959 /* 960 * the last->next->prev is never followed: std->next->prev = std; 961 */ 962 last->next = std; 963 last->itd_next = std->itd_self; 964 965 usb_pc_cpu_flush(last->page_cache); 966 967 return (std); 968} 969 970#define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last) 971static ehci_qh_t * 972_ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last) 973{ 974 DPRINTFN(11, "%p to %p\n", sqh, last); 975 976 if (sqh->prev != NULL) { 977 /* should not happen */ 978 DPRINTFN(0, "QH already linked!\n"); 979 return (last); 980 } 981 /* (sc->sc_bus.mtx) must be locked */ 982 983 sqh->next = last->next; 984 sqh->qh_link = last->qh_link; 985 986 sqh->prev = last; 987 988 usb_pc_cpu_flush(sqh->page_cache); 989 990 /* 991 * the last->next->prev is never followed: sqh->next->prev = sqh; 992 */ 993 994 last->next = sqh; 995 last->qh_link = sqh->qh_self; 996 997 usb_pc_cpu_flush(last->page_cache); 998 999 return (sqh); 1000} 1001 1002#define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last) 1003static ehci_sitd_t * 1004_ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 1005{ 1006 DPRINTFN(11, "%p from %p\n", std, last); 1007 1008 /* (sc->sc_bus.mtx) must be locked */ 1009 1010 std->prev->next = std->next; 1011 std->prev->sitd_next = std->sitd_next; 1012 1013 usb_pc_cpu_flush(std->prev->page_cache); 1014 1015 if (std->next) { 1016 std->next->prev = std->prev; 1017 usb_pc_cpu_flush(std->next->page_cache); 1018 } 1019 return ((last == std) ? std->prev : last); 1020} 1021 1022#define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last) 1023static ehci_itd_t * 1024_ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1025{ 1026 DPRINTFN(11, "%p from %p\n", std, last); 1027 1028 /* (sc->sc_bus.mtx) must be locked */ 1029 1030 std->prev->next = std->next; 1031 std->prev->itd_next = std->itd_next; 1032 1033 usb_pc_cpu_flush(std->prev->page_cache); 1034 1035 if (std->next) { 1036 std->next->prev = std->prev; 1037 usb_pc_cpu_flush(std->next->page_cache); 1038 } 1039 return ((last == std) ? std->prev : last); 1040} 1041 1042#define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last) 1043static ehci_qh_t * 1044_ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1045{ 1046 DPRINTFN(11, "%p from %p\n", sqh, last); 1047 1048 /* (sc->sc_bus.mtx) must be locked */ 1049 1050 /* only remove if not removed from a queue */ 1051 if (sqh->prev) { 1052 sqh->prev->next = sqh->next; 1053 sqh->prev->qh_link = sqh->qh_link; 1054 1055 usb_pc_cpu_flush(sqh->prev->page_cache); 1056 1057 if (sqh->next) { 1058 sqh->next->prev = sqh->prev; 1059 usb_pc_cpu_flush(sqh->next->page_cache); 1060 } 1061 last = ((last == sqh) ? sqh->prev : last); 1062 1063 sqh->prev = 0; 1064 1065 usb_pc_cpu_flush(sqh->page_cache); 1066 } 1067 return (last); 1068} 1069 1070static void 1071ehci_data_toggle_update(struct usb_xfer *xfer, uint16_t actlen, uint16_t xlen) 1072{ 1073 uint16_t rem; 1074 uint8_t dt; 1075 1076 /* count number of full packets */ 1077 dt = (actlen / xfer->max_packet_size) & 1; 1078 1079 /* compute remainder */ 1080 rem = actlen % xfer->max_packet_size; 1081 1082 if (rem > 0) 1083 dt ^= 1; /* short packet at the end */ 1084 else if (actlen != xlen) 1085 dt ^= 1; /* zero length packet at the end */ 1086 else if (xlen == 0) 1087 dt ^= 1; /* zero length transfer */ 1088 1089 xfer->endpoint->toggle_next ^= dt; 1090} 1091 1092static usb_error_t 1093ehci_non_isoc_done_sub(struct usb_xfer *xfer) 1094{ 1095 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1096 ehci_qtd_t *td; 1097 ehci_qtd_t *td_alt_next; 1098 uint32_t status; 1099 uint16_t len; 1100 1101 td = xfer->td_transfer_cache; 1102 td_alt_next = td->alt_next; 1103 1104 if (xfer->aframes != xfer->nframes) { 1105 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 1106 } 1107 while (1) { 1108 usb_pc_cpu_invalidate(td->page_cache); 1109 status = hc32toh(sc, td->qtd_status); 1110 1111 len = EHCI_QTD_GET_BYTES(status); 1112 1113 /* 1114 * Verify the status length and 1115 * add the length to "frlengths[]": 1116 */ 1117 if (len > td->len) { 1118 /* should not happen */ 1119 DPRINTF("Invalid status length, " 1120 "0x%04x/0x%04x bytes\n", len, td->len); 1121 status |= EHCI_QTD_HALTED; 1122 } else if (xfer->aframes != xfer->nframes) { 1123 xfer->frlengths[xfer->aframes] += td->len - len; 1124 /* manually update data toggle */ 1125 ehci_data_toggle_update(xfer, td->len - len, td->len); 1126 } 1127 1128 /* Check for last transfer */ 1129 if (((void *)td) == xfer->td_transfer_last) { 1130 td = NULL; 1131 break; 1132 } 1133 /* Check for transfer error */ 1134 if (status & EHCI_QTD_HALTED) { 1135 /* the transfer is finished */ 1136 td = NULL; 1137 break; 1138 } 1139 /* Check for short transfer */ 1140 if (len > 0) { 1141 if (xfer->flags_int.short_frames_ok) { 1142 /* follow alt next */ 1143 td = td->alt_next; 1144 } else { 1145 /* the transfer is finished */ 1146 td = NULL; 1147 } 1148 break; 1149 } 1150 td = td->obj_next; 1151 1152 if (td->alt_next != td_alt_next) { 1153 /* this USB frame is complete */ 1154 break; 1155 } 1156 } 1157 1158 /* update transfer cache */ 1159 1160 xfer->td_transfer_cache = td; 1161 1162#ifdef USB_DEBUG 1163 if (status & EHCI_QTD_STATERRS) { 1164 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x" 1165 "status=%s%s%s%s%s%s%s%s\n", 1166 xfer->address, xfer->endpointno, xfer->aframes, 1167 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1168 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "", 1169 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "", 1170 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "", 1171 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "", 1172 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "", 1173 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "", 1174 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : ""); 1175 } 1176#endif 1177 if (status & EHCI_QTD_HALTED) { 1178 if ((xfer->xroot->udev->parent_hs_hub != NULL) || 1179 (xfer->xroot->udev->address != 0)) { 1180 /* try to separate I/O errors from STALL */ 1181 if (EHCI_QTD_GET_CERR(status) == 0) 1182 return (USB_ERR_IOERROR); 1183 } 1184 return (USB_ERR_STALLED); 1185 } 1186 return (USB_ERR_NORMAL_COMPLETION); 1187} 1188 1189static void 1190ehci_non_isoc_done(struct usb_xfer *xfer) 1191{ 1192 ehci_qh_t *qh; 1193 usb_error_t err = 0; 1194 1195 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1196 xfer, xfer->endpoint); 1197 1198#ifdef USB_DEBUG 1199 if (ehcidebug > 10) { 1200 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1201 1202 ehci_dump_sqtds(sc, xfer->td_transfer_first); 1203 } 1204#endif 1205 1206 /* extract data toggle directly from the QH's overlay area */ 1207 1208 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1209 1210 usb_pc_cpu_invalidate(qh->page_cache); 1211 1212 /* reset scanner */ 1213 1214 xfer->td_transfer_cache = xfer->td_transfer_first; 1215 1216 if (xfer->flags_int.control_xfr) { 1217 if (xfer->flags_int.control_hdr) { 1218 err = ehci_non_isoc_done_sub(xfer); 1219 } 1220 xfer->aframes = 1; 1221 1222 if (xfer->td_transfer_cache == NULL) { 1223 goto done; 1224 } 1225 } 1226 while (xfer->aframes != xfer->nframes) { 1227 err = ehci_non_isoc_done_sub(xfer); 1228 xfer->aframes++; 1229 1230 if (xfer->td_transfer_cache == NULL) { 1231 goto done; 1232 } 1233 } 1234 1235 if (xfer->flags_int.control_xfr && 1236 !xfer->flags_int.control_act) { 1237 err = ehci_non_isoc_done_sub(xfer); 1238 } 1239done: 1240 ehci_device_done(xfer, err); 1241} 1242 1243/*------------------------------------------------------------------------* 1244 * ehci_check_transfer 1245 * 1246 * Return values: 1247 * 0: USB transfer is not finished 1248 * Else: USB transfer is finished 1249 *------------------------------------------------------------------------*/ 1250static uint8_t 1251ehci_check_transfer(struct usb_xfer *xfer) 1252{ 1253 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 1254 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1255 1256 uint32_t status; 1257 1258 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1259 1260 if (methods == &ehci_device_isoc_fs_methods) { 1261 ehci_sitd_t *td; 1262 1263 /* isochronous full speed transfer */ 1264 1265 td = xfer->td_transfer_last; 1266 usb_pc_cpu_invalidate(td->page_cache); 1267 status = hc32toh(sc, td->sitd_status); 1268 1269 /* also check if first is complete */ 1270 1271 td = xfer->td_transfer_first; 1272 usb_pc_cpu_invalidate(td->page_cache); 1273 status |= hc32toh(sc, td->sitd_status); 1274 1275 if (!(status & EHCI_SITD_ACTIVE)) { 1276 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1277 goto transferred; 1278 } 1279 } else if (methods == &ehci_device_isoc_hs_methods) { 1280 ehci_itd_t *td; 1281 1282 /* isochronous high speed transfer */ 1283 1284 /* check last transfer */ 1285 td = xfer->td_transfer_last; 1286 usb_pc_cpu_invalidate(td->page_cache); 1287 status = td->itd_status[0]; 1288 status |= td->itd_status[1]; 1289 status |= td->itd_status[2]; 1290 status |= td->itd_status[3]; 1291 status |= td->itd_status[4]; 1292 status |= td->itd_status[5]; 1293 status |= td->itd_status[6]; 1294 status |= td->itd_status[7]; 1295 1296 /* also check first transfer */ 1297 td = xfer->td_transfer_first; 1298 usb_pc_cpu_invalidate(td->page_cache); 1299 status |= td->itd_status[0]; 1300 status |= td->itd_status[1]; 1301 status |= td->itd_status[2]; 1302 status |= td->itd_status[3]; 1303 status |= td->itd_status[4]; 1304 status |= td->itd_status[5]; 1305 status |= td->itd_status[6]; 1306 status |= td->itd_status[7]; 1307 1308 /* if no transactions are active we continue */ 1309 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) { 1310 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1311 goto transferred; 1312 } 1313 } else { 1314 ehci_qtd_t *td; 1315 ehci_qh_t *qh; 1316 1317 /* non-isochronous transfer */ 1318 1319 /* 1320 * check whether there is an error somewhere in the middle, 1321 * or whether there was a short packet (SPD and not ACTIVE) 1322 */ 1323 td = xfer->td_transfer_cache; 1324 1325 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1326 1327 usb_pc_cpu_invalidate(qh->page_cache); 1328 1329 status = hc32toh(sc, qh->qh_qtd.qtd_status); 1330 if (status & EHCI_QTD_ACTIVE) { 1331 /* transfer is pending */ 1332 goto done; 1333 } 1334 1335 while (1) { 1336 usb_pc_cpu_invalidate(td->page_cache); 1337 status = hc32toh(sc, td->qtd_status); 1338 1339 /* 1340 * Check if there is an active TD which 1341 * indicates that the transfer isn't done. 1342 */ 1343 if (status & EHCI_QTD_ACTIVE) { 1344 /* update cache */ 1345 xfer->td_transfer_cache = td; 1346 goto done; 1347 } 1348 /* 1349 * last transfer descriptor makes the transfer done 1350 */ 1351 if (((void *)td) == xfer->td_transfer_last) { 1352 break; 1353 } 1354 /* 1355 * any kind of error makes the transfer done 1356 */ 1357 if (status & EHCI_QTD_HALTED) { 1358 break; 1359 } 1360 /* 1361 * if there is no alternate next transfer, a short 1362 * packet also makes the transfer done 1363 */ 1364 if (EHCI_QTD_GET_BYTES(status)) { 1365 if (xfer->flags_int.short_frames_ok) { 1366 /* follow alt next */ 1367 if (td->alt_next) { 1368 td = td->alt_next; 1369 continue; 1370 } 1371 } 1372 /* transfer is done */ 1373 break; 1374 } 1375 td = td->obj_next; 1376 } 1377 ehci_non_isoc_done(xfer); 1378 goto transferred; 1379 } 1380 1381done: 1382 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1383 return (0); 1384 1385transferred: 1386 return (1); 1387} 1388 1389static void 1390ehci_pcd_enable(ehci_softc_t *sc) 1391{ 1392 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1393 1394 sc->sc_eintrs |= EHCI_STS_PCD; 1395 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1396 1397 /* acknowledge any PCD interrupt */ 1398 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD); 1399 1400 ehci_root_intr(sc); 1401} 1402 1403static void 1404ehci_interrupt_poll(ehci_softc_t *sc) 1405{ 1406 struct usb_xfer *xfer; 1407 1408repeat: 1409 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1410 /* 1411 * check if transfer is transferred 1412 */ 1413 if (ehci_check_transfer(xfer)) { 1414 /* queue has been modified */ 1415 goto repeat; 1416 } 1417 } 1418} 1419 1420/* 1421 * Some EHCI chips from VIA / ATI seem to trigger interrupts before 1422 * writing back the qTD status, or miss signalling occasionally under 1423 * heavy load. If the host machine is too fast, we can miss 1424 * transaction completion - when we scan the active list the 1425 * transaction still seems to be active. This generally exhibits 1426 * itself as a umass stall that never recovers. 1427 * 1428 * We work around this behaviour by setting up this callback after any 1429 * softintr that completes with transactions still pending, giving us 1430 * another chance to check for completion after the writeback has 1431 * taken place. 1432 */ 1433static void 1434ehci_poll_timeout(void *arg) 1435{ 1436 ehci_softc_t *sc = arg; 1437 1438 DPRINTFN(3, "\n"); 1439 ehci_interrupt_poll(sc); 1440} 1441 1442/*------------------------------------------------------------------------* 1443 * ehci_interrupt - EHCI interrupt handler 1444 * 1445 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1446 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1447 * is present ! 1448 *------------------------------------------------------------------------*/ 1449void 1450ehci_interrupt(ehci_softc_t *sc) 1451{ 1452 uint32_t status; 1453 1454 USB_BUS_LOCK(&sc->sc_bus); 1455 1456 DPRINTFN(16, "real interrupt\n"); 1457 1458#ifdef USB_DEBUG 1459 if (ehcidebug > 15) { 1460 ehci_dump_regs(sc); 1461 } 1462#endif 1463 1464 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1465 if (status == 0) { 1466 /* the interrupt was not for us */ 1467 goto done; 1468 } 1469 if (!(status & sc->sc_eintrs)) { 1470 goto done; 1471 } 1472 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */ 1473 1474 status &= sc->sc_eintrs; 1475 1476 if (status & EHCI_STS_HSE) { 1477 printf("%s: unrecoverable error, " 1478 "controller halted\n", __FUNCTION__); 1479#ifdef USB_DEBUG 1480 ehci_dump_regs(sc); 1481 ehci_dump_isoc(sc); 1482#endif 1483 } 1484 if (status & EHCI_STS_PCD) { 1485 /* 1486 * Disable PCD interrupt for now, because it will be 1487 * on until the port has been reset. 1488 */ 1489 sc->sc_eintrs &= ~EHCI_STS_PCD; 1490 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1491 1492 ehci_root_intr(sc); 1493 1494 /* do not allow RHSC interrupts > 1 per second */ 1495 usb_callout_reset(&sc->sc_tmo_pcd, hz, 1496 (void *)&ehci_pcd_enable, sc); 1497 } 1498 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA); 1499 1500 if (status != 0) { 1501 /* block unprocessed interrupts */ 1502 sc->sc_eintrs &= ~status; 1503 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1504 printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status); 1505 } 1506 /* poll all the USB transfers */ 1507 ehci_interrupt_poll(sc); 1508 1509 if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) { 1510 usb_callout_reset(&sc->sc_tmo_poll, hz / 128, 1511 (void *)&ehci_poll_timeout, sc); 1512 } 1513 1514done: 1515 USB_BUS_UNLOCK(&sc->sc_bus); 1516} 1517 1518/* 1519 * called when a request does not complete 1520 */ 1521static void 1522ehci_timeout(void *arg) 1523{ 1524 struct usb_xfer *xfer = arg; 1525 1526 DPRINTF("xfer=%p\n", xfer); 1527 1528 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1529 1530 /* transfer is transferred */ 1531 ehci_device_done(xfer, USB_ERR_TIMEOUT); 1532} 1533 1534static void 1535ehci_do_poll(struct usb_bus *bus) 1536{ 1537 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1538 1539 USB_BUS_LOCK(&sc->sc_bus); 1540 ehci_interrupt_poll(sc); 1541 USB_BUS_UNLOCK(&sc->sc_bus); 1542} 1543 1544static void 1545ehci_setup_standard_chain_sub(struct ehci_std_temp *temp) 1546{ 1547 struct usb_page_search buf_res; 1548 ehci_qtd_t *td; 1549 ehci_qtd_t *td_next; 1550 ehci_qtd_t *td_alt_next; 1551 uint32_t buf_offset; 1552 uint32_t average; 1553 uint32_t len_old; 1554 uint32_t terminate; 1555 uint32_t qtd_altnext; 1556 uint8_t shortpkt_old; 1557 uint8_t precompute; 1558 1559 terminate = temp->sc->sc_terminate_self; 1560 qtd_altnext = temp->sc->sc_terminate_self; 1561 td_alt_next = NULL; 1562 buf_offset = 0; 1563 shortpkt_old = temp->shortpkt; 1564 len_old = temp->len; 1565 precompute = 1; 1566 1567restart: 1568 1569 td = temp->td; 1570 td_next = temp->td_next; 1571 1572 while (1) { 1573 if (temp->len == 0) { 1574 if (temp->shortpkt) { 1575 break; 1576 } 1577 /* send a Zero Length Packet, ZLP, last */ 1578 1579 temp->shortpkt = 1; 1580 average = 0; 1581 1582 } else { 1583 average = temp->average; 1584 1585 if (temp->len < average) { 1586 if (temp->len % temp->max_frame_size) { 1587 temp->shortpkt = 1; 1588 } 1589 average = temp->len; 1590 } 1591 } 1592 1593 if (td_next == NULL) { 1594 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__); 1595 } 1596 /* get next TD */ 1597 1598 td = td_next; 1599 td_next = td->obj_next; 1600 1601 /* check if we are pre-computing */ 1602 1603 if (precompute) { 1604 /* update remaining length */ 1605 1606 temp->len -= average; 1607 1608 continue; 1609 } 1610 /* fill out current TD */ 1611 1612 td->qtd_status = 1613 temp->qtd_status | 1614 htohc32(temp->sc, EHCI_QTD_IOC | 1615 EHCI_QTD_SET_BYTES(average)); 1616 1617 if (average == 0) { 1618 if (temp->auto_data_toggle == 0) { 1619 /* update data toggle, ZLP case */ 1620 1621 temp->qtd_status ^= 1622 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1623 } 1624 td->len = 0; 1625 1626 /* properly reset reserved fields */ 1627 td->qtd_buffer[0] = 0; 1628 td->qtd_buffer[1] = 0; 1629 td->qtd_buffer[2] = 0; 1630 td->qtd_buffer[3] = 0; 1631 td->qtd_buffer[4] = 0; 1632 td->qtd_buffer_hi[0] = 0; 1633 td->qtd_buffer_hi[1] = 0; 1634 td->qtd_buffer_hi[2] = 0; 1635 td->qtd_buffer_hi[3] = 0; 1636 td->qtd_buffer_hi[4] = 0; 1637 } else { 1638 uint8_t x; 1639 1640 if (temp->auto_data_toggle == 0) { 1641 /* update data toggle */ 1642 1643 if (howmany(average, temp->max_frame_size) & 1) { 1644 temp->qtd_status ^= 1645 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1646 } 1647 } 1648 td->len = average; 1649 1650 /* update remaining length */ 1651 1652 temp->len -= average; 1653 1654 /* fill out buffer pointers */ 1655 1656 usbd_get_page(temp->pc, buf_offset, &buf_res); 1657 td->qtd_buffer[0] = 1658 htohc32(temp->sc, buf_res.physaddr); 1659 td->qtd_buffer_hi[0] = 0; 1660 1661 x = 1; 1662 1663 while (average > EHCI_PAGE_SIZE) { 1664 average -= EHCI_PAGE_SIZE; 1665 buf_offset += EHCI_PAGE_SIZE; 1666 usbd_get_page(temp->pc, buf_offset, &buf_res); 1667 td->qtd_buffer[x] = 1668 htohc32(temp->sc, 1669 buf_res.physaddr & (~0xFFF)); 1670 td->qtd_buffer_hi[x] = 0; 1671 x++; 1672 } 1673 1674 /* 1675 * NOTE: The "average" variable is never zero after 1676 * exiting the loop above ! 1677 * 1678 * NOTE: We have to subtract one from the offset to 1679 * ensure that we are computing the physical address 1680 * of a valid page ! 1681 */ 1682 buf_offset += average; 1683 usbd_get_page(temp->pc, buf_offset - 1, &buf_res); 1684 td->qtd_buffer[x] = 1685 htohc32(temp->sc, 1686 buf_res.physaddr & (~0xFFF)); 1687 td->qtd_buffer_hi[x] = 0; 1688 1689 /* properly reset reserved fields */ 1690 while (++x < EHCI_QTD_NBUFFERS) { 1691 td->qtd_buffer[x] = 0; 1692 td->qtd_buffer_hi[x] = 0; 1693 } 1694 } 1695 1696 if (td_next) { 1697 /* link the current TD with the next one */ 1698 td->qtd_next = td_next->qtd_self; 1699 } 1700 td->qtd_altnext = qtd_altnext; 1701 td->alt_next = td_alt_next; 1702 1703 usb_pc_cpu_flush(td->page_cache); 1704 } 1705 1706 if (precompute) { 1707 precompute = 0; 1708 1709 /* setup alt next pointer, if any */ 1710 if (temp->last_frame) { 1711 td_alt_next = NULL; 1712 qtd_altnext = terminate; 1713 } else { 1714 /* we use this field internally */ 1715 td_alt_next = td_next; 1716 if (temp->setup_alt_next) { 1717 qtd_altnext = td_next->qtd_self; 1718 } else { 1719 qtd_altnext = terminate; 1720 } 1721 } 1722 1723 /* restore */ 1724 temp->shortpkt = shortpkt_old; 1725 temp->len = len_old; 1726 goto restart; 1727 } 1728 temp->td = td; 1729 temp->td_next = td_next; 1730} 1731 1732static void 1733ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last) 1734{ 1735 struct ehci_std_temp temp; 1736 const struct usb_pipe_methods *methods; 1737 ehci_qh_t *qh; 1738 ehci_qtd_t *td; 1739 uint32_t qh_endp; 1740 uint32_t qh_endphub; 1741 uint32_t x; 1742 1743 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1744 xfer->address, UE_GET_ADDR(xfer->endpointno), 1745 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1746 1747 temp.average = xfer->max_hc_frame_size; 1748 temp.max_frame_size = xfer->max_frame_size; 1749 temp.sc = EHCI_BUS2SC(xfer->xroot->bus); 1750 1751 /* toggle the DMA set we are using */ 1752 xfer->flags_int.curr_dma_set ^= 1; 1753 1754 /* get next DMA set */ 1755 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1756 1757 xfer->td_transfer_first = td; 1758 xfer->td_transfer_cache = td; 1759 1760 temp.td = NULL; 1761 temp.td_next = td; 1762 temp.qtd_status = 0; 1763 temp.last_frame = 0; 1764 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1765 1766 if (xfer->flags_int.control_xfr) { 1767 if (xfer->endpoint->toggle_next) { 1768 /* DATA1 is next */ 1769 temp.qtd_status |= 1770 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1771 } 1772 temp.auto_data_toggle = 0; 1773 } else { 1774 temp.auto_data_toggle = 1; 1775 } 1776 1777 if ((xfer->xroot->udev->parent_hs_hub != NULL) || 1778 (xfer->xroot->udev->address != 0)) { 1779 /* max 3 retries */ 1780 temp.qtd_status |= 1781 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1782 } 1783 /* check if we should prepend a setup message */ 1784 1785 if (xfer->flags_int.control_xfr) { 1786 if (xfer->flags_int.control_hdr) { 1787 xfer->endpoint->toggle_next = 0; 1788 1789 temp.qtd_status &= 1790 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1791 temp.qtd_status |= htohc32(temp.sc, 1792 EHCI_QTD_ACTIVE | 1793 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 1794 EHCI_QTD_SET_TOGGLE(0)); 1795 1796 temp.len = xfer->frlengths[0]; 1797 temp.pc = xfer->frbuffers + 0; 1798 temp.shortpkt = temp.len ? 1 : 0; 1799 /* check for last frame */ 1800 if (xfer->nframes == 1) { 1801 /* no STATUS stage yet, SETUP is last */ 1802 if (xfer->flags_int.control_act) { 1803 temp.last_frame = 1; 1804 temp.setup_alt_next = 0; 1805 } 1806 } 1807 ehci_setup_standard_chain_sub(&temp); 1808 } 1809 x = 1; 1810 } else { 1811 x = 0; 1812 } 1813 1814 while (x != xfer->nframes) { 1815 /* DATA0 / DATA1 message */ 1816 1817 temp.len = xfer->frlengths[x]; 1818 temp.pc = xfer->frbuffers + x; 1819 1820 x++; 1821 1822 if (x == xfer->nframes) { 1823 if (xfer->flags_int.control_xfr) { 1824 /* no STATUS stage yet, DATA is last */ 1825 if (xfer->flags_int.control_act) { 1826 temp.last_frame = 1; 1827 temp.setup_alt_next = 0; 1828 } 1829 } else { 1830 temp.last_frame = 1; 1831 temp.setup_alt_next = 0; 1832 } 1833 } 1834 /* keep previous data toggle and error count */ 1835 1836 temp.qtd_status &= 1837 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1838 EHCI_QTD_SET_TOGGLE(1)); 1839 1840 if (temp.len == 0) { 1841 /* make sure that we send an USB packet */ 1842 1843 temp.shortpkt = 0; 1844 1845 } else { 1846 /* regular data transfer */ 1847 1848 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1849 } 1850 1851 /* set endpoint direction */ 1852 1853 temp.qtd_status |= 1854 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 1855 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1856 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) : 1857 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1858 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT)); 1859 1860 ehci_setup_standard_chain_sub(&temp); 1861 } 1862 1863 /* check if we should append a status stage */ 1864 1865 if (xfer->flags_int.control_xfr && 1866 !xfer->flags_int.control_act) { 1867 /* 1868 * Send a DATA1 message and invert the current endpoint 1869 * direction. 1870 */ 1871 1872 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1873 EHCI_QTD_SET_TOGGLE(1)); 1874 temp.qtd_status |= 1875 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ? 1876 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1877 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) | 1878 EHCI_QTD_SET_TOGGLE(1)) : 1879 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1880 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) | 1881 EHCI_QTD_SET_TOGGLE(1)); 1882 1883 temp.len = 0; 1884 temp.pc = NULL; 1885 temp.shortpkt = 0; 1886 temp.last_frame = 1; 1887 temp.setup_alt_next = 0; 1888 1889 ehci_setup_standard_chain_sub(&temp); 1890 } 1891 td = temp.td; 1892 1893 /* the last TD terminates the transfer: */ 1894 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1895 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1896 1897 usb_pc_cpu_flush(td->page_cache); 1898 1899 /* must have at least one frame! */ 1900 1901 xfer->td_transfer_last = td; 1902 1903#ifdef USB_DEBUG 1904 if (ehcidebug > 8) { 1905 DPRINTF("nexttog=%d; data before transfer:\n", 1906 xfer->endpoint->toggle_next); 1907 ehci_dump_sqtds(temp.sc, 1908 xfer->td_transfer_first); 1909 } 1910#endif 1911 1912 methods = xfer->endpoint->methods; 1913 1914 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1915 1916 /* the "qh_link" field is filled when the QH is added */ 1917 1918 qh_endp = 1919 (EHCI_QH_SET_ADDR(xfer->address) | 1920 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 1921 EHCI_QH_SET_MPL(xfer->max_packet_size)); 1922 1923 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 1924 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH); 1925 if (methods != &ehci_device_intr_methods) 1926 qh_endp |= EHCI_QH_SET_NRL(8); 1927 } else { 1928 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) { 1929 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL); 1930 } else { 1931 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW); 1932 } 1933 1934 if (methods == &ehci_device_ctrl_methods) { 1935 qh_endp |= EHCI_QH_CTL; 1936 } 1937 if (methods != &ehci_device_intr_methods) { 1938 /* Only try one time per microframe! */ 1939 qh_endp |= EHCI_QH_SET_NRL(1); 1940 } 1941 } 1942 1943 if (temp.auto_data_toggle == 0) { 1944 /* software computes the data toggle */ 1945 qh_endp |= EHCI_QH_DTC; 1946 } 1947 1948 qh->qh_endp = htohc32(temp.sc, qh_endp); 1949 1950 qh_endphub = 1951 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) | 1952 EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) | 1953 EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) | 1954 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 1955 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no)); 1956 1957 qh->qh_endphub = htohc32(temp.sc, qh_endphub); 1958 qh->qh_curqtd = 0; 1959 1960 /* fill the overlay qTD */ 1961 1962 if (temp.auto_data_toggle && xfer->endpoint->toggle_next) { 1963 /* DATA1 is next */ 1964 qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1965 } else { 1966 qh->qh_qtd.qtd_status = 0; 1967 } 1968 1969 td = xfer->td_transfer_first; 1970 1971 qh->qh_qtd.qtd_next = td->qtd_self; 1972 qh->qh_qtd.qtd_altnext = 1973 htohc32(temp.sc, EHCI_LINK_TERMINATE); 1974 1975 /* properly reset reserved fields */ 1976 qh->qh_qtd.qtd_buffer[0] = 0; 1977 qh->qh_qtd.qtd_buffer[1] = 0; 1978 qh->qh_qtd.qtd_buffer[2] = 0; 1979 qh->qh_qtd.qtd_buffer[3] = 0; 1980 qh->qh_qtd.qtd_buffer[4] = 0; 1981 qh->qh_qtd.qtd_buffer_hi[0] = 0; 1982 qh->qh_qtd.qtd_buffer_hi[1] = 0; 1983 qh->qh_qtd.qtd_buffer_hi[2] = 0; 1984 qh->qh_qtd.qtd_buffer_hi[3] = 0; 1985 qh->qh_qtd.qtd_buffer_hi[4] = 0; 1986 1987 usb_pc_cpu_flush(qh->page_cache); 1988 1989 if (xfer->xroot->udev->flags.self_suspended == 0) { 1990 EHCI_APPEND_QH(qh, *qh_last); 1991 } 1992} 1993 1994static void 1995ehci_root_intr(ehci_softc_t *sc) 1996{ 1997 uint16_t i; 1998 uint16_t m; 1999 2000 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2001 2002 /* clear any old interrupt data */ 2003 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2004 2005 /* set bits */ 2006 m = (sc->sc_noport + 1); 2007 if (m > (8 * sizeof(sc->sc_hub_idata))) { 2008 m = (8 * sizeof(sc->sc_hub_idata)); 2009 } 2010 for (i = 1; i < m; i++) { 2011 /* pick out CHANGE bits from the status register */ 2012 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) { 2013 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2014 DPRINTF("port %d changed\n", i); 2015 } 2016 } 2017 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2018 sizeof(sc->sc_hub_idata)); 2019} 2020 2021static void 2022ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2023{ 2024 uint32_t nframes = xfer->nframes; 2025 uint32_t status; 2026 uint32_t *plen = xfer->frlengths; 2027 uint16_t len = 0; 2028 ehci_sitd_t *td = xfer->td_transfer_first; 2029 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos]; 2030 2031 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2032 xfer, xfer->endpoint); 2033 2034 while (nframes--) { 2035 if (td == NULL) { 2036 panic("%s:%d: out of TD's\n", 2037 __FUNCTION__, __LINE__); 2038 } 2039 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2040 pp_last = &sc->sc_isoc_fs_p_last[0]; 2041 } 2042#ifdef USB_DEBUG 2043 if (ehcidebug > 15) { 2044 DPRINTF("isoc FS-TD\n"); 2045 ehci_dump_sitd(sc, td); 2046 } 2047#endif 2048 usb_pc_cpu_invalidate(td->page_cache); 2049 status = hc32toh(sc, td->sitd_status); 2050 2051 len = EHCI_SITD_GET_LEN(status); 2052 2053 DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len); 2054 2055 if (*plen >= len) { 2056 len = *plen - len; 2057 } else { 2058 len = 0; 2059 } 2060 2061 *plen = len; 2062 2063 /* remove FS-TD from schedule */ 2064 EHCI_REMOVE_FS_TD(td, *pp_last); 2065 2066 pp_last++; 2067 plen++; 2068 td = td->obj_next; 2069 } 2070 2071 xfer->aframes = xfer->nframes; 2072} 2073 2074static void 2075ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2076{ 2077 uint32_t nframes = xfer->nframes; 2078 uint32_t status; 2079 uint32_t *plen = xfer->frlengths; 2080 uint16_t len = 0; 2081 uint8_t td_no = 0; 2082 ehci_itd_t *td = xfer->td_transfer_first; 2083 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos]; 2084 2085 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2086 xfer, xfer->endpoint); 2087 2088 while (nframes) { 2089 if (td == NULL) { 2090 panic("%s:%d: out of TD's\n", 2091 __FUNCTION__, __LINE__); 2092 } 2093 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2094 pp_last = &sc->sc_isoc_hs_p_last[0]; 2095 } 2096#ifdef USB_DEBUG 2097 if (ehcidebug > 15) { 2098 DPRINTF("isoc HS-TD\n"); 2099 ehci_dump_itd(sc, td); 2100 } 2101#endif 2102 2103 usb_pc_cpu_invalidate(td->page_cache); 2104 status = hc32toh(sc, td->itd_status[td_no]); 2105 2106 len = EHCI_ITD_GET_LEN(status); 2107 2108 DPRINTFN(2, "status=0x%08x, len=%u\n", status, len); 2109 2110 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2111 if (*plen >= len) { 2112 /* 2113 * The length is valid. NOTE: The 2114 * complete length is written back 2115 * into the status field, and not the 2116 * remainder like with other transfer 2117 * descriptor types. 2118 */ 2119 } else { 2120 /* Invalid length - truncate */ 2121 len = 0; 2122 } 2123 2124 *plen = len; 2125 plen++; 2126 nframes--; 2127 } 2128 2129 td_no++; 2130 2131 if ((td_no == 8) || (nframes == 0)) { 2132 /* remove HS-TD from schedule */ 2133 EHCI_REMOVE_HS_TD(td, *pp_last); 2134 pp_last++; 2135 2136 td_no = 0; 2137 td = td->obj_next; 2138 } 2139 } 2140 xfer->aframes = xfer->nframes; 2141} 2142 2143/* NOTE: "done" can be run two times in a row, 2144 * from close and from interrupt 2145 */ 2146static void 2147ehci_device_done(struct usb_xfer *xfer, usb_error_t error) 2148{ 2149 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 2150 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2151 2152 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2153 2154 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2155 xfer, xfer->endpoint, error); 2156 2157 if ((methods == &ehci_device_bulk_methods) || 2158 (methods == &ehci_device_ctrl_methods)) { 2159#ifdef USB_DEBUG 2160 if (ehcidebug > 8) { 2161 DPRINTF("nexttog=%d; data after transfer:\n", 2162 xfer->endpoint->toggle_next); 2163 ehci_dump_sqtds(sc, 2164 xfer->td_transfer_first); 2165 } 2166#endif 2167 2168 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2169 sc->sc_async_p_last); 2170 } 2171 if (methods == &ehci_device_intr_methods) { 2172 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2173 sc->sc_intr_p_last[xfer->qh_pos]); 2174 } 2175 /* 2176 * Only finish isochronous transfers once which will update 2177 * "xfer->frlengths". 2178 */ 2179 if (xfer->td_transfer_first && 2180 xfer->td_transfer_last) { 2181 if (methods == &ehci_device_isoc_fs_methods) { 2182 ehci_isoc_fs_done(sc, xfer); 2183 } 2184 if (methods == &ehci_device_isoc_hs_methods) { 2185 ehci_isoc_hs_done(sc, xfer); 2186 } 2187 xfer->td_transfer_first = NULL; 2188 xfer->td_transfer_last = NULL; 2189 } 2190 /* dequeue transfer and start next transfer */ 2191 usbd_transfer_done(xfer, error); 2192} 2193 2194/*------------------------------------------------------------------------* 2195 * ehci bulk support 2196 *------------------------------------------------------------------------*/ 2197static void 2198ehci_device_bulk_open(struct usb_xfer *xfer) 2199{ 2200 return; 2201} 2202 2203static void 2204ehci_device_bulk_close(struct usb_xfer *xfer) 2205{ 2206 ehci_device_done(xfer, USB_ERR_CANCELLED); 2207} 2208 2209static void 2210ehci_device_bulk_enter(struct usb_xfer *xfer) 2211{ 2212 return; 2213} 2214 2215static void 2216ehci_doorbell_async(struct ehci_softc *sc) 2217{ 2218 uint32_t temp; 2219 2220 /* 2221 * XXX Performance quirk: Some Host Controllers have a too low 2222 * interrupt rate. Issue an IAAD to stimulate the Host 2223 * Controller after queueing the BULK transfer. 2224 * 2225 * XXX Force the host controller to refresh any QH caches. 2226 */ 2227 temp = EOREAD4(sc, EHCI_USBCMD); 2228 if (!(temp & EHCI_CMD_IAAD)) 2229 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD); 2230} 2231 2232static void 2233ehci_device_bulk_start(struct usb_xfer *xfer) 2234{ 2235 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2236 2237 /* setup TD's and QH */ 2238 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2239 2240 /* put transfer on interrupt queue */ 2241 ehci_transfer_intr_enqueue(xfer); 2242 2243 /* 2244 * XXX Certain nVidia chipsets choke when using the IAAD 2245 * feature too frequently. 2246 */ 2247 if (sc->sc_flags & EHCI_SCFLG_IAADBUG) 2248 return; 2249 2250 ehci_doorbell_async(sc); 2251} 2252 2253static const struct usb_pipe_methods ehci_device_bulk_methods = 2254{ 2255 .open = ehci_device_bulk_open, 2256 .close = ehci_device_bulk_close, 2257 .enter = ehci_device_bulk_enter, 2258 .start = ehci_device_bulk_start, 2259}; 2260 2261/*------------------------------------------------------------------------* 2262 * ehci control support 2263 *------------------------------------------------------------------------*/ 2264static void 2265ehci_device_ctrl_open(struct usb_xfer *xfer) 2266{ 2267 return; 2268} 2269 2270static void 2271ehci_device_ctrl_close(struct usb_xfer *xfer) 2272{ 2273 ehci_device_done(xfer, USB_ERR_CANCELLED); 2274} 2275 2276static void 2277ehci_device_ctrl_enter(struct usb_xfer *xfer) 2278{ 2279 return; 2280} 2281 2282static void 2283ehci_device_ctrl_start(struct usb_xfer *xfer) 2284{ 2285 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2286 2287 /* setup TD's and QH */ 2288 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2289 2290 /* put transfer on interrupt queue */ 2291 ehci_transfer_intr_enqueue(xfer); 2292} 2293 2294static const struct usb_pipe_methods ehci_device_ctrl_methods = 2295{ 2296 .open = ehci_device_ctrl_open, 2297 .close = ehci_device_ctrl_close, 2298 .enter = ehci_device_ctrl_enter, 2299 .start = ehci_device_ctrl_start, 2300}; 2301 2302/*------------------------------------------------------------------------* 2303 * ehci interrupt support 2304 *------------------------------------------------------------------------*/ 2305static void 2306ehci_device_intr_open(struct usb_xfer *xfer) 2307{ 2308 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2309 uint16_t best; 2310 uint16_t bit; 2311 uint16_t x; 2312 2313 usb_hs_bandwidth_alloc(xfer); 2314 2315 /* 2316 * Find the best QH position corresponding to the given interval: 2317 */ 2318 2319 best = 0; 2320 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 2321 while (bit) { 2322 if (xfer->interval >= bit) { 2323 x = bit; 2324 best = bit; 2325 while (x & bit) { 2326 if (sc->sc_intr_stat[x] < 2327 sc->sc_intr_stat[best]) { 2328 best = x; 2329 } 2330 x++; 2331 } 2332 break; 2333 } 2334 bit >>= 1; 2335 } 2336 2337 sc->sc_intr_stat[best]++; 2338 xfer->qh_pos = best; 2339 2340 DPRINTFN(3, "best=%d interval=%d\n", 2341 best, xfer->interval); 2342} 2343 2344static void 2345ehci_device_intr_close(struct usb_xfer *xfer) 2346{ 2347 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2348 2349 sc->sc_intr_stat[xfer->qh_pos]--; 2350 2351 ehci_device_done(xfer, USB_ERR_CANCELLED); 2352 2353 /* bandwidth must be freed after device done */ 2354 usb_hs_bandwidth_free(xfer); 2355} 2356 2357static void 2358ehci_device_intr_enter(struct usb_xfer *xfer) 2359{ 2360 return; 2361} 2362 2363static void 2364ehci_device_intr_start(struct usb_xfer *xfer) 2365{ 2366 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2367 2368 /* setup TD's and QH */ 2369 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 2370 2371 /* put transfer on interrupt queue */ 2372 ehci_transfer_intr_enqueue(xfer); 2373} 2374 2375static const struct usb_pipe_methods ehci_device_intr_methods = 2376{ 2377 .open = ehci_device_intr_open, 2378 .close = ehci_device_intr_close, 2379 .enter = ehci_device_intr_enter, 2380 .start = ehci_device_intr_start, 2381}; 2382 2383/*------------------------------------------------------------------------* 2384 * ehci full speed isochronous support 2385 *------------------------------------------------------------------------*/ 2386static void 2387ehci_device_isoc_fs_open(struct usb_xfer *xfer) 2388{ 2389 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2390 ehci_sitd_t *td; 2391 uint32_t sitd_portaddr; 2392 uint8_t ds; 2393 2394 sitd_portaddr = 2395 EHCI_SITD_SET_ADDR(xfer->address) | 2396 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 2397 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 2398 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no); 2399 2400 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 2401 sitd_portaddr |= EHCI_SITD_SET_DIR_IN; 2402 2403 sitd_portaddr = htohc32(sc, sitd_portaddr); 2404 2405 /* initialize all TD's */ 2406 2407 for (ds = 0; ds != 2; ds++) { 2408 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2409 td->sitd_portaddr = sitd_portaddr; 2410 2411 /* 2412 * TODO: make some kind of automatic 2413 * SMASK/CMASK selection based on micro-frame 2414 * usage 2415 * 2416 * micro-frame usage (8 microframes per 1ms) 2417 */ 2418 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE); 2419 2420 usb_pc_cpu_flush(td->page_cache); 2421 } 2422 } 2423} 2424 2425static void 2426ehci_device_isoc_fs_close(struct usb_xfer *xfer) 2427{ 2428 ehci_device_done(xfer, USB_ERR_CANCELLED); 2429} 2430 2431static void 2432ehci_device_isoc_fs_enter(struct usb_xfer *xfer) 2433{ 2434 struct usb_page_search buf_res; 2435 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2436 ehci_sitd_t *td; 2437 ehci_sitd_t *td_last = NULL; 2438 ehci_sitd_t **pp_last; 2439 uint32_t *plen; 2440 uint32_t buf_offset; 2441 uint32_t nframes; 2442 uint32_t startframe; 2443 uint32_t temp; 2444 uint32_t sitd_mask; 2445 uint16_t tlen; 2446 uint8_t sa; 2447 uint8_t sb; 2448 2449#ifdef USB_DEBUG 2450 uint8_t once = 1; 2451 2452#endif 2453 2454 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2455 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2456 2457 /* get the current frame index */ 2458 2459 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2460 2461 if (usbd_xfer_get_isochronous_start_frame( 2462 xfer, nframes, 0, 1, EHCI_VIRTUAL_FRAMELIST_COUNT - 1, &startframe)) 2463 DPRINTFN(3, "start next=%d\n", startframe); 2464 2465 /* get the real number of frames */ 2466 2467 nframes = xfer->nframes; 2468 2469 buf_offset = 0; 2470 2471 plen = xfer->frlengths; 2472 2473 /* toggle the DMA set we are using */ 2474 xfer->flags_int.curr_dma_set ^= 1; 2475 2476 /* get next DMA set */ 2477 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2478 xfer->td_transfer_first = td; 2479 2480 pp_last = &sc->sc_isoc_fs_p_last[startframe]; 2481 2482 /* store starting position */ 2483 2484 xfer->qh_pos = startframe; 2485 2486 while (nframes--) { 2487 if (td == NULL) { 2488 panic("%s:%d: out of TD's\n", 2489 __FUNCTION__, __LINE__); 2490 } 2491 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) 2492 pp_last = &sc->sc_isoc_fs_p_last[0]; 2493 2494 /* reuse sitd_portaddr and sitd_back from last transfer */ 2495 2496 if (*plen > xfer->max_frame_size) { 2497#ifdef USB_DEBUG 2498 if (once) { 2499 once = 0; 2500 printf("%s: frame length(%d) exceeds %d " 2501 "bytes (frame truncated)\n", 2502 __FUNCTION__, *plen, 2503 xfer->max_frame_size); 2504 } 2505#endif 2506 *plen = xfer->max_frame_size; 2507 } 2508 2509 /* allocate a slot */ 2510 2511 sa = usbd_fs_isoc_schedule_alloc_slot(xfer, 2512 xfer->isoc_time_complete - nframes - 1); 2513 2514 if (sa == 255) { 2515 /* 2516 * Schedule is FULL, set length to zero: 2517 */ 2518 2519 *plen = 0; 2520 sa = USB_FS_ISOC_UFRAME_MAX - 1; 2521 } 2522 if (*plen) { 2523 /* 2524 * only call "usbd_get_page()" when we have a 2525 * non-zero length 2526 */ 2527 usbd_get_page(xfer->frbuffers, buf_offset, &buf_res); 2528 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr); 2529 buf_offset += *plen; 2530 /* 2531 * NOTE: We need to subtract one from the offset so 2532 * that we are on a valid page! 2533 */ 2534 usbd_get_page(xfer->frbuffers, buf_offset - 1, 2535 &buf_res); 2536 temp = buf_res.physaddr & ~0xFFF; 2537 } else { 2538 td->sitd_bp[0] = 0; 2539 temp = 0; 2540 } 2541 2542 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) { 2543 tlen = *plen; 2544 if (tlen <= 188) { 2545 temp |= 1; /* T-count = 1, TP = ALL */ 2546 tlen = 1; 2547 } else { 2548 tlen += 187; 2549 tlen /= 188; 2550 temp |= tlen; /* T-count = [1..6] */ 2551 temp |= 8; /* TP = Begin */ 2552 } 2553 2554 tlen += sa; 2555 2556 if (tlen >= 8) { 2557 sb = 0; 2558 } else { 2559 sb = (1 << tlen); 2560 } 2561 2562 sa = (1 << sa); 2563 sa = (sb - sa) & 0x3F; 2564 sb = 0; 2565 } else { 2566 sb = (-(4 << sa)) & 0xFE; 2567 sa = (1 << sa) & 0x3F; 2568 } 2569 2570 sitd_mask = (EHCI_SITD_SET_SMASK(sa) | 2571 EHCI_SITD_SET_CMASK(sb)); 2572 2573 td->sitd_bp[1] = htohc32(sc, temp); 2574 2575 td->sitd_mask = htohc32(sc, sitd_mask); 2576 2577 if (nframes == 0) { 2578 td->sitd_status = htohc32(sc, 2579 EHCI_SITD_IOC | 2580 EHCI_SITD_ACTIVE | 2581 EHCI_SITD_SET_LEN(*plen)); 2582 } else { 2583 td->sitd_status = htohc32(sc, 2584 EHCI_SITD_ACTIVE | 2585 EHCI_SITD_SET_LEN(*plen)); 2586 } 2587 usb_pc_cpu_flush(td->page_cache); 2588 2589#ifdef USB_DEBUG 2590 if (ehcidebug > 15) { 2591 DPRINTF("FS-TD %d\n", nframes); 2592 ehci_dump_sitd(sc, td); 2593 } 2594#endif 2595 /* insert TD into schedule */ 2596 EHCI_APPEND_FS_TD(td, *pp_last); 2597 pp_last++; 2598 2599 plen++; 2600 td_last = td; 2601 td = td->obj_next; 2602 } 2603 2604 xfer->td_transfer_last = td_last; 2605 2606 /* 2607 * We don't allow cancelling of the SPLIT transaction USB FULL 2608 * speed transfer, because it disturbs the bandwidth 2609 * computation algorithm. 2610 */ 2611 xfer->flags_int.can_cancel_immed = 0; 2612} 2613 2614static void 2615ehci_device_isoc_fs_start(struct usb_xfer *xfer) 2616{ 2617 /* 2618 * We don't allow cancelling of the SPLIT transaction USB FULL 2619 * speed transfer, because it disturbs the bandwidth 2620 * computation algorithm. 2621 */ 2622 xfer->flags_int.can_cancel_immed = 0; 2623 2624 /* set a default timeout */ 2625 if (xfer->timeout == 0) 2626 xfer->timeout = 500; /* ms */ 2627 2628 /* put transfer on interrupt queue */ 2629 ehci_transfer_intr_enqueue(xfer); 2630} 2631 2632static const struct usb_pipe_methods ehci_device_isoc_fs_methods = 2633{ 2634 .open = ehci_device_isoc_fs_open, 2635 .close = ehci_device_isoc_fs_close, 2636 .enter = ehci_device_isoc_fs_enter, 2637 .start = ehci_device_isoc_fs_start, 2638}; 2639 2640/*------------------------------------------------------------------------* 2641 * ehci high speed isochronous support 2642 *------------------------------------------------------------------------*/ 2643static void 2644ehci_device_isoc_hs_open(struct usb_xfer *xfer) 2645{ 2646 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2647 ehci_itd_t *td; 2648 uint32_t temp; 2649 uint8_t ds; 2650 2651 usb_hs_bandwidth_alloc(xfer); 2652 2653 /* initialize all TD's */ 2654 2655 for (ds = 0; ds != 2; ds++) { 2656 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2657 /* set TD inactive */ 2658 td->itd_status[0] = 0; 2659 td->itd_status[1] = 0; 2660 td->itd_status[2] = 0; 2661 td->itd_status[3] = 0; 2662 td->itd_status[4] = 0; 2663 td->itd_status[5] = 0; 2664 td->itd_status[6] = 0; 2665 td->itd_status[7] = 0; 2666 2667 /* set endpoint and address */ 2668 td->itd_bp[0] = htohc32(sc, 2669 EHCI_ITD_SET_ADDR(xfer->address) | 2670 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno))); 2671 2672 temp = 2673 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF); 2674 2675 /* set direction */ 2676 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 2677 temp |= EHCI_ITD_SET_DIR_IN; 2678 } 2679 /* set maximum packet size */ 2680 td->itd_bp[1] = htohc32(sc, temp); 2681 2682 /* set transfer multiplier */ 2683 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3); 2684 2685 usb_pc_cpu_flush(td->page_cache); 2686 } 2687 } 2688} 2689 2690static void 2691ehci_device_isoc_hs_close(struct usb_xfer *xfer) 2692{ 2693 ehci_device_done(xfer, USB_ERR_CANCELLED); 2694 2695 /* bandwidth must be freed after device done */ 2696 usb_hs_bandwidth_free(xfer); 2697} 2698 2699static void 2700ehci_device_isoc_hs_enter(struct usb_xfer *xfer) 2701{ 2702 struct usb_page_search buf_res; 2703 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2704 ehci_itd_t *td; 2705 ehci_itd_t *td_last = NULL; 2706 ehci_itd_t **pp_last; 2707 bus_size_t page_addr; 2708 uint32_t *plen; 2709 uint32_t status; 2710 uint32_t buf_offset; 2711 uint32_t nframes; 2712 uint32_t startframe; 2713 uint32_t itd_offset[8 + 1]; 2714 uint8_t x; 2715 uint8_t td_no; 2716 uint8_t page_no; 2717 2718#ifdef USB_DEBUG 2719 uint8_t once = 1; 2720 2721#endif 2722 2723 DPRINTFN(6, "xfer=%p next=%d nframes=%d shift=%d\n", 2724 xfer, xfer->endpoint->isoc_next, xfer->nframes, 2725 usbd_xfer_get_fps_shift(xfer)); 2726 2727 /* get the current frame index */ 2728 2729 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2730 2731 if (usbd_xfer_get_isochronous_start_frame( 2732 xfer, nframes, 0, 1, EHCI_VIRTUAL_FRAMELIST_COUNT - 1, &startframe)) 2733 DPRINTFN(3, "start next=%d\n", startframe); 2734 2735 nframes = xfer->nframes; 2736 2737 buf_offset = 0; 2738 td_no = 0; 2739 2740 plen = xfer->frlengths; 2741 2742 /* toggle the DMA set we are using */ 2743 xfer->flags_int.curr_dma_set ^= 1; 2744 2745 /* get next DMA set */ 2746 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2747 xfer->td_transfer_first = td; 2748 2749 pp_last = &sc->sc_isoc_hs_p_last[startframe]; 2750 2751 /* store starting position */ 2752 2753 xfer->qh_pos = startframe; 2754 2755 while (nframes) { 2756 if (td == NULL) { 2757 panic("%s:%d: out of TD's\n", 2758 __FUNCTION__, __LINE__); 2759 } 2760 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2761 pp_last = &sc->sc_isoc_hs_p_last[0]; 2762 } 2763 /* range check */ 2764 if (*plen > xfer->max_frame_size) { 2765#ifdef USB_DEBUG 2766 if (once) { 2767 once = 0; 2768 printf("%s: frame length(%d) exceeds %d bytes " 2769 "(frame truncated)\n", 2770 __FUNCTION__, *plen, xfer->max_frame_size); 2771 } 2772#endif 2773 *plen = xfer->max_frame_size; 2774 } 2775 2776 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2777 status = (EHCI_ITD_SET_LEN(*plen) | 2778 EHCI_ITD_ACTIVE | 2779 EHCI_ITD_SET_PG(0)); 2780 td->itd_status[td_no] = htohc32(sc, status); 2781 itd_offset[td_no] = buf_offset; 2782 buf_offset += *plen; 2783 plen++; 2784 nframes --; 2785 } else { 2786 td->itd_status[td_no] = 0; /* not active */ 2787 itd_offset[td_no] = buf_offset; 2788 } 2789 2790 td_no++; 2791 2792 if ((td_no == 8) || (nframes == 0)) { 2793 /* the rest of the transfers are not active, if any */ 2794 for (x = td_no; x != 8; x++) { 2795 td->itd_status[x] = 0; /* not active */ 2796 } 2797 2798 /* check if there is any data to be transferred */ 2799 if (itd_offset[0] != buf_offset) { 2800 page_no = 0; 2801 itd_offset[td_no] = buf_offset; 2802 2803 /* get first page offset */ 2804 usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res); 2805 /* get page address */ 2806 page_addr = buf_res.physaddr & ~0xFFF; 2807 /* update page address */ 2808 td->itd_bp[0] &= htohc32(sc, 0xFFF); 2809 td->itd_bp[0] |= htohc32(sc, page_addr); 2810 2811 for (x = 0; x != td_no; x++) { 2812 /* set page number and page offset */ 2813 status = (EHCI_ITD_SET_PG(page_no) | 2814 (buf_res.physaddr & 0xFFF)); 2815 td->itd_status[x] |= htohc32(sc, status); 2816 2817 /* get next page offset */ 2818 if (itd_offset[x + 1] == buf_offset) { 2819 /* 2820 * We subtract one so that 2821 * we don't go off the last 2822 * page! 2823 */ 2824 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 2825 } else { 2826 usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res); 2827 } 2828 2829 /* check if we need a new page */ 2830 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) { 2831 /* new page needed */ 2832 page_addr = buf_res.physaddr & ~0xFFF; 2833 if (page_no == 6) { 2834 panic("%s: too many pages\n", __FUNCTION__); 2835 } 2836 page_no++; 2837 /* update page address */ 2838 td->itd_bp[page_no] &= htohc32(sc, 0xFFF); 2839 td->itd_bp[page_no] |= htohc32(sc, page_addr); 2840 } 2841 } 2842 } 2843 /* set IOC bit if we are complete */ 2844 if (nframes == 0) { 2845 td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC); 2846 } 2847 usb_pc_cpu_flush(td->page_cache); 2848#ifdef USB_DEBUG 2849 if (ehcidebug > 15) { 2850 DPRINTF("HS-TD %d\n", nframes); 2851 ehci_dump_itd(sc, td); 2852 } 2853#endif 2854 /* insert TD into schedule */ 2855 EHCI_APPEND_HS_TD(td, *pp_last); 2856 pp_last++; 2857 2858 td_no = 0; 2859 td_last = td; 2860 td = td->obj_next; 2861 } 2862 } 2863 2864 xfer->td_transfer_last = td_last; 2865} 2866 2867static void 2868ehci_device_isoc_hs_start(struct usb_xfer *xfer) 2869{ 2870 /* put transfer on interrupt queue */ 2871 ehci_transfer_intr_enqueue(xfer); 2872} 2873 2874static const struct usb_pipe_methods ehci_device_isoc_hs_methods = 2875{ 2876 .open = ehci_device_isoc_hs_open, 2877 .close = ehci_device_isoc_hs_close, 2878 .enter = ehci_device_isoc_hs_enter, 2879 .start = ehci_device_isoc_hs_start, 2880}; 2881 2882/*------------------------------------------------------------------------* 2883 * ehci root control support 2884 *------------------------------------------------------------------------* 2885 * Simulate a hardware hub by handling all the necessary requests. 2886 *------------------------------------------------------------------------*/ 2887 2888static const 2889struct usb_device_descriptor ehci_devd = 2890{ 2891 sizeof(struct usb_device_descriptor), 2892 UDESC_DEVICE, /* type */ 2893 {0x00, 0x02}, /* USB version */ 2894 UDCLASS_HUB, /* class */ 2895 UDSUBCLASS_HUB, /* subclass */ 2896 UDPROTO_HSHUBSTT, /* protocol */ 2897 64, /* max packet */ 2898 {0}, {0}, {0x00, 0x01}, /* device id */ 2899 1, 2, 0, /* string indexes */ 2900 1 /* # of configurations */ 2901}; 2902 2903static const 2904struct usb_device_qualifier ehci_odevd = 2905{ 2906 sizeof(struct usb_device_qualifier), 2907 UDESC_DEVICE_QUALIFIER, /* type */ 2908 {0x00, 0x02}, /* USB version */ 2909 UDCLASS_HUB, /* class */ 2910 UDSUBCLASS_HUB, /* subclass */ 2911 UDPROTO_FSHUB, /* protocol */ 2912 0, /* max packet */ 2913 0, /* # of configurations */ 2914 0 2915}; 2916 2917static const struct ehci_config_desc ehci_confd = { 2918 .confd = { 2919 .bLength = sizeof(struct usb_config_descriptor), 2920 .bDescriptorType = UDESC_CONFIG, 2921 .wTotalLength[0] = sizeof(ehci_confd), 2922 .bNumInterface = 1, 2923 .bConfigurationValue = 1, 2924 .iConfiguration = 0, 2925 .bmAttributes = UC_SELF_POWERED, 2926 .bMaxPower = 0 /* max power */ 2927 }, 2928 .ifcd = { 2929 .bLength = sizeof(struct usb_interface_descriptor), 2930 .bDescriptorType = UDESC_INTERFACE, 2931 .bNumEndpoints = 1, 2932 .bInterfaceClass = UICLASS_HUB, 2933 .bInterfaceSubClass = UISUBCLASS_HUB, 2934 .bInterfaceProtocol = 0, 2935 }, 2936 .endpd = { 2937 .bLength = sizeof(struct usb_endpoint_descriptor), 2938 .bDescriptorType = UDESC_ENDPOINT, 2939 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT, 2940 .bmAttributes = UE_INTERRUPT, 2941 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 2942 .bInterval = 255, 2943 }, 2944}; 2945 2946static const 2947struct usb_hub_descriptor ehci_hubd = 2948{ 2949 .bDescLength = 0, /* dynamic length */ 2950 .bDescriptorType = UDESC_HUB, 2951}; 2952 2953uint16_t 2954ehci_get_port_speed_portsc(struct ehci_softc *sc, uint16_t index) 2955{ 2956 uint32_t v; 2957 2958 v = EOREAD4(sc, EHCI_PORTSC(index)); 2959 v = (v >> EHCI_PORTSC_PSPD_SHIFT) & EHCI_PORTSC_PSPD_MASK; 2960 2961 if (v == EHCI_PORT_SPEED_HIGH) 2962 return (UPS_HIGH_SPEED); 2963 if (v == EHCI_PORT_SPEED_LOW) 2964 return (UPS_LOW_SPEED); 2965 return (0); 2966} 2967 2968uint16_t 2969ehci_get_port_speed_hostc(struct ehci_softc *sc, uint16_t index) 2970{ 2971 uint32_t v; 2972 2973 v = EOREAD4(sc, EHCI_HOSTC(index)); 2974 v = (v >> EHCI_HOSTC_PSPD_SHIFT) & EHCI_HOSTC_PSPD_MASK; 2975 2976 if (v == EHCI_PORT_SPEED_HIGH) 2977 return (UPS_HIGH_SPEED); 2978 if (v == EHCI_PORT_SPEED_LOW) 2979 return (UPS_LOW_SPEED); 2980 return (0); 2981} 2982 2983static void 2984ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed) 2985{ 2986 uint32_t port; 2987 uint32_t v; 2988 2989 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed); 2990 2991 port = EHCI_PORTSC(index); 2992 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 2993 EOWRITE4(sc, port, v | EHCI_PS_PO); 2994} 2995 2996static usb_error_t 2997ehci_roothub_exec(struct usb_device *udev, 2998 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2999{ 3000 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3001 const char *str_ptr; 3002 const void *ptr; 3003 uint32_t port; 3004 uint32_t v; 3005 uint16_t len; 3006 uint16_t i; 3007 uint16_t value; 3008 uint16_t index; 3009 usb_error_t err; 3010 3011 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3012 3013 /* buffer reset */ 3014 ptr = (const void *)&sc->sc_hub_desc; 3015 len = 0; 3016 err = 0; 3017 3018 value = UGETW(req->wValue); 3019 index = UGETW(req->wIndex); 3020 3021 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3022 "wValue=0x%04x wIndex=0x%04x\n", 3023 req->bmRequestType, req->bRequest, 3024 UGETW(req->wLength), value, index); 3025 3026#define C(x,y) ((x) | ((y) << 8)) 3027 switch (C(req->bRequest, req->bmRequestType)) { 3028 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3029 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3030 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3031 /* 3032 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3033 * for the integrated root hub. 3034 */ 3035 break; 3036 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3037 len = 1; 3038 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3039 break; 3040 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3041 switch (value >> 8) { 3042 case UDESC_DEVICE: 3043 if ((value & 0xff) != 0) { 3044 err = USB_ERR_IOERROR; 3045 goto done; 3046 } 3047 len = sizeof(ehci_devd); 3048 ptr = (const void *)&ehci_devd; 3049 break; 3050 /* 3051 * We can't really operate at another speed, 3052 * but the specification says we need this 3053 * descriptor: 3054 */ 3055 case UDESC_DEVICE_QUALIFIER: 3056 if ((value & 0xff) != 0) { 3057 err = USB_ERR_IOERROR; 3058 goto done; 3059 } 3060 len = sizeof(ehci_odevd); 3061 ptr = (const void *)&ehci_odevd; 3062 break; 3063 3064 case UDESC_CONFIG: 3065 if ((value & 0xff) != 0) { 3066 err = USB_ERR_IOERROR; 3067 goto done; 3068 } 3069 len = sizeof(ehci_confd); 3070 ptr = (const void *)&ehci_confd; 3071 break; 3072 3073 case UDESC_STRING: 3074 switch (value & 0xff) { 3075 case 0: /* Language table */ 3076 str_ptr = "\001"; 3077 break; 3078 3079 case 1: /* Vendor */ 3080 str_ptr = sc->sc_vendor; 3081 break; 3082 3083 case 2: /* Product */ 3084 str_ptr = "EHCI root HUB"; 3085 break; 3086 3087 default: 3088 str_ptr = ""; 3089 break; 3090 } 3091 3092 len = usb_make_str_desc( 3093 sc->sc_hub_desc.temp, 3094 sizeof(sc->sc_hub_desc.temp), 3095 str_ptr); 3096 break; 3097 default: 3098 err = USB_ERR_IOERROR; 3099 goto done; 3100 } 3101 break; 3102 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3103 len = 1; 3104 sc->sc_hub_desc.temp[0] = 0; 3105 break; 3106 case C(UR_GET_STATUS, UT_READ_DEVICE): 3107 len = 2; 3108 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3109 break; 3110 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3111 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3112 len = 2; 3113 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3114 break; 3115 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3116 if (value >= EHCI_MAX_DEVICES) { 3117 err = USB_ERR_IOERROR; 3118 goto done; 3119 } 3120 sc->sc_addr = value; 3121 break; 3122 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3123 if ((value != 0) && (value != 1)) { 3124 err = USB_ERR_IOERROR; 3125 goto done; 3126 } 3127 sc->sc_conf = value; 3128 break; 3129 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3130 break; 3131 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3132 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3133 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3134 err = USB_ERR_IOERROR; 3135 goto done; 3136 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3137 break; 3138 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3139 break; 3140 /* Hub requests */ 3141 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3142 break; 3143 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3144 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3145 3146 if ((index < 1) || 3147 (index > sc->sc_noport)) { 3148 err = USB_ERR_IOERROR; 3149 goto done; 3150 } 3151 port = EHCI_PORTSC(index); 3152 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3153 switch (value) { 3154 case UHF_PORT_ENABLE: 3155 EOWRITE4(sc, port, v & ~EHCI_PS_PE); 3156 break; 3157 case UHF_PORT_SUSPEND: 3158 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) { 3159 /* 3160 * waking up a High Speed device is rather 3161 * complicated if 3162 */ 3163 EOWRITE4(sc, port, v | EHCI_PS_FPR); 3164 } 3165 /* wait 20ms for resume sequence to complete */ 3166 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3167 3168 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP | 3169 EHCI_PS_FPR | (3 << 10) /* High Speed */ )); 3170 3171 /* 4ms settle time */ 3172 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3173 break; 3174 case UHF_PORT_POWER: 3175 EOWRITE4(sc, port, v & ~EHCI_PS_PP); 3176 break; 3177 case UHF_PORT_TEST: 3178 DPRINTFN(3, "clear port test " 3179 "%d\n", index); 3180 break; 3181 case UHF_PORT_INDICATOR: 3182 DPRINTFN(3, "clear port ind " 3183 "%d\n", index); 3184 EOWRITE4(sc, port, v & ~EHCI_PS_PIC); 3185 break; 3186 case UHF_C_PORT_CONNECTION: 3187 EOWRITE4(sc, port, v | EHCI_PS_CSC); 3188 break; 3189 case UHF_C_PORT_ENABLE: 3190 EOWRITE4(sc, port, v | EHCI_PS_PEC); 3191 break; 3192 case UHF_C_PORT_SUSPEND: 3193 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3194 break; 3195 case UHF_C_PORT_OVER_CURRENT: 3196 EOWRITE4(sc, port, v | EHCI_PS_OCC); 3197 break; 3198 case UHF_C_PORT_RESET: 3199 sc->sc_isreset = 0; 3200 break; 3201 default: 3202 err = USB_ERR_IOERROR; 3203 goto done; 3204 } 3205 break; 3206 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3207 if ((value & 0xff) != 0) { 3208 err = USB_ERR_IOERROR; 3209 goto done; 3210 } 3211 v = EREAD4(sc, EHCI_HCSPARAMS); 3212 3213 sc->sc_hub_desc.hubd = ehci_hubd; 3214 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3215 3216 if (EHCI_HCS_PPC(v)) 3217 i = UHD_PWR_INDIVIDUAL; 3218 else 3219 i = UHD_PWR_NO_SWITCH; 3220 3221 if (EHCI_HCS_P_INDICATOR(v)) 3222 i |= UHD_PORT_IND; 3223 3224 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3225 /* XXX can't find out? */ 3226 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200; 3227 /* XXX don't know if ports are removable or not */ 3228 sc->sc_hub_desc.hubd.bDescLength = 3229 8 + ((sc->sc_noport + 7) / 8); 3230 len = sc->sc_hub_desc.hubd.bDescLength; 3231 break; 3232 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3233 len = 16; 3234 memset(sc->sc_hub_desc.temp, 0, 16); 3235 break; 3236 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3237 DPRINTFN(9, "get port status i=%d\n", 3238 index); 3239 if ((index < 1) || 3240 (index > sc->sc_noport)) { 3241 err = USB_ERR_IOERROR; 3242 goto done; 3243 } 3244 v = EOREAD4(sc, EHCI_PORTSC(index)); 3245 DPRINTFN(9, "port status=0x%04x\n", v); 3246 if (sc->sc_flags & EHCI_SCFLG_TT) { 3247 if (sc->sc_vendor_get_port_speed != NULL) { 3248 i = sc->sc_vendor_get_port_speed(sc, index); 3249 } else { 3250 device_printf(sc->sc_bus.bdev, 3251 "EHCI_SCFLG_TT quirk is set but " 3252 "sc_vendor_get_hub_speed() is NULL\n"); 3253 i = UPS_HIGH_SPEED; 3254 } 3255 } else { 3256 i = UPS_HIGH_SPEED; 3257 } 3258 if (v & EHCI_PS_CS) 3259 i |= UPS_CURRENT_CONNECT_STATUS; 3260 if (v & EHCI_PS_PE) 3261 i |= UPS_PORT_ENABLED; 3262 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR)) 3263 i |= UPS_SUSPEND; 3264 if (v & EHCI_PS_OCA) 3265 i |= UPS_OVERCURRENT_INDICATOR; 3266 if (v & EHCI_PS_PR) 3267 i |= UPS_RESET; 3268 if (v & EHCI_PS_PP) 3269 i |= UPS_PORT_POWER; 3270 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3271 i = 0; 3272 if (v & EHCI_PS_CSC) 3273 i |= UPS_C_CONNECT_STATUS; 3274 if (v & EHCI_PS_PEC) 3275 i |= UPS_C_PORT_ENABLED; 3276 if (v & EHCI_PS_OCC) 3277 i |= UPS_C_OVERCURRENT_INDICATOR; 3278 if (v & EHCI_PS_FPR) 3279 i |= UPS_C_SUSPEND; 3280 if (sc->sc_isreset) 3281 i |= UPS_C_PORT_RESET; 3282 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3283 len = sizeof(sc->sc_hub_desc.ps); 3284 break; 3285 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3286 err = USB_ERR_IOERROR; 3287 goto done; 3288 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3289 break; 3290 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3291 if ((index < 1) || 3292 (index > sc->sc_noport)) { 3293 err = USB_ERR_IOERROR; 3294 goto done; 3295 } 3296 port = EHCI_PORTSC(index); 3297 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3298 switch (value) { 3299 case UHF_PORT_ENABLE: 3300 EOWRITE4(sc, port, v | EHCI_PS_PE); 3301 break; 3302 case UHF_PORT_SUSPEND: 3303 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3304 break; 3305 case UHF_PORT_RESET: 3306 DPRINTFN(6, "reset port %d\n", index); 3307#ifdef USB_DEBUG 3308 if (ehcinohighspeed) { 3309 /* 3310 * Connect USB device to companion 3311 * controller. 3312 */ 3313 ehci_disown(sc, index, 1); 3314 break; 3315 } 3316#endif 3317 if (EHCI_PS_IS_LOWSPEED(v) && 3318 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3319 /* Low speed device, give up ownership. */ 3320 ehci_disown(sc, index, 1); 3321 break; 3322 } 3323 /* Start reset sequence. */ 3324 v &= ~(EHCI_PS_PE | EHCI_PS_PR); 3325 EOWRITE4(sc, port, v | EHCI_PS_PR); 3326 3327 /* Wait for reset to complete. */ 3328 usb_pause_mtx(&sc->sc_bus.bus_mtx, 3329 USB_MS_TO_TICKS(usb_port_root_reset_delay)); 3330 3331 /* Terminate reset sequence. */ 3332 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM)) 3333 EOWRITE4(sc, port, v); 3334 3335 /* Wait for HC to complete reset. */ 3336 usb_pause_mtx(&sc->sc_bus.bus_mtx, 3337 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE)); 3338 3339 v = EOREAD4(sc, port); 3340 DPRINTF("ehci after reset, status=0x%08x\n", v); 3341 if (v & EHCI_PS_PR) { 3342 device_printf(sc->sc_bus.bdev, 3343 "port reset timeout\n"); 3344 err = USB_ERR_TIMEOUT; 3345 goto done; 3346 } 3347 if (!(v & EHCI_PS_PE) && 3348 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3349 /* Not a high speed device, give up ownership.*/ 3350 ehci_disown(sc, index, 0); 3351 break; 3352 } 3353 sc->sc_isreset = 1; 3354 DPRINTF("ehci port %d reset, status = 0x%08x\n", 3355 index, v); 3356 break; 3357 3358 case UHF_PORT_POWER: 3359 DPRINTFN(3, "set port power %d\n", index); 3360 EOWRITE4(sc, port, v | EHCI_PS_PP); 3361 break; 3362 3363 case UHF_PORT_TEST: 3364 DPRINTFN(3, "set port test %d\n", index); 3365 break; 3366 3367 case UHF_PORT_INDICATOR: 3368 DPRINTFN(3, "set port ind %d\n", index); 3369 EOWRITE4(sc, port, v | EHCI_PS_PIC); 3370 break; 3371 3372 default: 3373 err = USB_ERR_IOERROR; 3374 goto done; 3375 } 3376 break; 3377 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3378 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3379 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3380 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3381 break; 3382 default: 3383 err = USB_ERR_IOERROR; 3384 goto done; 3385 } 3386done: 3387 *plength = len; 3388 *pptr = ptr; 3389 return (err); 3390} 3391 3392static void 3393ehci_xfer_setup(struct usb_setup_params *parm) 3394{ 3395 struct usb_page_search page_info; 3396 struct usb_page_cache *pc; 3397 ehci_softc_t *sc; 3398 struct usb_xfer *xfer; 3399 void *last_obj; 3400 uint32_t nqtd; 3401 uint32_t nqh; 3402 uint32_t nsitd; 3403 uint32_t nitd; 3404 uint32_t n; 3405 3406 sc = EHCI_BUS2SC(parm->udev->bus); 3407 xfer = parm->curr_xfer; 3408 3409 nqtd = 0; 3410 nqh = 0; 3411 nsitd = 0; 3412 nitd = 0; 3413 3414 /* 3415 * compute maximum number of some structures 3416 */ 3417 if (parm->methods == &ehci_device_ctrl_methods) { 3418 /* 3419 * The proof for the "nqtd" formula is illustrated like 3420 * this: 3421 * 3422 * +------------------------------------+ 3423 * | | 3424 * | |remainder -> | 3425 * | +-----+---+ | 3426 * | | xxx | x | frm 0 | 3427 * | +-----+---++ | 3428 * | | xxx | xx | frm 1 | 3429 * | +-----+----+ | 3430 * | ... | 3431 * +------------------------------------+ 3432 * 3433 * "xxx" means a completely full USB transfer descriptor 3434 * 3435 * "x" and "xx" means a short USB packet 3436 * 3437 * For the remainder of an USB transfer modulo 3438 * "max_data_length" we need two USB transfer descriptors. 3439 * One to transfer the remaining data and one to finalise 3440 * with a zero length packet in case the "force_short_xfer" 3441 * flag is set. We only need two USB transfer descriptors in 3442 * the case where the transfer length of the first one is a 3443 * factor of "max_frame_size". The rest of the needed USB 3444 * transfer descriptors is given by the buffer size divided 3445 * by the maximum data payload. 3446 */ 3447 parm->hc_max_packet_size = 0x400; 3448 parm->hc_max_packet_count = 1; 3449 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3450 xfer->flags_int.bdma_enable = 1; 3451 3452 usbd_transfer_setup_sub(parm); 3453 3454 nqh = 1; 3455 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */ 3456 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3457 3458 } else if (parm->methods == &ehci_device_bulk_methods) { 3459 parm->hc_max_packet_size = 0x400; 3460 parm->hc_max_packet_count = 1; 3461 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3462 xfer->flags_int.bdma_enable = 1; 3463 3464 usbd_transfer_setup_sub(parm); 3465 3466 nqh = 1; 3467 nqtd = ((2 * xfer->nframes) 3468 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3469 3470 } else if (parm->methods == &ehci_device_intr_methods) { 3471 if (parm->speed == USB_SPEED_HIGH) { 3472 parm->hc_max_packet_size = 0x400; 3473 parm->hc_max_packet_count = 3; 3474 } else if (parm->speed == USB_SPEED_FULL) { 3475 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME; 3476 parm->hc_max_packet_count = 1; 3477 } else { 3478 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8; 3479 parm->hc_max_packet_count = 1; 3480 } 3481 3482 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3483 xfer->flags_int.bdma_enable = 1; 3484 3485 usbd_transfer_setup_sub(parm); 3486 3487 nqh = 1; 3488 nqtd = ((2 * xfer->nframes) 3489 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3490 3491 } else if (parm->methods == &ehci_device_isoc_fs_methods) { 3492 parm->hc_max_packet_size = 0x3FF; 3493 parm->hc_max_packet_count = 1; 3494 parm->hc_max_frame_size = 0x3FF; 3495 xfer->flags_int.bdma_enable = 1; 3496 3497 usbd_transfer_setup_sub(parm); 3498 3499 nsitd = xfer->nframes; 3500 3501 } else if (parm->methods == &ehci_device_isoc_hs_methods) { 3502 parm->hc_max_packet_size = 0x400; 3503 parm->hc_max_packet_count = 3; 3504 parm->hc_max_frame_size = 0xC00; 3505 xfer->flags_int.bdma_enable = 1; 3506 3507 usbd_transfer_setup_sub(parm); 3508 3509 nitd = ((xfer->nframes + 7) / 8) << 3510 usbd_xfer_get_fps_shift(xfer); 3511 3512 } else { 3513 parm->hc_max_packet_size = 0x400; 3514 parm->hc_max_packet_count = 1; 3515 parm->hc_max_frame_size = 0x400; 3516 3517 usbd_transfer_setup_sub(parm); 3518 } 3519 3520alloc_dma_set: 3521 3522 if (parm->err) { 3523 return; 3524 } 3525 /* 3526 * Allocate queue heads and transfer descriptors 3527 */ 3528 last_obj = NULL; 3529 3530 if (usbd_transfer_setup_sub_malloc( 3531 parm, &pc, sizeof(ehci_itd_t), 3532 EHCI_ITD_ALIGN, nitd)) { 3533 parm->err = USB_ERR_NOMEM; 3534 return; 3535 } 3536 if (parm->buf) { 3537 for (n = 0; n != nitd; n++) { 3538 ehci_itd_t *td; 3539 3540 usbd_get_page(pc + n, 0, &page_info); 3541 3542 td = page_info.buffer; 3543 3544 /* init TD */ 3545 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD); 3546 td->obj_next = last_obj; 3547 td->page_cache = pc + n; 3548 3549 last_obj = td; 3550 3551 usb_pc_cpu_flush(pc + n); 3552 } 3553 } 3554 if (usbd_transfer_setup_sub_malloc( 3555 parm, &pc, sizeof(ehci_sitd_t), 3556 EHCI_SITD_ALIGN, nsitd)) { 3557 parm->err = USB_ERR_NOMEM; 3558 return; 3559 } 3560 if (parm->buf) { 3561 for (n = 0; n != nsitd; n++) { 3562 ehci_sitd_t *td; 3563 3564 usbd_get_page(pc + n, 0, &page_info); 3565 3566 td = page_info.buffer; 3567 3568 /* init TD */ 3569 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD); 3570 td->obj_next = last_obj; 3571 td->page_cache = pc + n; 3572 3573 last_obj = td; 3574 3575 usb_pc_cpu_flush(pc + n); 3576 } 3577 } 3578 if (usbd_transfer_setup_sub_malloc( 3579 parm, &pc, sizeof(ehci_qtd_t), 3580 EHCI_QTD_ALIGN, nqtd)) { 3581 parm->err = USB_ERR_NOMEM; 3582 return; 3583 } 3584 if (parm->buf) { 3585 for (n = 0; n != nqtd; n++) { 3586 ehci_qtd_t *qtd; 3587 3588 usbd_get_page(pc + n, 0, &page_info); 3589 3590 qtd = page_info.buffer; 3591 3592 /* init TD */ 3593 qtd->qtd_self = htohc32(sc, page_info.physaddr); 3594 qtd->obj_next = last_obj; 3595 qtd->page_cache = pc + n; 3596 3597 last_obj = qtd; 3598 3599 usb_pc_cpu_flush(pc + n); 3600 } 3601 } 3602 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3603 3604 last_obj = NULL; 3605 3606 if (usbd_transfer_setup_sub_malloc( 3607 parm, &pc, sizeof(ehci_qh_t), 3608 EHCI_QH_ALIGN, nqh)) { 3609 parm->err = USB_ERR_NOMEM; 3610 return; 3611 } 3612 if (parm->buf) { 3613 for (n = 0; n != nqh; n++) { 3614 ehci_qh_t *qh; 3615 3616 usbd_get_page(pc + n, 0, &page_info); 3617 3618 qh = page_info.buffer; 3619 3620 /* init QH */ 3621 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH); 3622 qh->obj_next = last_obj; 3623 qh->page_cache = pc + n; 3624 3625 last_obj = qh; 3626 3627 usb_pc_cpu_flush(pc + n); 3628 } 3629 } 3630 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3631 3632 if (!xfer->flags_int.curr_dma_set) { 3633 xfer->flags_int.curr_dma_set = 1; 3634 goto alloc_dma_set; 3635 } 3636} 3637 3638static void 3639ehci_xfer_unsetup(struct usb_xfer *xfer) 3640{ 3641 return; 3642} 3643 3644static void 3645ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3646 struct usb_endpoint *ep) 3647{ 3648 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3649 3650 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3651 ep, udev->address, 3652 edesc->bEndpointAddress, udev->flags.usb_mode, 3653 sc->sc_addr); 3654 3655 if (udev->device_index != sc->sc_addr) { 3656 if ((udev->speed != USB_SPEED_HIGH) && 3657 ((udev->hs_hub_addr == 0) || 3658 (udev->hs_port_no == 0) || 3659 (udev->parent_hs_hub == NULL) || 3660 (udev->parent_hs_hub->hub == NULL))) { 3661 /* We need a transaction translator */ 3662 goto done; 3663 } 3664 switch (edesc->bmAttributes & UE_XFERTYPE) { 3665 case UE_CONTROL: 3666 ep->methods = &ehci_device_ctrl_methods; 3667 break; 3668 case UE_INTERRUPT: 3669 ep->methods = &ehci_device_intr_methods; 3670 break; 3671 case UE_ISOCHRONOUS: 3672 if (udev->speed == USB_SPEED_HIGH) { 3673 ep->methods = &ehci_device_isoc_hs_methods; 3674 } else if (udev->speed == USB_SPEED_FULL) { 3675 ep->methods = &ehci_device_isoc_fs_methods; 3676 } 3677 break; 3678 case UE_BULK: 3679 ep->methods = &ehci_device_bulk_methods; 3680 break; 3681 default: 3682 /* do nothing */ 3683 break; 3684 } 3685 } 3686done: 3687 return; 3688} 3689 3690static void 3691ehci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3692{ 3693 /* 3694 * Wait until the hardware has finished any possible use of 3695 * the transfer descriptor(s) and QH 3696 */ 3697 *pus = (1125); /* microseconds */ 3698} 3699 3700static void 3701ehci_device_resume(struct usb_device *udev) 3702{ 3703 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3704 struct usb_xfer *xfer; 3705 const struct usb_pipe_methods *methods; 3706 3707 DPRINTF("\n"); 3708 3709 USB_BUS_LOCK(udev->bus); 3710 3711 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3712 if (xfer->xroot->udev == udev) { 3713 methods = xfer->endpoint->methods; 3714 3715 if ((methods == &ehci_device_bulk_methods) || 3716 (methods == &ehci_device_ctrl_methods)) { 3717 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3718 sc->sc_async_p_last); 3719 } 3720 if (methods == &ehci_device_intr_methods) { 3721 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3722 sc->sc_intr_p_last[xfer->qh_pos]); 3723 } 3724 } 3725 } 3726 3727 USB_BUS_UNLOCK(udev->bus); 3728 3729 return; 3730} 3731 3732static void 3733ehci_device_suspend(struct usb_device *udev) 3734{ 3735 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3736 struct usb_xfer *xfer; 3737 const struct usb_pipe_methods *methods; 3738 3739 DPRINTF("\n"); 3740 3741 USB_BUS_LOCK(udev->bus); 3742 3743 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3744 if (xfer->xroot->udev == udev) { 3745 methods = xfer->endpoint->methods; 3746 3747 if ((methods == &ehci_device_bulk_methods) || 3748 (methods == &ehci_device_ctrl_methods)) { 3749 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3750 sc->sc_async_p_last); 3751 } 3752 if (methods == &ehci_device_intr_methods) { 3753 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3754 sc->sc_intr_p_last[xfer->qh_pos]); 3755 } 3756 } 3757 } 3758 3759 USB_BUS_UNLOCK(udev->bus); 3760} 3761 3762static void 3763ehci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 3764{ 3765 struct ehci_softc *sc = EHCI_BUS2SC(bus); 3766 3767 switch (state) { 3768 case USB_HW_POWER_SUSPEND: 3769 case USB_HW_POWER_SHUTDOWN: 3770 ehci_suspend(sc); 3771 break; 3772 case USB_HW_POWER_RESUME: 3773 ehci_resume(sc); 3774 break; 3775 default: 3776 break; 3777 } 3778} 3779 3780static void 3781ehci_set_hw_power(struct usb_bus *bus) 3782{ 3783 ehci_softc_t *sc = EHCI_BUS2SC(bus); 3784 uint32_t temp; 3785 uint32_t flags; 3786 3787 DPRINTF("\n"); 3788 3789 USB_BUS_LOCK(bus); 3790 3791 flags = bus->hw_power_state; 3792 3793 temp = EOREAD4(sc, EHCI_USBCMD); 3794 3795 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 3796 3797 if (flags & (USB_HW_POWER_CONTROL | 3798 USB_HW_POWER_BULK)) { 3799 DPRINTF("Async is active\n"); 3800 temp |= EHCI_CMD_ASE; 3801 } 3802 if (flags & (USB_HW_POWER_INTERRUPT | 3803 USB_HW_POWER_ISOC)) { 3804 DPRINTF("Periodic is active\n"); 3805 temp |= EHCI_CMD_PSE; 3806 } 3807 EOWRITE4(sc, EHCI_USBCMD, temp); 3808 3809 USB_BUS_UNLOCK(bus); 3810 3811 return; 3812} 3813 3814static void 3815ehci_start_dma_delay_second(struct usb_xfer *xfer) 3816{ 3817 struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus); 3818 3819 DPRINTF("\n"); 3820 3821 /* trigger doorbell */ 3822 ehci_doorbell_async(sc); 3823 3824 /* give the doorbell 4ms */ 3825 usbd_transfer_timeout_ms(xfer, 3826 (void (*)(void *))&usb_dma_delay_done_cb, 4); 3827} 3828 3829/* 3830 * Ring the doorbell twice before freeing any DMA descriptors. Some host 3831 * controllers apparently cache the QH descriptors and need a message 3832 * that the cache needs to be discarded. 3833 */ 3834static void 3835ehci_start_dma_delay(struct usb_xfer *xfer) 3836{ 3837 struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus); 3838 3839 DPRINTF("\n"); 3840 3841 /* trigger doorbell */ 3842 ehci_doorbell_async(sc); 3843 3844 /* give the doorbell 4ms */ 3845 usbd_transfer_timeout_ms(xfer, 3846 (void (*)(void *))&ehci_start_dma_delay_second, 4); 3847} 3848 3849static const struct usb_bus_methods ehci_bus_methods = 3850{ 3851 .endpoint_init = ehci_ep_init, 3852 .xfer_setup = ehci_xfer_setup, 3853 .xfer_unsetup = ehci_xfer_unsetup, 3854 .get_dma_delay = ehci_get_dma_delay, 3855 .device_resume = ehci_device_resume, 3856 .device_suspend = ehci_device_suspend, 3857 .set_hw_power = ehci_set_hw_power, 3858 .set_hw_power_sleep = ehci_set_hw_power_sleep, 3859 .roothub_exec = ehci_roothub_exec, 3860 .xfer_poll = ehci_do_poll, 3861 .start_dma_delay = ehci_start_dma_delay, 3862}; 3863