1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * USB Device Port register definitions, copied from ATMEGA documentation 30 * provided by ATMEL. 31 */ 32 33#ifndef _ATMEGADCI_H_ 34#define _ATMEGADCI_H_ 35 36#define ATMEGA_MAX_DEVICES (USB_MIN_DEVICES + 1) 37 38#define ATMEGA_OTGTCON 0xF9 39#define ATMEGA_OTGTCON_VALUE(x) ((x) << 0) 40#define ATMEGA_OTGTCON_PAGE(x) ((x) << 5) 41 42#define ATMEGA_UEINT 0xF4 43#define ATMEGA_UEINT_MASK(n) (1 << (n)) /* endpoint interrupt mask */ 44 45#define ATMEGA_UEBCHX 0xF3 /* FIFO byte count high */ 46#define ATMEGA_UEBCLX 0xF2 /* FIFO byte count low */ 47#define ATMEGA_UEDATX 0xF1 /* FIFO data */ 48 49#define ATMEGA_UEIENX 0xF0 /* interrupt enable register */ 50#define ATMEGA_UEIENX_TXINE (1 << 0) 51#define ATMEGA_UEIENX_STALLEDE (1 << 1) 52#define ATMEGA_UEIENX_RXOUTE (1 << 2) 53#define ATMEGA_UEIENX_RXSTPE (1 << 3) /* received SETUP packet */ 54#define ATMEGA_UEIENX_NAKOUTE (1 << 4) 55#define ATMEGA_UEIENX_NAKINE (1 << 6) 56#define ATMEGA_UEIENX_FLERRE (1 << 7) 57 58#define ATMEGA_UESTA1X 0xEF 59#define ATMEGA_UESTA1X_CURRBK (3 << 0) /* current bank */ 60#define ATMEGA_UESTA1X_CTRLDIR (1 << 2) /* control endpoint direction */ 61 62#define ATMEGA_UESTA0X 0xEE 63#define ATMEGA_UESTA0X_NBUSYBK (3 << 0) 64#define ATMEGA_UESTA0X_DTSEQ (3 << 2) 65#define ATMEGA_UESTA0X_UNDERFI (1 << 5) /* underflow */ 66#define ATMEGA_UESTA0X_OVERFI (1 << 6) /* overflow */ 67#define ATMEGA_UESTA0X_CFGOK (1 << 7) 68 69#define ATMEGA_UECFG1X 0xED /* endpoint config register */ 70#define ATMEGA_UECFG1X_ALLOC (1 << 1) 71#define ATMEGA_UECFG1X_EPBK0 (0 << 2) 72#define ATMEGA_UECFG1X_EPBK1 (1 << 2) 73#define ATMEGA_UECFG1X_EPBK2 (2 << 2) 74#define ATMEGA_UECFG1X_EPBK3 (3 << 2) 75#define ATMEGA_UECFG1X_EPSIZE(n) ((n) << 4) 76 77#define ATMEGA_UECFG0X 0xEC 78#define ATMEGA_UECFG0X_EPDIR (1 << 0) /* endpoint direction */ 79#define ATMEGA_UECFG0X_EPTYPE0 (0 << 6) 80#define ATMEGA_UECFG0X_EPTYPE1 (1 << 6) 81#define ATMEGA_UECFG0X_EPTYPE2 (2 << 6) 82#define ATMEGA_UECFG0X_EPTYPE3 (3 << 6) 83 84#define ATMEGA_UECONX 0xEB 85#define ATMEGA_UECONX_EPEN (1 << 0) 86#define ATMEGA_UECONX_RSTDT (1 << 3) 87#define ATMEGA_UECONX_STALLRQC (1 << 4) /* stall request clear */ 88#define ATMEGA_UECONX_STALLRQ (1 << 5) /* stall request set */ 89 90#define ATMEGA_UERST 0xEA /* endpoint reset register */ 91#define ATMEGA_UERST_MASK(n) (1 << (n)) 92 93#define ATMEGA_UENUM 0xE9 /* endpoint number */ 94 95#define ATMEGA_UEINTX 0xE8 /* interrupt register */ 96#define ATMEGA_UEINTX_TXINI (1 << 0) 97#define ATMEGA_UEINTX_STALLEDI (1 << 1) 98#define ATMEGA_UEINTX_RXOUTI (1 << 2) 99#define ATMEGA_UEINTX_RXSTPI (1 << 3) /* received setup packet */ 100#define ATMEGA_UEINTX_NAKOUTI (1 << 4) 101#define ATMEGA_UEINTX_RWAL (1 << 5) 102#define ATMEGA_UEINTX_NAKINI (1 << 6) 103#define ATMEGA_UEINTX_FIFOCON (1 << 7) 104 105#define ATMEGA_UDMFN 0xE6 106#define ATMEGA_UDMFN_FNCERR (1 << 4) 107 108#define ATMEGA_UDFNUMH 0xE5 /* frame number high */ 109#define ATMEGA_UDFNUMH_MASK 7 110 111#define ATMEGA_UDFNUML 0xE4 /* frame number low */ 112#define ATMEGA_UDFNUML_MASK 0xFF 113 114#define ATMEGA_FRAME_MASK 0x7FF 115 116#define ATMEGA_UDADDR 0xE3 /* USB address */ 117#define ATMEGA_UDADDR_MASK 0x7F 118#define ATMEGA_UDADDR_ADDEN (1 << 7) 119 120#define ATMEGA_UDIEN 0xE2 /* USB device interrupt enable */ 121#define ATMEGA_UDINT_SUSPE (1 << 0) 122#define ATMEGA_UDINT_MSOFE (1 << 1) 123#define ATMEGA_UDINT_SOFE (1 << 2) 124#define ATMEGA_UDINT_EORSTE (1 << 3) 125#define ATMEGA_UDINT_WAKEUPE (1 << 4) 126#define ATMEGA_UDINT_EORSME (1 << 5) 127#define ATMEGA_UDINT_UPRSME (1 << 6) 128 129#define ATMEGA_UDINT 0xE1 /* USB device interrupt status */ 130#define ATMEGA_UDINT_SUSPI (1 << 0) 131#define ATMEGA_UDINT_MSOFI (1 << 1) 132#define ATMEGA_UDINT_SOFI (1 << 2) 133#define ATMEGA_UDINT_EORSTI (1 << 3) 134#define ATMEGA_UDINT_WAKEUPI (1 << 4) 135#define ATMEGA_UDINT_EORSMI (1 << 5) 136#define ATMEGA_UDINT_UPRSMI (1 << 6) 137 138#define ATMEGA_UDCON 0xE0 /* USB device connection register */ 139#define ATMEGA_UDCON_DETACH (1 << 0) 140#define ATMEGA_UDCON_RMWKUP (1 << 1) 141#define ATMEGA_UDCON_LSM (1 << 2) 142#define ATMEGA_UDCON_RSTCPU (1 << 3) 143 144#define ATMEGA_OTGINT 0xDF 145 146#define ATMEGA_OTGCON 0xDD 147#define ATMEGA_OTGCON_VBUSRQC (1 << 0) 148#define ATMEGA_OTGCON_VBUSREQ (1 << 1) 149#define ATMEGA_OTGCON_VBUSHWC (1 << 2) 150#define ATMEGA_OTGCON_SRPSEL (1 << 3) 151#define ATMEGA_OTGCON_SRPREQ (1 << 4) 152#define ATMEGA_OTGCON_HNPREQ (1 << 5) 153 154#define ATMEGA_USBINT 0xDA 155#define ATMEGA_USBINT_VBUSTI (1 << 0) /* USB VBUS interrupt */ 156#define ATMEGA_USBINT_IDI (1 << 1) /* USB ID interrupt */ 157 158#define ATMEGA_USBSTA 0xD9 159#define ATMEGA_USBSTA_VBUS (1 << 0) 160#define ATMEGA_USBSTA_ID (1 << 1) 161 162#define ATMEGA_USBCON 0xD8 163#define ATMEGA_USBCON_VBUSTE (1 << 0) 164#define ATMEGA_USBCON_IDE (1 << 1) 165#define ATMEGA_USBCON_OTGPADE (1 << 4) 166#define ATMEGA_USBCON_FRZCLK (1 << 5) 167#define ATMEGA_USBCON_USBE (1 << 7) 168 169#define ATMEGA_UHWCON 0xD7 170#define ATMEGA_UHWCON_UVREGE (1 << 0) 171#define ATMEGA_UHWCON_UVCONE (1 << 4) 172#define ATMEGA_UHWCON_UIDE (1 << 6) 173#define ATMEGA_UHWCON_UIMOD (1 << 7) 174 175#define ATMEGA_READ_1(sc, reg) \ 176 bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg) 177 178#define ATMEGA_WRITE_1(sc, reg, data) \ 179 bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) 180 181#define ATMEGA_WRITE_MULTI_1(sc, reg, ptr, len) \ 182 bus_space_write_multi_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len) 183 184#define ATMEGA_READ_MULTI_1(sc, reg, ptr, len) \ 185 bus_space_read_multi_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len) 186 187/* 188 * Maximum number of endpoints supported: 189 */ 190#define ATMEGA_EP_MAX 7 191 192struct atmegadci_td; 193 194typedef uint8_t (atmegadci_cmd_t)(struct atmegadci_td *td); 195typedef void (atmegadci_clocks_t)(struct usb_bus *); 196 197struct atmegadci_td { 198 struct atmegadci_td *obj_next; 199 atmegadci_cmd_t *func; 200 struct usb_page_cache *pc; 201 uint32_t offset; 202 uint32_t remainder; 203 uint16_t max_packet_size; 204 uint8_t error:1; 205 uint8_t alt_next:1; 206 uint8_t short_pkt:1; 207 uint8_t support_multi_buffer:1; 208 uint8_t did_stall:1; 209 uint8_t ep_no:3; 210}; 211 212struct atmegadci_std_temp { 213 atmegadci_cmd_t *func; 214 struct usb_page_cache *pc; 215 struct atmegadci_td *td; 216 struct atmegadci_td *td_next; 217 uint32_t len; 218 uint32_t offset; 219 uint16_t max_frame_size; 220 uint8_t short_pkt; 221 /* 222 * short_pkt = 0: transfer should be short terminated 223 * short_pkt = 1: transfer should not be short terminated 224 */ 225 uint8_t setup_alt_next; 226 uint8_t did_stall; 227}; 228 229struct atmegadci_config_desc { 230 struct usb_config_descriptor confd; 231 struct usb_interface_descriptor ifcd; 232 struct usb_endpoint_descriptor endpd; 233} __packed; 234 235union atmegadci_hub_temp { 236 uWord wValue; 237 struct usb_port_status ps; 238}; 239 240struct atmegadci_flags { 241 uint8_t change_connect:1; 242 uint8_t change_suspend:1; 243 uint8_t status_suspend:1; /* set if suspended */ 244 uint8_t status_vbus:1; /* set if present */ 245 uint8_t status_bus_reset:1; /* set if reset complete */ 246 uint8_t remote_wakeup:1; 247 uint8_t self_powered:1; 248 uint8_t clocks_off:1; 249 uint8_t port_powered:1; 250 uint8_t port_enabled:1; 251 uint8_t d_pulled_up:1; 252}; 253 254struct atmegadci_softc { 255 struct usb_bus sc_bus; 256 union atmegadci_hub_temp sc_hub_temp; 257 258 /* must be set by by the bus interface layer */ 259 atmegadci_clocks_t *sc_clocks_on; 260 atmegadci_clocks_t *sc_clocks_off; 261 262 struct usb_device *sc_devices[ATMEGA_MAX_DEVICES]; 263 struct resource *sc_irq_res; 264 void *sc_intr_hdl; 265 struct resource *sc_io_res; 266 bus_space_tag_t sc_io_tag; 267 bus_space_handle_t sc_io_hdl; 268 269 uint8_t sc_rt_addr; /* root hub address */ 270 uint8_t sc_dv_addr; /* device address */ 271 uint8_t sc_conf; /* root hub config */ 272 273 uint8_t sc_hub_idata[1]; 274 275 struct atmegadci_flags sc_flags; 276}; 277 278/* prototypes */ 279 280usb_error_t atmegadci_init(struct atmegadci_softc *sc); 281void atmegadci_uninit(struct atmegadci_softc *sc); 282void atmegadci_interrupt(struct atmegadci_softc *sc); 283 284#endif /* _ATMEGADCI_H_ */ 285