1/*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Device driver optimized for the Symbios/LSI 53C896/53C895A/53C1010 5 * PCI-SCSI controllers. 6 * 7 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr> 8 * 9 * This driver also supports the following Symbios/LSI PCI-SCSI chips: 10 * 53C810A, 53C825A, 53C860, 53C875, 53C876, 53C885, 53C895, 11 * 53C810, 53C815, 53C825 and the 53C1510D is 53C8XX mode. 12 * 13 * 14 * This driver for FreeBSD-CAM is derived from the Linux sym53c8xx driver. 15 * Copyright (C) 1998-1999 Gerard Roudier 16 * 17 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been 18 * a port of the FreeBSD ncr driver to Linux-1.2.13. 19 * 20 * The original ncr driver has been written for 386bsd and FreeBSD by 21 * Wolfgang Stanglmeier <wolf@cologne.de> 22 * Stefan Esser <se@mi.Uni-Koeln.de> 23 * Copyright (C) 1994 Wolfgang Stanglmeier 24 * 25 * The initialisation code, and part of the code that addresses 26 * FreeBSD-CAM services is based on the aic7xxx driver for FreeBSD-CAM 27 * written by Justin T. Gibbs. 28 * 29 * Other major contributions: 30 * 31 * NVRAM detection and reading. 32 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk> 33 * 34 *----------------------------------------------------------------------------- 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 48 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 49 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 50 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 51 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 52 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 53 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 55 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 56 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 57 * SUCH DAMAGE. 58 */ 59 60 61/* 62 * Scripts for SYMBIOS-Processor 63 * 64 * We have to know the offsets of all labels before we reach 65 * them (for forward jumps). Therefore we declare a struct 66 * here. If you make changes inside the script, 67 * 68 * DONT FORGET TO CHANGE THE LENGTHS HERE! 69 */ 70 71/* 72 * Script fragments which are loaded into the on-chip RAM 73 * of 825A, 875, 876, 895, 895A, 896 and 1010 chips. 74 * Must not exceed 4K bytes. 75 */ 76struct SYM_FWA_SCR { 77 u32 start [ 11]; 78 u32 getjob_begin [ 4]; 79 u32 _sms_a10 [ 5]; 80 u32 getjob_end [ 4]; 81 u32 _sms_a20 [ 4]; 82 u32 select [ 8]; 83 u32 _sms_a30 [ 8]; 84 u32 wf_sel_done [ 2]; 85 u32 send_ident [ 2]; 86#ifdef SYM_CONF_IARB_SUPPORT 87 u32 select2 [ 8]; 88#else 89 u32 select2 [ 2]; 90#endif 91 u32 command [ 2]; 92 u32 dispatch [ 28]; 93 u32 sel_no_cmd [ 10]; 94 u32 init [ 6]; 95 u32 clrack [ 4]; 96 u32 disp_status [ 4]; 97 u32 datai_done [ 26]; 98 u32 datao_done [ 12]; 99 u32 datai_phase [ 2]; 100 u32 datao_phase [ 2]; 101 u32 msg_in [ 2]; 102 u32 msg_in2 [ 10]; 103#ifdef SYM_CONF_IARB_SUPPORT 104 u32 status [ 14]; 105#else 106 u32 status [ 10]; 107#endif 108 u32 complete [ 9]; 109 u32 complete2 [ 8]; 110 u32 _sms_a40 [ 12]; 111 u32 complete_error [ 5]; 112 u32 done [ 5]; 113 u32 _sms_a50 [ 5]; 114 u32 _sms_a60 [ 2]; 115 u32 done_end [ 4]; 116 u32 save_dp [ 9]; 117 u32 restore_dp [ 5]; 118 u32 disconnect [ 20]; 119 u32 disconnect2 [ 5]; 120 u32 _sms_a65 [ 3]; 121#ifdef SYM_CONF_IARB_SUPPORT 122 u32 idle [ 4]; 123#else 124 u32 idle [ 2]; 125#endif 126#ifdef SYM_CONF_IARB_SUPPORT 127 u32 ungetjob [ 7]; 128#else 129 u32 ungetjob [ 5]; 130#endif 131 u32 reselect [ 4]; 132 u32 reselected [ 19]; 133 u32 _sms_a70 [ 6]; 134 u32 _sms_a80 [ 4]; 135 u32 reselected1 [ 25]; 136 u32 _sms_a90 [ 4]; 137 u32 resel_lun0 [ 7]; 138 u32 _sms_a100 [ 4]; 139 u32 resel_tag [ 8]; 140#if SYM_CONF_MAX_TASK*4 > 512 141 u32 _sms_a110 [ 23]; 142#elif SYM_CONF_MAX_TASK*4 > 256 143 u32 _sms_a110 [ 17]; 144#else 145 u32 _sms_a110 [ 13]; 146#endif 147 u32 _sms_a120 [ 2]; 148 u32 resel_go [ 4]; 149 u32 _sms_a130 [ 7]; 150 u32 resel_dsa [ 2]; 151 u32 resel_dsa1 [ 4]; 152 u32 _sms_a140 [ 10]; 153 u32 resel_no_tag [ 4]; 154 u32 _sms_a145 [ 7]; 155 u32 data_in [SYM_CONF_MAX_SG * 2]; 156 u32 data_in2 [ 4]; 157 u32 data_out [SYM_CONF_MAX_SG * 2]; 158 u32 data_out2 [ 4]; 159 u32 pm0_data [ 12]; 160 u32 pm0_data_out [ 6]; 161 u32 pm0_data_end [ 7]; 162 u32 pm_data_end [ 4]; 163 u32 _sms_a150 [ 4]; 164 u32 pm1_data [ 12]; 165 u32 pm1_data_out [ 6]; 166 u32 pm1_data_end [ 9]; 167}; 168 169/* 170 * Script fragments which stay in main memory for all chips 171 * except for chips that support 8K on-chip RAM. 172 */ 173struct SYM_FWB_SCR { 174 u32 no_data [ 2]; 175 u32 sel_for_abort [ 18]; 176 u32 sel_for_abort_1 [ 2]; 177 u32 msg_in_etc [ 12]; 178 u32 msg_received [ 5]; 179 u32 msg_weird_seen [ 5]; 180 u32 msg_extended [ 17]; 181 u32 _sms_b10 [ 4]; 182 u32 msg_bad [ 6]; 183 u32 msg_weird [ 4]; 184 u32 msg_weird1 [ 8]; 185 u32 wdtr_resp [ 6]; 186 u32 send_wdtr [ 4]; 187 u32 sdtr_resp [ 6]; 188 u32 send_sdtr [ 4]; 189 u32 ppr_resp [ 6]; 190 u32 send_ppr [ 4]; 191 u32 nego_bad_phase [ 4]; 192 u32 msg_out [ 4]; 193 u32 msg_out_done [ 4]; 194 u32 data_ovrun [ 3]; 195 u32 data_ovrun1 [ 22]; 196 u32 data_ovrun2 [ 8]; 197 u32 abort_resel [ 16]; 198 u32 resend_ident [ 4]; 199 u32 ident_break [ 4]; 200 u32 ident_break_atn [ 4]; 201 u32 sdata_in [ 6]; 202 u32 resel_bad_lun [ 4]; 203 u32 bad_i_t_l [ 4]; 204 u32 bad_i_t_l_q [ 4]; 205 u32 bad_status [ 7]; 206 u32 wsr_ma_helper [ 4]; 207 208 /* Data area */ 209 u32 zero [ 1]; 210 u32 scratch [ 1]; 211 u32 scratch1 [ 1]; 212 u32 prev_done [ 1]; 213 u32 done_pos [ 1]; 214 u32 nextjob [ 1]; 215 u32 startpos [ 1]; 216 u32 targtbl [ 1]; 217 /* End of data area */ 218 219 u32 snooptest [ 9]; 220 u32 snoopend [ 2]; 221}; 222 223static const struct SYM_FWA_SCR SYM_FWA_SCR = { 224/*--------------------------< START >----------------------------*/ { 225 /* 226 * Switch the LED on. 227 * Will be patched with a NO_OP if LED 228 * not needed or not desired. 229 */ 230 SCR_REG_REG (gpreg, SCR_AND, 0xfe), 231 0, 232 /* 233 * Clear SIGP. 234 */ 235 SCR_FROM_REG (ctest2), 236 0, 237 /* 238 * Stop here if the C code wants to perform 239 * some error recovery procedure manually. 240 * (Indicate this by setting SEM in ISTAT) 241 */ 242 SCR_FROM_REG (istat), 243 0, 244 /* 245 * Report to the C code the next position in 246 * the start queue the SCRIPTS will schedule. 247 * The C code must not change SCRATCHA. 248 */ 249 SCR_COPY (4), 250 PADDR_B (startpos), 251 RADDR_1 (scratcha), 252 SCR_INT ^ IFTRUE (MASK (SEM, SEM)), 253 SIR_SCRIPT_STOPPED, 254 /* 255 * Start the next job. 256 * 257 * @DSA = start point for this job. 258 * SCRATCHA = address of this job in the start queue. 259 * 260 * We will restore startpos with SCRATCHA if we fails the 261 * arbitration or if it is the idle job. 262 * 263 * The below GETJOB_BEGIN to GETJOB_END section of SCRIPTS 264 * is a critical path. If it is partially executed, it then 265 * may happen that the job address is not yet in the DSA 266 * and the next queue position points to the next JOB. 267 */ 268}/*-------------------------< GETJOB_BEGIN >---------------------*/,{ 269 /* 270 * Copy to a fixed location both the next STARTPOS 271 * and the current JOB address, using self modifying 272 * SCRIPTS. 273 */ 274 SCR_COPY (4), 275 RADDR_1 (scratcha), 276 PADDR_A (_sms_a10), 277 SCR_COPY (8), 278}/*-------------------------< _SMS_A10 >-------------------------*/,{ 279 0, 280 PADDR_B (nextjob), 281 /* 282 * Move the start address to TEMP using self- 283 * modifying SCRIPTS and jump indirectly to 284 * that address. 285 */ 286 SCR_COPY (4), 287 PADDR_B (nextjob), 288 RADDR_1 (dsa), 289}/*-------------------------< GETJOB_END >-----------------------*/,{ 290 SCR_COPY (4), 291 RADDR_1 (dsa), 292 PADDR_A (_sms_a20), 293 SCR_COPY (4), 294}/*-------------------------< _SMS_A20 >-------------------------*/,{ 295 0, 296 RADDR_1 (temp), 297 SCR_RETURN, 298 0, 299}/*-------------------------< SELECT >---------------------------*/,{ 300 /* 301 * DSA contains the address of a scheduled 302 * data structure. 303 * 304 * SCRATCHA contains the address of the start queue 305 * entry which points to the next job. 306 * 307 * Set Initiator mode. 308 * 309 * (Target mode is left as an exercise for the reader) 310 */ 311 SCR_CLR (SCR_TRG), 312 0, 313 /* 314 * And try to select this target. 315 */ 316 SCR_SEL_TBL_ATN ^ offsetof (struct sym_dsb, select), 317 PADDR_A (ungetjob), 318 /* 319 * Now there are 4 possibilities: 320 * 321 * (1) The chip loses arbitration. 322 * This is ok, because it will try again, 323 * when the bus becomes idle. 324 * (But beware of the timeout function!) 325 * 326 * (2) The chip is reselected. 327 * Then the script processor takes the jump 328 * to the RESELECT label. 329 * 330 * (3) The chip wins arbitration. 331 * Then it will execute SCRIPTS instruction until 332 * the next instruction that checks SCSI phase. 333 * Then will stop and wait for selection to be 334 * complete or selection time-out to occur. 335 * 336 * After having won arbitration, the SCRIPTS 337 * processor is able to execute instructions while 338 * the SCSI core is performing SCSI selection. 339 */ 340 341 /* 342 * Copy the CCB header to a fixed location 343 * in the HCB using self-modifying SCRIPTS. 344 */ 345 SCR_COPY (4), 346 RADDR_1 (dsa), 347 PADDR_A (_sms_a30), 348 SCR_COPY (sizeof(struct sym_ccbh)), 349}/*-------------------------< _SMS_A30 >-------------------------*/,{ 350 0, 351 HADDR_1 (ccb_head), 352 /* 353 * Load the savep (saved data pointer) into 354 * the actual data pointer. 355 */ 356 SCR_COPY (4), 357 HADDR_1 (ccb_head.savep), 358 RADDR_1 (temp), 359 /* 360 * Initialize the status register 361 */ 362 SCR_COPY (4), 363 HADDR_1 (ccb_head.status), 364 RADDR_1 (scr0), 365}/*-------------------------< WF_SEL_DONE >----------------------*/,{ 366 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)), 367 SIR_SEL_ATN_NO_MSG_OUT, 368}/*-------------------------< SEND_IDENT >-----------------------*/,{ 369 /* 370 * Selection complete. 371 * Send the IDENTIFY and possibly the TAG message 372 * and negotiation message if present. 373 */ 374 SCR_MOVE_TBL ^ SCR_MSG_OUT, 375 offsetof (struct sym_dsb, smsg), 376}/*-------------------------< SELECT2 >--------------------------*/,{ 377#ifdef SYM_CONF_IARB_SUPPORT 378 /* 379 * Set IMMEDIATE ARBITRATION if we have been given 380 * a hint to do so. (Some job to do after this one). 381 */ 382 SCR_FROM_REG (HF_REG), 383 0, 384 SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)), 385 8, 386 SCR_REG_REG (scntl1, SCR_OR, IARB), 387 0, 388#endif 389 /* 390 * Anticipate the COMMAND phase. 391 * This is the PHASE we expect at this point. 392 */ 393 SCR_JUMP ^ IFFALSE (WHEN (SCR_COMMAND)), 394 PADDR_A (sel_no_cmd), 395}/*-------------------------< COMMAND >--------------------------*/,{ 396 /* 397 * ... and send the command 398 */ 399 SCR_MOVE_TBL ^ SCR_COMMAND, 400 offsetof (struct sym_dsb, cmd), 401}/*-------------------------< DISPATCH >-------------------------*/,{ 402 /* 403 * MSG_IN is the only phase that shall be 404 * entered at least once for each (re)selection. 405 * So we test it first. 406 */ 407 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 408 PADDR_A (msg_in), 409 SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT)), 410 PADDR_A (datao_phase), 411 SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN)), 412 PADDR_A (datai_phase), 413 SCR_JUMP ^ IFTRUE (IF (SCR_STATUS)), 414 PADDR_A (status), 415 SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND)), 416 PADDR_A (command), 417 SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT)), 418 PADDR_B (msg_out), 419 /* 420 * Discard as many illegal phases as 421 * required and tell the C code about. 422 */ 423 SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_OUT)), 424 16, 425 SCR_MOVE_ABS (1) ^ SCR_ILG_OUT, 426 HADDR_1 (scratch), 427 SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_OUT)), 428 -16, 429 SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_IN)), 430 16, 431 SCR_MOVE_ABS (1) ^ SCR_ILG_IN, 432 HADDR_1 (scratch), 433 SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_IN)), 434 -16, 435 SCR_INT, 436 SIR_BAD_PHASE, 437 SCR_JUMP, 438 PADDR_A (dispatch), 439}/*-------------------------< SEL_NO_CMD >-----------------------*/,{ 440 /* 441 * The target does not switch to command 442 * phase after IDENTIFY has been sent. 443 * 444 * If it stays in MSG OUT phase send it 445 * the IDENTIFY again. 446 */ 447 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)), 448 PADDR_B (resend_ident), 449 /* 450 * If target does not switch to MSG IN phase 451 * and we sent a negotiation, assert the 452 * failure immediately. 453 */ 454 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 455 PADDR_A (dispatch), 456 SCR_FROM_REG (HS_REG), 457 0, 458 SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)), 459 SIR_NEGO_FAILED, 460 /* 461 * Jump to dispatcher. 462 */ 463 SCR_JUMP, 464 PADDR_A (dispatch), 465}/*-------------------------< INIT >-----------------------------*/,{ 466 /* 467 * Wait for the SCSI RESET signal to be 468 * inactive before restarting operations, 469 * since the chip may hang on SEL_ATN 470 * if SCSI RESET is active. 471 */ 472 SCR_FROM_REG (sstat0), 473 0, 474 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)), 475 -16, 476 SCR_JUMP, 477 PADDR_A (start), 478}/*-------------------------< CLRACK >---------------------------*/,{ 479 /* 480 * Terminate possible pending message phase. 481 */ 482 SCR_CLR (SCR_ACK), 483 0, 484 SCR_JUMP, 485 PADDR_A (dispatch), 486}/*-------------------------< DISP_STATUS >----------------------*/,{ 487 /* 488 * Anticipate STATUS phase. 489 * 490 * Does spare 3 SCRIPTS instructions when we have 491 * completed the INPUT of the data. 492 */ 493 SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)), 494 PADDR_A (status), 495 SCR_JUMP, 496 PADDR_A (dispatch), 497}/*-------------------------< DATAI_DONE >-----------------------*/,{ 498 /* 499 * If the device still wants to send us data, 500 * we must count the extra bytes. 501 */ 502 SCR_JUMP ^ IFTRUE (WHEN (SCR_DATA_IN)), 503 PADDR_B (data_ovrun), 504 /* 505 * If the SWIDE is not full, jump to dispatcher. 506 * We anticipate a STATUS phase. 507 */ 508 SCR_FROM_REG (scntl2), 509 0, 510 SCR_JUMP ^ IFFALSE (MASK (WSR, WSR)), 511 PADDR_A (disp_status), 512 /* 513 * The SWIDE is full. 514 * Clear this condition. 515 */ 516 SCR_REG_REG (scntl2, SCR_OR, WSR), 517 0, 518 /* 519 * We are expecting an IGNORE RESIDUE message 520 * from the device, otherwise we are in data 521 * overrun condition. Check against MSG_IN phase. 522 */ 523 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)), 524 SIR_SWIDE_OVERRUN, 525 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 526 PADDR_A (disp_status), 527 /* 528 * We are in MSG_IN phase, 529 * Read the first byte of the message. 530 * If it is not an IGNORE RESIDUE message, 531 * signal overrun and jump to message 532 * processing. 533 */ 534 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 535 HADDR_1 (msgin[0]), 536 SCR_INT ^ IFFALSE (DATA (M_IGN_RESIDUE)), 537 SIR_SWIDE_OVERRUN, 538 SCR_JUMP ^ IFFALSE (DATA (M_IGN_RESIDUE)), 539 PADDR_A (msg_in2), 540 /* 541 * We got the message we expected. 542 * Read the 2nd byte, and jump to dispatcher. 543 */ 544 SCR_CLR (SCR_ACK), 545 0, 546 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 547 HADDR_1 (msgin[1]), 548 SCR_CLR (SCR_ACK), 549 0, 550 SCR_JUMP, 551 PADDR_A (disp_status), 552}/*-------------------------< DATAO_DONE >-----------------------*/,{ 553 /* 554 * If the device wants us to send more data, 555 * we must count the extra bytes. 556 */ 557 SCR_JUMP ^ IFTRUE (WHEN (SCR_DATA_OUT)), 558 PADDR_B (data_ovrun), 559 /* 560 * If the SODL is not full jump to dispatcher. 561 * We anticipate a STATUS phase. 562 */ 563 SCR_FROM_REG (scntl2), 564 0, 565 SCR_JUMP ^ IFFALSE (MASK (WSS, WSS)), 566 PADDR_A (disp_status), 567 /* 568 * The SODL is full, clear this condition. 569 */ 570 SCR_REG_REG (scntl2, SCR_OR, WSS), 571 0, 572 /* 573 * And signal a DATA UNDERRUN condition 574 * to the C code. 575 */ 576 SCR_INT, 577 SIR_SODL_UNDERRUN, 578 SCR_JUMP, 579 PADDR_A (dispatch), 580}/*-------------------------< DATAI_PHASE >----------------------*/,{ 581 SCR_RETURN, 582 0, 583}/*-------------------------< DATAO_PHASE >----------------------*/,{ 584 SCR_RETURN, 585 0, 586}/*-------------------------< MSG_IN >---------------------------*/,{ 587 /* 588 * Get the first byte of the message. 589 * 590 * The script processor doesn't negate the 591 * ACK signal after this transfer. 592 */ 593 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 594 HADDR_1 (msgin[0]), 595}/*-------------------------< MSG_IN2 >--------------------------*/,{ 596 /* 597 * Check first against 1 byte messages 598 * that we handle from SCRIPTS. 599 */ 600 SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE)), 601 PADDR_A (complete), 602 SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT)), 603 PADDR_A (disconnect), 604 SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP)), 605 PADDR_A (save_dp), 606 SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP)), 607 PADDR_A (restore_dp), 608 /* 609 * We handle all other messages from the 610 * C code, so no need to waste on-chip RAM 611 * for those ones. 612 */ 613 SCR_JUMP, 614 PADDR_B (msg_in_etc), 615}/*-------------------------< STATUS >---------------------------*/,{ 616 /* 617 * get the status 618 */ 619 SCR_MOVE_ABS (1) ^ SCR_STATUS, 620 HADDR_1 (scratch), 621#ifdef SYM_CONF_IARB_SUPPORT 622 /* 623 * If STATUS is not GOOD, clear IMMEDIATE ARBITRATION, 624 * since we may have to tamper the start queue from 625 * the C code. 626 */ 627 SCR_JUMPR ^ IFTRUE (DATA (S_GOOD)), 628 8, 629 SCR_REG_REG (scntl1, SCR_AND, ~IARB), 630 0, 631#endif 632 /* 633 * save status to scsi_status. 634 * mark as complete. 635 */ 636 SCR_TO_REG (SS_REG), 637 0, 638 SCR_LOAD_REG (HS_REG, HS_COMPLETE), 639 0, 640 /* 641 * Anticipate the MESSAGE PHASE for 642 * the TASK COMPLETE message. 643 */ 644 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 645 PADDR_A (msg_in), 646 SCR_JUMP, 647 PADDR_A (dispatch), 648}/*-------------------------< COMPLETE >-------------------------*/,{ 649 /* 650 * Complete message. 651 * 652 * Copy the data pointer to LASTP. 653 */ 654 SCR_COPY (4), 655 RADDR_1 (temp), 656 HADDR_1 (ccb_head.lastp), 657 /* 658 * When we terminate the cycle by clearing ACK, 659 * the target may disconnect immediately. 660 * 661 * We don't want to be told of an "unexpected disconnect", 662 * so we disable this feature. 663 */ 664 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 665 0, 666 /* 667 * Terminate cycle ... 668 */ 669 SCR_CLR (SCR_ACK|SCR_ATN), 670 0, 671 /* 672 * ... and wait for the disconnect. 673 */ 674 SCR_WAIT_DISC, 675 0, 676}/*-------------------------< COMPLETE2 >------------------------*/,{ 677 /* 678 * Save host status. 679 */ 680 SCR_COPY (4), 681 RADDR_1 (scr0), 682 HADDR_1 (ccb_head.status), 683 /* 684 * Move back the CCB header using self-modifying 685 * SCRIPTS. 686 */ 687 SCR_COPY (4), 688 RADDR_1 (dsa), 689 PADDR_A (_sms_a40), 690 SCR_COPY (sizeof(struct sym_ccbh)), 691 HADDR_1 (ccb_head), 692}/*-------------------------< _SMS_A40 >-------------------------*/,{ 693 0, 694 /* 695 * Some bridges may reorder DMA writes to memory. 696 * We donnot want the CPU to deal with completions 697 * without all the posted write having been flushed 698 * to memory. This DUMMY READ should flush posted 699 * buffers prior to the CPU having to deal with 700 * completions. 701 */ 702 SCR_COPY (4), /* DUMMY READ */ 703 HADDR_1 (ccb_head.status), 704 RADDR_1 (scr0), 705 /* 706 * If command resulted in not GOOD status, 707 * call the C code if needed. 708 */ 709 SCR_FROM_REG (SS_REG), 710 0, 711 SCR_CALL ^ IFFALSE (DATA (S_GOOD)), 712 PADDR_B (bad_status), 713 /* 714 * If we performed an auto-sense, call 715 * the C code to synchronyze task aborts 716 * with UNIT ATTENTION conditions. 717 */ 718 SCR_FROM_REG (HF_REG), 719 0, 720 SCR_JUMP ^ IFTRUE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))), 721 PADDR_A (done), 722}/*-------------------------< COMPLETE_ERROR >-------------------*/,{ 723 SCR_COPY (4), 724 PADDR_B (startpos), 725 RADDR_1 (scratcha), 726 SCR_INT, 727 SIR_COMPLETE_ERROR, 728}/*-------------------------< DONE >-----------------------------*/,{ 729 /* 730 * Copy the DSA to the DONE QUEUE and 731 * signal completion to the host. 732 * If we are interrupted between DONE 733 * and DONE_END, we must reset, otherwise 734 * the completed CCB may be lost. 735 */ 736 SCR_COPY (4), 737 PADDR_B (done_pos), 738 PADDR_A (_sms_a50), 739 SCR_COPY (4), 740 RADDR_1 (dsa), 741}/*-------------------------< _SMS_A50 >-------------------------*/,{ 742 0, 743 SCR_COPY (4), 744 PADDR_B (done_pos), 745 PADDR_A (_sms_a60), 746 /* 747 * The instruction below reads the DONE QUEUE next 748 * free position from memory. 749 * In addition it ensures that all PCI posted writes 750 * are flushed and so the DSA value of the done 751 * CCB is visible by the CPU before INTFLY is raised. 752 */ 753 SCR_COPY (8), 754}/*-------------------------< _SMS_A60 >-------------------------*/,{ 755 0, 756 PADDR_B (prev_done), 757}/*-------------------------< DONE_END >-------------------------*/,{ 758 SCR_INT_FLY, 759 0, 760 SCR_JUMP, 761 PADDR_A (start), 762}/*-------------------------< SAVE_DP >--------------------------*/,{ 763 /* 764 * Clear ACK immediately. 765 * No need to delay it. 766 */ 767 SCR_CLR (SCR_ACK), 768 0, 769 /* 770 * Keep track we received a SAVE DP, so 771 * we will switch to the other PM context 772 * on the next PM since the DP may point 773 * to the current PM context. 774 */ 775 SCR_REG_REG (HF_REG, SCR_OR, HF_DP_SAVED), 776 0, 777 /* 778 * SAVE_DP message: 779 * Copy the data pointer to SAVEP. 780 */ 781 SCR_COPY (4), 782 RADDR_1 (temp), 783 HADDR_1 (ccb_head.savep), 784 SCR_JUMP, 785 PADDR_A (dispatch), 786}/*-------------------------< RESTORE_DP >-----------------------*/,{ 787 /* 788 * RESTORE_DP message: 789 * Copy SAVEP to actual data pointer. 790 */ 791 SCR_COPY (4), 792 HADDR_1 (ccb_head.savep), 793 RADDR_1 (temp), 794 SCR_JUMP, 795 PADDR_A (clrack), 796}/*-------------------------< DISCONNECT >-----------------------*/,{ 797 /* 798 * DISCONNECTing ... 799 * 800 * disable the "unexpected disconnect" feature, 801 * and remove the ACK signal. 802 */ 803 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 804 0, 805 SCR_CLR (SCR_ACK|SCR_ATN), 806 0, 807 /* 808 * Wait for the disconnect. 809 */ 810 SCR_WAIT_DISC, 811 0, 812 /* 813 * Status is: DISCONNECTED. 814 */ 815 SCR_LOAD_REG (HS_REG, HS_DISCONNECT), 816 0, 817 /* 818 * Save host status. 819 */ 820 SCR_COPY (4), 821 RADDR_1 (scr0), 822 HADDR_1 (ccb_head.status), 823 /* 824 * If QUIRK_AUTOSAVE is set, 825 * do a "save pointer" operation. 826 */ 827 SCR_FROM_REG (QU_REG), 828 0, 829 SCR_JUMP ^ IFFALSE (MASK (SYM_QUIRK_AUTOSAVE, SYM_QUIRK_AUTOSAVE)), 830 PADDR_A (disconnect2), 831 /* 832 * like SAVE_DP message: 833 * Remember we saved the data pointer. 834 * Copy data pointer to SAVEP. 835 */ 836 SCR_REG_REG (HF_REG, SCR_OR, HF_DP_SAVED), 837 0, 838 SCR_COPY (4), 839 RADDR_1 (temp), 840 HADDR_1 (ccb_head.savep), 841}/*-------------------------< DISCONNECT2 >----------------------*/,{ 842 /* 843 * Move back the CCB header using self-modifying 844 * SCRIPTS. 845 */ 846 SCR_COPY (4), 847 RADDR_1 (dsa), 848 PADDR_A (_sms_a65), 849 SCR_COPY (sizeof(struct sym_ccbh)), 850 HADDR_1 (ccb_head), 851}/*-------------------------< _SMS_A65 >-------------------------*/,{ 852 0, 853 SCR_JUMP, 854 PADDR_A (start), 855}/*-------------------------< IDLE >-----------------------------*/,{ 856 /* 857 * Nothing to do? 858 * Switch the LED off and wait for reselect. 859 * Will be patched with a NO_OP if LED 860 * not needed or not desired. 861 */ 862 SCR_REG_REG (gpreg, SCR_OR, 0x01), 863 0, 864#ifdef SYM_CONF_IARB_SUPPORT 865 SCR_JUMPR, 866 8, 867#endif 868}/*-------------------------< UNGETJOB >-------------------------*/,{ 869#ifdef SYM_CONF_IARB_SUPPORT 870 /* 871 * Set IMMEDIATE ARBITRATION, for the next time. 872 * This will give us better chance to win arbitration 873 * for the job we just wanted to do. 874 */ 875 SCR_REG_REG (scntl1, SCR_OR, IARB), 876 0, 877#endif 878 /* 879 * We are not able to restart the SCRIPTS if we are 880 * interrupted and these instruction haven't been 881 * all executed. BTW, this is very unlikely to 882 * happen, but we check that from the C code. 883 */ 884 SCR_LOAD_REG (dsa, 0xff), 885 0, 886 SCR_COPY (4), 887 RADDR_1 (scratcha), 888 PADDR_B (startpos), 889}/*-------------------------< RESELECT >-------------------------*/,{ 890 /* 891 * Make sure we are in initiator mode. 892 */ 893 SCR_CLR (SCR_TRG), 894 0, 895 /* 896 * Sleep waiting for a reselection. 897 */ 898 SCR_WAIT_RESEL, 899 PADDR_A(start), 900}/*-------------------------< RESELECTED >-----------------------*/,{ 901 /* 902 * Switch the LED on. 903 * Will be patched with a NO_OP if LED 904 * not needed or not desired. 905 */ 906 SCR_REG_REG (gpreg, SCR_AND, 0xfe), 907 0, 908 /* 909 * load the target id into the sdid 910 */ 911 SCR_REG_SFBR (ssid, SCR_AND, 0x8F), 912 0, 913 SCR_TO_REG (sdid), 914 0, 915 /* 916 * Load the target control block address 917 */ 918 SCR_COPY (4), 919 PADDR_B (targtbl), 920 RADDR_1 (dsa), 921 SCR_SFBR_REG (dsa, SCR_SHL, 0), 922 0, 923 SCR_REG_REG (dsa, SCR_SHL, 0), 924 0, 925 SCR_REG_REG (dsa, SCR_AND, 0x3c), 926 0, 927 SCR_COPY (4), 928 RADDR_1 (dsa), 929 PADDR_A (_sms_a70), 930 SCR_COPY (4), 931}/*-------------------------< _SMS_A70 >-------------------------*/,{ 932 0, 933 RADDR_1 (dsa), 934 /* 935 * Copy the TCB header to a fixed place in 936 * the HCB. 937 */ 938 SCR_COPY (4), 939 RADDR_1 (dsa), 940 PADDR_A (_sms_a80), 941 SCR_COPY (sizeof(struct sym_tcbh)), 942}/*-------------------------< _SMS_A80 >-------------------------*/,{ 943 0, 944 HADDR_1 (tcb_head), 945 /* 946 * We expect MESSAGE IN phase. 947 * If not, get help from the C code. 948 */ 949 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)), 950 SIR_RESEL_NO_MSG_IN, 951}/*-------------------------< RESELECTED1 >----------------------*/,{ 952 /* 953 * Load the synchronous transfer registers. 954 */ 955 SCR_COPY (1), 956 HADDR_1 (tcb_head.wval), 957 RADDR_1 (scntl3), 958 SCR_COPY (1), 959 HADDR_1 (tcb_head.sval), 960 RADDR_1 (sxfer), 961 /* 962 * Get the IDENTIFY message. 963 */ 964 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 965 HADDR_1 (msgin), 966 /* 967 * If IDENTIFY LUN #0, use a faster path 968 * to find the LCB structure. 969 */ 970 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)), 971 PADDR_A (resel_lun0), 972 /* 973 * If message isn't an IDENTIFY, 974 * tell the C code about. 975 */ 976 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)), 977 SIR_RESEL_NO_IDENTIFY, 978 /* 979 * It is an IDENTIFY message, 980 * Load the LUN control block address. 981 */ 982 SCR_COPY (4), 983 HADDR_1 (tcb_head.luntbl_sa), 984 RADDR_1 (dsa), 985 SCR_SFBR_REG (dsa, SCR_SHL, 0), 986 0, 987 SCR_REG_REG (dsa, SCR_SHL, 0), 988 0, 989 SCR_REG_REG (dsa, SCR_AND, 0xfc), 990 0, 991 SCR_COPY (4), 992 RADDR_1 (dsa), 993 PADDR_A (_sms_a90), 994 SCR_COPY (4), 995}/*-------------------------< _SMS_A90 >-------------------------*/,{ 996 0, 997 RADDR_1 (dsa), 998 SCR_JUMPR, 999 12, 1000}/*-------------------------< RESEL_LUN0 >-----------------------*/,{ 1001 /* 1002 * LUN 0 special case (but usual one :)) 1003 */ 1004 SCR_COPY (4), 1005 HADDR_1 (tcb_head.lun0_sa), 1006 RADDR_1 (dsa), 1007 /* 1008 * Jump indirectly to the reselect action for this LUN. 1009 * (lcb.head.resel_sa assumed at offset zero of lcb). 1010 */ 1011 SCR_COPY (4), 1012 RADDR_1 (dsa), 1013 PADDR_A (_sms_a100), 1014 SCR_COPY (4), 1015}/*-------------------------< _SMS_A100 >------------------------*/,{ 1016 0, 1017 RADDR_1 (temp), 1018 SCR_RETURN, 1019 0, 1020 /* In normal situations, we jump to RESEL_TAG or RESEL_NO_TAG */ 1021}/*-------------------------< RESEL_TAG >------------------------*/,{ 1022 /* 1023 * ACK the IDENTIFY previously received. 1024 */ 1025 SCR_CLR (SCR_ACK), 1026 0, 1027 /* 1028 * It shall be a tagged command. 1029 * Read SIMPLE+TAG. 1030 * The C code will deal with errors. 1031 * Aggressive optimization, isn't it? :) 1032 */ 1033 SCR_MOVE_ABS (2) ^ SCR_MSG_IN, 1034 HADDR_1 (msgin), 1035 /* 1036 * Copy the LCB header to a fixed place in 1037 * the HCB using self-modifying SCRIPTS. 1038 */ 1039 SCR_COPY (4), 1040 RADDR_1 (dsa), 1041 PADDR_A (_sms_a110), 1042 SCR_COPY (sizeof(struct sym_lcbh)), 1043}/*-------------------------< _SMS_A110 >------------------------*/,{ 1044 0, 1045 HADDR_1 (lcb_head), 1046 /* 1047 * Load the pointer to the tagged task 1048 * table for this LUN. 1049 */ 1050 SCR_COPY (4), 1051 HADDR_1 (lcb_head.itlq_tbl_sa), 1052 RADDR_1 (dsa), 1053 /* 1054 * The SIDL still contains the TAG value. 1055 * Aggressive optimization, isn't it? :):) 1056 */ 1057 SCR_REG_SFBR (sidl, SCR_SHL, 0), 1058 0, 1059#if SYM_CONF_MAX_TASK*4 > 512 1060 SCR_JUMPR ^ IFFALSE (CARRYSET), 1061 8, 1062 SCR_REG_REG (dsa1, SCR_OR, 2), 1063 0, 1064 SCR_REG_REG (sfbr, SCR_SHL, 0), 1065 0, 1066 SCR_JUMPR ^ IFFALSE (CARRYSET), 1067 8, 1068 SCR_REG_REG (dsa1, SCR_OR, 1), 1069 0, 1070#elif SYM_CONF_MAX_TASK*4 > 256 1071 SCR_JUMPR ^ IFFALSE (CARRYSET), 1072 8, 1073 SCR_REG_REG (dsa1, SCR_OR, 1), 1074 0, 1075#endif 1076 /* 1077 * Retrieve the DSA of this task. 1078 * JUMP indirectly to the restart point of the CCB. 1079 */ 1080 SCR_SFBR_REG (dsa, SCR_AND, 0xfc), 1081 0, 1082 SCR_COPY (4), 1083 RADDR_1 (dsa), 1084 PADDR_A (_sms_a120), 1085 SCR_COPY (4), 1086}/*-------------------------< _SMS_A120 >------------------------*/,{ 1087 0, 1088 RADDR_1 (dsa), 1089}/*-------------------------< RESEL_GO >-------------------------*/,{ 1090 SCR_COPY (4), 1091 RADDR_1 (dsa), 1092 PADDR_A (_sms_a130), 1093 /* 1094 * Move 'ccb.phys.head.go' action to 1095 * scratch/scratch1. So scratch1 will 1096 * contain the 'restart' field of the 1097 * 'go' structure. 1098 */ 1099 SCR_COPY (8), 1100}/*-------------------------< _SMS_A130 >------------------------*/,{ 1101 0, 1102 PADDR_B (scratch), 1103 SCR_COPY (4), 1104 PADDR_B (scratch1), /* phys.head.go.restart */ 1105 RADDR_1 (temp), 1106 SCR_RETURN, 1107 0, 1108 /* In normal situations we branch to RESEL_DSA */ 1109}/*-------------------------< RESEL_DSA >------------------------*/,{ 1110 /* 1111 * ACK the IDENTIFY or TAG previously received. 1112 */ 1113 SCR_CLR (SCR_ACK), 1114 0, 1115}/*-------------------------< RESEL_DSA1 >-----------------------*/,{ 1116 /* 1117 * Copy the CCB header to a fixed location 1118 * in the HCB using self-modifying SCRIPTS. 1119 */ 1120 SCR_COPY (4), 1121 RADDR_1 (dsa), 1122 PADDR_A (_sms_a140), 1123 SCR_COPY (sizeof(struct sym_ccbh)), 1124}/*-------------------------< _SMS_A140 >------------------------*/,{ 1125 0, 1126 HADDR_1 (ccb_head), 1127 /* 1128 * Load the savep (saved data pointer) into 1129 * the actual data pointer. 1130 */ 1131 SCR_COPY (4), 1132 HADDR_1 (ccb_head.savep), 1133 RADDR_1 (temp), 1134 /* 1135 * Initialize the status register 1136 */ 1137 SCR_COPY (4), 1138 HADDR_1 (ccb_head.status), 1139 RADDR_1 (scr0), 1140 /* 1141 * Jump to dispatcher. 1142 */ 1143 SCR_JUMP, 1144 PADDR_A (dispatch), 1145}/*-------------------------< RESEL_NO_TAG >---------------------*/,{ 1146 /* 1147 * Copy the LCB header to a fixed place in 1148 * the HCB using self-modifying SCRIPTS. 1149 */ 1150 SCR_COPY (4), 1151 RADDR_1 (dsa), 1152 PADDR_A (_sms_a145), 1153 SCR_COPY (sizeof(struct sym_lcbh)), 1154}/*-------------------------< _SMS_A145 >------------------------*/,{ 1155 0, 1156 HADDR_1 (lcb_head), 1157 /* 1158 * Load the DSA with the unique ITL task. 1159 */ 1160 SCR_COPY (4), 1161 HADDR_1 (lcb_head.itl_task_sa), 1162 RADDR_1 (dsa), 1163 SCR_JUMP, 1164 PADDR_A (resel_go), 1165}/*-------------------------< DATA_IN >--------------------------*/,{ 1166/* 1167 * Because the size depends on the 1168 * #define SYM_CONF_MAX_SG parameter, 1169 * it is filled in at runtime. 1170 * 1171 * ##===========< i=0; i<SYM_CONF_MAX_SG >========= 1172 * || SCR_CHMOV_TBL ^ SCR_DATA_IN, 1173 * || offsetof (struct sym_dsb, data[ i]), 1174 * ##========================================== 1175 */ 11760 1177}/*-------------------------< DATA_IN2 >-------------------------*/,{ 1178 SCR_CALL, 1179 PADDR_A (datai_done), 1180 SCR_JUMP, 1181 PADDR_B (data_ovrun), 1182}/*-------------------------< DATA_OUT >-------------------------*/,{ 1183/* 1184 * Because the size depends on the 1185 * #define SYM_CONF_MAX_SG parameter, 1186 * it is filled in at runtime. 1187 * 1188 * ##===========< i=0; i<SYM_CONF_MAX_SG >========= 1189 * || SCR_CHMOV_TBL ^ SCR_DATA_OUT, 1190 * || offsetof (struct sym_dsb, data[ i]), 1191 * ##========================================== 1192 */ 11930 1194}/*-------------------------< DATA_OUT2 >------------------------*/,{ 1195 SCR_CALL, 1196 PADDR_A (datao_done), 1197 SCR_JUMP, 1198 PADDR_B (data_ovrun), 1199}/*-------------------------< PM0_DATA >-------------------------*/,{ 1200 /* 1201 * Read our host flags to SFBR, so we will be able 1202 * to check against the data direction we expect. 1203 */ 1204 SCR_FROM_REG (HF_REG), 1205 0, 1206 /* 1207 * Check against actual DATA PHASE. 1208 */ 1209 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)), 1210 PADDR_A (pm0_data_out), 1211 /* 1212 * Actual phase is DATA IN. 1213 * Check against expected direction. 1214 */ 1215 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)), 1216 PADDR_B (data_ovrun), 1217 /* 1218 * Keep track we are moving data from the 1219 * PM0 DATA mini-script. 1220 */ 1221 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0), 1222 0, 1223 /* 1224 * Move the data to memory. 1225 */ 1226 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1227 offsetof (struct sym_ccb, phys.pm0.sg), 1228 SCR_JUMP, 1229 PADDR_A (pm0_data_end), 1230}/*-------------------------< PM0_DATA_OUT >---------------------*/,{ 1231 /* 1232 * Actual phase is DATA OUT. 1233 * Check against expected direction. 1234 */ 1235 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)), 1236 PADDR_B (data_ovrun), 1237 /* 1238 * Keep track we are moving data from the 1239 * PM0 DATA mini-script. 1240 */ 1241 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0), 1242 0, 1243 /* 1244 * Move the data from memory. 1245 */ 1246 SCR_CHMOV_TBL ^ SCR_DATA_OUT, 1247 offsetof (struct sym_ccb, phys.pm0.sg), 1248}/*-------------------------< PM0_DATA_END >---------------------*/,{ 1249 /* 1250 * Clear the flag that told we were moving 1251 * data from the PM0 DATA mini-script. 1252 */ 1253 SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM0)), 1254 0, 1255 /* 1256 * Return to the previous DATA script which 1257 * is guaranteed by design (if no bug) to be 1258 * the main DATA script for this transfer. 1259 */ 1260 SCR_COPY (4), 1261 RADDR_1 (dsa), 1262 RADDR_1 (scratcha), 1263 SCR_REG_REG (scratcha, SCR_ADD, offsetof (struct sym_ccb,phys.pm0.ret)), 1264 0, 1265}/*-------------------------< PM_DATA_END >----------------------*/,{ 1266 SCR_COPY (4), 1267 RADDR_1 (scratcha), 1268 PADDR_A (_sms_a150), 1269 SCR_COPY (4), 1270}/*-------------------------< _SMS_A150 >------------------------*/,{ 1271 0, 1272 RADDR_1 (temp), 1273 SCR_RETURN, 1274 0, 1275}/*-------------------------< PM1_DATA >-------------------------*/,{ 1276 /* 1277 * Read our host flags to SFBR, so we will be able 1278 * to check against the data direction we expect. 1279 */ 1280 SCR_FROM_REG (HF_REG), 1281 0, 1282 /* 1283 * Check against actual DATA PHASE. 1284 */ 1285 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)), 1286 PADDR_A (pm1_data_out), 1287 /* 1288 * Actual phase is DATA IN. 1289 * Check against expected direction. 1290 */ 1291 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)), 1292 PADDR_B (data_ovrun), 1293 /* 1294 * Keep track we are moving data from the 1295 * PM1 DATA mini-script. 1296 */ 1297 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1), 1298 0, 1299 /* 1300 * Move the data to memory. 1301 */ 1302 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1303 offsetof (struct sym_ccb, phys.pm1.sg), 1304 SCR_JUMP, 1305 PADDR_A (pm1_data_end), 1306}/*-------------------------< PM1_DATA_OUT >---------------------*/,{ 1307 /* 1308 * Actual phase is DATA OUT. 1309 * Check against expected direction. 1310 */ 1311 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)), 1312 PADDR_B (data_ovrun), 1313 /* 1314 * Keep track we are moving data from the 1315 * PM1 DATA mini-script. 1316 */ 1317 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1), 1318 0, 1319 /* 1320 * Move the data from memory. 1321 */ 1322 SCR_CHMOV_TBL ^ SCR_DATA_OUT, 1323 offsetof (struct sym_ccb, phys.pm1.sg), 1324}/*-------------------------< PM1_DATA_END >---------------------*/,{ 1325 /* 1326 * Clear the flag that told we were moving 1327 * data from the PM1 DATA mini-script. 1328 */ 1329 SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM1)), 1330 0, 1331 /* 1332 * Return to the previous DATA script which 1333 * is guaranteed by design (if no bug) to be 1334 * the main DATA script for this transfer. 1335 */ 1336 SCR_COPY (4), 1337 RADDR_1 (dsa), 1338 RADDR_1 (scratcha), 1339 SCR_REG_REG (scratcha, SCR_ADD, offsetof (struct sym_ccb,phys.pm1.ret)), 1340 0, 1341 SCR_JUMP, 1342 PADDR_A (pm_data_end), 1343}/*--------------------------<>----------------------------------*/ 1344}; 1345 1346static const struct SYM_FWB_SCR SYM_FWB_SCR = { 1347/*-------------------------< NO_DATA >--------------------------*/ { 1348 SCR_JUMP, 1349 PADDR_B (data_ovrun), 1350}/*-------------------------< SEL_FOR_ABORT >--------------------*/,{ 1351 /* 1352 * We are jumped here by the C code, if we have 1353 * some target to reset or some disconnected 1354 * job to abort. Since error recovery is a serious 1355 * busyness, we will really reset the SCSI BUS, if 1356 * case of a SCSI interrupt occurring in this path. 1357 */ 1358 1359 /* 1360 * Set initiator mode. 1361 */ 1362 SCR_CLR (SCR_TRG), 1363 0, 1364 /* 1365 * And try to select this target. 1366 */ 1367 SCR_SEL_TBL_ATN ^ offsetof (struct sym_hcb, abrt_sel), 1368 PADDR_A (reselect), 1369 /* 1370 * Wait for the selection to complete or 1371 * the selection to time out. 1372 */ 1373 SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1374 -8, 1375 /* 1376 * Call the C code. 1377 */ 1378 SCR_INT, 1379 SIR_TARGET_SELECTED, 1380 /* 1381 * The C code should let us continue here. 1382 * Send the 'kiss of death' message. 1383 * We expect an immediate disconnect once 1384 * the target has eaten the message. 1385 */ 1386 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 1387 0, 1388 SCR_MOVE_TBL ^ SCR_MSG_OUT, 1389 offsetof (struct sym_hcb, abrt_tbl), 1390 SCR_CLR (SCR_ACK|SCR_ATN), 1391 0, 1392 SCR_WAIT_DISC, 1393 0, 1394 /* 1395 * Tell the C code that we are done. 1396 */ 1397 SCR_INT, 1398 SIR_ABORT_SENT, 1399}/*-------------------------< SEL_FOR_ABORT_1 >------------------*/,{ 1400 /* 1401 * Jump at scheduler. 1402 */ 1403 SCR_JUMP, 1404 PADDR_A (start), 1405}/*-------------------------< MSG_IN_ETC >-----------------------*/,{ 1406 /* 1407 * If it is an EXTENDED (variable size message) 1408 * Handle it. 1409 */ 1410 SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED)), 1411 PADDR_B (msg_extended), 1412 /* 1413 * Let the C code handle any other 1414 * 1 byte message. 1415 */ 1416 SCR_JUMP ^ IFTRUE (MASK (0x00, 0xf0)), 1417 PADDR_B (msg_received), 1418 SCR_JUMP ^ IFTRUE (MASK (0x10, 0xf0)), 1419 PADDR_B (msg_received), 1420 /* 1421 * We donnot handle 2 bytes messages from SCRIPTS. 1422 * So, let the C code deal with these ones too. 1423 */ 1424 SCR_JUMP ^ IFFALSE (MASK (0x20, 0xf0)), 1425 PADDR_B (msg_weird_seen), 1426 SCR_CLR (SCR_ACK), 1427 0, 1428 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 1429 HADDR_1 (msgin[1]), 1430}/*-------------------------< MSG_RECEIVED >---------------------*/,{ 1431 SCR_COPY (4), /* DUMMY READ */ 1432 HADDR_1 (cache), 1433 RADDR_1 (scratcha), 1434 SCR_INT, 1435 SIR_MSG_RECEIVED, 1436}/*-------------------------< MSG_WEIRD_SEEN >-------------------*/,{ 1437 SCR_COPY (4), /* DUMMY READ */ 1438 HADDR_1 (cache), 1439 RADDR_1 (scratcha), 1440 SCR_INT, 1441 SIR_MSG_WEIRD, 1442}/*-------------------------< MSG_EXTENDED >---------------------*/,{ 1443 /* 1444 * Clear ACK and get the next byte 1445 * assumed to be the message length. 1446 */ 1447 SCR_CLR (SCR_ACK), 1448 0, 1449 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 1450 HADDR_1 (msgin[1]), 1451 /* 1452 * Try to catch some unlikely situations as 0 length 1453 * or too large the length. 1454 */ 1455 SCR_JUMP ^ IFTRUE (DATA (0)), 1456 PADDR_B (msg_weird_seen), 1457 SCR_TO_REG (scratcha), 1458 0, 1459 SCR_REG_REG (sfbr, SCR_ADD, (256-8)), 1460 0, 1461 SCR_JUMP ^ IFTRUE (CARRYSET), 1462 PADDR_B (msg_weird_seen), 1463 /* 1464 * We donnot handle extended messages from SCRIPTS. 1465 * Read the amount of data corresponding to the 1466 * message length and call the C code. 1467 */ 1468 SCR_COPY (1), 1469 RADDR_1 (scratcha), 1470 PADDR_B (_sms_b10), 1471 SCR_CLR (SCR_ACK), 1472 0, 1473}/*-------------------------< _SMS_B10 >-------------------------*/,{ 1474 SCR_MOVE_ABS (0) ^ SCR_MSG_IN, 1475 HADDR_1 (msgin[2]), 1476 SCR_JUMP, 1477 PADDR_B (msg_received), 1478}/*-------------------------< MSG_BAD >--------------------------*/,{ 1479 /* 1480 * unimplemented message - reject it. 1481 */ 1482 SCR_INT, 1483 SIR_REJECT_TO_SEND, 1484 SCR_SET (SCR_ATN), 1485 0, 1486 SCR_JUMP, 1487 PADDR_A (clrack), 1488}/*-------------------------< MSG_WEIRD >------------------------*/,{ 1489 /* 1490 * weird message received 1491 * ignore all MSG IN phases and reject it. 1492 */ 1493 SCR_INT, 1494 SIR_REJECT_TO_SEND, 1495 SCR_SET (SCR_ATN), 1496 0, 1497}/*-------------------------< MSG_WEIRD1 >-----------------------*/,{ 1498 SCR_CLR (SCR_ACK), 1499 0, 1500 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 1501 PADDR_A (dispatch), 1502 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 1503 HADDR_1 (scratch), 1504 SCR_JUMP, 1505 PADDR_B (msg_weird1), 1506}/*-------------------------< WDTR_RESP >------------------------*/,{ 1507 /* 1508 * let the target fetch our answer. 1509 */ 1510 SCR_SET (SCR_ATN), 1511 0, 1512 SCR_CLR (SCR_ACK), 1513 0, 1514 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1515 PADDR_B (nego_bad_phase), 1516}/*-------------------------< SEND_WDTR >------------------------*/,{ 1517 /* 1518 * Send the M_X_WIDE_REQ 1519 */ 1520 SCR_MOVE_ABS (4) ^ SCR_MSG_OUT, 1521 HADDR_1 (msgout), 1522 SCR_JUMP, 1523 PADDR_B (msg_out_done), 1524}/*-------------------------< SDTR_RESP >------------------------*/,{ 1525 /* 1526 * let the target fetch our answer. 1527 */ 1528 SCR_SET (SCR_ATN), 1529 0, 1530 SCR_CLR (SCR_ACK), 1531 0, 1532 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1533 PADDR_B (nego_bad_phase), 1534}/*-------------------------< SEND_SDTR >------------------------*/,{ 1535 /* 1536 * Send the M_X_SYNC_REQ 1537 */ 1538 SCR_MOVE_ABS (5) ^ SCR_MSG_OUT, 1539 HADDR_1 (msgout), 1540 SCR_JUMP, 1541 PADDR_B (msg_out_done), 1542}/*-------------------------< PPR_RESP >-------------------------*/,{ 1543 /* 1544 * let the target fetch our answer. 1545 */ 1546 SCR_SET (SCR_ATN), 1547 0, 1548 SCR_CLR (SCR_ACK), 1549 0, 1550 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1551 PADDR_B (nego_bad_phase), 1552}/*-------------------------< SEND_PPR >-------------------------*/,{ 1553 /* 1554 * Send the M_X_PPR_REQ 1555 */ 1556 SCR_MOVE_ABS (8) ^ SCR_MSG_OUT, 1557 HADDR_1 (msgout), 1558 SCR_JUMP, 1559 PADDR_B (msg_out_done), 1560}/*-------------------------< NEGO_BAD_PHASE >-------------------*/,{ 1561 SCR_INT, 1562 SIR_NEGO_PROTO, 1563 SCR_JUMP, 1564 PADDR_A (dispatch), 1565}/*-------------------------< MSG_OUT >--------------------------*/,{ 1566 /* 1567 * The target requests a message. 1568 * We donnot send messages that may 1569 * require the device to go to bus free. 1570 */ 1571 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT, 1572 HADDR_1 (msgout), 1573 /* 1574 * ... wait for the next phase 1575 * if it's a message out, send it again, ... 1576 */ 1577 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)), 1578 PADDR_B (msg_out), 1579}/*-------------------------< MSG_OUT_DONE >---------------------*/,{ 1580 /* 1581 * Let the C code be aware of the 1582 * sent message and clear the message. 1583 */ 1584 SCR_INT, 1585 SIR_MSG_OUT_DONE, 1586 /* 1587 * ... and process the next phase 1588 */ 1589 SCR_JUMP, 1590 PADDR_A (dispatch), 1591}/*-------------------------< DATA_OVRUN >-----------------------*/,{ 1592 /* 1593 * Zero scratcha that will count the 1594 * extras bytes. 1595 */ 1596 SCR_COPY (4), 1597 PADDR_B (zero), 1598 RADDR_1 (scratcha), 1599}/*-------------------------< DATA_OVRUN1 >----------------------*/,{ 1600 /* 1601 * The target may want to transfer too much data. 1602 * 1603 * If phase is DATA OUT write 1 byte and count it. 1604 */ 1605 SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_OUT)), 1606 16, 1607 SCR_CHMOV_ABS (1) ^ SCR_DATA_OUT, 1608 HADDR_1 (scratch), 1609 SCR_JUMP, 1610 PADDR_B (data_ovrun2), 1611 /* 1612 * If WSR is set, clear this condition, and 1613 * count this byte. 1614 */ 1615 SCR_FROM_REG (scntl2), 1616 0, 1617 SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)), 1618 16, 1619 SCR_REG_REG (scntl2, SCR_OR, WSR), 1620 0, 1621 SCR_JUMP, 1622 PADDR_B (data_ovrun2), 1623 /* 1624 * Finally check against DATA IN phase. 1625 * Signal data overrun to the C code 1626 * and jump to dispatcher if not so. 1627 * Read 1 byte otherwise and count it. 1628 */ 1629 SCR_JUMPR ^ IFTRUE (WHEN (SCR_DATA_IN)), 1630 16, 1631 SCR_INT, 1632 SIR_DATA_OVERRUN, 1633 SCR_JUMP, 1634 PADDR_A (dispatch), 1635 SCR_CHMOV_ABS (1) ^ SCR_DATA_IN, 1636 HADDR_1 (scratch), 1637}/*-------------------------< DATA_OVRUN2 >----------------------*/,{ 1638 /* 1639 * Count this byte. 1640 * This will allow to return a negative 1641 * residual to user. 1642 */ 1643 SCR_REG_REG (scratcha, SCR_ADD, 0x01), 1644 0, 1645 SCR_REG_REG (scratcha1, SCR_ADDC, 0), 1646 0, 1647 SCR_REG_REG (scratcha2, SCR_ADDC, 0), 1648 0, 1649 /* 1650 * .. and repeat as required. 1651 */ 1652 SCR_JUMP, 1653 PADDR_B (data_ovrun1), 1654}/*-------------------------< ABORT_RESEL >----------------------*/,{ 1655 SCR_SET (SCR_ATN), 1656 0, 1657 SCR_CLR (SCR_ACK), 1658 0, 1659 /* 1660 * send the abort/abortag/reset message 1661 * we expect an immediate disconnect 1662 */ 1663 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 1664 0, 1665 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT, 1666 HADDR_1 (msgout), 1667 SCR_CLR (SCR_ACK|SCR_ATN), 1668 0, 1669 SCR_WAIT_DISC, 1670 0, 1671 SCR_INT, 1672 SIR_RESEL_ABORTED, 1673 SCR_JUMP, 1674 PADDR_A (start), 1675}/*-------------------------< RESEND_IDENT >---------------------*/,{ 1676 /* 1677 * The target stays in MSG OUT phase after having acked 1678 * Identify [+ Tag [+ Extended message ]]. Targets shall 1679 * behave this way on parity error. 1680 * We must send it again all the messages. 1681 */ 1682 SCR_SET (SCR_ATN), /* Shall be asserted 2 deskew delays before the */ 1683 0, /* 1rst ACK = 90 ns. Hope the chip isn't too fast */ 1684 SCR_JUMP, 1685 PADDR_A (send_ident), 1686}/*-------------------------< IDENT_BREAK >----------------------*/,{ 1687 SCR_CLR (SCR_ATN), 1688 0, 1689 SCR_JUMP, 1690 PADDR_A (select2), 1691}/*-------------------------< IDENT_BREAK_ATN >------------------*/,{ 1692 SCR_SET (SCR_ATN), 1693 0, 1694 SCR_JUMP, 1695 PADDR_A (select2), 1696}/*-------------------------< SDATA_IN >-------------------------*/,{ 1697 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1698 offsetof (struct sym_dsb, sense), 1699 SCR_CALL, 1700 PADDR_A (datai_done), 1701 SCR_JUMP, 1702 PADDR_B (data_ovrun), 1703}/*-------------------------< RESEL_BAD_LUN >--------------------*/,{ 1704 /* 1705 * Message is an IDENTIFY, but lun is unknown. 1706 * Signal problem to C code for logging the event. 1707 * Send a M_ABORT to clear all pending tasks. 1708 */ 1709 SCR_INT, 1710 SIR_RESEL_BAD_LUN, 1711 SCR_JUMP, 1712 PADDR_B (abort_resel), 1713}/*-------------------------< BAD_I_T_L >------------------------*/,{ 1714 /* 1715 * We donnot have a task for that I_T_L. 1716 * Signal problem to C code for logging the event. 1717 * Send a M_ABORT message. 1718 */ 1719 SCR_INT, 1720 SIR_RESEL_BAD_I_T_L, 1721 SCR_JUMP, 1722 PADDR_B (abort_resel), 1723}/*-------------------------< BAD_I_T_L_Q >----------------------*/,{ 1724 /* 1725 * We donnot have a task that matches the tag. 1726 * Signal problem to C code for logging the event. 1727 * Send a M_ABORTTAG message. 1728 */ 1729 SCR_INT, 1730 SIR_RESEL_BAD_I_T_L_Q, 1731 SCR_JUMP, 1732 PADDR_B (abort_resel), 1733}/*-------------------------< BAD_STATUS >-----------------------*/,{ 1734 /* 1735 * Anything different from INTERMEDIATE 1736 * CONDITION MET should be a bad SCSI status, 1737 * given that GOOD status has already been tested. 1738 * Call the C code. 1739 */ 1740 SCR_COPY (4), 1741 PADDR_B (startpos), 1742 RADDR_1 (scratcha), 1743 SCR_INT ^ IFFALSE (DATA (S_COND_MET)), 1744 SIR_BAD_SCSI_STATUS, 1745 SCR_RETURN, 1746 0, 1747}/*-------------------------< WSR_MA_HELPER >--------------------*/,{ 1748 /* 1749 * Helper for the C code when WSR bit is set. 1750 * Perform the move of the residual byte. 1751 */ 1752 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1753 offsetof (struct sym_ccb, phys.wresid), 1754 SCR_JUMP, 1755 PADDR_A (dispatch), 1756}/*-------------------------< ZERO >-----------------------------*/,{ 1757 SCR_DATA_ZERO, 1758}/*-------------------------< SCRATCH >--------------------------*/,{ 1759 SCR_DATA_ZERO, /* MUST BE BEFORE SCRATCH1 */ 1760}/*-------------------------< SCRATCH1 >-------------------------*/,{ 1761 SCR_DATA_ZERO, 1762}/*-------------------------< PREV_DONE >------------------------*/,{ 1763 SCR_DATA_ZERO, /* MUST BE BEFORE DONE_POS ! */ 1764}/*-------------------------< DONE_POS >-------------------------*/,{ 1765 SCR_DATA_ZERO, 1766}/*-------------------------< NEXTJOB >--------------------------*/,{ 1767 SCR_DATA_ZERO, /* MUST BE BEFORE STARTPOS ! */ 1768}/*-------------------------< STARTPOS >-------------------------*/,{ 1769 SCR_DATA_ZERO, 1770}/*-------------------------< TARGTBL >--------------------------*/,{ 1771 SCR_DATA_ZERO, 1772 1773}/*-------------------------< SNOOPTEST >------------------------*/,{ 1774 /* 1775 * Read the variable. 1776 */ 1777 SCR_COPY (4), 1778 HADDR_1 (cache), 1779 RADDR_1 (scratcha), 1780 /* 1781 * Write the variable. 1782 */ 1783 SCR_COPY (4), 1784 RADDR_1 (temp), 1785 HADDR_1 (cache), 1786 /* 1787 * Read back the variable. 1788 */ 1789 SCR_COPY (4), 1790 HADDR_1 (cache), 1791 RADDR_1 (temp), 1792}/*-------------------------< SNOOPEND >-------------------------*/,{ 1793 /* 1794 * And stop. 1795 */ 1796 SCR_INT, 1797 99, 1798}/*--------------------------<>----------------------------------*/ 1799}; 1800