1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2022 Ruslan Bukin <br@bsdpad.com>
5 *
6 * This work was supported by Innovate UK project 105694, "Digital Security
7 * by Design (DSbD) Technology Platform Prototype".
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/bus.h>
34#include <sys/rman.h>
35#include <sys/kernel.h>
36#include <sys/module.h>
37
38#include <machine/bus.h>
39
40#include <dev/fdt/simplebus.h>
41#include <dev/fdt/fdt_common.h>
42#include <dev/ofw/ofw_bus_subr.h>
43
44#include "mmio_sram_if.h"
45
46#define	dprintf(fmt, ...)
47
48static struct resource_spec mmio_sram_spec[] = {
49	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
50	{ -1, 0 }
51};
52
53struct mmio_sram_softc {
54	struct simplebus_softc	simplebus_sc;
55	struct resource		*res[1];
56	device_t		dev;
57};
58
59static int
60mmio_sram_probe(device_t dev)
61{
62
63	if (!ofw_bus_is_compatible(dev, "mmio-sram"))
64		return (ENXIO);
65
66	if (!ofw_bus_status_okay(dev))
67		return (ENXIO);
68
69	device_set_desc(dev, "MMIO SRAM");
70
71	return (BUS_PROBE_DEFAULT);
72}
73
74static int
75mmio_sram_attach(device_t dev)
76{
77	struct mmio_sram_softc *sc;
78	phandle_t node;
79
80	sc = device_get_softc(dev);
81	sc->dev = dev;
82
83	if (bus_alloc_resources(dev, mmio_sram_spec, sc->res) != 0) {
84		device_printf(dev, "Can't allocate resources for device.\n");
85		return (ENXIO);
86	}
87
88	node = ofw_bus_get_node(dev);
89	if (node == -1)
90		return (ENXIO);
91
92	simplebus_init(dev, node);
93
94	/*
95	 * Allow devices to identify.
96	 */
97	bus_generic_probe(dev);
98
99	/*
100	 * Now walk the OFW tree and attach top-level devices.
101	 */
102	for (node = OF_child(node); node > 0; node = OF_peer(node))
103		simplebus_add_device(dev, node, 0, NULL, -1, NULL);
104
105	return (bus_generic_attach(dev));
106}
107
108static int
109mmio_sram_detach(device_t dev)
110{
111	struct mmio_sram_softc *sc;
112
113	sc = device_get_softc(dev);
114
115	bus_release_resources(dev, mmio_sram_spec, sc->res);
116
117	return (0);
118}
119
120static uint8_t
121mmio_sram_read_1(device_t dev, bus_size_t offset)
122{
123	struct mmio_sram_softc *sc;
124
125	sc = device_get_softc(dev);
126
127	dprintf("%s: reading from %lx\n", __func__, offset);
128
129	return (bus_read_1(sc->res[0], offset));
130}
131
132static void
133mmio_sram_write_1(device_t dev, bus_size_t offset, uint8_t val)
134{
135	struct mmio_sram_softc *sc;
136
137	sc = device_get_softc(dev);
138
139	dprintf("%s: writing to %lx val %x\n", __func__, offset, val);
140
141	bus_write_1(sc->res[0], offset, val);
142}
143
144static device_method_t mmio_sram_methods[] = {
145	/* Device Interface */
146	DEVMETHOD(device_probe,		mmio_sram_probe),
147	DEVMETHOD(device_attach,	mmio_sram_attach),
148	DEVMETHOD(device_detach,	mmio_sram_detach),
149
150	/* MMIO interface */
151	DEVMETHOD(mmio_sram_read_1,	mmio_sram_read_1),
152	DEVMETHOD(mmio_sram_write_1,	mmio_sram_write_1),
153	DEVMETHOD_END
154};
155
156DEFINE_CLASS_1(mmio_sram, mmio_sram_driver, mmio_sram_methods,
157    sizeof(struct mmio_sram_softc), simplebus_driver);
158
159EARLY_DRIVER_MODULE(mmio_sram, simplebus, mmio_sram_driver, 0, 0,
160    BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE);
161MODULE_VERSION(mmio_sram, 1);
162