1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2019 Oleksandr Tymoshenko <gonzo@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/param.h>
29#include <sys/systm.h>
30#include <sys/bus.h>
31#include <sys/kernel.h>
32#include <sys/lock.h>
33#include <sys/module.h>
34#include <sys/mutex.h>
35#include <sys/rman.h>
36#include <sys/resource.h>
37#include <machine/bus.h>
38
39#include <dev/ofw/ofw_bus.h>
40#include <dev/ofw/ofw_bus_subr.h>
41
42#include <dev/spibus/spi.h>
43#include <dev/spibus/spibusvar.h>
44
45#include <dev/clk/clk.h>
46#include <dev/hwreset/hwreset.h>
47
48#include "spibus_if.h"
49
50#define	RK_SPI_CTRLR0		0x0000
51#define		CTRLR0_OPM_MASTER	(0 << 20)
52#define		CTRLR0_XFM_TR		(0 << 18)
53#define		CTRLR0_FRF_MOTO		(0 << 16)
54#define		CTRLR0_BHT_8BIT		(1 << 13)
55#define		CTRLR0_EM_BIG		(1 << 11)
56#define		CTRLR0_SSD_ONE		(1 << 10)
57#define		CTRLR0_SCPOL		(1 <<  7)
58#define		CTRLR0_SCPH		(1 <<  6)
59#define		CTRLR0_DFS_8BIT		(1 <<  0)
60#define	RK_SPI_CTRLR1		0x0004
61#define	RK_SPI_ENR		0x0008
62#define	RK_SPI_SER		0x000c
63#define	RK_SPI_BAUDR		0x0010
64#define	RK_SPI_TXFTLR		0x0014
65#define	RK_SPI_RXFTLR		0x0018
66#define	RK_SPI_TXFLR		0x001c
67#define	RK_SPI_RXFLR		0x0020
68#define	RK_SPI_SR		0x0024
69#define		SR_BUSY			(1 <<  0)
70#define	RK_SPI_IPR		0x0028
71#define	RK_SPI_IMR		0x002c
72#define		IMR_RFFIM		(1 <<  4)
73#define		IMR_TFEIM		(1 <<  0)
74#define	RK_SPI_ISR		0x0030
75#define		ISR_RFFIS		(1 <<  4)
76#define		ISR_TFEIS		(1 <<  0)
77#define	RK_SPI_RISR		0x0034
78#define	RK_SPI_ICR		0x0038
79#define	RK_SPI_DMACR		0x003c
80#define	RK_SPI_DMATDLR		0x0040
81#define	RK_SPI_DMARDLR		0x0044
82#define	RK_SPI_TXDR		0x0400
83#define	RK_SPI_RXDR		0x0800
84
85#define	CS_MAX			1
86
87static struct ofw_compat_data compat_data[] = {
88	{ "rockchip,rk3328-spi",		1 },
89	{ "rockchip,rk3399-spi",		1 },
90	{ "rockchip,rk3568-spi",		1 },
91	{ NULL,					0 }
92};
93
94static struct resource_spec rk_spi_spec[] = {
95	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
96	{ SYS_RES_IRQ,		0,	RF_ACTIVE | RF_SHAREABLE },
97	{ -1, 0 }
98};
99
100struct rk_spi_softc {
101	device_t	dev;
102	device_t	spibus;
103	struct resource	*res[2];
104	struct mtx	mtx;
105	clk_t		clk_apb;
106	clk_t		clk_spi;
107	void *		intrhand;
108	int		transfer;
109	uint32_t	fifo_size;
110	uint64_t	max_freq;
111
112	uint32_t	intreg;
113	uint8_t		*rxbuf;
114	uint32_t	rxidx;
115	uint8_t		*txbuf;
116	uint32_t	txidx;
117	uint32_t	txlen;
118	uint32_t	rxlen;
119};
120
121#define	RK_SPI_LOCK(sc)			mtx_lock(&(sc)->mtx)
122#define	RK_SPI_UNLOCK(sc)		mtx_unlock(&(sc)->mtx)
123#define	RK_SPI_READ_4(sc, reg)		bus_read_4((sc)->res[0], (reg))
124#define	RK_SPI_WRITE_4(sc, reg, val)	bus_write_4((sc)->res[0], (reg), (val))
125
126static int rk_spi_probe(device_t dev);
127static int rk_spi_attach(device_t dev);
128static int rk_spi_detach(device_t dev);
129static void rk_spi_intr(void *arg);
130
131static void
132rk_spi_enable_chip(struct rk_spi_softc *sc, int enable)
133{
134
135	RK_SPI_WRITE_4(sc, RK_SPI_ENR, enable ? 1 : 0);
136}
137
138static int
139rk_spi_set_cs(struct rk_spi_softc *sc, uint32_t cs, bool active)
140{
141	uint32_t reg;
142
143	if (cs & SPIBUS_CS_HIGH) {
144		device_printf(sc->dev, "SPIBUS_CS_HIGH is not supported\n");
145		return (EINVAL);
146	}
147
148	if (cs > CS_MAX)
149		return (EINVAL);
150
151	reg = RK_SPI_READ_4(sc, RK_SPI_SER);
152	if (active)
153		reg |= (1 << cs);
154	else
155		reg &= ~(1 << cs);
156	RK_SPI_WRITE_4(sc, RK_SPI_SER, reg);
157
158	return (0);
159}
160
161static void
162rk_spi_hw_setup(struct rk_spi_softc *sc, uint32_t mode, uint32_t freq)
163{
164	uint32_t cr0;
165	uint32_t div;
166
167	cr0 =  CTRLR0_OPM_MASTER | CTRLR0_XFM_TR | CTRLR0_FRF_MOTO |
168	    CTRLR0_BHT_8BIT | CTRLR0_EM_BIG | CTRLR0_SSD_ONE |
169	    CTRLR0_DFS_8BIT;
170
171	if (mode & SPIBUS_MODE_CPHA)
172		cr0 |= CTRLR0_SCPH;
173	if (mode & SPIBUS_MODE_CPOL)
174		cr0 |= CTRLR0_SCPOL;
175
176	/* minimum divider is 2 */
177	if (sc->max_freq < freq*2) {
178		clk_set_freq(sc->clk_spi, 2 * freq, CLK_SET_ROUND_DOWN);
179		clk_get_freq(sc->clk_spi, &sc->max_freq);
180	}
181
182	div = ((sc->max_freq + freq - 1) / freq);
183	div = (div + 1) & 0xfffe;
184	RK_SPI_WRITE_4(sc, RK_SPI_BAUDR, div);
185
186	RK_SPI_WRITE_4(sc, RK_SPI_CTRLR0, cr0);
187}
188
189static uint32_t
190rk_spi_fifo_size(struct rk_spi_softc *sc)
191{
192	uint32_t txftlr, reg;
193
194	for (txftlr = 2; txftlr < 32; txftlr++) {
195		RK_SPI_WRITE_4(sc, RK_SPI_TXFTLR, txftlr);
196		reg = RK_SPI_READ_4(sc, RK_SPI_TXFTLR);
197		if (reg != txftlr)
198			break;
199	}
200	RK_SPI_WRITE_4(sc, RK_SPI_TXFTLR, 0);
201
202	if (txftlr == 31)
203		return 0;
204
205	return txftlr;
206}
207
208static void
209rk_spi_empty_rxfifo(struct rk_spi_softc *sc)
210{
211	uint32_t rxlevel;
212	rxlevel = RK_SPI_READ_4(sc, RK_SPI_RXFLR);
213	while (sc->rxidx < sc->rxlen &&
214	    (rxlevel-- > 0)) {
215		sc->rxbuf[sc->rxidx++] = (uint8_t)RK_SPI_READ_4(sc, RK_SPI_RXDR);
216	}
217}
218
219static void
220rk_spi_fill_txfifo(struct rk_spi_softc *sc)
221{
222	uint32_t txlevel;
223	txlevel = RK_SPI_READ_4(sc, RK_SPI_TXFLR);
224
225	while (sc->txidx < sc->txlen && txlevel < sc->fifo_size) {
226		RK_SPI_WRITE_4(sc, RK_SPI_TXDR, sc->txbuf[sc->txidx++]);
227		txlevel++;
228	}
229
230	if (sc->txidx != sc->txlen)
231		sc->intreg |= (IMR_TFEIM  | IMR_RFFIM);
232}
233
234static int
235rk_spi_xfer_buf(struct rk_spi_softc *sc, void *rxbuf, void *txbuf, uint32_t len)
236{
237	int err;
238
239	if (len == 0)
240		return (0);
241
242	sc->rxbuf = rxbuf;
243	sc->rxlen = len;
244	sc->rxidx = 0;
245	sc->txbuf = txbuf;
246	sc->txlen = len;
247	sc->txidx = 0;
248	sc->intreg = 0;
249	rk_spi_fill_txfifo(sc);
250
251	RK_SPI_WRITE_4(sc, RK_SPI_IMR, sc->intreg);
252
253	err = 0;
254	while (err == 0 && sc->intreg != 0)
255		err = msleep(sc, &sc->mtx, 0, "rk_spi", 10 * hz);
256
257	while (err == 0 && sc->rxidx != sc->txidx) {
258		/* read residual data from RX fifo */
259		rk_spi_empty_rxfifo(sc);
260	}
261
262	if (sc->rxidx != sc->rxlen || sc->txidx != sc->txlen)
263		err = EIO;
264
265	return (err);
266}
267
268static int
269rk_spi_probe(device_t dev)
270{
271	if (!ofw_bus_status_okay(dev))
272		return (ENXIO);
273
274	if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
275		return (ENXIO);
276
277	device_set_desc(dev, "Rockchip SPI");
278	return (BUS_PROBE_DEFAULT);
279}
280
281static int
282rk_spi_attach(device_t dev)
283{
284	struct rk_spi_softc *sc;
285	int error;
286
287	sc = device_get_softc(dev);
288	sc->dev = dev;
289
290	mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
291
292	if (bus_alloc_resources(dev, rk_spi_spec, sc->res) != 0) {
293		device_printf(dev, "cannot allocate resources for device\n");
294		error = ENXIO;
295		goto fail;
296	}
297
298	if (bus_setup_intr(dev, sc->res[1],
299	    INTR_TYPE_MISC | INTR_MPSAFE, NULL, rk_spi_intr, sc,
300	    &sc->intrhand)) {
301		bus_release_resources(dev, rk_spi_spec, sc->res);
302		device_printf(dev, "cannot setup interrupt handler\n");
303		return (ENXIO);
304	}
305
306	/* Activate the module clock. */
307	error = clk_get_by_ofw_name(dev, 0, "apb_pclk", &sc->clk_apb);
308	if (error != 0) {
309		device_printf(dev, "cannot get apb_pclk clock\n");
310		goto fail;
311	}
312	error = clk_get_by_ofw_name(dev, 0, "spiclk", &sc->clk_spi);
313	if (error != 0) {
314		device_printf(dev, "cannot get spiclk clock\n");
315		goto fail;
316	}
317	error = clk_enable(sc->clk_apb);
318	if (error != 0) {
319		device_printf(dev, "cannot enable ahb clock\n");
320		goto fail;
321	}
322	error = clk_enable(sc->clk_spi);
323	if (error != 0) {
324		device_printf(dev, "cannot enable spiclk clock\n");
325		goto fail;
326	}
327	clk_get_freq(sc->clk_spi, &sc->max_freq);
328
329	sc->fifo_size = rk_spi_fifo_size(sc);
330	if (sc->fifo_size == 0) {
331		device_printf(dev, "failed to get fifo size\n");
332		goto fail;
333	}
334
335	sc->spibus = device_add_child(dev, "spibus", -1);
336
337	RK_SPI_WRITE_4(sc, RK_SPI_IMR, 0);
338	RK_SPI_WRITE_4(sc, RK_SPI_TXFTLR, sc->fifo_size/2 - 1);
339	RK_SPI_WRITE_4(sc, RK_SPI_RXFTLR, sc->fifo_size/2 - 1);
340
341	return (bus_generic_attach(dev));
342
343fail:
344	rk_spi_detach(dev);
345	return (error);
346}
347
348static int
349rk_spi_detach(device_t dev)
350{
351	struct rk_spi_softc *sc;
352
353	sc = device_get_softc(dev);
354
355	bus_generic_detach(sc->dev);
356	if (sc->spibus != NULL)
357		device_delete_child(dev, sc->spibus);
358
359	if (sc->clk_spi != NULL)
360		clk_release(sc->clk_spi);
361	if (sc->clk_apb)
362		clk_release(sc->clk_apb);
363
364	if (sc->intrhand != NULL)
365		bus_teardown_intr(sc->dev, sc->res[1], sc->intrhand);
366
367	bus_release_resources(dev, rk_spi_spec, sc->res);
368	mtx_destroy(&sc->mtx);
369
370	return (0);
371}
372
373static void
374rk_spi_intr(void *arg)
375{
376	struct rk_spi_softc *sc;
377	uint32_t intreg, isr;
378
379	sc = arg;
380
381	RK_SPI_LOCK(sc);
382	intreg = RK_SPI_READ_4(sc, RK_SPI_IMR);
383	isr = RK_SPI_READ_4(sc, RK_SPI_ISR);
384	RK_SPI_WRITE_4(sc, RK_SPI_ICR, isr);
385
386	if (isr & ISR_RFFIS)
387		rk_spi_empty_rxfifo(sc);
388
389	if (isr & ISR_TFEIS)
390		rk_spi_fill_txfifo(sc);
391
392	/* no bytes left, disable interrupt */
393	if (sc->txidx == sc->txlen) {
394		sc->intreg = 0;
395		wakeup(sc);
396	}
397
398	if (sc->intreg != intreg) {
399		(void)RK_SPI_WRITE_4(sc, RK_SPI_IMR, sc->intreg);
400		(void)RK_SPI_READ_4(sc, RK_SPI_IMR);
401	}
402
403	RK_SPI_UNLOCK(sc);
404}
405
406static phandle_t
407rk_spi_get_node(device_t bus, device_t dev)
408{
409
410	return ofw_bus_get_node(bus);
411}
412
413static int
414rk_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
415{
416	struct rk_spi_softc *sc;
417	uint32_t cs, mode, clock;
418	int err = 0;
419
420	sc = device_get_softc(dev);
421
422	spibus_get_cs(child, &cs);
423	spibus_get_clock(child, &clock);
424	spibus_get_mode(child, &mode);
425
426	RK_SPI_LOCK(sc);
427	rk_spi_hw_setup(sc, mode, clock);
428	rk_spi_enable_chip(sc, 1);
429	err = rk_spi_set_cs(sc, cs, true);
430	if (err != 0) {
431		rk_spi_enable_chip(sc, 0);
432		RK_SPI_UNLOCK(sc);
433		return (err);
434	}
435
436	/* Transfer command then data bytes. */
437	err = 0;
438	if (cmd->tx_cmd_sz > 0)
439		err = rk_spi_xfer_buf(sc, cmd->rx_cmd, cmd->tx_cmd,
440		    cmd->tx_cmd_sz);
441	if (cmd->tx_data_sz > 0 && err == 0)
442		err = rk_spi_xfer_buf(sc, cmd->rx_data, cmd->tx_data,
443		    cmd->tx_data_sz);
444
445	rk_spi_set_cs(sc, cs, false);
446	rk_spi_enable_chip(sc, 0);
447	RK_SPI_UNLOCK(sc);
448
449	return (err);
450}
451
452static device_method_t rk_spi_methods[] = {
453	/* Device interface */
454	DEVMETHOD(device_probe,		rk_spi_probe),
455	DEVMETHOD(device_attach,	rk_spi_attach),
456	DEVMETHOD(device_detach,	rk_spi_detach),
457
458        /* spibus_if  */
459	DEVMETHOD(spibus_transfer,	rk_spi_transfer),
460
461        /* ofw_bus_if */
462	DEVMETHOD(ofw_bus_get_node,	rk_spi_get_node),
463
464	DEVMETHOD_END
465};
466
467static driver_t rk_spi_driver = {
468	"spi",
469	rk_spi_methods,
470	sizeof(struct rk_spi_softc),
471};
472
473DRIVER_MODULE(rk_spi, simplebus, rk_spi_driver, 0, 0);
474DRIVER_MODULE(ofw_spibus, rk_spi, ofw_spibus_driver, 0, 0);
475MODULE_DEPEND(rk_spi, ofw_spibus, 1, 1, 1);
476OFWBUS_PNP_INFO(compat_data);
477