1/*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org> 5 * Copyright (c) 1997, 1998, 1999 6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36#include <sys/cdefs.h> 37/* 38 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 39 * available from http://www.sis.com.tw. 40 * 41 * This driver also supports the NatSemi DP83815. Datasheets are 42 * available from http://www.national.com. 43 * 44 * Written by Bill Paul <wpaul@ee.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48/* 49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 50 * simple TX and RX descriptors of 3 longwords in size. The receiver 51 * has a single perfect filter entry for the station address and a 52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 53 * transceiver while the 7016 requires an external transceiver chip. 54 * Both chips offer the standard bit-bang MII interface as well as 55 * an enchanced PHY interface which simplifies accessing MII registers. 56 * 57 * The only downside to this chipset is that RX descriptors must be 58 * longword aligned. 59 */ 60 61#ifdef HAVE_KERNEL_OPTION_HEADERS 62#include "opt_device_polling.h" 63#endif 64 65#include <sys/param.h> 66#include <sys/systm.h> 67#include <sys/bus.h> 68#include <sys/endian.h> 69#include <sys/kernel.h> 70#include <sys/lock.h> 71#include <sys/malloc.h> 72#include <sys/mbuf.h> 73#include <sys/module.h> 74#include <sys/socket.h> 75#include <sys/sockio.h> 76#include <sys/sysctl.h> 77 78#include <net/if.h> 79#include <net/if_var.h> 80#include <net/if_arp.h> 81#include <net/ethernet.h> 82#include <net/if_dl.h> 83#include <net/if_media.h> 84#include <net/if_types.h> 85#include <net/if_vlan_var.h> 86 87#include <net/bpf.h> 88 89#include <machine/bus.h> 90#include <machine/resource.h> 91#include <sys/rman.h> 92 93#include <dev/mii/mii.h> 94#include <dev/mii/mii_bitbang.h> 95#include <dev/mii/miivar.h> 96 97#include <dev/pci/pcireg.h> 98#include <dev/pci/pcivar.h> 99 100#define SIS_USEIOSPACE 101 102#include <dev/sis/if_sisreg.h> 103 104MODULE_DEPEND(sis, pci, 1, 1, 1); 105MODULE_DEPEND(sis, ether, 1, 1, 1); 106MODULE_DEPEND(sis, miibus, 1, 1, 1); 107 108/* "device miibus" required. See GENERIC if you get errors here. */ 109#include "miibus_if.h" 110 111#define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx) 112#define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx) 113#define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED) 114 115/* 116 * register space access macros 117 */ 118#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val) 119 120#define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg) 121 122#define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg) 123 124#define CSR_BARRIER(sc, reg, length, flags) \ 125 bus_barrier(sc->sis_res[0], reg, length, flags) 126 127/* 128 * Various supported device vendors/types and their names. 129 */ 130static const struct sis_type sis_devs[] = { 131 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 132 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 133 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 134 { 0, 0, NULL } 135}; 136 137static int sis_detach(device_t); 138static __inline void sis_discard_rxbuf(struct sis_rxdesc *); 139static int sis_dma_alloc(struct sis_softc *); 140static void sis_dma_free(struct sis_softc *); 141static int sis_dma_ring_alloc(struct sis_softc *, bus_size_t, bus_size_t, 142 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 143static void sis_dmamap_cb(void *, bus_dma_segment_t *, int, int); 144#ifndef __NO_STRICT_ALIGNMENT 145static __inline void sis_fixup_rx(struct mbuf *); 146#endif 147static void sis_ifmedia_sts(if_t, struct ifmediareq *); 148static int sis_ifmedia_upd(if_t); 149static void sis_init(void *); 150static void sis_initl(struct sis_softc *); 151static void sis_intr(void *); 152static int sis_ioctl(if_t, u_long, caddr_t); 153static uint32_t sis_mii_bitbang_read(device_t); 154static void sis_mii_bitbang_write(device_t, uint32_t); 155static int sis_newbuf(struct sis_softc *, struct sis_rxdesc *); 156static int sis_resume(device_t); 157static int sis_rxeof(struct sis_softc *); 158static void sis_rxfilter(struct sis_softc *); 159static void sis_rxfilter_ns(struct sis_softc *); 160static void sis_rxfilter_sis(struct sis_softc *); 161static void sis_start(if_t); 162static void sis_startl(if_t); 163static void sis_stop(struct sis_softc *); 164static int sis_suspend(device_t); 165static void sis_add_sysctls(struct sis_softc *); 166static void sis_watchdog(struct sis_softc *); 167static void sis_wol(struct sis_softc *); 168 169/* 170 * MII bit-bang glue 171 */ 172static const struct mii_bitbang_ops sis_mii_bitbang_ops = { 173 sis_mii_bitbang_read, 174 sis_mii_bitbang_write, 175 { 176 SIS_MII_DATA, /* MII_BIT_MDO */ 177 SIS_MII_DATA, /* MII_BIT_MDI */ 178 SIS_MII_CLK, /* MII_BIT_MDC */ 179 SIS_MII_DIR, /* MII_BIT_DIR_HOST_PHY */ 180 0, /* MII_BIT_DIR_PHY_HOST */ 181 } 182}; 183 184static struct resource_spec sis_res_spec[] = { 185#ifdef SIS_USEIOSPACE 186 { SYS_RES_IOPORT, SIS_PCI_LOIO, RF_ACTIVE}, 187#else 188 { SYS_RES_MEMORY, SIS_PCI_LOMEM, RF_ACTIVE}, 189#endif 190 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE}, 191 { -1, 0 } 192}; 193 194#define SIS_SETBIT(sc, reg, x) \ 195 CSR_WRITE_4(sc, reg, \ 196 CSR_READ_4(sc, reg) | (x)) 197 198#define SIS_CLRBIT(sc, reg, x) \ 199 CSR_WRITE_4(sc, reg, \ 200 CSR_READ_4(sc, reg) & ~(x)) 201 202#define SIO_SET(x) \ 203 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 204 205#define SIO_CLR(x) \ 206 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 207 208/* 209 * Routine to reverse the bits in a word. Stolen almost 210 * verbatim from /usr/games/fortune. 211 */ 212static uint16_t 213sis_reverse(uint16_t n) 214{ 215 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 216 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 217 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 218 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 219 220 return (n); 221} 222 223static void 224sis_delay(struct sis_softc *sc) 225{ 226 int idx; 227 228 for (idx = (300 / 33) + 1; idx > 0; idx--) 229 CSR_READ_4(sc, SIS_CSR); 230} 231 232static void 233sis_eeprom_idle(struct sis_softc *sc) 234{ 235 int i; 236 237 SIO_SET(SIS_EECTL_CSEL); 238 sis_delay(sc); 239 SIO_SET(SIS_EECTL_CLK); 240 sis_delay(sc); 241 242 for (i = 0; i < 25; i++) { 243 SIO_CLR(SIS_EECTL_CLK); 244 sis_delay(sc); 245 SIO_SET(SIS_EECTL_CLK); 246 sis_delay(sc); 247 } 248 249 SIO_CLR(SIS_EECTL_CLK); 250 sis_delay(sc); 251 SIO_CLR(SIS_EECTL_CSEL); 252 sis_delay(sc); 253 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 254} 255 256/* 257 * Send a read command and address to the EEPROM, check for ACK. 258 */ 259static void 260sis_eeprom_putbyte(struct sis_softc *sc, int addr) 261{ 262 int d, i; 263 264 d = addr | SIS_EECMD_READ; 265 266 /* 267 * Feed in each bit and stobe the clock. 268 */ 269 for (i = 0x400; i; i >>= 1) { 270 if (d & i) { 271 SIO_SET(SIS_EECTL_DIN); 272 } else { 273 SIO_CLR(SIS_EECTL_DIN); 274 } 275 sis_delay(sc); 276 SIO_SET(SIS_EECTL_CLK); 277 sis_delay(sc); 278 SIO_CLR(SIS_EECTL_CLK); 279 sis_delay(sc); 280 } 281} 282 283/* 284 * Read a word of data stored in the EEPROM at address 'addr.' 285 */ 286static void 287sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest) 288{ 289 int i; 290 uint16_t word = 0; 291 292 /* Force EEPROM to idle state. */ 293 sis_eeprom_idle(sc); 294 295 /* Enter EEPROM access mode. */ 296 sis_delay(sc); 297 SIO_CLR(SIS_EECTL_CLK); 298 sis_delay(sc); 299 SIO_SET(SIS_EECTL_CSEL); 300 sis_delay(sc); 301 302 /* 303 * Send address of word we want to read. 304 */ 305 sis_eeprom_putbyte(sc, addr); 306 307 /* 308 * Start reading bits from EEPROM. 309 */ 310 for (i = 0x8000; i; i >>= 1) { 311 SIO_SET(SIS_EECTL_CLK); 312 sis_delay(sc); 313 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 314 word |= i; 315 sis_delay(sc); 316 SIO_CLR(SIS_EECTL_CLK); 317 sis_delay(sc); 318 } 319 320 /* Turn off EEPROM access mode. */ 321 sis_eeprom_idle(sc); 322 323 *dest = word; 324} 325 326/* 327 * Read a sequence of words from the EEPROM. 328 */ 329static void 330sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap) 331{ 332 int i; 333 uint16_t word = 0, *ptr; 334 335 for (i = 0; i < cnt; i++) { 336 sis_eeprom_getword(sc, off + i, &word); 337 ptr = (uint16_t *)(dest + (i * 2)); 338 if (swap) 339 *ptr = ntohs(word); 340 else 341 *ptr = word; 342 } 343} 344 345#if defined(__i386__) || defined(__amd64__) 346static device_t 347sis_find_bridge(device_t dev) 348{ 349 devclass_t pci_devclass; 350 device_t *pci_devices; 351 int pci_count = 0; 352 device_t *pci_children; 353 int pci_childcount = 0; 354 device_t *busp, *childp; 355 device_t child = NULL; 356 int i, j; 357 358 if ((pci_devclass = devclass_find("pci")) == NULL) 359 return (NULL); 360 361 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 362 363 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 364 if (device_get_children(*busp, &pci_children, &pci_childcount)) 365 continue; 366 for (j = 0, childp = pci_children; 367 j < pci_childcount; j++, childp++) { 368 if (pci_get_vendor(*childp) == SIS_VENDORID && 369 pci_get_device(*childp) == 0x0008) { 370 child = *childp; 371 free(pci_children, M_TEMP); 372 goto done; 373 } 374 } 375 free(pci_children, M_TEMP); 376 } 377 378done: 379 free(pci_devices, M_TEMP); 380 return (child); 381} 382 383static void 384sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt) 385{ 386 device_t bridge; 387 uint8_t reg; 388 int i; 389 bus_space_tag_t btag; 390 391 bridge = sis_find_bridge(dev); 392 if (bridge == NULL) 393 return; 394 reg = pci_read_config(bridge, 0x48, 1); 395 pci_write_config(bridge, 0x48, reg|0x40, 1); 396 397 /* XXX */ 398#if defined(__amd64__) || defined(__i386__) 399 btag = X86_BUS_SPACE_IO; 400#endif 401 402 for (i = 0; i < cnt; i++) { 403 bus_space_write_1(btag, 0x0, 0x70, i + off); 404 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 405 } 406 407 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 408} 409 410static void 411sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest) 412{ 413 uint32_t filtsave, csrsave; 414 415 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 416 csrsave = CSR_READ_4(sc, SIS_CSR); 417 418 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 419 CSR_WRITE_4(sc, SIS_CSR, 0); 420 421 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 422 423 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 424 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 425 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 426 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 427 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 428 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 429 430 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 431 CSR_WRITE_4(sc, SIS_CSR, csrsave); 432} 433#endif 434 435/* 436 * Read the MII serial port for the MII bit-bang module. 437 */ 438static uint32_t 439sis_mii_bitbang_read(device_t dev) 440{ 441 struct sis_softc *sc; 442 uint32_t val; 443 444 sc = device_get_softc(dev); 445 446 val = CSR_READ_4(sc, SIS_EECTL); 447 CSR_BARRIER(sc, SIS_EECTL, 4, 448 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 449 return (val); 450} 451 452/* 453 * Write the MII serial port for the MII bit-bang module. 454 */ 455static void 456sis_mii_bitbang_write(device_t dev, uint32_t val) 457{ 458 struct sis_softc *sc; 459 460 sc = device_get_softc(dev); 461 462 CSR_WRITE_4(sc, SIS_EECTL, val); 463 CSR_BARRIER(sc, SIS_EECTL, 4, 464 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 465} 466 467static int 468sis_miibus_readreg(device_t dev, int phy, int reg) 469{ 470 struct sis_softc *sc; 471 472 sc = device_get_softc(dev); 473 474 if (sc->sis_type == SIS_TYPE_83815) { 475 if (phy != 0) 476 return (0); 477 /* 478 * The NatSemi chip can take a while after 479 * a reset to come ready, during which the BMSR 480 * returns a value of 0. This is *never* supposed 481 * to happen: some of the BMSR bits are meant to 482 * be hardwired in the on position, and this can 483 * confuse the miibus code a bit during the probe 484 * and attach phase. So we make an effort to check 485 * for this condition and wait for it to clear. 486 */ 487 if (!CSR_READ_4(sc, NS_BMSR)) 488 DELAY(1000); 489 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 490 } 491 492 /* 493 * Chipsets < SIS_635 seem not to be able to read/write 494 * through mdio. Use the enhanced PHY access register 495 * again for them. 496 */ 497 if (sc->sis_type == SIS_TYPE_900 && 498 sc->sis_rev < SIS_REV_635) { 499 int i, val = 0; 500 501 if (phy != 0) 502 return (0); 503 504 CSR_WRITE_4(sc, SIS_PHYCTL, 505 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 506 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 507 508 for (i = 0; i < SIS_TIMEOUT; i++) { 509 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 510 break; 511 } 512 513 if (i == SIS_TIMEOUT) { 514 device_printf(sc->sis_dev, 515 "PHY failed to come ready\n"); 516 return (0); 517 } 518 519 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 520 521 if (val == 0xFFFF) 522 return (0); 523 524 return (val); 525 } else 526 return (mii_bitbang_readreg(dev, &sis_mii_bitbang_ops, phy, 527 reg)); 528} 529 530static int 531sis_miibus_writereg(device_t dev, int phy, int reg, int data) 532{ 533 struct sis_softc *sc; 534 535 sc = device_get_softc(dev); 536 537 if (sc->sis_type == SIS_TYPE_83815) { 538 if (phy != 0) 539 return (0); 540 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 541 return (0); 542 } 543 544 /* 545 * Chipsets < SIS_635 seem not to be able to read/write 546 * through mdio. Use the enhanced PHY access register 547 * again for them. 548 */ 549 if (sc->sis_type == SIS_TYPE_900 && 550 sc->sis_rev < SIS_REV_635) { 551 int i; 552 553 if (phy != 0) 554 return (0); 555 556 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 557 (reg << 6) | SIS_PHYOP_WRITE); 558 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 559 560 for (i = 0; i < SIS_TIMEOUT; i++) { 561 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 562 break; 563 } 564 565 if (i == SIS_TIMEOUT) 566 device_printf(sc->sis_dev, 567 "PHY failed to come ready\n"); 568 } else 569 mii_bitbang_writereg(dev, &sis_mii_bitbang_ops, phy, reg, 570 data); 571 return (0); 572} 573 574static void 575sis_miibus_statchg(device_t dev) 576{ 577 struct sis_softc *sc; 578 struct mii_data *mii; 579 if_t ifp; 580 uint32_t reg; 581 582 sc = device_get_softc(dev); 583 SIS_LOCK_ASSERT(sc); 584 585 mii = device_get_softc(sc->sis_miibus); 586 ifp = sc->sis_ifp; 587 if (mii == NULL || ifp == NULL || 588 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 589 return; 590 591 sc->sis_flags &= ~SIS_FLAG_LINK; 592 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 593 (IFM_ACTIVE | IFM_AVALID)) { 594 switch (IFM_SUBTYPE(mii->mii_media_active)) { 595 case IFM_10_T: 596 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 597 sc->sis_flags |= SIS_FLAG_LINK; 598 break; 599 case IFM_100_TX: 600 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 601 sc->sis_flags |= SIS_FLAG_LINK; 602 break; 603 default: 604 break; 605 } 606 } 607 608 if ((sc->sis_flags & SIS_FLAG_LINK) == 0) { 609 /* 610 * Stopping MACs seem to reset SIS_TX_LISTPTR and 611 * SIS_RX_LISTPTR which in turn requires resetting 612 * TX/RX buffers. So just don't do anything for 613 * lost link. 614 */ 615 return; 616 } 617 618 /* Set full/half duplex mode. */ 619 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 620 SIS_SETBIT(sc, SIS_TX_CFG, 621 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR)); 622 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 623 } else { 624 SIS_CLRBIT(sc, SIS_TX_CFG, 625 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR)); 626 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 627 } 628 629 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 630 /* 631 * MPII03.D: Half Duplex Excessive Collisions. 632 * Also page 49 in 83816 manual 633 */ 634 SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D); 635 } 636 637 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A && 638 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 639 /* 640 * Short Cable Receive Errors (MP21.E) 641 */ 642 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 643 reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff; 644 CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000); 645 DELAY(100); 646 reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff; 647 if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) { 648 device_printf(sc->sis_dev, 649 "Applying short cable fix (reg=%x)\n", reg); 650 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); 651 SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20); 652 } 653 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 654 } 655 /* Enable TX/RX MACs. */ 656 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE); 657 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE | SIS_CSR_RX_ENABLE); 658} 659 660static uint32_t 661sis_mchash(struct sis_softc *sc, const uint8_t *addr) 662{ 663 uint32_t crc; 664 665 /* Compute CRC for the address value. */ 666 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 667 668 /* 669 * return the filter bit position 670 * 671 * The NatSemi chip has a 512-bit filter, which is 672 * different than the SiS, so we special-case it. 673 */ 674 if (sc->sis_type == SIS_TYPE_83815) 675 return (crc >> 23); 676 else if (sc->sis_rev >= SIS_REV_635 || 677 sc->sis_rev == SIS_REV_900B) 678 return (crc >> 24); 679 else 680 return (crc >> 25); 681} 682 683static void 684sis_rxfilter(struct sis_softc *sc) 685{ 686 687 SIS_LOCK_ASSERT(sc); 688 689 if (sc->sis_type == SIS_TYPE_83815) 690 sis_rxfilter_ns(sc); 691 else 692 sis_rxfilter_sis(sc); 693} 694 695static u_int 696sis_write_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 697{ 698 struct sis_softc *sc = arg; 699 uint32_t h; 700 int bit, index; 701 702 h = sis_mchash(sc, LLADDR(sdl)); 703 index = h >> 3; 704 bit = h & 0x1F; 705 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 706 if (bit > 0xF) 707 bit -= 0x10; 708 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 709 710 return (1); 711} 712 713static void 714sis_rxfilter_ns(struct sis_softc *sc) 715{ 716 if_t ifp; 717 uint32_t i, filter; 718 719 ifp = sc->sis_ifp; 720 filter = CSR_READ_4(sc, SIS_RXFILT_CTL); 721 if (filter & SIS_RXFILTCTL_ENABLE) { 722 /* 723 * Filter should be disabled to program other bits. 724 */ 725 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE); 726 CSR_READ_4(sc, SIS_RXFILT_CTL); 727 } 728 filter &= ~(NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT | 729 NS_RXFILTCTL_MCHASH | SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD | 730 SIS_RXFILTCTL_ALLMULTI); 731 732 if (if_getflags(ifp) & IFF_BROADCAST) 733 filter |= SIS_RXFILTCTL_BROAD; 734 /* 735 * For the NatSemi chip, we have to explicitly enable the 736 * reception of ARP frames, as well as turn on the 'perfect 737 * match' filter where we store the station address, otherwise 738 * we won't receive unicasts meant for this host. 739 */ 740 filter |= NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT; 741 742 if (if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) { 743 filter |= SIS_RXFILTCTL_ALLMULTI; 744 if (if_getflags(ifp) & IFF_PROMISC) 745 filter |= SIS_RXFILTCTL_ALLPHYS; 746 } else { 747 /* 748 * We have to explicitly enable the multicast hash table 749 * on the NatSemi chip if we want to use it, which we do. 750 */ 751 filter |= NS_RXFILTCTL_MCHASH; 752 753 /* first, zot all the existing hash bits */ 754 for (i = 0; i < 32; i++) { 755 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + 756 (i * 2)); 757 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 758 } 759 760 if_foreach_llmaddr(ifp, sis_write_maddr, sc); 761 } 762 763 /* Turn the receive filter on */ 764 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter | SIS_RXFILTCTL_ENABLE); 765 CSR_READ_4(sc, SIS_RXFILT_CTL); 766} 767 768struct sis_hash_maddr_ctx { 769 struct sis_softc *sc; 770 uint16_t hashes[16]; 771}; 772 773static u_int 774sis_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 775{ 776 struct sis_hash_maddr_ctx *ctx = arg; 777 uint32_t h; 778 779 h = sis_mchash(ctx->sc, LLADDR(sdl)); 780 ctx->hashes[h >> 4] |= 1 << (h & 0xf); 781 782 return (1); 783} 784 785static void 786sis_rxfilter_sis(struct sis_softc *sc) 787{ 788 if_t ifp; 789 struct sis_hash_maddr_ctx ctx; 790 uint32_t filter, i, n; 791 792 ifp = sc->sis_ifp; 793 794 /* hash table size */ 795 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 796 n = 16; 797 else 798 n = 8; 799 800 filter = CSR_READ_4(sc, SIS_RXFILT_CTL); 801 if (filter & SIS_RXFILTCTL_ENABLE) { 802 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE); 803 CSR_READ_4(sc, SIS_RXFILT_CTL); 804 } 805 filter &= ~(SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD | 806 SIS_RXFILTCTL_ALLMULTI); 807 if (if_getflags(ifp) & IFF_BROADCAST) 808 filter |= SIS_RXFILTCTL_BROAD; 809 810 if (if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) { 811 filter |= SIS_RXFILTCTL_ALLMULTI; 812 if (if_getflags(ifp) & IFF_PROMISC) 813 filter |= SIS_RXFILTCTL_ALLPHYS; 814 for (i = 0; i < n; i++) 815 ctx.hashes[i] = ~0; 816 } else { 817 for (i = 0; i < n; i++) 818 ctx.hashes[i] = 0; 819 ctx.sc = sc; 820 if (if_foreach_llmaddr(ifp, sis_hash_maddr, &ctx) > n) { 821 filter |= SIS_RXFILTCTL_ALLMULTI; 822 for (i = 0; i < n; i++) 823 ctx.hashes[i] = ~0; 824 } 825 } 826 827 for (i = 0; i < n; i++) { 828 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 829 CSR_WRITE_4(sc, SIS_RXFILT_DATA, ctx.hashes[i]); 830 } 831 832 /* Turn the receive filter on */ 833 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter | SIS_RXFILTCTL_ENABLE); 834 CSR_READ_4(sc, SIS_RXFILT_CTL); 835} 836 837static void 838sis_reset(struct sis_softc *sc) 839{ 840 int i; 841 842 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 843 844 for (i = 0; i < SIS_TIMEOUT; i++) { 845 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 846 break; 847 } 848 849 if (i == SIS_TIMEOUT) 850 device_printf(sc->sis_dev, "reset never completed\n"); 851 852 /* Wait a little while for the chip to get its brains in order. */ 853 DELAY(1000); 854 855 /* 856 * If this is a NetSemi chip, make sure to clear 857 * PME mode. 858 */ 859 if (sc->sis_type == SIS_TYPE_83815) { 860 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 861 CSR_WRITE_4(sc, NS_CLKRUN, 0); 862 } else { 863 /* Disable WOL functions. */ 864 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, 0); 865 } 866} 867 868/* 869 * Probe for an SiS chip. Check the PCI vendor and device 870 * IDs against our list and return a device name if we find a match. 871 */ 872static int 873sis_probe(device_t dev) 874{ 875 const struct sis_type *t; 876 877 t = sis_devs; 878 879 while (t->sis_name != NULL) { 880 if ((pci_get_vendor(dev) == t->sis_vid) && 881 (pci_get_device(dev) == t->sis_did)) { 882 device_set_desc(dev, t->sis_name); 883 return (BUS_PROBE_DEFAULT); 884 } 885 t++; 886 } 887 888 return (ENXIO); 889} 890 891/* 892 * Attach the interface. Allocate softc structures, do ifmedia 893 * setup and ethernet/BPF attach. 894 */ 895static int 896sis_attach(device_t dev) 897{ 898 u_char eaddr[ETHER_ADDR_LEN]; 899 struct sis_softc *sc; 900 if_t ifp; 901 int error = 0, pmc; 902 903 sc = device_get_softc(dev); 904 905 sc->sis_dev = dev; 906 907 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 908 MTX_DEF); 909 callout_init_mtx(&sc->sis_stat_ch, &sc->sis_mtx, 0); 910 911 if (pci_get_device(dev) == SIS_DEVICEID_900) 912 sc->sis_type = SIS_TYPE_900; 913 if (pci_get_device(dev) == SIS_DEVICEID_7016) 914 sc->sis_type = SIS_TYPE_7016; 915 if (pci_get_vendor(dev) == NS_VENDORID) 916 sc->sis_type = SIS_TYPE_83815; 917 918 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 919 /* 920 * Map control/status registers. 921 */ 922 pci_enable_busmaster(dev); 923 924 error = bus_alloc_resources(dev, sis_res_spec, sc->sis_res); 925 if (error) { 926 device_printf(dev, "couldn't allocate resources\n"); 927 goto fail; 928 } 929 930 /* Reset the adapter. */ 931 sis_reset(sc); 932 933 if (sc->sis_type == SIS_TYPE_900 && 934 (sc->sis_rev == SIS_REV_635 || 935 sc->sis_rev == SIS_REV_900B)) { 936 SIO_SET(SIS_CFG_RND_CNT); 937 SIO_SET(SIS_CFG_PERR_DETECT); 938 } 939 940 /* 941 * Get station address from the EEPROM. 942 */ 943 switch (pci_get_vendor(dev)) { 944 case NS_VENDORID: 945 sc->sis_srr = CSR_READ_4(sc, NS_SRR); 946 947 /* We can't update the device description, so spew */ 948 if (sc->sis_srr == NS_SRR_15C) 949 device_printf(dev, "Silicon Revision: DP83815C\n"); 950 else if (sc->sis_srr == NS_SRR_15D) 951 device_printf(dev, "Silicon Revision: DP83815D\n"); 952 else if (sc->sis_srr == NS_SRR_16A) 953 device_printf(dev, "Silicon Revision: DP83816A\n"); 954 else 955 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr); 956 957 /* 958 * Reading the MAC address out of the EEPROM on 959 * the NatSemi chip takes a bit more work than 960 * you'd expect. The address spans 4 16-bit words, 961 * with the first word containing only a single bit. 962 * You have to shift everything over one bit to 963 * get it aligned properly. Also, the bits are 964 * stored backwards (the LSB is really the MSB, 965 * and so on) so you have to reverse them in order 966 * to get the MAC address into the form we want. 967 * Why? Who the hell knows. 968 */ 969 { 970 uint16_t tmp[4]; 971 972 sis_read_eeprom(sc, (caddr_t)&tmp, 973 NS_EE_NODEADDR, 4, 0); 974 975 /* Shift everything over one bit. */ 976 tmp[3] = tmp[3] >> 1; 977 tmp[3] |= tmp[2] << 15; 978 tmp[2] = tmp[2] >> 1; 979 tmp[2] |= tmp[1] << 15; 980 tmp[1] = tmp[1] >> 1; 981 tmp[1] |= tmp[0] << 15; 982 983 /* Now reverse all the bits. */ 984 tmp[3] = sis_reverse(tmp[3]); 985 tmp[2] = sis_reverse(tmp[2]); 986 tmp[1] = sis_reverse(tmp[1]); 987 988 eaddr[0] = (tmp[1] >> 0) & 0xFF; 989 eaddr[1] = (tmp[1] >> 8) & 0xFF; 990 eaddr[2] = (tmp[2] >> 0) & 0xFF; 991 eaddr[3] = (tmp[2] >> 8) & 0xFF; 992 eaddr[4] = (tmp[3] >> 0) & 0xFF; 993 eaddr[5] = (tmp[3] >> 8) & 0xFF; 994 } 995 break; 996 case SIS_VENDORID: 997 default: 998#if defined(__i386__) || defined(__amd64__) 999 /* 1000 * If this is a SiS 630E chipset with an embedded 1001 * SiS 900 controller, we have to read the MAC address 1002 * from the APC CMOS RAM. Our method for doing this 1003 * is very ugly since we have to reach out and grab 1004 * ahold of hardware for which we cannot properly 1005 * allocate resources. This code is only compiled on 1006 * the i386 architecture since the SiS 630E chipset 1007 * is for x86 motherboards only. Note that there are 1008 * a lot of magic numbers in this hack. These are 1009 * taken from SiS's Linux driver. I'd like to replace 1010 * them with proper symbolic definitions, but that 1011 * requires some datasheets that I don't have access 1012 * to at the moment. 1013 */ 1014 if (sc->sis_rev == SIS_REV_630S || 1015 sc->sis_rev == SIS_REV_630E || 1016 sc->sis_rev == SIS_REV_630EA1) 1017 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1018 1019 else if (sc->sis_rev == SIS_REV_635 || 1020 sc->sis_rev == SIS_REV_630ET) 1021 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1022 else if (sc->sis_rev == SIS_REV_96x) { 1023 /* Allow to read EEPROM from LAN. It is shared 1024 * between a 1394 controller and the NIC and each 1025 * time we access it, we need to set SIS_EECMD_REQ. 1026 */ 1027 SIO_SET(SIS_EECMD_REQ); 1028 for (int waittime = 0; waittime < SIS_TIMEOUT; 1029 waittime++) { 1030 /* Force EEPROM to idle state. */ 1031 sis_eeprom_idle(sc); 1032 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1033 sis_read_eeprom(sc, (caddr_t)&eaddr, 1034 SIS_EE_NODEADDR, 3, 0); 1035 break; 1036 } 1037 DELAY(1); 1038 } 1039 /* 1040 * Set SIS_EECTL_CLK to high, so a other master 1041 * can operate on the i2c bus. 1042 */ 1043 SIO_SET(SIS_EECTL_CLK); 1044 /* Refuse EEPROM access by LAN */ 1045 SIO_SET(SIS_EECMD_DONE); 1046 } else 1047#endif 1048 sis_read_eeprom(sc, (caddr_t)&eaddr, 1049 SIS_EE_NODEADDR, 3, 0); 1050 break; 1051 } 1052 1053 sis_add_sysctls(sc); 1054 1055 /* Allocate DMA'able memory. */ 1056 if ((error = sis_dma_alloc(sc)) != 0) 1057 goto fail; 1058 1059 ifp = sc->sis_ifp = if_alloc(IFT_ETHER); 1060 if (ifp == NULL) { 1061 device_printf(dev, "can not if_alloc()\n"); 1062 error = ENOSPC; 1063 goto fail; 1064 } 1065 if_setsoftc(ifp, sc); 1066 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1067 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1068 if_setioctlfn(ifp, sis_ioctl); 1069 if_setstartfn(ifp, sis_start); 1070 if_setinitfn(ifp, sis_init); 1071 if_setsendqlen(ifp, SIS_TX_LIST_CNT - 1); 1072 if_setsendqready(ifp); 1073 1074 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) == 0) { 1075 if (sc->sis_type == SIS_TYPE_83815) 1076 if_setcapabilitiesbit(ifp, IFCAP_WOL, 0); 1077 else 1078 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); 1079 if_setcapenable(ifp, if_getcapabilities(ifp)); 1080 } 1081 1082 /* 1083 * Do MII setup. 1084 */ 1085 error = mii_attach(dev, &sc->sis_miibus, ifp, sis_ifmedia_upd, 1086 sis_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 1087 if (error != 0) { 1088 device_printf(dev, "attaching PHYs failed\n"); 1089 goto fail; 1090 } 1091 1092 /* 1093 * Call MI attach routine. 1094 */ 1095 ether_ifattach(ifp, eaddr); 1096 1097 /* 1098 * Tell the upper layer(s) we support long frames. 1099 */ 1100 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1101 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 1102 if_setcapenable(ifp, if_getcapabilities(ifp)); 1103#ifdef DEVICE_POLLING 1104 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 1105#endif 1106 1107 /* Hook interrupt last to avoid having to lock softc */ 1108 error = bus_setup_intr(dev, sc->sis_res[1], INTR_TYPE_NET | INTR_MPSAFE, 1109 NULL, sis_intr, sc, &sc->sis_intrhand); 1110 1111 if (error) { 1112 device_printf(dev, "couldn't set up irq\n"); 1113 ether_ifdetach(ifp); 1114 goto fail; 1115 } 1116 1117fail: 1118 if (error) 1119 sis_detach(dev); 1120 1121 return (error); 1122} 1123 1124/* 1125 * Shutdown hardware and free up resources. This can be called any 1126 * time after the mutex has been initialized. It is called in both 1127 * the error case in attach and the normal detach case so it needs 1128 * to be careful about only freeing resources that have actually been 1129 * allocated. 1130 */ 1131static int 1132sis_detach(device_t dev) 1133{ 1134 struct sis_softc *sc; 1135 if_t ifp; 1136 1137 sc = device_get_softc(dev); 1138 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); 1139 ifp = sc->sis_ifp; 1140 1141#ifdef DEVICE_POLLING 1142 if (if_getcapenable(ifp) & IFCAP_POLLING) 1143 ether_poll_deregister(ifp); 1144#endif 1145 1146 /* These should only be active if attach succeeded. */ 1147 if (device_is_attached(dev)) { 1148 SIS_LOCK(sc); 1149 sis_stop(sc); 1150 SIS_UNLOCK(sc); 1151 callout_drain(&sc->sis_stat_ch); 1152 ether_ifdetach(ifp); 1153 } 1154 if (sc->sis_miibus) 1155 device_delete_child(dev, sc->sis_miibus); 1156 bus_generic_detach(dev); 1157 1158 if (sc->sis_intrhand) 1159 bus_teardown_intr(dev, sc->sis_res[1], sc->sis_intrhand); 1160 bus_release_resources(dev, sis_res_spec, sc->sis_res); 1161 1162 if (ifp) 1163 if_free(ifp); 1164 1165 sis_dma_free(sc); 1166 1167 mtx_destroy(&sc->sis_mtx); 1168 1169 return (0); 1170} 1171 1172struct sis_dmamap_arg { 1173 bus_addr_t sis_busaddr; 1174}; 1175 1176static void 1177sis_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1178{ 1179 struct sis_dmamap_arg *ctx; 1180 1181 if (error != 0) 1182 return; 1183 1184 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1185 1186 ctx = (struct sis_dmamap_arg *)arg; 1187 ctx->sis_busaddr = segs[0].ds_addr; 1188} 1189 1190static int 1191sis_dma_ring_alloc(struct sis_softc *sc, bus_size_t alignment, 1192 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, 1193 bus_addr_t *paddr, const char *msg) 1194{ 1195 struct sis_dmamap_arg ctx; 1196 int error; 1197 1198 error = bus_dma_tag_create(sc->sis_parent_tag, alignment, 0, 1199 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1, 1200 maxsize, 0, NULL, NULL, tag); 1201 if (error != 0) { 1202 device_printf(sc->sis_dev, 1203 "could not create %s dma tag\n", msg); 1204 return (ENOMEM); 1205 } 1206 /* Allocate DMA'able memory for ring. */ 1207 error = bus_dmamem_alloc(*tag, (void **)ring, 1208 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 1209 if (error != 0) { 1210 device_printf(sc->sis_dev, 1211 "could not allocate DMA'able memory for %s\n", msg); 1212 return (ENOMEM); 1213 } 1214 /* Load the address of the ring. */ 1215 ctx.sis_busaddr = 0; 1216 error = bus_dmamap_load(*tag, *map, *ring, maxsize, sis_dmamap_cb, 1217 &ctx, BUS_DMA_NOWAIT); 1218 if (error != 0) { 1219 device_printf(sc->sis_dev, 1220 "could not load DMA'able memory for %s\n", msg); 1221 return (ENOMEM); 1222 } 1223 *paddr = ctx.sis_busaddr; 1224 return (0); 1225} 1226 1227static int 1228sis_dma_alloc(struct sis_softc *sc) 1229{ 1230 struct sis_rxdesc *rxd; 1231 struct sis_txdesc *txd; 1232 int error, i; 1233 1234 /* Allocate the parent bus DMA tag appropriate for PCI. */ 1235 error = bus_dma_tag_create(bus_get_dma_tag(sc->sis_dev), 1236 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1237 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 1238 0, NULL, NULL, &sc->sis_parent_tag); 1239 if (error != 0) { 1240 device_printf(sc->sis_dev, 1241 "could not allocate parent dma tag\n"); 1242 return (ENOMEM); 1243 } 1244 1245 /* Create RX ring. */ 1246 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_RX_LIST_SZ, 1247 &sc->sis_rx_list_tag, (uint8_t **)&sc->sis_rx_list, 1248 &sc->sis_rx_list_map, &sc->sis_rx_paddr, "RX ring"); 1249 if (error) 1250 return (error); 1251 1252 /* Create TX ring. */ 1253 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_TX_LIST_SZ, 1254 &sc->sis_tx_list_tag, (uint8_t **)&sc->sis_tx_list, 1255 &sc->sis_tx_list_map, &sc->sis_tx_paddr, "TX ring"); 1256 if (error) 1257 return (error); 1258 1259 /* Create tag for RX mbufs. */ 1260 error = bus_dma_tag_create(sc->sis_parent_tag, SIS_RX_BUF_ALIGN, 0, 1261 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 1262 MCLBYTES, 0, NULL, NULL, &sc->sis_rx_tag); 1263 if (error) { 1264 device_printf(sc->sis_dev, "could not allocate RX dma tag\n"); 1265 return (error); 1266 } 1267 1268 /* Create tag for TX mbufs. */ 1269 error = bus_dma_tag_create(sc->sis_parent_tag, 1, 0, 1270 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1271 MCLBYTES * SIS_MAXTXSEGS, SIS_MAXTXSEGS, MCLBYTES, 0, NULL, NULL, 1272 &sc->sis_tx_tag); 1273 if (error) { 1274 device_printf(sc->sis_dev, "could not allocate TX dma tag\n"); 1275 return (error); 1276 } 1277 1278 /* Create DMA maps for RX buffers. */ 1279 error = bus_dmamap_create(sc->sis_rx_tag, 0, &sc->sis_rx_sparemap); 1280 if (error) { 1281 device_printf(sc->sis_dev, 1282 "can't create spare DMA map for RX\n"); 1283 return (error); 1284 } 1285 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1286 rxd = &sc->sis_rxdesc[i]; 1287 rxd->rx_m = NULL; 1288 error = bus_dmamap_create(sc->sis_rx_tag, 0, &rxd->rx_dmamap); 1289 if (error) { 1290 device_printf(sc->sis_dev, 1291 "can't create DMA map for RX\n"); 1292 return (error); 1293 } 1294 } 1295 1296 /* Create DMA maps for TX buffers. */ 1297 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1298 txd = &sc->sis_txdesc[i]; 1299 txd->tx_m = NULL; 1300 error = bus_dmamap_create(sc->sis_tx_tag, 0, &txd->tx_dmamap); 1301 if (error) { 1302 device_printf(sc->sis_dev, 1303 "can't create DMA map for TX\n"); 1304 return (error); 1305 } 1306 } 1307 1308 return (0); 1309} 1310 1311static void 1312sis_dma_free(struct sis_softc *sc) 1313{ 1314 struct sis_rxdesc *rxd; 1315 struct sis_txdesc *txd; 1316 int i; 1317 1318 /* Destroy DMA maps for RX buffers. */ 1319 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1320 rxd = &sc->sis_rxdesc[i]; 1321 if (rxd->rx_dmamap) 1322 bus_dmamap_destroy(sc->sis_rx_tag, rxd->rx_dmamap); 1323 } 1324 if (sc->sis_rx_sparemap) 1325 bus_dmamap_destroy(sc->sis_rx_tag, sc->sis_rx_sparemap); 1326 1327 /* Destroy DMA maps for TX buffers. */ 1328 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1329 txd = &sc->sis_txdesc[i]; 1330 if (txd->tx_dmamap) 1331 bus_dmamap_destroy(sc->sis_tx_tag, txd->tx_dmamap); 1332 } 1333 1334 if (sc->sis_rx_tag) 1335 bus_dma_tag_destroy(sc->sis_rx_tag); 1336 if (sc->sis_tx_tag) 1337 bus_dma_tag_destroy(sc->sis_tx_tag); 1338 1339 /* Destroy RX ring. */ 1340 if (sc->sis_rx_paddr) 1341 bus_dmamap_unload(sc->sis_rx_list_tag, sc->sis_rx_list_map); 1342 if (sc->sis_rx_list) 1343 bus_dmamem_free(sc->sis_rx_list_tag, sc->sis_rx_list, 1344 sc->sis_rx_list_map); 1345 1346 if (sc->sis_rx_list_tag) 1347 bus_dma_tag_destroy(sc->sis_rx_list_tag); 1348 1349 /* Destroy TX ring. */ 1350 if (sc->sis_tx_paddr) 1351 bus_dmamap_unload(sc->sis_tx_list_tag, sc->sis_tx_list_map); 1352 1353 if (sc->sis_tx_list) 1354 bus_dmamem_free(sc->sis_tx_list_tag, sc->sis_tx_list, 1355 sc->sis_tx_list_map); 1356 1357 if (sc->sis_tx_list_tag) 1358 bus_dma_tag_destroy(sc->sis_tx_list_tag); 1359 1360 /* Destroy the parent tag. */ 1361 if (sc->sis_parent_tag) 1362 bus_dma_tag_destroy(sc->sis_parent_tag); 1363} 1364 1365/* 1366 * Initialize the TX and RX descriptors and allocate mbufs for them. Note that 1367 * we arrange the descriptors in a closed ring, so that the last descriptor 1368 * points back to the first. 1369 */ 1370static int 1371sis_ring_init(struct sis_softc *sc) 1372{ 1373 struct sis_rxdesc *rxd; 1374 struct sis_txdesc *txd; 1375 bus_addr_t next; 1376 int error, i; 1377 1378 bzero(&sc->sis_tx_list[0], SIS_TX_LIST_SZ); 1379 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1380 txd = &sc->sis_txdesc[i]; 1381 txd->tx_m = NULL; 1382 if (i == SIS_TX_LIST_CNT - 1) 1383 next = SIS_TX_RING_ADDR(sc, 0); 1384 else 1385 next = SIS_TX_RING_ADDR(sc, i + 1); 1386 sc->sis_tx_list[i].sis_next = htole32(SIS_ADDR_LO(next)); 1387 } 1388 sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0; 1389 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, 1390 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1391 1392 sc->sis_rx_cons = 0; 1393 bzero(&sc->sis_rx_list[0], SIS_RX_LIST_SZ); 1394 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1395 rxd = &sc->sis_rxdesc[i]; 1396 rxd->rx_desc = &sc->sis_rx_list[i]; 1397 if (i == SIS_RX_LIST_CNT - 1) 1398 next = SIS_RX_RING_ADDR(sc, 0); 1399 else 1400 next = SIS_RX_RING_ADDR(sc, i + 1); 1401 rxd->rx_desc->sis_next = htole32(SIS_ADDR_LO(next)); 1402 error = sis_newbuf(sc, rxd); 1403 if (error) 1404 return (error); 1405 } 1406 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, 1407 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1408 1409 return (0); 1410} 1411 1412/* 1413 * Initialize an RX descriptor and attach an MBUF cluster. 1414 */ 1415static int 1416sis_newbuf(struct sis_softc *sc, struct sis_rxdesc *rxd) 1417{ 1418 struct mbuf *m; 1419 bus_dma_segment_t segs[1]; 1420 bus_dmamap_t map; 1421 int nsegs; 1422 1423 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1424 if (m == NULL) 1425 return (ENOBUFS); 1426 m->m_len = m->m_pkthdr.len = SIS_RXLEN; 1427#ifndef __NO_STRICT_ALIGNMENT 1428 m_adj(m, SIS_RX_BUF_ALIGN); 1429#endif 1430 1431 if (bus_dmamap_load_mbuf_sg(sc->sis_rx_tag, sc->sis_rx_sparemap, m, 1432 segs, &nsegs, 0) != 0) { 1433 m_freem(m); 1434 return (ENOBUFS); 1435 } 1436 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1437 1438 if (rxd->rx_m != NULL) { 1439 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, 1440 BUS_DMASYNC_POSTREAD); 1441 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap); 1442 } 1443 map = rxd->rx_dmamap; 1444 rxd->rx_dmamap = sc->sis_rx_sparemap; 1445 sc->sis_rx_sparemap = map; 1446 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_PREREAD); 1447 rxd->rx_m = m; 1448 rxd->rx_desc->sis_ptr = htole32(SIS_ADDR_LO(segs[0].ds_addr)); 1449 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN); 1450 return (0); 1451} 1452 1453static __inline void 1454sis_discard_rxbuf(struct sis_rxdesc *rxd) 1455{ 1456 1457 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN); 1458} 1459 1460#ifndef __NO_STRICT_ALIGNMENT 1461static __inline void 1462sis_fixup_rx(struct mbuf *m) 1463{ 1464 uint16_t *src, *dst; 1465 int i; 1466 1467 src = mtod(m, uint16_t *); 1468 dst = src - (SIS_RX_BUF_ALIGN - ETHER_ALIGN) / sizeof(*src); 1469 1470 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1471 *dst++ = *src++; 1472 1473 m->m_data -= SIS_RX_BUF_ALIGN - ETHER_ALIGN; 1474} 1475#endif 1476 1477/* 1478 * A frame has been uploaded: pass the resulting mbuf chain up to 1479 * the higher level protocols. 1480 */ 1481static int 1482sis_rxeof(struct sis_softc *sc) 1483{ 1484 struct mbuf *m; 1485 if_t ifp; 1486 struct sis_rxdesc *rxd; 1487 struct sis_desc *cur_rx; 1488 int prog, rx_cons, rx_npkts = 0, total_len; 1489 uint32_t rxstat; 1490 1491 SIS_LOCK_ASSERT(sc); 1492 1493 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, 1494 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1495 1496 rx_cons = sc->sis_rx_cons; 1497 ifp = sc->sis_ifp; 1498 1499 for (prog = 0; (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0; 1500 SIS_INC(rx_cons, SIS_RX_LIST_CNT), prog++) { 1501#ifdef DEVICE_POLLING 1502 if (if_getcapenable(ifp) & IFCAP_POLLING) { 1503 if (sc->rxcycles <= 0) 1504 break; 1505 sc->rxcycles--; 1506 } 1507#endif 1508 cur_rx = &sc->sis_rx_list[rx_cons]; 1509 rxstat = le32toh(cur_rx->sis_cmdsts); 1510 if ((rxstat & SIS_CMDSTS_OWN) == 0) 1511 break; 1512 rxd = &sc->sis_rxdesc[rx_cons]; 1513 1514 total_len = (rxstat & SIS_CMDSTS_BUFLEN) - ETHER_CRC_LEN; 1515 if ((if_getcapenable(ifp) & IFCAP_VLAN_MTU) != 0 && 1516 total_len <= (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - 1517 ETHER_CRC_LEN)) 1518 rxstat &= ~SIS_RXSTAT_GIANT; 1519 if (SIS_RXSTAT_ERROR(rxstat) != 0) { 1520 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1521 if (rxstat & SIS_RXSTAT_COLL) 1522 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 1523 sis_discard_rxbuf(rxd); 1524 continue; 1525 } 1526 1527 /* Add a new receive buffer to the ring. */ 1528 m = rxd->rx_m; 1529 if (sis_newbuf(sc, rxd) != 0) { 1530 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1531 sis_discard_rxbuf(rxd); 1532 continue; 1533 } 1534 1535 /* No errors; receive the packet. */ 1536 m->m_pkthdr.len = m->m_len = total_len; 1537#ifndef __NO_STRICT_ALIGNMENT 1538 /* 1539 * On architectures without alignment problems we try to 1540 * allocate a new buffer for the receive ring, and pass up 1541 * the one where the packet is already, saving the expensive 1542 * copy operation. 1543 */ 1544 sis_fixup_rx(m); 1545#endif 1546 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1547 m->m_pkthdr.rcvif = ifp; 1548 1549 SIS_UNLOCK(sc); 1550 if_input(ifp, m); 1551 SIS_LOCK(sc); 1552 rx_npkts++; 1553 } 1554 1555 if (prog > 0) { 1556 sc->sis_rx_cons = rx_cons; 1557 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, 1558 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1559 } 1560 1561 return (rx_npkts); 1562} 1563 1564/* 1565 * A frame was downloaded to the chip. It's safe for us to clean up 1566 * the list buffers. 1567 */ 1568 1569static void 1570sis_txeof(struct sis_softc *sc) 1571{ 1572 if_t ifp; 1573 struct sis_desc *cur_tx; 1574 struct sis_txdesc *txd; 1575 uint32_t cons, txstat; 1576 1577 SIS_LOCK_ASSERT(sc); 1578 1579 cons = sc->sis_tx_cons; 1580 if (cons == sc->sis_tx_prod) 1581 return; 1582 1583 ifp = sc->sis_ifp; 1584 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, 1585 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1586 1587 /* 1588 * Go through our tx list and free mbufs for those 1589 * frames that have been transmitted. 1590 */ 1591 for (; cons != sc->sis_tx_prod; SIS_INC(cons, SIS_TX_LIST_CNT)) { 1592 cur_tx = &sc->sis_tx_list[cons]; 1593 txstat = le32toh(cur_tx->sis_cmdsts); 1594 if ((txstat & SIS_CMDSTS_OWN) != 0) 1595 break; 1596 txd = &sc->sis_txdesc[cons]; 1597 if (txd->tx_m != NULL) { 1598 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, 1599 BUS_DMASYNC_POSTWRITE); 1600 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); 1601 m_freem(txd->tx_m); 1602 txd->tx_m = NULL; 1603 if ((txstat & SIS_CMDSTS_PKT_OK) != 0) { 1604 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1605 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1606 (txstat & SIS_TXSTAT_COLLCNT) >> 16); 1607 } else { 1608 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1609 if (txstat & SIS_TXSTAT_EXCESSCOLLS) 1610 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 1611 if (txstat & SIS_TXSTAT_OUTOFWINCOLL) 1612 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 1613 } 1614 } 1615 sc->sis_tx_cnt--; 1616 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1617 } 1618 sc->sis_tx_cons = cons; 1619 if (sc->sis_tx_cnt == 0) 1620 sc->sis_watchdog_timer = 0; 1621} 1622 1623static void 1624sis_tick(void *xsc) 1625{ 1626 struct sis_softc *sc; 1627 struct mii_data *mii; 1628 1629 sc = xsc; 1630 SIS_LOCK_ASSERT(sc); 1631 1632 mii = device_get_softc(sc->sis_miibus); 1633 mii_tick(mii); 1634 sis_watchdog(sc); 1635 if ((sc->sis_flags & SIS_FLAG_LINK) == 0) 1636 sis_miibus_statchg(sc->sis_dev); 1637 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 1638} 1639 1640#ifdef DEVICE_POLLING 1641static poll_handler_t sis_poll; 1642 1643static int 1644sis_poll(if_t ifp, enum poll_cmd cmd, int count) 1645{ 1646 struct sis_softc *sc = if_getsoftc(ifp); 1647 int rx_npkts = 0; 1648 1649 SIS_LOCK(sc); 1650 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 1651 SIS_UNLOCK(sc); 1652 return (rx_npkts); 1653 } 1654 1655 /* 1656 * On the sis, reading the status register also clears it. 1657 * So before returning to intr mode we must make sure that all 1658 * possible pending sources of interrupts have been served. 1659 * In practice this means run to completion the *eof routines, 1660 * and then call the interrupt routine 1661 */ 1662 sc->rxcycles = count; 1663 rx_npkts = sis_rxeof(sc); 1664 sis_txeof(sc); 1665 if (!if_sendq_empty(ifp)) 1666 sis_startl(ifp); 1667 1668 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1669 uint32_t status; 1670 1671 /* Reading the ISR register clears all interrupts. */ 1672 status = CSR_READ_4(sc, SIS_ISR); 1673 1674 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1675 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1676 1677 if (status & (SIS_ISR_RX_IDLE)) 1678 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1679 1680 if (status & SIS_ISR_SYSERR) { 1681 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1682 sis_initl(sc); 1683 } 1684 } 1685 1686 SIS_UNLOCK(sc); 1687 return (rx_npkts); 1688} 1689#endif /* DEVICE_POLLING */ 1690 1691static void 1692sis_intr(void *arg) 1693{ 1694 struct sis_softc *sc; 1695 if_t ifp; 1696 uint32_t status; 1697 1698 sc = arg; 1699 ifp = sc->sis_ifp; 1700 1701 SIS_LOCK(sc); 1702#ifdef DEVICE_POLLING 1703 if (if_getcapenable(ifp) & IFCAP_POLLING) { 1704 SIS_UNLOCK(sc); 1705 return; 1706 } 1707#endif 1708 1709 /* Reading the ISR register clears all interrupts. */ 1710 status = CSR_READ_4(sc, SIS_ISR); 1711 if ((status & SIS_INTRS) == 0) { 1712 /* Not ours. */ 1713 SIS_UNLOCK(sc); 1714 return; 1715 } 1716 1717 /* Disable interrupts. */ 1718 CSR_WRITE_4(sc, SIS_IER, 0); 1719 1720 for (;(status & SIS_INTRS) != 0;) { 1721 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 1722 break; 1723 if (status & 1724 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1725 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 1726 sis_txeof(sc); 1727 1728 if (status & (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | 1729 SIS_ISR_RX_ERR | SIS_ISR_RX_IDLE)) 1730 sis_rxeof(sc); 1731 1732 if (status & SIS_ISR_RX_OFLOW) 1733 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1734 1735 if (status & (SIS_ISR_RX_IDLE)) 1736 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1737 1738 if (status & SIS_ISR_SYSERR) { 1739 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1740 sis_initl(sc); 1741 SIS_UNLOCK(sc); 1742 return; 1743 } 1744 status = CSR_READ_4(sc, SIS_ISR); 1745 } 1746 1747 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1748 /* Re-enable interrupts. */ 1749 CSR_WRITE_4(sc, SIS_IER, 1); 1750 1751 if (!if_sendq_empty(ifp)) 1752 sis_startl(ifp); 1753 } 1754 1755 SIS_UNLOCK(sc); 1756} 1757 1758/* 1759 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1760 * pointers to the fragment pointers. 1761 */ 1762static int 1763sis_encap(struct sis_softc *sc, struct mbuf **m_head) 1764{ 1765 struct mbuf *m; 1766 struct sis_txdesc *txd; 1767 struct sis_desc *f; 1768 bus_dma_segment_t segs[SIS_MAXTXSEGS]; 1769 bus_dmamap_t map; 1770 int error, i, frag, nsegs, prod; 1771 int padlen; 1772 1773 prod = sc->sis_tx_prod; 1774 txd = &sc->sis_txdesc[prod]; 1775 if ((sc->sis_flags & SIS_FLAG_MANUAL_PAD) != 0 && 1776 (*m_head)->m_pkthdr.len < SIS_MIN_FRAMELEN) { 1777 m = *m_head; 1778 padlen = SIS_MIN_FRAMELEN - m->m_pkthdr.len; 1779 if (M_WRITABLE(m) == 0) { 1780 /* Get a writable copy. */ 1781 m = m_dup(*m_head, M_NOWAIT); 1782 m_freem(*m_head); 1783 if (m == NULL) { 1784 *m_head = NULL; 1785 return (ENOBUFS); 1786 } 1787 *m_head = m; 1788 } 1789 if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) { 1790 m = m_defrag(m, M_NOWAIT); 1791 if (m == NULL) { 1792 m_freem(*m_head); 1793 *m_head = NULL; 1794 return (ENOBUFS); 1795 } 1796 } 1797 /* 1798 * Manually pad short frames, and zero the pad space 1799 * to avoid leaking data. 1800 */ 1801 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1802 m->m_pkthdr.len += padlen; 1803 m->m_len = m->m_pkthdr.len; 1804 *m_head = m; 1805 } 1806 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap, 1807 *m_head, segs, &nsegs, 0); 1808 if (error == EFBIG) { 1809 m = m_collapse(*m_head, M_NOWAIT, SIS_MAXTXSEGS); 1810 if (m == NULL) { 1811 m_freem(*m_head); 1812 *m_head = NULL; 1813 return (ENOBUFS); 1814 } 1815 *m_head = m; 1816 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap, 1817 *m_head, segs, &nsegs, 0); 1818 if (error != 0) { 1819 m_freem(*m_head); 1820 *m_head = NULL; 1821 return (error); 1822 } 1823 } else if (error != 0) 1824 return (error); 1825 1826 /* Check for descriptor overruns. */ 1827 if (sc->sis_tx_cnt + nsegs > SIS_TX_LIST_CNT - 1) { 1828 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); 1829 return (ENOBUFS); 1830 } 1831 1832 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, BUS_DMASYNC_PREWRITE); 1833 1834 frag = prod; 1835 for (i = 0; i < nsegs; i++) { 1836 f = &sc->sis_tx_list[prod]; 1837 if (i == 0) 1838 f->sis_cmdsts = htole32(segs[i].ds_len | 1839 SIS_CMDSTS_MORE); 1840 else 1841 f->sis_cmdsts = htole32(segs[i].ds_len | 1842 SIS_CMDSTS_OWN | SIS_CMDSTS_MORE); 1843 f->sis_ptr = htole32(SIS_ADDR_LO(segs[i].ds_addr)); 1844 SIS_INC(prod, SIS_TX_LIST_CNT); 1845 sc->sis_tx_cnt++; 1846 } 1847 1848 /* Update producer index. */ 1849 sc->sis_tx_prod = prod; 1850 1851 /* Remove MORE flag on the last descriptor. */ 1852 prod = (prod - 1) & (SIS_TX_LIST_CNT - 1); 1853 f = &sc->sis_tx_list[prod]; 1854 f->sis_cmdsts &= ~htole32(SIS_CMDSTS_MORE); 1855 1856 /* Lastly transfer ownership of packet to the controller. */ 1857 f = &sc->sis_tx_list[frag]; 1858 f->sis_cmdsts |= htole32(SIS_CMDSTS_OWN); 1859 1860 /* Swap the last and the first dmamaps. */ 1861 map = txd->tx_dmamap; 1862 txd->tx_dmamap = sc->sis_txdesc[prod].tx_dmamap; 1863 sc->sis_txdesc[prod].tx_dmamap = map; 1864 sc->sis_txdesc[prod].tx_m = *m_head; 1865 1866 return (0); 1867} 1868 1869static void 1870sis_start(if_t ifp) 1871{ 1872 struct sis_softc *sc; 1873 1874 sc = if_getsoftc(ifp); 1875 SIS_LOCK(sc); 1876 sis_startl(ifp); 1877 SIS_UNLOCK(sc); 1878} 1879 1880static void 1881sis_startl(if_t ifp) 1882{ 1883 struct sis_softc *sc; 1884 struct mbuf *m_head; 1885 int queued; 1886 1887 sc = if_getsoftc(ifp); 1888 1889 SIS_LOCK_ASSERT(sc); 1890 1891 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1892 IFF_DRV_RUNNING || (sc->sis_flags & SIS_FLAG_LINK) == 0) 1893 return; 1894 1895 for (queued = 0; !if_sendq_empty(ifp) && 1896 sc->sis_tx_cnt < SIS_TX_LIST_CNT - 4;) { 1897 m_head = if_dequeue(ifp); 1898 if (m_head == NULL) 1899 break; 1900 1901 if (sis_encap(sc, &m_head) != 0) { 1902 if (m_head == NULL) 1903 break; 1904 if_sendq_prepend(ifp, m_head); 1905 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1906 break; 1907 } 1908 1909 queued++; 1910 1911 /* 1912 * If there's a BPF listener, bounce a copy of this frame 1913 * to him. 1914 */ 1915 BPF_MTAP(ifp, m_head); 1916 } 1917 1918 if (queued) { 1919 /* Transmit */ 1920 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, 1921 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1922 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1923 1924 /* 1925 * Set a timeout in case the chip goes out to lunch. 1926 */ 1927 sc->sis_watchdog_timer = 5; 1928 } 1929} 1930 1931static void 1932sis_init(void *xsc) 1933{ 1934 struct sis_softc *sc = xsc; 1935 1936 SIS_LOCK(sc); 1937 sis_initl(sc); 1938 SIS_UNLOCK(sc); 1939} 1940 1941static void 1942sis_initl(struct sis_softc *sc) 1943{ 1944 if_t ifp = sc->sis_ifp; 1945 struct mii_data *mii; 1946 uint8_t *eaddr; 1947 1948 SIS_LOCK_ASSERT(sc); 1949 1950 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1951 return; 1952 1953 /* 1954 * Cancel pending I/O and free all RX/TX buffers. 1955 */ 1956 sis_stop(sc); 1957 /* 1958 * Reset the chip to a known state. 1959 */ 1960 sis_reset(sc); 1961#ifdef notyet 1962 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 1963 /* 1964 * Configure 400usec of interrupt holdoff. This is based 1965 * on empirical tests on a Soekris 4801. 1966 */ 1967 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4); 1968 } 1969#endif 1970 1971 mii = device_get_softc(sc->sis_miibus); 1972 1973 /* Set MAC address */ 1974 eaddr = if_getlladdr(sc->sis_ifp); 1975 if (sc->sis_type == SIS_TYPE_83815) { 1976 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1977 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8); 1978 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1979 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8); 1980 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1981 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8); 1982 } else { 1983 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1984 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8); 1985 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1986 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8); 1987 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1988 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8); 1989 } 1990 1991 /* Init circular TX/RX lists. */ 1992 if (sis_ring_init(sc) != 0) { 1993 device_printf(sc->sis_dev, 1994 "initialization failed: no memory for rx buffers\n"); 1995 sis_stop(sc); 1996 return; 1997 } 1998 1999 if (sc->sis_type == SIS_TYPE_83815) { 2000 if (sc->sis_manual_pad != 0) 2001 sc->sis_flags |= SIS_FLAG_MANUAL_PAD; 2002 else 2003 sc->sis_flags &= ~SIS_FLAG_MANUAL_PAD; 2004 } 2005 2006 /* 2007 * Short Cable Receive Errors (MP21.E) 2008 * also: Page 78 of the DP83815 data sheet (september 2002 version) 2009 * recommends the following register settings "for optimum 2010 * performance." for rev 15C. Set this also for 15D parts as 2011 * they require it in practice. 2012 */ 2013 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) { 2014 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2015 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2016 /* set val for c2 */ 2017 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2018 /* load/kill c2 */ 2019 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2020 /* rais SD off, from 4 to c */ 2021 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2022 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2023 } 2024 2025 sis_rxfilter(sc); 2026 2027 /* 2028 * Load the address of the RX and TX lists. 2029 */ 2030 CSR_WRITE_4(sc, SIS_RX_LISTPTR, SIS_ADDR_LO(sc->sis_rx_paddr)); 2031 CSR_WRITE_4(sc, SIS_TX_LISTPTR, SIS_ADDR_LO(sc->sis_tx_paddr)); 2032 2033 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 2034 * the PCI bus. When this bit is set, the Max DMA Burst Size 2035 * for TX/RX DMA should be no larger than 16 double words. 2036 */ 2037 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 2038 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 2039 } else { 2040 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 2041 } 2042 2043 /* Accept Long Packets for VLAN support */ 2044 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 2045 2046 /* 2047 * Assume 100Mbps link, actual MAC configuration is done 2048 * after getting a valid link. 2049 */ 2050 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 2051 2052 /* 2053 * Enable interrupts. 2054 */ 2055 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 2056#ifdef DEVICE_POLLING 2057 /* 2058 * ... only enable interrupts if we are not polling, make sure 2059 * they are off otherwise. 2060 */ 2061 if (if_getcapenable(ifp) & IFCAP_POLLING) 2062 CSR_WRITE_4(sc, SIS_IER, 0); 2063 else 2064#endif 2065 CSR_WRITE_4(sc, SIS_IER, 1); 2066 2067 /* Clear MAC disable. */ 2068 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE); 2069 2070 sc->sis_flags &= ~SIS_FLAG_LINK; 2071 mii_mediachg(mii); 2072 2073 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2074 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2075 2076 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 2077} 2078 2079/* 2080 * Set media options. 2081 */ 2082static int 2083sis_ifmedia_upd(if_t ifp) 2084{ 2085 struct sis_softc *sc; 2086 struct mii_data *mii; 2087 struct mii_softc *miisc; 2088 int error; 2089 2090 sc = if_getsoftc(ifp); 2091 2092 SIS_LOCK(sc); 2093 mii = device_get_softc(sc->sis_miibus); 2094 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2095 PHY_RESET(miisc); 2096 error = mii_mediachg(mii); 2097 SIS_UNLOCK(sc); 2098 2099 return (error); 2100} 2101 2102/* 2103 * Report current media status. 2104 */ 2105static void 2106sis_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 2107{ 2108 struct sis_softc *sc; 2109 struct mii_data *mii; 2110 2111 sc = if_getsoftc(ifp); 2112 2113 SIS_LOCK(sc); 2114 mii = device_get_softc(sc->sis_miibus); 2115 mii_pollstat(mii); 2116 ifmr->ifm_active = mii->mii_media_active; 2117 ifmr->ifm_status = mii->mii_media_status; 2118 SIS_UNLOCK(sc); 2119} 2120 2121static int 2122sis_ioctl(if_t ifp, u_long command, caddr_t data) 2123{ 2124 struct sis_softc *sc = if_getsoftc(ifp); 2125 struct ifreq *ifr = (struct ifreq *) data; 2126 struct mii_data *mii; 2127 int error = 0, mask; 2128 2129 switch (command) { 2130 case SIOCSIFFLAGS: 2131 SIS_LOCK(sc); 2132 if (if_getflags(ifp) & IFF_UP) { 2133 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 2134 ((if_getflags(ifp) ^ sc->sis_if_flags) & 2135 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2136 sis_rxfilter(sc); 2137 else 2138 sis_initl(sc); 2139 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2140 sis_stop(sc); 2141 sc->sis_if_flags = if_getflags(ifp); 2142 SIS_UNLOCK(sc); 2143 break; 2144 case SIOCADDMULTI: 2145 case SIOCDELMULTI: 2146 SIS_LOCK(sc); 2147 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2148 sis_rxfilter(sc); 2149 SIS_UNLOCK(sc); 2150 break; 2151 case SIOCGIFMEDIA: 2152 case SIOCSIFMEDIA: 2153 mii = device_get_softc(sc->sis_miibus); 2154 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2155 break; 2156 case SIOCSIFCAP: 2157 SIS_LOCK(sc); 2158 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 2159#ifdef DEVICE_POLLING 2160 if ((mask & IFCAP_POLLING) != 0 && 2161 (IFCAP_POLLING & if_getcapabilities(ifp)) != 0) { 2162 if_togglecapenable(ifp, IFCAP_POLLING); 2163 if ((IFCAP_POLLING & if_getcapenable(ifp)) != 0) { 2164 error = ether_poll_register(sis_poll, ifp); 2165 if (error != 0) { 2166 SIS_UNLOCK(sc); 2167 break; 2168 } 2169 /* Disable interrupts. */ 2170 CSR_WRITE_4(sc, SIS_IER, 0); 2171 } else { 2172 error = ether_poll_deregister(ifp); 2173 /* Enable interrupts. */ 2174 CSR_WRITE_4(sc, SIS_IER, 1); 2175 } 2176 } 2177#endif /* DEVICE_POLLING */ 2178 if ((mask & IFCAP_WOL) != 0 && 2179 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) { 2180 if ((mask & IFCAP_WOL_UCAST) != 0) 2181 if_togglecapenable(ifp, IFCAP_WOL_UCAST); 2182 if ((mask & IFCAP_WOL_MCAST) != 0) 2183 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 2184 if ((mask & IFCAP_WOL_MAGIC) != 0) 2185 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 2186 } 2187 SIS_UNLOCK(sc); 2188 break; 2189 default: 2190 error = ether_ioctl(ifp, command, data); 2191 break; 2192 } 2193 2194 return (error); 2195} 2196 2197static void 2198sis_watchdog(struct sis_softc *sc) 2199{ 2200 2201 SIS_LOCK_ASSERT(sc); 2202 2203 if (sc->sis_watchdog_timer == 0 || --sc->sis_watchdog_timer >0) 2204 return; 2205 2206 device_printf(sc->sis_dev, "watchdog timeout\n"); 2207 if_inc_counter(sc->sis_ifp, IFCOUNTER_OERRORS, 1); 2208 2209 if_setdrvflagbits(sc->sis_ifp, 0, IFF_DRV_RUNNING); 2210 sis_initl(sc); 2211 2212 if (!if_sendq_empty(sc->sis_ifp)) 2213 sis_startl(sc->sis_ifp); 2214} 2215 2216/* 2217 * Stop the adapter and free any mbufs allocated to the 2218 * RX and TX lists. 2219 */ 2220static void 2221sis_stop(struct sis_softc *sc) 2222{ 2223 if_t ifp; 2224 struct sis_rxdesc *rxd; 2225 struct sis_txdesc *txd; 2226 int i; 2227 2228 SIS_LOCK_ASSERT(sc); 2229 2230 ifp = sc->sis_ifp; 2231 sc->sis_watchdog_timer = 0; 2232 2233 callout_stop(&sc->sis_stat_ch); 2234 2235 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2236 CSR_WRITE_4(sc, SIS_IER, 0); 2237 CSR_WRITE_4(sc, SIS_IMR, 0); 2238 CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */ 2239 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2240 DELAY(1000); 2241 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2242 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2243 2244 sc->sis_flags &= ~SIS_FLAG_LINK; 2245 2246 /* 2247 * Free data in the RX lists. 2248 */ 2249 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2250 rxd = &sc->sis_rxdesc[i]; 2251 if (rxd->rx_m != NULL) { 2252 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, 2253 BUS_DMASYNC_POSTREAD); 2254 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap); 2255 m_freem(rxd->rx_m); 2256 rxd->rx_m = NULL; 2257 } 2258 } 2259 2260 /* 2261 * Free the TX list buffers. 2262 */ 2263 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2264 txd = &sc->sis_txdesc[i]; 2265 if (txd->tx_m != NULL) { 2266 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, 2267 BUS_DMASYNC_POSTWRITE); 2268 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); 2269 m_freem(txd->tx_m); 2270 txd->tx_m = NULL; 2271 } 2272 } 2273} 2274 2275/* 2276 * Stop all chip I/O so that the kernel's probe routines don't 2277 * get confused by errant DMAs when rebooting. 2278 */ 2279static int 2280sis_shutdown(device_t dev) 2281{ 2282 2283 return (sis_suspend(dev)); 2284} 2285 2286static int 2287sis_suspend(device_t dev) 2288{ 2289 struct sis_softc *sc; 2290 2291 sc = device_get_softc(dev); 2292 SIS_LOCK(sc); 2293 sis_stop(sc); 2294 sis_wol(sc); 2295 SIS_UNLOCK(sc); 2296 return (0); 2297} 2298 2299static int 2300sis_resume(device_t dev) 2301{ 2302 struct sis_softc *sc; 2303 if_t ifp; 2304 2305 sc = device_get_softc(dev); 2306 SIS_LOCK(sc); 2307 ifp = sc->sis_ifp; 2308 if ((if_getflags(ifp) & IFF_UP) != 0) { 2309 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2310 sis_initl(sc); 2311 } 2312 SIS_UNLOCK(sc); 2313 return (0); 2314} 2315 2316static void 2317sis_wol(struct sis_softc *sc) 2318{ 2319 if_t ifp; 2320 uint32_t val; 2321 uint16_t pmstat; 2322 int pmc; 2323 2324 ifp = sc->sis_ifp; 2325 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) 2326 return; 2327 2328 if (sc->sis_type == SIS_TYPE_83815) { 2329 /* Reset RXDP. */ 2330 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2331 2332 /* Configure WOL events. */ 2333 CSR_READ_4(sc, NS_WCSR); 2334 val = 0; 2335 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) != 0) 2336 val |= NS_WCSR_WAKE_UCAST; 2337 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 2338 val |= NS_WCSR_WAKE_MCAST; 2339 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2340 val |= NS_WCSR_WAKE_MAGIC; 2341 CSR_WRITE_4(sc, NS_WCSR, val); 2342 /* Enable PME and clear PMESTS. */ 2343 val = CSR_READ_4(sc, NS_CLKRUN); 2344 val |= NS_CLKRUN_PMEENB | NS_CLKRUN_PMESTS; 2345 CSR_WRITE_4(sc, NS_CLKRUN, val); 2346 /* Enable silent RX mode. */ 2347 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2348 } else { 2349 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) != 0) 2350 return; 2351 val = 0; 2352 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2353 val |= SIS_PWRMAN_WOL_MAGIC; 2354 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, val); 2355 /* Request PME. */ 2356 pmstat = pci_read_config(sc->sis_dev, 2357 pmc + PCIR_POWER_STATUS, 2); 2358 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2359 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2360 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2361 pci_write_config(sc->sis_dev, 2362 pmc + PCIR_POWER_STATUS, pmstat, 2); 2363 } 2364} 2365 2366static void 2367sis_add_sysctls(struct sis_softc *sc) 2368{ 2369 struct sysctl_ctx_list *ctx; 2370 struct sysctl_oid_list *children; 2371 2372 ctx = device_get_sysctl_ctx(sc->sis_dev); 2373 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sis_dev)); 2374 2375 /* 2376 * Unlike most other controllers, NS DP83815/DP83816 controllers 2377 * seem to pad with 0xFF when it encounter short frames. According 2378 * to RFC 1042 the pad bytes should be 0x00. Turning this tunable 2379 * on will have driver pad manully but it's disabled by default 2380 * because it will consume extra CPU cycles for short frames. 2381 */ 2382 sc->sis_manual_pad = 0; 2383 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "manual_pad", 2384 CTLFLAG_RWTUN, &sc->sis_manual_pad, 0, "Manually pad short frames"); 2385} 2386 2387static device_method_t sis_methods[] = { 2388 /* Device interface */ 2389 DEVMETHOD(device_probe, sis_probe), 2390 DEVMETHOD(device_attach, sis_attach), 2391 DEVMETHOD(device_detach, sis_detach), 2392 DEVMETHOD(device_shutdown, sis_shutdown), 2393 DEVMETHOD(device_suspend, sis_suspend), 2394 DEVMETHOD(device_resume, sis_resume), 2395 2396 /* MII interface */ 2397 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 2398 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 2399 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 2400 2401 DEVMETHOD_END 2402}; 2403 2404static driver_t sis_driver = { 2405 "sis", 2406 sis_methods, 2407 sizeof(struct sis_softc) 2408}; 2409 2410DRIVER_MODULE(sis, pci, sis_driver, 0, 0); 2411DRIVER_MODULE(miibus, sis, miibus_driver, 0, 0); 2412