1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2009-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 */ 32 33#include <sys/cdefs.h> 34#include "efx.h" 35#include "efx_impl.h" 36 37#if EFSYS_OPT_SIENA 38 39 __checkReturn efx_rc_t 40siena_mac_poll( 41 __in efx_nic_t *enp, 42 __out efx_link_mode_t *link_modep) 43{ 44 efx_port_t *epp = &(enp->en_port); 45 siena_link_state_t sls; 46 efx_rc_t rc; 47 48 if ((rc = siena_phy_get_link(enp, &sls)) != 0) 49 goto fail1; 50 51 epp->ep_adv_cap_mask = sls.sls_adv_cap_mask; 52 epp->ep_fcntl = sls.sls_fcntl; 53 54 *link_modep = sls.sls_link_mode; 55 56 return (0); 57 58fail1: 59 EFSYS_PROBE1(fail1, efx_rc_t, rc); 60 61 *link_modep = EFX_LINK_UNKNOWN; 62 63 return (rc); 64} 65 66 __checkReturn efx_rc_t 67siena_mac_up( 68 __in efx_nic_t *enp, 69 __out boolean_t *mac_upp) 70{ 71 siena_link_state_t sls; 72 efx_rc_t rc; 73 74 /* 75 * Because Siena doesn't *require* polling, we can't rely on 76 * siena_mac_poll() being executed to populate epp->ep_mac_up. 77 */ 78 if ((rc = siena_phy_get_link(enp, &sls)) != 0) 79 goto fail1; 80 81 *mac_upp = sls.sls_mac_up; 82 83 return (0); 84 85fail1: 86 EFSYS_PROBE1(fail1, efx_rc_t, rc); 87 88 return (rc); 89} 90 91 __checkReturn efx_rc_t 92siena_mac_reconfigure( 93 __in efx_nic_t *enp) 94{ 95 efx_port_t *epp = &(enp->en_port); 96 efx_oword_t multicast_hash[2]; 97 efx_mcdi_req_t req; 98 EFX_MCDI_DECLARE_BUF(payload, 99 MAX(MC_CMD_SET_MAC_IN_LEN, MC_CMD_SET_MCAST_HASH_IN_LEN), 100 MAX(MC_CMD_SET_MAC_OUT_LEN, MC_CMD_SET_MCAST_HASH_OUT_LEN)); 101 102 unsigned int fcntl; 103 efx_rc_t rc; 104 105 req.emr_cmd = MC_CMD_SET_MAC; 106 req.emr_in_buf = payload; 107 req.emr_in_length = MC_CMD_SET_MAC_IN_LEN; 108 req.emr_out_buf = payload; 109 req.emr_out_length = MC_CMD_SET_MAC_OUT_LEN; 110 111 MCDI_IN_SET_DWORD(req, SET_MAC_IN_MTU, epp->ep_mac_pdu); 112 MCDI_IN_SET_DWORD(req, SET_MAC_IN_DRAIN, epp->ep_mac_drain ? 1 : 0); 113 EFX_MAC_ADDR_COPY(MCDI_IN2(req, uint8_t, SET_MAC_IN_ADDR), 114 epp->ep_mac_addr); 115 MCDI_IN_POPULATE_DWORD_2(req, SET_MAC_IN_REJECT, 116 SET_MAC_IN_REJECT_UNCST, !epp->ep_all_unicst, 117 SET_MAC_IN_REJECT_BRDCST, !epp->ep_brdcst); 118 119 if (epp->ep_fcntl_autoneg) 120 /* efx_fcntl_set() has already set the phy capabilities */ 121 fcntl = MC_CMD_FCNTL_AUTO; 122 else if (epp->ep_fcntl & EFX_FCNTL_RESPOND) 123 fcntl = (epp->ep_fcntl & EFX_FCNTL_GENERATE) 124 ? MC_CMD_FCNTL_BIDIR 125 : MC_CMD_FCNTL_RESPOND; 126 else 127 fcntl = MC_CMD_FCNTL_OFF; 128 129 MCDI_IN_SET_DWORD(req, SET_MAC_IN_FCNTL, fcntl); 130 131 efx_mcdi_execute(enp, &req); 132 133 if (req.emr_rc != 0) { 134 rc = req.emr_rc; 135 goto fail1; 136 } 137 138 /* Push multicast hash */ 139 140 if (epp->ep_all_mulcst) { 141 /* A hash matching all multicast is all 1s */ 142 EFX_SET_OWORD(multicast_hash[0]); 143 EFX_SET_OWORD(multicast_hash[1]); 144 } else if (epp->ep_mulcst) { 145 /* Use the hash set by the multicast list */ 146 multicast_hash[0] = epp->ep_multicst_hash[0]; 147 multicast_hash[1] = epp->ep_multicst_hash[1]; 148 } else { 149 /* A hash matching no traffic is simply 0 */ 150 EFX_ZERO_OWORD(multicast_hash[0]); 151 EFX_ZERO_OWORD(multicast_hash[1]); 152 } 153 154 /* 155 * Broadcast packets go through the multicast hash filter. 156 * The IEEE 802.3 CRC32 of the broadcast address is 0xbe2612ff 157 * so we always add bit 0xff to the mask (bit 0x7f in the 158 * second octword). 159 */ 160 if (epp->ep_brdcst) { 161 /* 162 * NOTE: due to constant folding, some of this evaluates 163 * to null expressions, giving E_EXPR_NULL_EFFECT during 164 * lint on Illumos. No good way to fix this without 165 * explicit coding the individual word/bit setting. 166 * So just suppress lint for this one line. 167 */ 168 /* LINTED */ 169 EFX_SET_OWORD_BIT(multicast_hash[1], 0x7f); 170 } 171 172 (void) memset(payload, 0, sizeof (payload)); 173 req.emr_cmd = MC_CMD_SET_MCAST_HASH; 174 req.emr_in_buf = payload; 175 req.emr_in_length = MC_CMD_SET_MCAST_HASH_IN_LEN; 176 req.emr_out_buf = payload; 177 req.emr_out_length = MC_CMD_SET_MCAST_HASH_OUT_LEN; 178 179 memcpy(MCDI_IN2(req, uint8_t, SET_MCAST_HASH_IN_HASH0), 180 multicast_hash, sizeof (multicast_hash)); 181 182 efx_mcdi_execute(enp, &req); 183 184 if (req.emr_rc != 0) { 185 rc = req.emr_rc; 186 goto fail2; 187 } 188 189 return (0); 190 191fail2: 192 EFSYS_PROBE(fail2); 193fail1: 194 EFSYS_PROBE1(fail1, efx_rc_t, rc); 195 196 return (rc); 197} 198 199#if EFSYS_OPT_LOOPBACK 200 201 __checkReturn efx_rc_t 202siena_mac_loopback_set( 203 __in efx_nic_t *enp, 204 __in efx_link_mode_t link_mode, 205 __in efx_loopback_type_t loopback_type) 206{ 207 efx_port_t *epp = &(enp->en_port); 208 const efx_phy_ops_t *epop = epp->ep_epop; 209 efx_loopback_type_t old_loopback_type; 210 efx_link_mode_t old_loopback_link_mode; 211 efx_rc_t rc; 212 213 /* The PHY object handles this on Siena */ 214 old_loopback_type = epp->ep_loopback_type; 215 old_loopback_link_mode = epp->ep_loopback_link_mode; 216 epp->ep_loopback_type = loopback_type; 217 epp->ep_loopback_link_mode = link_mode; 218 219 if ((rc = epop->epo_reconfigure(enp)) != 0) 220 goto fail1; 221 222 return (0); 223 224fail1: 225 EFSYS_PROBE1(fail1, efx_rc_t, rc); 226 227 epp->ep_loopback_type = old_loopback_type; 228 epp->ep_loopback_link_mode = old_loopback_link_mode; 229 230 return (rc); 231} 232 233#endif /* EFSYS_OPT_LOOPBACK */ 234 235#if EFSYS_OPT_MAC_STATS 236 237 __checkReturn efx_rc_t 238siena_mac_stats_get_mask( 239 __in efx_nic_t *enp, 240 __inout_bcount(mask_size) uint32_t *maskp, 241 __in size_t mask_size) 242{ 243 const struct efx_mac_stats_range siena_stats[] = { 244 { EFX_MAC_RX_OCTETS, EFX_MAC_RX_GE_15XX_PKTS }, 245 /* EFX_MAC_RX_ERRORS is not supported */ 246 { EFX_MAC_RX_FCS_ERRORS, EFX_MAC_TX_EX_DEF_PKTS }, 247 }; 248 efx_rc_t rc; 249 250 _NOTE(ARGUNUSED(enp)) 251 252 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size, 253 siena_stats, EFX_ARRAY_SIZE(siena_stats))) != 0) 254 goto fail1; 255 256 return (0); 257 258fail1: 259 EFSYS_PROBE1(fail1, efx_rc_t, rc); 260 261 return (rc); 262} 263 264#define SIENA_MAC_STAT_READ(_esmp, _field, _eqp) \ 265 EFSYS_MEM_READQ((_esmp), (_field) * sizeof (efx_qword_t), _eqp) 266 267 __checkReturn efx_rc_t 268siena_mac_stats_update( 269 __in efx_nic_t *enp, 270 __in efsys_mem_t *esmp, 271 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 272 __inout_opt uint32_t *generationp) 273{ 274 const efx_nic_cfg_t *encp = &enp->en_nic_cfg; 275 efx_qword_t generation_start; 276 efx_qword_t generation_end; 277 efx_qword_t value; 278 efx_rc_t rc; 279 280 if (encp->enc_mac_stats_nstats < MC_CMD_MAC_NSTATS) { 281 /* MAC stats count too small */ 282 rc = ENOSPC; 283 goto fail1; 284 } 285 if (EFSYS_MEM_SIZE(esmp) < 286 (encp->enc_mac_stats_nstats * sizeof (efx_qword_t))) { 287 /* DMA buffer too small */ 288 rc = ENOSPC; 289 goto fail2; 290 } 291 292 /* Read END first so we don't race with the MC */ 293 EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFSYS_MEM_SIZE(esmp)); 294 SIENA_MAC_STAT_READ(esmp, (encp->enc_mac_stats_nstats - 1), 295 &generation_end); 296 EFSYS_MEM_READ_BARRIER(); 297 298 /* TX */ 299 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PKTS, &value); 300 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value); 301 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_CONTROL_PKTS, &value); 302 EFSYS_STAT_SUBR_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value); 303 304 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PAUSE_PKTS, &value); 305 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PAUSE_PKTS]), &value); 306 307 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_UNICAST_PKTS, &value); 308 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_UNICST_PKTS]), &value); 309 310 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTICAST_PKTS, &value); 311 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULTICST_PKTS]), &value); 312 313 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BROADCAST_PKTS, &value); 314 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_BRDCST_PKTS]), &value); 315 316 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BYTES, &value); 317 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_OCTETS]), &value); 318 319 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LT64_PKTS, &value); 320 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value); 321 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_64_PKTS, &value); 322 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value); 323 324 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_65_TO_127_PKTS, &value); 325 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_65_TO_127_PKTS]), &value); 326 327 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_128_TO_255_PKTS, &value); 328 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_128_TO_255_PKTS]), &value); 329 330 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_256_TO_511_PKTS, &value); 331 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_256_TO_511_PKTS]), &value); 332 333 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_512_TO_1023_PKTS, &value); 334 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_512_TO_1023_PKTS]), &value); 335 336 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_1024_TO_15XX_PKTS, &value); 337 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_1024_TO_15XX_PKTS]), &value); 338 339 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS, &value); 340 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value); 341 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_GTJUMBO_PKTS, &value); 342 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value); 343 344 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BAD_FCS_PKTS, &value); 345 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_ERRORS]), &value); 346 347 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS, &value); 348 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_SGL_COL_PKTS]), &value); 349 350 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS, 351 &value); 352 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULT_COL_PKTS]), &value); 353 354 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS, 355 &value); 356 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_COL_PKTS]), &value); 357 358 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LATE_COLLISION_PKTS, &value); 359 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LATE_COL_PKTS]), &value); 360 361 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_DEFERRED_PKTS, &value); 362 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_DEF_PKTS]), &value); 363 364 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS, 365 &value); 366 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_DEF_PKTS]), &value); 367 368 /* RX */ 369 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BYTES, &value); 370 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_OCTETS]), &value); 371 372 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PKTS, &value); 373 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PKTS]), &value); 374 375 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNICAST_PKTS, &value); 376 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_UNICST_PKTS]), &value); 377 378 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MULTICAST_PKTS, &value); 379 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MULTICST_PKTS]), &value); 380 381 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BROADCAST_PKTS, &value); 382 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_BRDCST_PKTS]), &value); 383 384 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PAUSE_PKTS, &value); 385 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PAUSE_PKTS]), &value); 386 387 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNDERSIZE_PKTS, &value); 388 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value); 389 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_64_PKTS, &value); 390 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value); 391 392 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_65_TO_127_PKTS, &value); 393 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_65_TO_127_PKTS]), &value); 394 395 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_128_TO_255_PKTS, &value); 396 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_128_TO_255_PKTS]), &value); 397 398 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_256_TO_511_PKTS, &value); 399 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_256_TO_511_PKTS]), &value); 400 401 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_512_TO_1023_PKTS, &value); 402 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_512_TO_1023_PKTS]), &value); 403 404 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_1024_TO_15XX_PKTS, &value); 405 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_1024_TO_15XX_PKTS]), &value); 406 407 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS, &value); 408 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value); 409 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_GTJUMBO_PKTS, &value); 410 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value); 411 412 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BAD_FCS_PKTS, &value); 413 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FCS_ERRORS]), &value); 414 415 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_OVERFLOW_PKTS, &value); 416 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_DROP_EVENTS]), &value); 417 418 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_FALSE_CARRIER_PKTS, &value); 419 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FALSE_CARRIER_ERRORS]), &value); 420 421 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS, &value); 422 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_SYMBOL_ERRORS]), &value); 423 424 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_ALIGN_ERROR_PKTS, &value); 425 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_ALIGN_ERRORS]), &value); 426 427 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS, &value); 428 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_INTERNAL_ERRORS]), &value); 429 430 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_JABBER_PKTS, &value); 431 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_JABBER_PKTS]), &value); 432 433 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_CHAR_ERR, &value); 434 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_CHAR_ERR]), 435 &(value.eq_dword[0])); 436 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_CHAR_ERR]), 437 &(value.eq_dword[1])); 438 439 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_CHAR_ERR, &value); 440 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_CHAR_ERR]), 441 &(value.eq_dword[0])); 442 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_CHAR_ERR]), 443 &(value.eq_dword[1])); 444 445 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_DISP_ERR, &value); 446 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_DISP_ERR]), 447 &(value.eq_dword[0])); 448 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_DISP_ERR]), 449 &(value.eq_dword[1])); 450 451 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_DISP_ERR, &value); 452 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_DISP_ERR]), 453 &(value.eq_dword[0])); 454 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_DISP_ERR]), 455 &(value.eq_dword[1])); 456 457 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MATCH_FAULT, &value); 458 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MATCH_FAULT]), &value); 459 460 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_NODESC_DROPS, &value); 461 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_NODESC_DROP_CNT]), &value); 462 463 EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFSYS_MEM_SIZE(esmp)); 464 EFSYS_MEM_READ_BARRIER(); 465 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_GENERATION_START, 466 &generation_start); 467 468 /* Check that we didn't read the stats in the middle of a DMA */ 469 /* Not a good enough check ? */ 470 if (memcmp(&generation_start, &generation_end, 471 sizeof (generation_start))) 472 return (EAGAIN); 473 474 if (generationp) 475 *generationp = EFX_QWORD_FIELD(generation_start, EFX_DWORD_0); 476 477 return (0); 478 479fail2: 480 EFSYS_PROBE(fail2); 481fail1: 482 EFSYS_PROBE1(fail1, efx_rc_t, rc); 483 484 return (rc); 485} 486 487#endif /* EFSYS_OPT_MAC_STATS */ 488 489 __checkReturn efx_rc_t 490siena_mac_pdu_get( 491 __in efx_nic_t *enp, 492 __out size_t *pdu) 493{ 494 return (ENOTSUP); 495} 496 497#endif /* EFSYS_OPT_SIENA */ 498