1/*- 2 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#ifndef R12A_TX_DESC_H 28#define R12A_TX_DESC_H 29 30/* Tx MAC descriptor (common part). */ 31struct r12a_tx_desc { 32 uint16_t pktlen; 33 uint8_t offset; 34 uint8_t flags0; 35#define R12A_FLAGS0_BMCAST 0x01 36#define R12A_FLAGS0_LSG 0x04 37#define R12A_FLAGS0_FSG 0x08 38#define R12A_FLAGS0_OWN 0x80 39 40 uint32_t txdw1; 41#define R12A_TXDW1_MACID_M 0x0000003f 42#define R12A_TXDW1_MACID_S 0 43#define R12A_TXDW1_QSEL_M 0x00001f00 44#define R12A_TXDW1_QSEL_S 8 45 46#define R12A_TXDW1_QSEL_BE 0x00 /* or 0x03 */ 47#define R12A_TXDW1_QSEL_BK 0x01 /* or 0x02 */ 48#define R12A_TXDW1_QSEL_VI 0x04 /* or 0x05 */ 49#define R12A_TXDW1_QSEL_VO 0x06 /* or 0x07 */ 50#define RTWN_MAX_TID 8 51 52#define R12A_TXDW1_QSEL_BEACON 0x10 53#define R12A_TXDW1_QSEL_MGNT 0x12 54 55#define R12A_TXDW1_RAID_M 0x001f0000 56#define R12A_TXDW1_RAID_S 16 57#define R12A_TXDW1_CIPHER_M 0x00c00000 58#define R12A_TXDW1_CIPHER_S 22 59#define R12A_TXDW1_CIPHER_NONE 0 60#define R12A_TXDW1_CIPHER_RC4 1 61#define R12A_TXDW1_CIPHER_SM4 2 62#define R12A_TXDW1_CIPHER_AES 3 63#define R12A_TXDW1_PKTOFF_M 0x1f000000 64#define R12A_TXDW1_PKTOFF_S 24 65 66 uint32_t txdw2; 67#define R12A_TXDW2_AGGEN 0x00001000 68#define R12A_TXDW2_AGGBK 0x00010000 69#define R12A_TXDW2_MOREFRAG 0x00020000 70#define R12A_TXDW2_SPE_RPT 0x00080000 71#define R12A_TXDW2_AMPDU_DEN_M 0x00700000 72#define R12A_TXDW2_AMPDU_DEN_S 20 73 74 uint32_t txdw3; 75#define R12A_TXDW3_SEQ_SEL_M 0x000000c0 76#define R12A_TXDW3_SEQ_SEL_S 6 77#define R12A_TXDW3_DRVRATE 0x00000100 78#define R12A_TXDW3_DISRTSFB 0x00000200 79#define R12A_TXDW3_DISDATAFB 0x00000400 80#define R12A_TXDW3_CTS2SELF 0x00000800 81#define R12A_TXDW3_RTSEN 0x00001000 82#define R12A_TXDW3_HWRTSEN 0x00002000 83#define R12A_TXDW3_MAX_AGG_M 0x003e0000 84#define R12A_TXDW3_MAX_AGG_S 17 85 86 uint32_t txdw4; 87#define R12A_TXDW4_DATARATE_M 0x0000007f 88#define R12A_TXDW4_DATARATE_S 0 89#define R12A_TXDW4_DATARATE_FB_LMT_M 0x00001f00 90#define R12A_TXDW4_DATARATE_FB_LMT_S 8 91#define R12A_TXDW4_RTSRATE_FB_LMT_M 0x0001e000 92#define R12A_TXDW4_RTSRATE_FB_LMT_S 13 93#define R12A_TXDW4_RETRY_LMT_ENA 0x00020000 94#define R12A_TXDW4_RETRY_LMT_M 0x00fc0000 95#define R12A_TXDW4_RETRY_LMT_S 18 96#define R12A_TXDW4_RTSRATE_M 0x1f000000 97#define R12A_TXDW4_RTSRATE_S 24 98 99 uint32_t txdw5; 100#define R12A_TXDW5_DATA_PRIM_CHAN_M 0x0000000f 101#define R12A_TXDW5_DATA_PRIM_CHAN_S 0 102#define R12A_TXDW5_PRIM_CHAN_20_80_3 1 103#define R12A_TXDW5_PRIM_CHAN_20_80_2 2 104#define R12A_TXDW5_PRIM_CHAN_20_80_4 3 105#define R12A_TXDW5_PRIM_CHAN_20_80_1 4 106#define R12A_TXDW5_PRIM_CHAN_40_80_1 9 107#define R12A_TXDW5_PRIM_CHAN_40_80_2 10 108#define R12A_TXDW5_DATA_SHORT 0x00000010 109#define R12A_TXDW5_DATA_BW_M 0x00000060 110#define R12A_TXDW5_DATA_BW_S 5 111#define R12A_TXDW5_DATA_BW40 1 112#define R12A_TXDW5_DATA_BW80 2 113#define R12A_TXDW5_DATA_LDPC 0x00000080 114#define R12A_TXDW5_RTS_SHORT 0x00001000 115#define R12A_TXDW5_RTS_PRIM_CHAN_M 0x0001e000 116#define R12A_TXDW5_RTS_PRIM_CHAN_S 13 117 118 uint32_t txdw6; 119#define R21A_TXDW6_MBSSID_M 0x0000f000 120#define R21A_TXDW6_MBSSID_S 12 121 122 uint32_t reserved; 123 uint32_t txdw8; 124#define R12A_TXDW8_HWSEQ_EN 0x00008000 125 126 uint32_t txdw9; 127#define R12A_TXDW9_SEQ_M 0x00fff000 128#define R12A_TXDW9_SEQ_S 12 129} __packed __attribute__((aligned(4))); 130 131/* Rate adaptation modes. */ 132#define R12A_RAID_11BGN_2_40 0 133#define R12A_RAID_11BGN_1_40 1 134#define R12A_RAID_11BGN_2 2 135#define R12A_RAID_11BGN_1 3 136#define R12A_RAID_11GN_2 4 137#define R12A_RAID_11GN_1 5 138#define R12A_RAID_11BG 6 139#define R12A_RAID_11G 7 /* "pure" 11g */ 140#define R12A_RAID_11B 8 141#define R12A_RAID_11AC_2_80 9 142#define R12A_RAID_11AC_1_80 10 143#define R12A_RAID_11AC_1 11 144#define R12A_RAID_11AC_2 12 145 146#endif /* R12A_TX_DESC_H */ 147