1/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21#include <sys/cdefs.h> 22#include "opt_wlan.h" 23 24#include <sys/param.h> 25#include <sys/lock.h> 26#include <sys/mutex.h> 27#include <sys/mbuf.h> 28#include <sys/kernel.h> 29#include <sys/socket.h> 30#include <sys/systm.h> 31#include <sys/malloc.h> 32#include <sys/queue.h> 33#include <sys/taskqueue.h> 34#include <sys/bus.h> 35#include <sys/endian.h> 36#include <sys/linker.h> 37 38#include <net/if.h> 39#include <net/ethernet.h> 40#include <net/if_media.h> 41 42#include <net80211/ieee80211_var.h> 43#include <net80211/ieee80211_radiotap.h> 44 45#include <dev/rtwn/if_rtwnreg.h> 46#include <dev/rtwn/if_rtwnvar.h> 47 48#include <dev/rtwn/if_rtwn_debug.h> 49#include <dev/rtwn/if_rtwn_ridx.h> 50 51#include <dev/rtwn/rtl8192c/r92c.h> 52#include <dev/rtwn/rtl8192c/r92c_priv.h> 53#include <dev/rtwn/rtl8192c/r92c_reg.h> 54#include <dev/rtwn/rtl8192c/r92c_var.h> 55 56static int 57r92c_get_power_group(struct rtwn_softc *sc, struct ieee80211_channel *c) 58{ 59 uint8_t chan; 60 int group; 61 62 chan = rtwn_chan2centieee(c); 63 if (IEEE80211_IS_CHAN_2GHZ(c)) { 64 if (chan <= 3) group = 0; 65 else if (chan <= 9) group = 1; 66 else if (chan <= 14) group = 2; 67 else { 68 KASSERT(0, ("wrong 2GHz channel %d!\n", chan)); 69 return (-1); 70 } 71 } else { 72 KASSERT(0, ("wrong channel band (flags %08X)\n", c->ic_flags)); 73 return (-1); 74 } 75 76 return (group); 77} 78 79/* XXX recheck */ 80void 81r92c_get_txpower(struct rtwn_softc *sc, int chain, 82 struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT]) 83{ 84 struct r92c_softc *rs = sc->sc_priv; 85 struct rtwn_r92c_txpwr *rt = rs->rs_txpwr; 86 const struct rtwn_r92c_txagc *base = rs->rs_txagc; 87 uint8_t ofdmpow, htpow, diff, max; 88 int max_mcs, ridx, group; 89 90 /* Determine channel group. */ 91 group = r92c_get_power_group(sc, c); 92 if (group == -1) { /* shouldn't happen */ 93 device_printf(sc->sc_dev, "%s: incorrect channel\n", __func__); 94 return; 95 } 96 97 /* XXX net80211 regulatory */ 98 99 max_mcs = RTWN_RIDX_HT_MCS(sc->ntxchains * 8 - 1); 100 KASSERT(max_mcs <= RTWN_RIDX_COUNT, ("increase ridx limit\n")); 101 102 if (rs->regulatory == 0) { 103 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) 104 power[ridx] = base[chain].pwr[0][ridx]; 105 } 106 for (ridx = RTWN_RIDX_OFDM6; ridx < RTWN_RIDX_COUNT; ridx++) { 107 if (rs->regulatory == 3) { 108 power[ridx] = base[chain].pwr[0][ridx]; 109 /* Apply vendor limits. */ 110 if (IEEE80211_IS_CHAN_HT40(c)) 111 max = rt->ht40_max_pwr[chain][group]; 112 else 113 max = rt->ht20_max_pwr[chain][group]; 114 if (power[ridx] > max) 115 power[ridx] = max; 116 } else if (rs->regulatory == 1) { 117 if (!IEEE80211_IS_CHAN_HT40(c)) 118 power[ridx] = base[chain].pwr[group][ridx]; 119 } else if (rs->regulatory != 2) 120 power[ridx] = base[chain].pwr[0][ridx]; 121 } 122 123 /* Compute per-CCK rate Tx power. */ 124 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) 125 power[ridx] += rt->cck_tx_pwr[chain][group]; 126 127 htpow = rt->ht40_1s_tx_pwr[chain][group]; 128 if (sc->ntxchains > 1) { 129 /* Apply reduction for 2 spatial streams. */ 130 diff = rt->ht40_2s_tx_pwr_diff[chain][group]; 131 htpow = (htpow > diff) ? htpow - diff : 0; 132 } 133 134 /* Compute per-OFDM rate Tx power. */ 135 diff = rt->ofdm_tx_pwr_diff[chain][group]; 136 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 137 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++) 138 power[ridx] += ofdmpow; 139 140 /* Compute per-MCS Tx power. */ 141 if (!IEEE80211_IS_CHAN_HT40(c)) { 142 diff = rt->ht20_tx_pwr_diff[chain][group]; 143 htpow += diff; /* HT40->HT20 correction. */ 144 } 145 for (ridx = RTWN_RIDX_HT_MCS(0); ridx <= max_mcs; ridx++) 146 power[ridx] += htpow; 147 148 /* Apply max limit. */ 149 for (ridx = RTWN_RIDX_CCK1; ridx <= max_mcs; ridx++) { 150 if (power[ridx] > R92C_MAX_TX_PWR) 151 power[ridx] = R92C_MAX_TX_PWR; 152 } 153} 154 155void 156r92c_write_txpower(struct rtwn_softc *sc, int chain, 157 uint8_t power[RTWN_RIDX_COUNT]) 158{ 159 uint32_t reg; 160 161 /* Write per-CCK rate Tx power. */ 162 if (chain == 0) { 163 reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 164 reg = RW(reg, R92C_TXAGC_A_CCK1, power[RTWN_RIDX_CCK1]); 165 rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 166 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 167 reg = RW(reg, R92C_TXAGC_A_CCK2, power[RTWN_RIDX_CCK2]); 168 reg = RW(reg, R92C_TXAGC_A_CCK55, power[RTWN_RIDX_CCK55]); 169 reg = RW(reg, R92C_TXAGC_A_CCK11, power[RTWN_RIDX_CCK11]); 170 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 171 } else { 172 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 173 reg = RW(reg, R92C_TXAGC_B_CCK1, power[RTWN_RIDX_CCK1]); 174 reg = RW(reg, R92C_TXAGC_B_CCK2, power[RTWN_RIDX_CCK2]); 175 reg = RW(reg, R92C_TXAGC_B_CCK55, power[RTWN_RIDX_CCK55]); 176 rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 177 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 178 reg = RW(reg, R92C_TXAGC_B_CCK11, power[RTWN_RIDX_CCK11]); 179 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 180 } 181 /* Write per-OFDM rate Tx power. */ 182 rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 183 SM(R92C_TXAGC_RATE06, power[RTWN_RIDX_OFDM6]) | 184 SM(R92C_TXAGC_RATE09, power[RTWN_RIDX_OFDM9]) | 185 SM(R92C_TXAGC_RATE12, power[RTWN_RIDX_OFDM12]) | 186 SM(R92C_TXAGC_RATE18, power[RTWN_RIDX_OFDM18])); 187 rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 188 SM(R92C_TXAGC_RATE24, power[RTWN_RIDX_OFDM24]) | 189 SM(R92C_TXAGC_RATE36, power[RTWN_RIDX_OFDM36]) | 190 SM(R92C_TXAGC_RATE48, power[RTWN_RIDX_OFDM48]) | 191 SM(R92C_TXAGC_RATE54, power[RTWN_RIDX_OFDM54])); 192 /* Write per-MCS Tx power. */ 193 rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 194 SM(R92C_TXAGC_MCS00, power[RTWN_RIDX_HT_MCS(0)]) | 195 SM(R92C_TXAGC_MCS01, power[RTWN_RIDX_HT_MCS(1)]) | 196 SM(R92C_TXAGC_MCS02, power[RTWN_RIDX_HT_MCS(2)]) | 197 SM(R92C_TXAGC_MCS03, power[RTWN_RIDX_HT_MCS(3)])); 198 rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 199 SM(R92C_TXAGC_MCS04, power[RTWN_RIDX_HT_MCS(4)]) | 200 SM(R92C_TXAGC_MCS05, power[RTWN_RIDX_HT_MCS(5)]) | 201 SM(R92C_TXAGC_MCS06, power[RTWN_RIDX_HT_MCS(6)]) | 202 SM(R92C_TXAGC_MCS07, power[RTWN_RIDX_HT_MCS(7)])); 203 if (sc->ntxchains >= 2) { 204 rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 205 SM(R92C_TXAGC_MCS08, power[RTWN_RIDX_HT_MCS(8)]) | 206 SM(R92C_TXAGC_MCS09, power[RTWN_RIDX_HT_MCS(9)]) | 207 SM(R92C_TXAGC_MCS10, power[RTWN_RIDX_HT_MCS(10)]) | 208 SM(R92C_TXAGC_MCS11, power[RTWN_RIDX_HT_MCS(11)])); 209 rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 210 SM(R92C_TXAGC_MCS12, power[RTWN_RIDX_HT_MCS(12)]) | 211 SM(R92C_TXAGC_MCS13, power[RTWN_RIDX_HT_MCS(13)]) | 212 SM(R92C_TXAGC_MCS14, power[RTWN_RIDX_HT_MCS(14)]) | 213 SM(R92C_TXAGC_MCS15, power[RTWN_RIDX_HT_MCS(15)])); 214 } 215} 216 217static void 218r92c_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c) 219{ 220 uint8_t power[RTWN_RIDX_COUNT]; 221 int i; 222 223 for (i = 0; i < sc->ntxchains; i++) { 224 memset(power, 0, sizeof(power)); 225 /* Compute per-rate Tx power values. */ 226 rtwn_r92c_get_txpower(sc, i, c, power); 227#ifdef RTWN_DEBUG 228 if (sc->sc_debug & RTWN_DEBUG_TXPWR) { 229 int max_mcs, ridx; 230 231 max_mcs = RTWN_RIDX_HT_MCS(sc->ntxchains * 8 - 1); 232 233 /* Dump per-rate Tx power values. */ 234 printf("Tx power for chain %d:\n", i); 235 for (ridx = RTWN_RIDX_CCK1; ridx <= max_mcs; ridx++) 236 printf("Rate %d = %u\n", ridx, power[ridx]); 237 } 238#endif 239 /* Write per-rate Tx power values to hardware. */ 240 r92c_write_txpower(sc, i, power); 241 } 242} 243 244static void 245r92c_set_bw40(struct rtwn_softc *sc, uint8_t chan, int prichlo) 246{ 247 struct r92c_softc *rs = sc->sc_priv; 248 249 rtwn_setbits_1(sc, R92C_BWOPMODE, R92C_BWOPMODE_20MHZ, 0); 250 rtwn_setbits_1(sc, R92C_RRSR + 2, 0x6f, (prichlo ? 1 : 2) << 5); 251 252 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_40MHZ); 253 rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, 0, R92C_RFMOD_40MHZ); 254 255 /* Set CCK side band. */ 256 rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 0x10, 257 (prichlo ? 0 : 1) << 4); 258 259 rtwn_bb_setbits(sc, R92C_OFDM1_LSTF, 0x0c00, 260 (prichlo ? 1 : 2) << 10); 261 262 rtwn_bb_setbits(sc, R92C_FPGA0_ANAPARAM2, 263 R92C_FPGA0_ANAPARAM2_CBW20, 0); 264 265 rtwn_bb_setbits(sc, 0x818, 0x0c000000, (prichlo ? 2 : 1) << 26); 266 267 /* Select 40MHz bandwidth. */ 268 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 269 (rs->rf_chnlbw[0] & ~0xfff) | chan); 270} 271 272void 273r92c_set_bw20(struct rtwn_softc *sc, uint8_t chan) 274{ 275 struct r92c_softc *rs = sc->sc_priv; 276 277 rtwn_setbits_1(sc, R92C_BWOPMODE, 0, R92C_BWOPMODE_20MHZ); 278 279 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, R92C_RFMOD_40MHZ, 0); 280 rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, R92C_RFMOD_40MHZ, 0); 281 282 rtwn_bb_setbits(sc, R92C_FPGA0_ANAPARAM2, 0, 283 R92C_FPGA0_ANAPARAM2_CBW20); 284 285 /* Select 20MHz bandwidth. */ 286 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 287 (rs->rf_chnlbw[0] & ~0xfff) | chan | R92C_RF_CHNLBW_BW20); 288} 289 290void 291r92c_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c) 292{ 293 struct r92c_softc *rs = sc->sc_priv; 294 u_int chan; 295 int i; 296 297 chan = rtwn_chan2centieee(c); 298 299 /* Set Tx power for this new channel. */ 300 r92c_set_txpower(sc, c); 301 302 for (i = 0; i < sc->nrxchains; i++) { 303 rtwn_rf_write(sc, i, R92C_RF_CHNLBW, 304 RW(rs->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 305 } 306 if (IEEE80211_IS_CHAN_HT40(c)) 307 r92c_set_bw40(sc, chan, IEEE80211_IS_CHAN_HT40U(c)); 308 else 309 rtwn_r92c_set_bw20(sc, chan); 310} 311 312void 313r92c_set_gain(struct rtwn_softc *sc, uint8_t gain) 314{ 315 316 rtwn_bb_setbits(sc, R92C_OFDM0_AGCCORE1(0), 317 R92C_OFDM0_AGCCORE1_GAIN_M, gain); 318 rtwn_bb_setbits(sc, R92C_OFDM0_AGCCORE1(1), 319 R92C_OFDM0_AGCCORE1_GAIN_M, gain); 320} 321 322void 323r92c_scan_start(struct ieee80211com *ic) 324{ 325 struct rtwn_softc *sc = ic->ic_softc; 326 struct r92c_softc *rs = sc->sc_priv; 327 328 RTWN_LOCK(sc); 329 /* Set gain for scanning. */ 330 rtwn_r92c_set_gain(sc, 0x20); 331 RTWN_UNLOCK(sc); 332 333 rs->rs_scan_start(ic); 334} 335 336void 337r92c_scan_end(struct ieee80211com *ic) 338{ 339 struct rtwn_softc *sc = ic->ic_softc; 340 struct r92c_softc *rs = sc->sc_priv; 341 342 RTWN_LOCK(sc); 343 /* Set gain under link. */ 344 rtwn_r92c_set_gain(sc, 0x32); 345 RTWN_UNLOCK(sc); 346 347 rs->rs_scan_end(ic); 348} 349