1/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21#include <sys/cdefs.h> 22#include "opt_wlan.h" 23 24#include <sys/param.h> 25#include <sys/lock.h> 26#include <sys/mutex.h> 27#include <sys/mbuf.h> 28#include <sys/kernel.h> 29#include <sys/socket.h> 30#include <sys/systm.h> 31#include <sys/malloc.h> 32#include <sys/queue.h> 33#include <sys/taskqueue.h> 34#include <sys/bus.h> 35#include <sys/endian.h> 36#include <sys/linker.h> 37 38#include <net/if.h> 39#include <net/ethernet.h> 40#include <net/if_media.h> 41 42#include <net80211/ieee80211_var.h> 43#include <net80211/ieee80211_radiotap.h> 44 45#include <dev/rtwn/if_rtwnreg.h> 46#include <dev/rtwn/if_rtwnvar.h> 47#include <dev/rtwn/if_rtwn_debug.h> 48 49#include <dev/rtwn/rtl8192c/r92c.h> 50#include <dev/rtwn/rtl8192c/r92c_reg.h> 51 52/* Registers to save and restore during IQ calibration. */ 53struct r92c_iq_cal_reg_vals { 54 uint32_t adda[16]; 55 uint8_t txpause; 56 uint8_t bcn_ctrl[2]; 57 uint32_t gpio_muxcfg; 58 uint32_t cck0_afesetting; 59 uint32_t ofdm0_trxpathena; 60 uint32_t ofdm0_trmuxpar; 61 uint32_t fpga0_rfifacesw0; 62 uint32_t fpga0_rfifacesw1; 63 uint32_t fpga0_rfifaceoe0; 64 uint32_t fpga0_rfifaceoe1; 65 uint32_t config_ant0; 66 uint32_t config_ant1; 67}; 68 69/* XXX TODO: merge */ 70static int 71r92c_iq_calib_chain(struct rtwn_softc *sc, int chain, uint16_t tx[2], 72 uint16_t rx[2]) 73{ 74 uint32_t status; 75 76 if (chain == 0) { /* IQ calibration for chain 0. */ 77 /* IQ calibration settings for chain 0. */ 78 rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x10008c1f); 79 rtwn_bb_write(sc, R92C_RX_IQK_TONE(0), 0x10008c1f); 80 rtwn_bb_write(sc, R92C_TX_IQK_PI(0), 0x82140102); 81 82 if (sc->ntxchains > 1) { 83 rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160202); 84 /* IQ calibration settings for chain 1. */ 85 rtwn_bb_write(sc, R92C_TX_IQK_TONE(1), 0x10008c22); 86 rtwn_bb_write(sc, R92C_RX_IQK_TONE(1), 0x10008c22); 87 rtwn_bb_write(sc, R92C_TX_IQK_PI(1), 0x82140102); 88 rtwn_bb_write(sc, R92C_RX_IQK_PI(1), 0x28160202); 89 } else 90 rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160502); 91 92 /* LO calibration settings. */ 93 rtwn_bb_write(sc, R92C_IQK_AGC_RSP, 0x001028d1); 94 /* We're doing LO and IQ calibration in one shot. */ 95 rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf9000000); 96 rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf8000000); 97 98 } else { /* IQ calibration for chain 1. */ 99 /* We're doing LO and IQ calibration in one shot. */ 100 rtwn_bb_write(sc, R92C_IQK_AGC_CONT, 2); 101 rtwn_bb_write(sc, R92C_IQK_AGC_CONT, 0); 102 } 103 104 /* Give LO and IQ calibrations the time to complete. */ 105 rtwn_delay(sc, 10000); 106 107 /* Read IQ calibration status. */ 108 status = rtwn_bb_read(sc, R92C_RX_POWER_IQK_AFTER(0)); 109 110 if (status & (1 << (28 + chain * 3))) 111 return (0); /* Tx failed. */ 112 /* Read Tx IQ calibration results. */ 113 tx[0] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_BEFORE(chain)), 114 R92C_POWER_IQK_RESULT); 115 tx[1] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_AFTER(chain)), 116 R92C_POWER_IQK_RESULT); 117 if (tx[0] == 0x142 || tx[1] == 0x042) 118 return (0); /* Tx failed. */ 119 120 if (status & (1 << (27 + chain * 3))) 121 return (1); /* Rx failed. */ 122 /* Read Rx IQ calibration results. */ 123 rx[0] = MS(rtwn_bb_read(sc, R92C_RX_POWER_IQK_BEFORE(chain)), 124 R92C_POWER_IQK_RESULT); 125 rx[1] = MS(rtwn_bb_read(sc, R92C_RX_POWER_IQK_AFTER(chain)), 126 R92C_POWER_IQK_RESULT); 127 if (rx[0] == 0x132 || rx[1] == 0x036) 128 return (1); /* Rx failed. */ 129 130 return (3); /* Both Tx and Rx succeeded. */ 131} 132 133static void 134r92c_iq_calib_run(struct rtwn_softc *sc, int n, uint16_t tx[2][2], 135 uint16_t rx[2][2], struct r92c_iq_cal_reg_vals *vals) 136{ 137 /* Registers to save and restore during IQ calibration. */ 138 static const uint16_t reg_adda[16] = { 139 0x85c, 0xe6c, 0xe70, 0xe74, 140 0xe78, 0xe7c, 0xe80, 0xe84, 141 0xe88, 0xe8c, 0xed0, 0xed4, 142 0xed8, 0xedc, 0xee0, 0xeec 143 }; 144 int i, chain; 145 uint32_t hssi_param1; 146 147 if (n == 0) { 148 for (i = 0; i < nitems(reg_adda); i++) 149 vals->adda[i] = rtwn_bb_read(sc, reg_adda[i]); 150 151 vals->txpause = rtwn_read_1(sc, R92C_TXPAUSE); 152 vals->bcn_ctrl[0] = rtwn_read_1(sc, R92C_BCN_CTRL(0)); 153 vals->bcn_ctrl[1] = rtwn_read_1(sc, R92C_BCN_CTRL(1)); 154 vals->gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG); 155 } 156 157 if (sc->ntxchains == 1) { 158 rtwn_bb_write(sc, reg_adda[0], 0x0b1b25a0); 159 for (i = 1; i < nitems(reg_adda); i++) 160 rtwn_bb_write(sc, reg_adda[i], 0x0bdb25a0); 161 } else { 162 for (i = 0; i < nitems(reg_adda); i++) 163 rtwn_bb_write(sc, reg_adda[i], 0x04db25a4); 164 } 165 166 hssi_param1 = rtwn_bb_read(sc, R92C_HSSI_PARAM1(0)); 167 if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) { 168 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 169 hssi_param1 | R92C_HSSI_PARAM1_PI); 170 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 171 hssi_param1 | R92C_HSSI_PARAM1_PI); 172 } 173 174 if (n == 0) { 175 vals->cck0_afesetting = rtwn_bb_read(sc, R92C_CCK0_AFESETTING); 176 vals->ofdm0_trxpathena = 177 rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 178 vals->ofdm0_trmuxpar = rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 179 vals->fpga0_rfifacesw0 = 180 rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(0)); 181 vals->fpga0_rfifacesw1 = 182 rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 183 vals->fpga0_rfifaceoe0 = 184 rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0)); 185 vals->fpga0_rfifaceoe1 = 186 rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(1)); 187 vals->config_ant0 = rtwn_bb_read(sc, R92C_CONFIG_ANT(0)); 188 vals->config_ant1 = rtwn_bb_read(sc, R92C_CONFIG_ANT(1)); 189 } 190 191 rtwn_bb_setbits(sc, R92C_CCK0_AFESETTING, 0, 0x0f000000); 192 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 0x03a05600); 193 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, 0x000800e4); 194 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000); 195 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACESW(0), 0, 0x04000400); 196 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(0), 0x400, 0); 197 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(1), 0x400, 0); 198 199 if (sc->ntxchains > 1) { 200 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000); 201 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00010000); 202 } 203 204 rtwn_write_1(sc, R92C_TXPAUSE, 205 R92C_TX_QUEUE_AC | R92C_TX_QUEUE_MGT | R92C_TX_QUEUE_HIGH); 206 rtwn_write_1(sc, R92C_BCN_CTRL(0), 207 vals->bcn_ctrl[0] & ~R92C_BCN_CTRL_EN_BCN); 208 rtwn_write_1(sc, R92C_BCN_CTRL(1), 209 vals->bcn_ctrl[1] & ~R92C_BCN_CTRL_EN_BCN); 210 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 211 vals->gpio_muxcfg & ~R92C_GPIO_MUXCFG_ENBT); 212 213 rtwn_bb_write(sc, R92C_CONFIG_ANT(0), 0x00080000); 214 if (sc->ntxchains > 1) 215 rtwn_bb_write(sc, R92C_CONFIG_ANT(1), 0x00080000); 216 217 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000); 218 rtwn_bb_write(sc, R92C_TX_IQK, 0x01007c00); 219 rtwn_bb_write(sc, R92C_RX_IQK, 0x01004800); 220 221 for (chain = 0; chain < sc->ntxchains; chain++) { 222 if (chain > 0) { 223 /* Put chain 0 on standby. */ 224 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0); 225 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000); 226 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000); 227 228 /* Enable chain 1. */ 229 for (i = 0; i < nitems(reg_adda); i++) 230 rtwn_bb_write(sc, reg_adda[i], 0x0b1b25a4); 231 } 232 233 /* Run IQ calibration twice. */ 234 for (i = 0; i < 2; i++) { 235 int ret; 236 237 ret = r92c_iq_calib_chain(sc, chain, 238 tx[chain], rx[chain]); 239 if (ret == 0) { 240 RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB, 241 "%s: chain %d: Tx failed.\n", 242 __func__, chain); 243 tx[chain][0] = 0xff; 244 tx[chain][1] = 0xff; 245 rx[chain][0] = 0xff; 246 rx[chain][1] = 0xff; 247 } else if (ret == 1) { 248 RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB, 249 "%s: chain %d: Rx failed.\n", 250 __func__, chain); 251 rx[chain][0] = 0xff; 252 rx[chain][1] = 0xff; 253 } else if (ret == 3) { 254 RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB, 255 "%s: chain %d: Both Tx and Rx " 256 "succeeded.\n", __func__, chain); 257 } 258 } 259 260 RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB, 261 "%s: results for run %d chain %d: tx[0] 0x%x, " 262 "tx[1] 0x%x, rx[0] 0x%x, rx[1] 0x%x\n", __func__, n, chain, 263 tx[chain][0], tx[chain][1], rx[chain][0], rx[chain][1]); 264 } 265 266 rtwn_bb_write(sc, R92C_CCK0_AFESETTING, vals->cck0_afesetting); 267 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, vals->ofdm0_trxpathena); 268 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(0), vals->fpga0_rfifacesw0); 269 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), vals->fpga0_rfifacesw1); 270 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, vals->ofdm0_trmuxpar); 271 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0), vals->fpga0_rfifaceoe0); 272 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1), vals->fpga0_rfifaceoe1); 273 rtwn_bb_write(sc, R92C_CONFIG_ANT(0), vals->config_ant0); 274 rtwn_bb_write(sc, R92C_CONFIG_ANT(1), vals->config_ant1); 275 276 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0); 277 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00032ed3); 278 if (sc->ntxchains > 1) 279 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00032ed3); 280 281 if (n != 0) { 282 if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) { 283 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), hssi_param1); 284 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), hssi_param1); 285 } 286 287 for (i = 0; i < nitems(reg_adda); i++) 288 rtwn_bb_write(sc, reg_adda[i], vals->adda[i]); 289 290 rtwn_write_1(sc, R92C_TXPAUSE, vals->txpause); 291 rtwn_write_1(sc, R92C_BCN_CTRL(0), vals->bcn_ctrl[0]); 292 rtwn_write_1(sc, R92C_BCN_CTRL(1), vals->bcn_ctrl[1]); 293 rtwn_write_4(sc, R92C_GPIO_MUXCFG, vals->gpio_muxcfg); 294 295 rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x01008c00); 296 rtwn_bb_write(sc, R92C_RX_IQK_TONE(0), 0x01008c00); 297 } 298} 299 300#define RTWN_IQ_CAL_MAX_TOLERANCE 5 301static int 302r92c_iq_calib_compare_results(struct rtwn_softc *sc, uint16_t tx1[2][2], 303 uint16_t rx1[2][2], uint16_t tx2[2][2], uint16_t rx2[2][2]) 304{ 305 int chain, i, tx_ok[2], rx_ok[2]; 306 307 tx_ok[0] = tx_ok[1] = rx_ok[0] = rx_ok[1] = 0; 308 for (chain = 0; chain < sc->ntxchains; chain++) { 309 for (i = 0; i < 2; i++) { 310 if (tx1[chain][i] == 0xff || tx2[chain][i] == 0xff || 311 rx1[chain][i] == 0xff || rx2[chain][i] == 0xff) 312 continue; 313 314 tx_ok[chain] = (abs(tx1[chain][i] - tx2[chain][i]) <= 315 RTWN_IQ_CAL_MAX_TOLERANCE); 316 317 rx_ok[chain] = (abs(rx1[chain][i] - rx2[chain][i]) <= 318 RTWN_IQ_CAL_MAX_TOLERANCE); 319 } 320 } 321 322 if (sc->ntxchains > 1) 323 return (tx_ok[0] && tx_ok[1] && rx_ok[0] && rx_ok[1]); 324 else 325 return (tx_ok[0] && rx_ok[0]); 326} 327#undef RTWN_IQ_CAL_MAX_TOLERANCE 328 329static void 330r92c_iq_calib_write_results(struct rtwn_softc *sc, uint16_t tx[2], 331 uint16_t rx[2], int chain) 332{ 333 uint32_t reg, val, x; 334 long y, tx_c; 335 336 if (tx[0] == 0xff || tx[1] == 0xff) 337 return; 338 339 reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain)); 340 val = ((reg >> 22) & 0x3ff); 341 x = tx[0]; 342 if (x & 0x00000200) 343 x |= 0xfffffc00; 344 reg = (((x * val) >> 8) & 0x3ff); 345 rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(chain), 0x3ff, reg); 346 rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x80000000, 347 ((x * val) & 0x80) << 24); 348 349 y = tx[1]; 350 if (y & 0x00000200) 351 y |= 0xfffffc00; 352 tx_c = (y * val) >> 8; 353 rtwn_bb_setbits(sc, R92C_OFDM0_TXAFE(chain), 0xf0000000, 354 (tx_c & 0x3c0) << 22); 355 rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(chain), 0x003f0000, 356 (tx_c & 0x3f) << 16); 357 rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x20000000, 358 ((y * val) & 0x80) << 22); 359 360 if (rx[0] == 0xff || rx[1] == 0xff) 361 return; 362 363 rtwn_bb_setbits(sc, R92C_OFDM0_RXIQIMBALANCE(chain), 0x3ff, 364 rx[0] & 0x3ff); 365 rtwn_bb_setbits(sc, R92C_OFDM0_RXIQIMBALANCE(chain), 0xfc00, 366 (rx[1] & 0x3f) << 10); 367 368 if (chain == 0) { 369 rtwn_bb_setbits(sc, R92C_OFDM0_RXIQEXTANTA, 0xf0000000, 370 (rx[1] & 0x3c0) << 22); 371 } else { 372 rtwn_bb_setbits(sc, R92C_OFDM0_AGCRSSITABLE, 0xf000, 373 (rx[1] & 0x3c0) << 6); 374 } 375} 376 377#define RTWN_IQ_CAL_NRUN 3 378void 379r92c_iq_calib(struct rtwn_softc *sc) 380{ 381 struct r92c_iq_cal_reg_vals vals; 382 uint16_t tx[RTWN_IQ_CAL_NRUN][2][2], rx[RTWN_IQ_CAL_NRUN][2][2]; 383 int n, valid; 384 385 valid = 0; 386 for (n = 0; n < RTWN_IQ_CAL_NRUN; n++) { 387 r92c_iq_calib_run(sc, n, tx[n], rx[n], &vals); 388 389 if (n == 0) 390 continue; 391 392 /* Valid results remain stable after consecutive runs. */ 393 valid = r92c_iq_calib_compare_results(sc, tx[n - 1], 394 rx[n - 1], tx[n], rx[n]); 395 if (valid) 396 break; 397 } 398 399 if (valid) { 400 r92c_iq_calib_write_results(sc, tx[n][0], rx[n][0], 0); 401 if (sc->ntxchains > 1) 402 r92c_iq_calib_write_results(sc, tx[n][1], rx[n][1], 1); 403 } 404} 405#undef RTWN_IQ_CAL_NRUN 406 407void 408r92c_lc_calib(struct rtwn_softc *sc) 409{ 410 uint32_t rf_ac[2]; 411 uint8_t txmode; 412 int i; 413 414 txmode = rtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 415 if ((txmode & 0x70) != 0) { 416 /* Disable all continuous Tx. */ 417 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 418 419 /* Set RF mode to standby mode. */ 420 for (i = 0; i < sc->nrxchains; i++) { 421 rf_ac[i] = rtwn_rf_read(sc, i, R92C_RF_AC); 422 rtwn_rf_write(sc, i, R92C_RF_AC, 423 RW(rf_ac[i], R92C_RF_AC_MODE, 424 R92C_RF_AC_MODE_STANDBY)); 425 } 426 } else { 427 /* Block all Tx queues. */ 428 rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 429 } 430 /* Start calibration. */ 431 rtwn_rf_setbits(sc, 0, R92C_RF_CHNLBW, 0, R92C_RF_CHNLBW_LCSTART); 432 433 /* Give calibration the time to complete. */ 434 rtwn_delay(sc, 100000); /* 100ms */ 435 436 /* Restore configuration. */ 437 if ((txmode & 0x70) != 0) { 438 /* Restore Tx mode. */ 439 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 440 /* Restore RF mode. */ 441 for (i = 0; i < sc->nrxchains; i++) 442 rtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 443 } else { 444 /* Unblock all Tx queues. */ 445 rtwn_write_1(sc, R92C_TXPAUSE, 0x00); 446 } 447} 448 449void 450r92c_temp_measure(struct rtwn_softc *sc) 451{ 452 rtwn_rf_write(sc, 0, R92C_RF_T_METER, R92C_RF_T_METER_START); 453} 454 455uint8_t 456r92c_temp_read(struct rtwn_softc *sc) 457{ 458 return (MS(rtwn_rf_read(sc, 0, R92C_RF_T_METER), 459 R92C_RF_T_METER_VAL)); 460} 461