1/*
2 * Copyright (c) 2013-2016 Qlogic Corporation
3 * All rights reserved.
4 *
5 *  Redistribution and use in source and binary forms, with or without
6 *  modification, are permitted provided that the following conditions
7 *  are met:
8 *
9 *  1. Redistributions of source code must retain the above copyright
10 *     notice, this list of conditions and the following disclaimer.
11 *  2. Redistributions in binary form must reproduce the above copyright
12 *     notice, this list of conditions and the following disclaimer in the
13 *     documentation and/or other materials provided with the distribution.
14 *
15 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 *  POSSIBILITY OF SUCH DAMAGE.
26 */
27
28/*
29 * File: ql_minidump.h
30 */
31#ifndef _QL_MINIDUMP_H_
32#define _QL_MINIDUMP_H_
33
34#define QL_DBG_STATE_ARRAY_LEN          16
35#define QL_DBG_CAP_SIZE_ARRAY_LEN       8
36#define QL_NO_OF_OCM_WINDOWS            16
37
38typedef struct ql_mdump_tmplt_hdr {
39        uint32_t  entry_type ;
40        uint32_t  first_entry_offset ;
41        uint32_t  size_of_template ;
42        uint32_t  recommended_capture_mask;
43
44        uint32_t  num_of_entries ;
45        uint32_t  version ;
46        uint32_t  driver_timestamp ;
47        uint32_t  checksum ;
48
49        uint32_t  driver_capture_mask ;
50        uint32_t  driver_info_word2 ;
51        uint32_t  driver_info_word3 ;
52        uint32_t  driver_info_word4 ;
53
54        uint32_t  saved_state_array[QL_DBG_STATE_ARRAY_LEN] ;
55        uint32_t  capture_size_array[QL_DBG_CAP_SIZE_ARRAY_LEN] ;
56
57        uint32_t ocm_window_array[QL_NO_OF_OCM_WINDOWS] ;
58} ql_minidump_template_hdr_t ;
59
60/*
61 * MIU AGENT ADDRESSES.
62 */
63
64#define MD_TA_CTL_ENABLE                0x2
65#define MD_TA_CTL_START                 0x1
66#define MD_TA_CTL_BUSY                  0x8
67#define MD_TA_CTL_CHECK                 1000
68
69#define MD_MIU_TEST_AGT_CTRL            0x41000090
70#define MD_MIU_TEST_AGT_ADDR_LO         0x41000094
71#define MD_MIU_TEST_AGT_ADDR_HI         0x41000098
72
73#define MD_MIU_TEST_AGT_RDDATA_0_31     0x410000A8
74#define MD_MIU_TEST_AGT_RDDATA_32_63    0x410000AC
75#define MD_MIU_TEST_AGT_RDDATA_64_95    0x410000B8
76#define MD_MIU_TEST_AGT_RDDATA_96_127   0x410000BC
77
78#define MD_MIU_TEST_AGT_WRDATA_0_31     0x410000A0
79#define MD_MIU_TEST_AGT_WRDATA_32_63    0x410000A4
80#define MD_MIU_TEST_AGT_WRDATA_64_95    0x410000B0
81#define MD_MIU_TEST_AGT_WRDATA_96_127   0x410000B4
82
83/*
84 * ROM Read Address
85 */
86
87#define MD_DIRECT_ROM_WINDOW            0x42110030
88#define MD_DIRECT_ROM_READ_BASE         0x42150000
89
90/*
91 * Entry Type Defines
92 */
93
94#define RDNOP			0
95#define RDCRB			1
96#define	RDMUX			2
97#define QUEUE			3
98#define BOARD			4
99#define RDOCM			6
100#define L1DAT			11
101#define L1INS			12
102#define L2DTG                  	21
103#define L2ITG                  	22
104#define L2DAT                  	23
105#define L2INS                  	24
106#define POLLRD                  35
107#define RDMUX2                  36
108#define POLLRDMWR               37
109#define RDROM                  	71
110#define RDMEM                  	72
111#define CNTRL                  	98
112#define TLHDR                  	99
113#define RDEND			255
114
115/*
116 * Index of State Table.  The Template header maintains
117 * an array of 8 (0..7) words that is used to store some
118 * "State Information" from the board.
119 */
120
121#define QL_PCIE_FUNC_INDX       0
122#define QL_CLK_STATE_INDX       1
123#define QL_SRE_STATE_INDX       2
124#define QL_OCM0_ADDR_INDX       3
125
126#define QL_REVID_STATE_INDX     4
127#define QL_MAJVER_STATE_INDX    5
128#define QL_MINVER_STATE_INDX    6
129#define QL_SUBVER_STATE_INDX    7
130
131/*
132 * Opcodes for Control Entries.
133 * These Flags are bit fields.
134 */
135
136#define QL_DBG_OPCODE_WR        0x01
137#define QL_DBG_OPCODE_RW        0x02
138#define QL_DBG_OPCODE_AND       0x04
139#define QL_DBG_OPCODE_OR        0x08
140#define QL_DBG_OPCODE_POLL      0x10
141#define QL_DBG_OPCODE_RDSTATE   0x20
142#define QL_DBG_OPCODE_WRSTATE   0x40
143#define QL_DBG_OPCODE_MDSTATE   0x80
144
145typedef struct ql_minidump_entry_hdr_s {
146        uint32_t      entry_type ;
147        uint32_t      entry_size ;
148        uint32_t      entry_capture_size ;
149    	union {
150        	struct {
151            		uint8_t   entry_capture_mask ;
152            		uint8_t   entry_code ;
153            		uint8_t   driver_code ;
154            		uint8_t   driver_flags ;
155        	};
156        	uint32_t entry_ctrl_word ;
157    	};
158} ql_minidump_entry_hdr_t ;
159
160/*
161 * Driver Flags
162 */
163#define QL_DBG_SKIPPED_FLAG	0x80 /*  driver skipped this entry  */
164#define QL_DBG_SIZE_ERR_FLAG    0x40 /*  entry size vs capture size mismatch*/
165
166/*
167 * Generic Entry Including Header
168 */
169
170typedef struct ql_minidump_entry_s {
171        ql_minidump_entry_hdr_t hdr ;
172
173    uint32_t entry_data00 ;
174    uint32_t entry_data01 ;
175    uint32_t entry_data02 ;
176    uint32_t entry_data03 ;
177
178    uint32_t entry_data04 ;
179    uint32_t entry_data05 ;
180    uint32_t entry_data06 ;
181    uint32_t entry_data07 ;
182} ql_minidump_entry_t;
183
184/*
185 *  Read CRB Entry Header
186 */
187
188typedef struct ql_minidump_entry_rdcrb_s {
189        ql_minidump_entry_hdr_t h;
190
191        uint32_t addr ;
192    union {
193        struct {
194            uint8_t  addr_stride ;
195            uint8_t  rsvd_0;
196            uint16_t rsvd_1 ;
197        } ;
198            uint32_t addr_cntrl  ;
199    } ;
200
201        uint32_t data_size ;
202        uint32_t op_count;
203
204    uint32_t    rsvd_2 ;
205    uint32_t    rsvd_3 ;
206    uint32_t    rsvd_4 ;
207    uint32_t    rsvd_5 ;
208
209} ql_minidump_entry_rdcrb_t ;
210
211/*
212 * Cache Entry Header
213 */
214
215typedef struct ql_minidump_entry_cache_s {
216        ql_minidump_entry_hdr_t h;
217
218        uint32_t tag_reg_addr ;
219    	union {
220        	struct {
221            		uint16_t   tag_value_stride ;
222            		uint16_t  init_tag_value ;
223        	} ;
224            	uint32_t select_addr_cntrl  ;
225    	} ;
226
227        uint32_t data_size ;
228        uint32_t op_count;
229
230    	uint32_t control_addr ;
231    	union {
232        	struct {
233            		uint16_t  write_value ;
234            		uint8_t   poll_mask ;
235            		uint8_t   poll_wait ;
236        	};
237        	uint32_t control_value ;
238    	} ;
239
240    	uint32_t read_addr ;
241    	union {
242        	struct {
243            		uint8_t   read_addr_stride ;
244            		uint8_t   read_addr_cnt ;
245            		uint16_t  rsvd_1 ;
246        	} ;
247            	uint32_t read_addr_cntrl  ;
248    	} ;
249} ql_minidump_entry_cache_t ;
250
251/*
252 * Read OCM Entry Header
253 */
254
255typedef struct ql_minidump_entry_rdocm_s {
256        ql_minidump_entry_hdr_t h;
257
258        uint32_t rsvd_0 ;
259        uint32_t rsvd_1 ;
260
261        uint32_t data_size ;
262        uint32_t op_count;
263
264    uint32_t rsvd_2 ;
265    uint32_t rsvd_3 ;
266
267    uint32_t read_addr ;
268    uint32_t read_addr_stride ;
269
270} ql_minidump_entry_rdocm_t ;
271
272/*
273 * Read MEM Entry Header
274 */
275
276typedef struct ql_minidump_entry_rdmem_s {
277        ql_minidump_entry_hdr_t h;
278
279    uint32_t rsvd_0[6] ;
280
281    uint32_t read_addr ;
282    uint32_t read_data_size ;
283
284} ql_minidump_entry_rdmem_t ;
285
286/*
287 * Read ROM Entry Header
288 */
289
290typedef struct ql_minidump_entry_rdrom_s {
291        ql_minidump_entry_hdr_t h;
292
293    uint32_t rsvd_0[6] ;
294
295    uint32_t read_addr ;
296    uint32_t read_data_size ;
297
298} ql_minidump_entry_rdrom_t ;
299
300/*
301 * Read MUX Entry Header
302 */
303
304typedef struct ql_minidump_entry_mux_s {
305        ql_minidump_entry_hdr_t h;
306
307        uint32_t select_addr ;
308    union {
309        struct {
310            uint32_t rsvd_0 ;
311        } ;
312            uint32_t select_addr_cntrl  ;
313    } ;
314
315        uint32_t data_size ;
316        uint32_t op_count;
317
318    uint32_t select_value ;
319    uint32_t select_value_stride ;
320
321    uint32_t read_addr ;
322    uint32_t rsvd_1 ;
323
324} ql_minidump_entry_mux_t ;
325
326/*
327 * Read MUX2 Entry Header
328 */
329
330typedef struct ql_minidump_entry_mux2_s {
331        ql_minidump_entry_hdr_t h;
332
333        uint32_t select_addr_1;
334        uint32_t select_addr_2;
335        uint32_t select_value_1;
336        uint32_t select_value_2;
337        uint32_t select_value_count;
338        uint32_t select_value_mask;
339        uint32_t read_addr;
340        union {
341                struct {
342                        uint8_t select_value_stride;
343                        uint8_t data_size;
344                        uint8_t reserved_0;
345                        uint8_t reserved_1;
346                };
347                uint32_t select_addr_value_cntrl;
348        };
349
350} ql_minidump_entry_mux2_t;
351
352/*
353 * Read QUEUE Entry Header
354 */
355
356typedef struct ql_minidump_entry_queue_s {
357        ql_minidump_entry_hdr_t h;
358
359        uint32_t select_addr ;
360    union {
361        struct {
362            uint16_t  queue_id_stride ;
363            uint16_t  rsvd_0 ;
364        } ;
365            uint32_t select_addr_cntrl  ;
366    } ;
367
368        uint32_t data_size ;
369        uint32_t op_count ;
370
371    uint32_t rsvd_1 ;
372    uint32_t rsvd_2 ;
373
374    uint32_t read_addr ;
375    union {
376        struct {
377            uint8_t   read_addr_stride ;
378            uint8_t   read_addr_cnt ;
379            uint16_t  rsvd_3 ;
380        } ;
381            uint32_t read_addr_cntrl  ;
382    } ;
383
384} ql_minidump_entry_queue_t ;
385
386/*
387 * Control Entry Header
388 */
389
390typedef struct ql_minidump_entry_cntrl_s {
391        ql_minidump_entry_hdr_t h;
392
393        uint32_t addr ;
394    union {
395        struct {
396            uint8_t  addr_stride ;
397            uint8_t  state_index_a ;
398            uint16_t poll_timeout ;
399        } ;
400            uint32_t addr_cntrl  ;
401    } ;
402
403        uint32_t data_size ;
404        uint32_t op_count;
405
406    union {
407        struct {
408            uint8_t opcode ;
409            uint8_t state_index_v ;
410            uint8_t shl ;
411            uint8_t shr ;
412        } ;
413        uint32_t control_value ;
414    } ;
415
416    uint32_t value_1 ;
417    uint32_t value_2 ;
418    uint32_t value_3 ;
419} ql_minidump_entry_cntrl_t ;
420
421/*
422 * Read with poll.
423 */
424
425typedef struct ql_minidump_entry_rdcrb_with_poll_s {
426        ql_minidump_entry_hdr_t h;
427
428        uint32_t select_addr;
429        uint32_t read_addr;
430        uint32_t select_value;
431        union {
432                struct {
433                        uint16_t select_value_stride;
434                        uint16_t op_count;
435                };
436                uint32_t select_value_cntrl;
437        };
438
439        uint32_t poll;
440        uint32_t mask;
441
442        uint32_t data_size;
443        uint32_t rsvd_0;
444
445} ql_minidump_entry_pollrd_t;
446
447/*
448 * Read_Modify_Write with poll.
449 */
450
451typedef struct ql_minidump_entry_rd_modify_wr_with_poll_s {
452        ql_minidump_entry_hdr_t h;
453
454        uint32_t addr_1;
455        uint32_t addr_2;
456        uint32_t value_1;
457        uint32_t value_2;
458        uint32_t poll;
459        uint32_t mask;
460        uint32_t modify_mask;
461        uint32_t data_size;
462
463} ql_minidump_entry_rd_modify_wr_with_poll_t;
464
465#endif /* #ifndef _QL_MINIDUMP_H_ */
466