1/* 2 * Copyright (c) 2018-2019 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28/* 29 * File: qlnxr_os.c 30 */ 31#include <sys/cdefs.h> 32#include "qlnxr_def.h" 33 34SYSCTL_NODE(_dev, OID_AUTO, qnxr, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 35 "Qlogic RDMA module"); 36 37uint32_t delayed_ack = 0; 38SYSCTL_UINT(_dev_qnxr, OID_AUTO, delayed_ack, CTLFLAG_RW, &delayed_ack, 1, 39 "iWARP: Delayed Ack: 0 - Disabled 1 - Enabled. Default: Disabled"); 40 41uint32_t timestamp = 1; 42SYSCTL_UINT(_dev_qnxr, OID_AUTO, timestamp, CTLFLAG_RW, ×tamp, 1, 43 "iWARP: Timestamp: 0 - Disabled 1 - Enabled. Default:Enabled"); 44 45uint32_t rcv_wnd_size = 0; 46SYSCTL_UINT(_dev_qnxr, OID_AUTO, rcv_wnd_size, CTLFLAG_RW, &rcv_wnd_size, 1, 47 "iWARP: Receive Window Size in K. Default 1M"); 48 49uint32_t crc_needed = 1; 50SYSCTL_UINT(_dev_qnxr, OID_AUTO, crc_needed, CTLFLAG_RW, &crc_needed, 1, 51 "iWARP: CRC needed 0 - Disabled 1 - Enabled. Default:Enabled"); 52 53uint32_t peer2peer = 1; 54SYSCTL_UINT(_dev_qnxr, OID_AUTO, peer2peer, CTLFLAG_RW, &peer2peer, 1, 55 "iWARP: Support peer2peer ULPs 0 - Disabled 1 - Enabled. Default:Enabled"); 56 57uint32_t mpa_enhanced = 1; 58SYSCTL_UINT(_dev_qnxr, OID_AUTO, mpa_enhanced, CTLFLAG_RW, &mpa_enhanced, 1, 59 "iWARP: MPA Enhanced mode. Default:1"); 60 61uint32_t rtr_type = 7; 62SYSCTL_UINT(_dev_qnxr, OID_AUTO, rtr_type, CTLFLAG_RW, &rtr_type, 1, 63 "iWARP: RDMAP opcode to use for the RTR message: BITMAP 1: RDMA_SEND 2: RDMA_WRITE 4: RDMA_READ. Default: 7"); 64 65#define QNXR_WQ_MULTIPLIER_MIN (1) 66#define QNXR_WQ_MULTIPLIER_MAX (7) 67#define QNXR_WQ_MULTIPLIER_DFT (3) 68 69uint32_t wq_multiplier= QNXR_WQ_MULTIPLIER_DFT; 70SYSCTL_UINT(_dev_qnxr, OID_AUTO, wq_multiplier, CTLFLAG_RW, &wq_multiplier, 1, 71 " When creating a WQ the actual number of WQE created will" 72 " be multiplied by this number (default is 3)."); 73static ssize_t 74show_rev(struct device *device, struct device_attribute *attr, 75 char *buf) 76{ 77 struct qlnxr_dev *dev = dev_get_drvdata(device); 78 79 return sprintf(buf, "0x%x\n", dev->cdev->vendor_id); 80} 81 82static ssize_t 83show_hca_type(struct device *device, 84 struct device_attribute *attr, char *buf) 85{ 86 struct qlnxr_dev *dev = dev_get_drvdata(device); 87 return sprintf(buf, "QLogic0x%x\n", dev->cdev->device_id); 88} 89 90static ssize_t 91show_fw_ver(struct device *device, 92 struct device_attribute *attr, char *buf) 93{ 94 struct qlnxr_dev *dev = dev_get_drvdata(device); 95 uint32_t fw_ver = (uint32_t) dev->attr.fw_ver; 96 97 return sprintf(buf, "%d.%d.%d\n", 98 (fw_ver >> 24) & 0xff, (fw_ver >> 16) & 0xff, 99 (fw_ver >> 8) & 0xff); 100} 101static ssize_t 102show_board(struct device *device, 103 struct device_attribute *attr, char *buf) 104{ 105 struct qlnxr_dev *dev = dev_get_drvdata(device); 106 return sprintf(buf, "%x\n", dev->cdev->device_id); 107} 108 109static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 110static DEVICE_ATTR(hca_type, S_IRUGO, show_hca_type, NULL); 111static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL); 112static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 113 114static struct device_attribute *qlnxr_class_attributes[] = { 115 &dev_attr_hw_rev, 116 &dev_attr_hca_type, 117 &dev_attr_fw_ver, 118 &dev_attr_board_id 119}; 120 121static void 122qlnxr_ib_dispatch_event(qlnxr_dev_t *dev, uint8_t port_num, 123 enum ib_event_type type) 124{ 125 struct ib_event ibev; 126 127 QL_DPRINT12(dev->ha, "enter\n"); 128 129 ibev.device = &dev->ibdev; 130 ibev.element.port_num = port_num; 131 ibev.event = type; 132 133 ib_dispatch_event(&ibev); 134 135 QL_DPRINT12(dev->ha, "exit\n"); 136} 137 138static int 139__qlnxr_iw_destroy_listen(struct iw_cm_id *cm_id) 140{ 141 qlnxr_iw_destroy_listen(cm_id); 142 143 return (0); 144} 145 146static int 147qlnxr_register_device(qlnxr_dev_t *dev) 148{ 149 struct ib_device *ibdev; 150 struct iw_cm_verbs *iwcm; 151 int ret; 152 153 QL_DPRINT12(dev->ha, "enter\n"); 154 155 ibdev = &dev->ibdev; 156 157#define qlnxr_ib_ah qlnxr_ah 158#define qlnxr_ib_cq qlnxr_cq 159#define qlnxr_ib_pd qlnxr_pd 160#define qlnxr_ib_qp qlnxr_qp 161#define qlnxr_ib_srq qlnxr_srq 162#define qlnxr_ib_ucontext qlnxr_ucontext 163 INIT_IB_DEVICE_OPS(&ibdev->ops, qlnxr, QLNXR); 164 strlcpy(ibdev->name, "qlnxr%d", IB_DEVICE_NAME_MAX); 165 166 memset(&ibdev->node_guid, 0, sizeof(ibdev->node_guid)); 167 memcpy(&ibdev->node_guid, dev->ha->primary_mac, ETHER_ADDR_LEN); 168 169 memcpy(ibdev->node_desc, QLNXR_NODE_DESC, sizeof(QLNXR_NODE_DESC)); 170 171 ibdev->owner = THIS_MODULE; 172 ibdev->uverbs_abi_ver = 7; 173 ibdev->local_dma_lkey = 0; 174 175 ibdev->uverbs_cmd_mask = 176 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 177 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 178 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 179 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 180 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 181 (1ull << IB_USER_VERBS_CMD_REG_MR) | 182 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 183 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 184 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 185 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 186 (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) | 187 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 188 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 189 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 190 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 191 (1ull << IB_USER_VERBS_CMD_POLL_CQ) | 192 (1ull << IB_USER_VERBS_CMD_POST_SEND) | 193 (1ull << IB_USER_VERBS_CMD_POST_RECV); 194 195 if (QLNX_IS_IWARP(dev)) { 196 ibdev->node_type = RDMA_NODE_RNIC; 197 ibdev->query_gid = qlnxr_iw_query_gid; 198 } else { 199 ibdev->node_type = RDMA_NODE_IB_CA; 200 ibdev->query_gid = qlnxr_query_gid; 201 ibdev->uverbs_cmd_mask |= 202 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 203 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 204 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 205 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 206 (1ull << IB_USER_VERBS_CMD_POST_SRQ_RECV); 207 ibdev->create_srq = qlnxr_create_srq; 208 ibdev->destroy_srq = qlnxr_destroy_srq; 209 ibdev->modify_srq = qlnxr_modify_srq; 210 ibdev->query_srq = qlnxr_query_srq; 211 ibdev->post_srq_recv = qlnxr_post_srq_recv; 212 } 213 214 ibdev->phys_port_cnt = 1; 215 ibdev->num_comp_vectors = dev->num_cnq; 216 217 /* mandatory verbs. */ 218 ibdev->query_device = qlnxr_query_device; 219 ibdev->query_port = qlnxr_query_port; 220 ibdev->modify_port = qlnxr_modify_port; 221 222 ibdev->alloc_ucontext = qlnxr_alloc_ucontext; 223 ibdev->dealloc_ucontext = qlnxr_dealloc_ucontext; 224 /* mandatory to support user space verbs consumer. */ 225 ibdev->mmap = qlnxr_mmap; 226 227 ibdev->alloc_pd = qlnxr_alloc_pd; 228 ibdev->dealloc_pd = qlnxr_dealloc_pd; 229 230 ibdev->create_cq = qlnxr_create_cq; 231 ibdev->destroy_cq = qlnxr_destroy_cq; 232 ibdev->resize_cq = qlnxr_resize_cq; 233 ibdev->req_notify_cq = qlnxr_arm_cq; 234 235 ibdev->create_qp = qlnxr_create_qp; 236 ibdev->modify_qp = qlnxr_modify_qp; 237 ibdev->query_qp = qlnxr_query_qp; 238 ibdev->destroy_qp = qlnxr_destroy_qp; 239 240 ibdev->query_pkey = qlnxr_query_pkey; 241 ibdev->create_ah = qlnxr_create_ah; 242 ibdev->destroy_ah = qlnxr_destroy_ah; 243 ibdev->query_ah = qlnxr_query_ah; 244 ibdev->modify_ah = qlnxr_modify_ah; 245 ibdev->get_dma_mr = qlnxr_get_dma_mr; 246 ibdev->dereg_mr = qlnxr_dereg_mr; 247 ibdev->reg_user_mr = qlnxr_reg_user_mr; 248 249 ibdev->alloc_mr = qlnxr_alloc_mr; 250 ibdev->map_mr_sg = qlnxr_map_mr_sg; 251 ibdev->get_port_immutable = qlnxr_get_port_immutable; 252 253 ibdev->poll_cq = qlnxr_poll_cq; 254 ibdev->post_send = qlnxr_post_send; 255 ibdev->post_recv = qlnxr_post_recv; 256 ibdev->process_mad = qlnxr_process_mad; 257 258 ibdev->dma_device = &dev->pdev.dev; 259 260 ibdev->get_link_layer = qlnxr_link_layer; 261 262 if (QLNX_IS_IWARP(dev)) { 263 iwcm = kmalloc(sizeof(*iwcm), GFP_KERNEL); 264 265 device_printf(dev->ha->pci_dev, "device is IWARP\n"); 266 if (iwcm == NULL) 267 return (-ENOMEM); 268 269 ibdev->iwcm = iwcm; 270 271 iwcm->connect = qlnxr_iw_connect; 272 iwcm->accept = qlnxr_iw_accept; 273 iwcm->reject = qlnxr_iw_reject; 274 275 iwcm->create_listen = qlnxr_iw_create_listen; 276 iwcm->destroy_listen = __qlnxr_iw_destroy_listen; 277 278 iwcm->add_ref = qlnxr_iw_qp_add_ref; 279 iwcm->rem_ref = qlnxr_iw_qp_rem_ref; 280 iwcm->get_qp = qlnxr_iw_get_qp; 281 } 282 283 ret = ib_register_device(ibdev, NULL); 284 if (ret) { 285 kfree(iwcm); 286 } 287 288 QL_DPRINT12(dev->ha, "exit\n"); 289 return ret; 290} 291 292#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 293 294static void 295qlnxr_intr(void *handle) 296{ 297 struct qlnxr_cnq *cnq = handle; 298 struct qlnxr_cq *cq; 299 struct regpair *cq_handle; 300 u16 hw_comp_cons, sw_comp_cons; 301 qlnx_host_t *ha; 302 303 ha = cnq->dev->ha; 304 305 QL_DPRINT12(ha, "enter cnq = %p\n", handle); 306 307 ecore_sb_ack(cnq->sb, IGU_INT_DISABLE, 0 /*do not update*/); 308 309 ecore_sb_update_sb_idx(cnq->sb); 310 311 hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr); 312 sw_comp_cons = ecore_chain_get_cons_idx(&cnq->pbl); 313 314 rmb(); 315 316 QL_DPRINT12(ha, "enter cnq = %p hw_comp_cons = 0x%x sw_comp_cons = 0x%x\n", 317 handle, hw_comp_cons, sw_comp_cons); 318 319 while (sw_comp_cons != hw_comp_cons) { 320 cq_handle = (struct regpair *)ecore_chain_consume(&cnq->pbl); 321 cq = (struct qlnxr_cq *)(uintptr_t)HILO_U64(cq_handle->hi, 322 cq_handle->lo); 323 324 if (cq == NULL) { 325 QL_DPRINT11(ha, "cq == NULL\n"); 326 break; 327 } 328 329 if (cq->sig != QLNXR_CQ_MAGIC_NUMBER) { 330 QL_DPRINT11(ha, 331 "cq->sig = 0x%x QLNXR_CQ_MAGIC_NUMBER = 0x%x\n", 332 cq->sig, QLNXR_CQ_MAGIC_NUMBER); 333 break; 334 } 335 cq->arm_flags = 0; 336 337 if (!cq->destroyed && cq->ibcq.comp_handler) { 338 QL_DPRINT11(ha, "calling comp_handler = %p " 339 "ibcq = %p cq_context = 0x%x\n", 340 &cq->ibcq, cq->ibcq.cq_context); 341 342 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context); 343 } 344 cq->cnq_notif++; 345 346 sw_comp_cons = ecore_chain_get_cons_idx(&cnq->pbl); 347 348 cnq->n_comp++; 349 } 350 351 ecore_rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index, sw_comp_cons); 352 353 ecore_sb_ack(cnq->sb, IGU_INT_ENABLE, 1 /*update*/); 354 355 QL_DPRINT12(ha, "exit cnq = %p\n", handle); 356 return; 357} 358 359static void 360qlnxr_release_irqs(struct qlnxr_dev *dev) 361{ 362 int i; 363 qlnx_host_t *ha; 364 365 ha = dev->ha; 366 367 QL_DPRINT12(ha, "enter\n"); 368 369 for (i = 0; i < dev->num_cnq; i++) { 370 if (dev->cnq_array[i].irq_handle) 371 (void)bus_teardown_intr(dev->ha->pci_dev, 372 dev->cnq_array[i].irq, 373 dev->cnq_array[i].irq_handle); 374 375 if (dev->cnq_array[i].irq) 376 (void) bus_release_resource(dev->ha->pci_dev, 377 SYS_RES_IRQ, 378 dev->cnq_array[i].irq_rid, 379 dev->cnq_array[i].irq); 380 } 381 QL_DPRINT12(ha, "exit\n"); 382 return; 383} 384 385static int 386qlnxr_setup_irqs(struct qlnxr_dev *dev) 387{ 388 int start_irq_rid; 389 int i; 390 qlnx_host_t *ha; 391 392 ha = dev->ha; 393 394 start_irq_rid = dev->sb_start + 2; 395 396 QL_DPRINT12(ha, "enter start_irq_rid = %d num_rss = %d\n", 397 start_irq_rid, dev->ha->num_rss); 398 399 for (i = 0; i < dev->num_cnq; i++) { 400 dev->cnq_array[i].irq_rid = start_irq_rid + i; 401 402 dev->cnq_array[i].irq = bus_alloc_resource_any(dev->ha->pci_dev, 403 SYS_RES_IRQ, 404 &dev->cnq_array[i].irq_rid, 405 (RF_ACTIVE | RF_SHAREABLE)); 406 407 if (dev->cnq_array[i].irq == NULL) { 408 QL_DPRINT11(ha, 409 "bus_alloc_resource_any failed irq_rid = %d\n", 410 dev->cnq_array[i].irq_rid); 411 412 goto qlnxr_setup_irqs_err; 413 } 414 415 if (bus_setup_intr(dev->ha->pci_dev, 416 dev->cnq_array[i].irq, 417 (INTR_TYPE_NET | INTR_MPSAFE), 418 NULL, qlnxr_intr, &dev->cnq_array[i], 419 &dev->cnq_array[i].irq_handle)) { 420 QL_DPRINT11(ha, "bus_setup_intr failed\n"); 421 goto qlnxr_setup_irqs_err; 422 } 423 QL_DPRINT12(ha, "irq_rid = %d irq = %p irq_handle = %p\n", 424 dev->cnq_array[i].irq_rid, dev->cnq_array[i].irq, 425 dev->cnq_array[i].irq_handle); 426 } 427 428 QL_DPRINT12(ha, "exit\n"); 429 return (0); 430 431qlnxr_setup_irqs_err: 432 qlnxr_release_irqs(dev); 433 434 QL_DPRINT12(ha, "exit -1\n"); 435 return (-1); 436} 437 438static void 439qlnxr_free_resources(struct qlnxr_dev *dev) 440{ 441 int i; 442 qlnx_host_t *ha; 443 444 ha = dev->ha; 445 446 QL_DPRINT12(ha, "enter dev->num_cnq = %d\n", dev->num_cnq); 447 448 if (QLNX_IS_IWARP(dev)) { 449 if (dev->iwarp_wq != NULL) 450 destroy_workqueue(dev->iwarp_wq); 451 } 452 453 for (i = 0; i < dev->num_cnq; i++) { 454 qlnx_free_mem_sb(dev->ha, &dev->sb_array[i]); 455 ecore_chain_free(&dev->ha->cdev, &dev->cnq_array[i].pbl); 456 } 457 458 bzero(dev->cnq_array, (sizeof(struct qlnxr_cnq) * QLNXR_MAX_MSIX)); 459 bzero(dev->sb_array, (sizeof(struct ecore_sb_info) * QLNXR_MAX_MSIX)); 460 bzero(dev->sgid_tbl, (sizeof(union ib_gid) * QLNXR_MAX_SGID)); 461 462 if (mtx_initialized(&dev->idr_lock)) 463 mtx_destroy(&dev->idr_lock); 464 465 if (mtx_initialized(&dev->sgid_lock)) 466 mtx_destroy(&dev->sgid_lock); 467 468 QL_DPRINT12(ha, "exit\n"); 469 return; 470} 471 472static int 473qlnxr_alloc_resources(struct qlnxr_dev *dev) 474{ 475 uint16_t n_entries; 476 int i, rc; 477 qlnx_host_t *ha; 478 479 ha = dev->ha; 480 481 QL_DPRINT12(ha, "enter\n"); 482 483 bzero(dev->sgid_tbl, (sizeof (union ib_gid) * QLNXR_MAX_SGID)); 484 485 mtx_init(&dev->idr_lock, "idr_lock", NULL, MTX_DEF); 486 mtx_init(&dev->sgid_lock, "sgid_lock", NULL, MTX_DEF); 487 488 idr_init(&dev->qpidr); 489 490 bzero(dev->sb_array, (sizeof (struct ecore_sb_info) * QLNXR_MAX_MSIX)); 491 bzero(dev->cnq_array, (sizeof (struct qlnxr_cnq) * QLNXR_MAX_MSIX)); 492 493 dev->sb_start = ecore_rdma_get_sb_id(dev->rdma_ctx, 0); 494 495 QL_DPRINT12(ha, "dev->sb_start = 0x%x\n", dev->sb_start); 496 497 /* Allocate CNQ PBLs */ 498 499 n_entries = min_t(u32, ECORE_RDMA_MAX_CNQ_SIZE, QLNXR_ROCE_MAX_CNQ_SIZE); 500 501 for (i = 0; i < dev->num_cnq; i++) { 502 rc = qlnx_alloc_mem_sb(dev->ha, &dev->sb_array[i], 503 dev->sb_start + i); 504 if (rc) 505 goto qlnxr_alloc_resources_exit; 506 507 rc = ecore_chain_alloc(&dev->ha->cdev, 508 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE, 509 ECORE_CHAIN_MODE_PBL, 510 ECORE_CHAIN_CNT_TYPE_U16, 511 n_entries, 512 sizeof(struct regpair *), 513 &dev->cnq_array[i].pbl, 514 NULL); 515 516 /* configure cnq, except name since ibdev.name is still NULL */ 517 dev->cnq_array[i].dev = dev; 518 dev->cnq_array[i].sb = &dev->sb_array[i]; 519 dev->cnq_array[i].hw_cons_ptr = 520 &(dev->sb_array[i].sb_virt->pi_array[ECORE_ROCE_PROTOCOL_INDEX]); 521 dev->cnq_array[i].index = i; 522 sprintf(dev->cnq_array[i].name, "qlnxr%d@pci:%d", 523 i, (dev->ha->pci_func)); 524 } 525 526 QL_DPRINT12(ha, "exit\n"); 527 return 0; 528 529qlnxr_alloc_resources_exit: 530 531 qlnxr_free_resources(dev); 532 533 QL_DPRINT12(ha, "exit -ENOMEM\n"); 534 return -ENOMEM; 535} 536 537void 538qlnxr_affiliated_event(void *context, u8 e_code, void *fw_handle) 539{ 540#define EVENT_TYPE_NOT_DEFINED 0 541#define EVENT_TYPE_CQ 1 542#define EVENT_TYPE_QP 2 543#define EVENT_TYPE_GENERAL 3 544 545 struct qlnxr_dev *dev = (struct qlnxr_dev *)context; 546 struct regpair *async_handle = (struct regpair *)fw_handle; 547 u64 roceHandle64 = ((u64)async_handle->hi << 32) + async_handle->lo; 548 struct qlnxr_cq *cq = (struct qlnxr_cq *)(uintptr_t)roceHandle64; 549 struct qlnxr_qp *qp = (struct qlnxr_qp *)(uintptr_t)roceHandle64; 550 u8 event_type = EVENT_TYPE_NOT_DEFINED; 551 struct ib_event event; 552 qlnx_host_t *ha; 553 554 ha = dev->ha; 555 556 QL_DPRINT12(ha, "enter context = %p e_code = 0x%x fw_handle = %p\n", 557 context, e_code, fw_handle); 558 559 if (QLNX_IS_IWARP(dev)) { 560 switch (e_code) { 561 case ECORE_IWARP_EVENT_CQ_OVERFLOW: 562 event.event = IB_EVENT_CQ_ERR; 563 event_type = EVENT_TYPE_CQ; 564 break; 565 566 default: 567 QL_DPRINT12(ha, 568 "unsupported event %d on handle=%llx\n", 569 e_code, roceHandle64); 570 break; 571 } 572 } else { 573 switch (e_code) { 574 case ROCE_ASYNC_EVENT_CQ_OVERFLOW_ERR: 575 event.event = IB_EVENT_CQ_ERR; 576 event_type = EVENT_TYPE_CQ; 577 break; 578 579 case ROCE_ASYNC_EVENT_SQ_DRAINED: 580 event.event = IB_EVENT_SQ_DRAINED; 581 event_type = EVENT_TYPE_QP; 582 break; 583 584 case ROCE_ASYNC_EVENT_QP_CATASTROPHIC_ERR: 585 event.event = IB_EVENT_QP_FATAL; 586 event_type = EVENT_TYPE_QP; 587 break; 588 589 case ROCE_ASYNC_EVENT_LOCAL_INVALID_REQUEST_ERR: 590 event.event = IB_EVENT_QP_REQ_ERR; 591 event_type = EVENT_TYPE_QP; 592 break; 593 594 case ROCE_ASYNC_EVENT_LOCAL_ACCESS_ERR: 595 event.event = IB_EVENT_QP_ACCESS_ERR; 596 event_type = EVENT_TYPE_QP; 597 break; 598 599 /* NOTE the following are not implemented in FW 600 * ROCE_ASYNC_EVENT_CQ_ERR 601 * ROCE_ASYNC_EVENT_COMM_EST 602 */ 603 /* TODO associate the following events - 604 * ROCE_ASYNC_EVENT_SRQ_LIMIT 605 * ROCE_ASYNC_EVENT_LAST_WQE_REACHED 606 * ROCE_ASYNC_EVENT_LOCAL_CATASTROPHIC_ERR (un-affiliated) 607 */ 608 default: 609 QL_DPRINT12(ha, 610 "unsupported event 0x%x on fw_handle = %p\n", 611 e_code, fw_handle); 612 break; 613 } 614 } 615 616 switch (event_type) { 617 case EVENT_TYPE_CQ: 618 if (cq && cq->sig == QLNXR_CQ_MAGIC_NUMBER) { 619 struct ib_cq *ibcq = &cq->ibcq; 620 621 if (ibcq->event_handler) { 622 event.device = ibcq->device; 623 event.element.cq = ibcq; 624 ibcq->event_handler(&event, ibcq->cq_context); 625 } 626 } else { 627 QL_DPRINT11(ha, 628 "CQ event with invalid CQ pointer" 629 " Handle = %llx\n", roceHandle64); 630 } 631 QL_DPRINT12(ha, 632 "CQ event 0x%x on handle = %p\n", e_code, cq); 633 break; 634 635 case EVENT_TYPE_QP: 636 if (qp && qp->sig == QLNXR_QP_MAGIC_NUMBER) { 637 struct ib_qp *ibqp = &qp->ibqp; 638 639 if (ibqp->event_handler) { 640 event.device = ibqp->device; 641 event.element.qp = ibqp; 642 ibqp->event_handler(&event, ibqp->qp_context); 643 } 644 } else { 645 QL_DPRINT11(ha, 646 "QP event 0x%x with invalid QP pointer" 647 " qp handle = %p\n", 648 e_code, roceHandle64); 649 } 650 QL_DPRINT12(ha, "QP event 0x%x on qp handle = %p\n", 651 e_code, qp); 652 break; 653 654 case EVENT_TYPE_GENERAL: 655 break; 656 657 default: 658 break; 659 } 660 661 QL_DPRINT12(ha, "exit\n"); 662 663 return; 664} 665 666void 667qlnxr_unaffiliated_event(void *context, u8 e_code) 668{ 669 struct qlnxr_dev *dev = (struct qlnxr_dev *)context; 670 qlnx_host_t *ha; 671 672 ha = dev->ha; 673 674 QL_DPRINT12(ha, "enter/exit \n"); 675 return; 676} 677 678static int 679qlnxr_set_device_attr(struct qlnxr_dev *dev) 680{ 681 struct ecore_rdma_device *ecore_attr; 682 struct qlnxr_device_attr *attr; 683 u32 page_size; 684 685 ecore_attr = ecore_rdma_query_device(dev->rdma_ctx); 686 687 page_size = ~dev->attr.page_size_caps + 1; 688 if(page_size > PAGE_SIZE) { 689 QL_DPRINT12(dev->ha, "Kernel page size : %ld is smaller than" 690 " minimum page size : %ld required by qlnxr\n", 691 PAGE_SIZE, page_size); 692 return -ENODEV; 693 } 694 attr = &dev->attr; 695 attr->vendor_id = ecore_attr->vendor_id; 696 attr->vendor_part_id = ecore_attr->vendor_part_id; 697 698 QL_DPRINT12(dev->ha, "in qlnxr_set_device_attr, vendor : %x device : %x\n", 699 attr->vendor_id, attr->vendor_part_id); 700 701 attr->hw_ver = ecore_attr->hw_ver; 702 attr->fw_ver = ecore_attr->fw_ver; 703 attr->node_guid = ecore_attr->node_guid; 704 attr->sys_image_guid = ecore_attr->sys_image_guid; 705 attr->max_cnq = ecore_attr->max_cnq; 706 attr->max_sge = ecore_attr->max_sge; 707 attr->max_inline = ecore_attr->max_inline; 708 attr->max_sqe = min_t(u32, ecore_attr->max_wqe, QLNXR_MAX_SQE); 709 attr->max_rqe = min_t(u32, ecore_attr->max_wqe, QLNXR_MAX_RQE); 710 attr->max_qp_resp_rd_atomic_resc = ecore_attr->max_qp_resp_rd_atomic_resc; 711 attr->max_qp_req_rd_atomic_resc = ecore_attr->max_qp_req_rd_atomic_resc; 712 attr->max_dev_resp_rd_atomic_resc = 713 ecore_attr->max_dev_resp_rd_atomic_resc; 714 attr->max_cq = ecore_attr->max_cq; 715 attr->max_qp = ecore_attr->max_qp; 716 attr->max_mr = ecore_attr->max_mr; 717 attr->max_mr_size = ecore_attr->max_mr_size; 718 attr->max_cqe = min_t(u64, ecore_attr->max_cqe, QLNXR_MAX_CQES); 719 attr->max_mw = ecore_attr->max_mw; 720 attr->max_fmr = ecore_attr->max_fmr; 721 attr->max_mr_mw_fmr_pbl = ecore_attr->max_mr_mw_fmr_pbl; 722 attr->max_mr_mw_fmr_size = ecore_attr->max_mr_mw_fmr_size; 723 attr->max_pd = ecore_attr->max_pd; 724 attr->max_ah = ecore_attr->max_ah; 725 attr->max_pkey = ecore_attr->max_pkey; 726 attr->max_srq = ecore_attr->max_srq; 727 attr->max_srq_wr = ecore_attr->max_srq_wr; 728 //attr->dev_caps = ecore_attr->dev_caps; 729 attr->page_size_caps = ecore_attr->page_size_caps; 730 attr->dev_ack_delay = ecore_attr->dev_ack_delay; 731 attr->reserved_lkey = ecore_attr->reserved_lkey; 732 attr->bad_pkey_counter = ecore_attr->bad_pkey_counter; 733 attr->max_stats_queues = ecore_attr->max_stats_queues; 734 735 return 0; 736} 737 738static int 739qlnxr_init_hw(struct qlnxr_dev *dev) 740{ 741 struct ecore_rdma_events events; 742 struct ecore_rdma_add_user_out_params out_params; 743 struct ecore_rdma_cnq_params *cur_pbl; 744 struct ecore_rdma_start_in_params *in_params; 745 dma_addr_t p_phys_table; 746 u32 page_cnt; 747 int rc = 0; 748 int i; 749 qlnx_host_t *ha; 750 751 ha = dev->ha; 752 753 QL_DPRINT12(ha, "enter\n"); 754 755 in_params = kzalloc(sizeof(*in_params), GFP_KERNEL); 756 if (!in_params) { 757 rc = -ENOMEM; 758 goto out; 759 } 760 761 bzero(&out_params, sizeof(struct ecore_rdma_add_user_out_params)); 762 bzero(&events, sizeof(struct ecore_rdma_events)); 763 764 in_params->desired_cnq = dev->num_cnq; 765 766 for (i = 0; i < dev->num_cnq; i++) { 767 cur_pbl = &in_params->cnq_pbl_list[i]; 768 769 page_cnt = ecore_chain_get_page_cnt(&dev->cnq_array[i].pbl); 770 cur_pbl->num_pbl_pages = page_cnt; 771 772 p_phys_table = ecore_chain_get_pbl_phys(&dev->cnq_array[i].pbl); 773 cur_pbl->pbl_ptr = (u64)p_phys_table; 774 } 775 776 events.affiliated_event = qlnxr_affiliated_event; 777 events.unaffiliated_event = qlnxr_unaffiliated_event; 778 events.context = dev; 779 780 in_params->events = &events; 781 in_params->roce.cq_mode = ECORE_RDMA_CQ_MODE_32_BITS; 782 in_params->max_mtu = dev->ha->max_frame_size; 783 784 if (QLNX_IS_IWARP(dev)) { 785 if (delayed_ack) 786 in_params->iwarp.flags |= ECORE_IWARP_DA_EN; 787 788 if (timestamp) 789 in_params->iwarp.flags |= ECORE_IWARP_TS_EN; 790 791 in_params->iwarp.rcv_wnd_size = rcv_wnd_size*1024; 792 in_params->iwarp.crc_needed = crc_needed; 793 in_params->iwarp.ooo_num_rx_bufs = 794 (MAX_RXMIT_CONNS * in_params->iwarp.rcv_wnd_size) / 795 in_params->max_mtu; 796 797 in_params->iwarp.mpa_peer2peer = peer2peer; 798 in_params->iwarp.mpa_rev = 799 mpa_enhanced ? ECORE_MPA_REV2 : ECORE_MPA_REV1; 800 in_params->iwarp.mpa_rtr = rtr_type; 801 } 802 803 memcpy(&in_params->mac_addr[0], dev->ha->primary_mac, ETH_ALEN); 804 805 rc = ecore_rdma_start(dev->rdma_ctx, in_params); 806 if (rc) 807 goto out; 808 809 rc = ecore_rdma_add_user(dev->rdma_ctx, &out_params); 810 if (rc) 811 goto out; 812 813 dev->db_addr = (void *)(uintptr_t)out_params.dpi_addr; 814 dev->db_phys_addr = out_params.dpi_phys_addr; 815 dev->db_size = out_params.dpi_size; 816 dev->dpi = out_params.dpi; 817 818 qlnxr_set_device_attr(dev); 819 820 QL_DPRINT12(ha, 821 "cdev->doorbells = %p, db_phys_addr = %p db_size = 0x%x\n", 822 (void *)ha->cdev.doorbells, 823 (void *)ha->cdev.db_phys_addr, ha->cdev.db_size); 824 825 QL_DPRINT12(ha, 826 "db_addr = %p db_phys_addr = %p db_size = 0x%x dpi = 0x%x\n", 827 (void *)dev->db_addr, (void *)dev->db_phys_addr, 828 dev->db_size, dev->dpi); 829out: 830 kfree(in_params); 831 832 QL_DPRINT12(ha, "exit\n"); 833 return rc; 834} 835 836static void 837qlnxr_build_sgid_mac(union ib_gid *sgid, unsigned char *mac_addr, 838 bool is_vlan, u16 vlan_id) 839{ 840 sgid->global.subnet_prefix = OSAL_CPU_TO_BE64(0xfe80000000000000LL); 841 sgid->raw[8] = mac_addr[0] ^ 2; 842 sgid->raw[9] = mac_addr[1]; 843 sgid->raw[10] = mac_addr[2]; 844 if (is_vlan) { 845 sgid->raw[11] = vlan_id >> 8; 846 sgid->raw[12] = vlan_id & 0xff; 847 } else { 848 sgid->raw[11] = 0xff; 849 sgid->raw[12] = 0xfe; 850 } 851 sgid->raw[13] = mac_addr[3]; 852 sgid->raw[14] = mac_addr[4]; 853 sgid->raw[15] = mac_addr[5]; 854} 855static bool 856qlnxr_add_sgid(struct qlnxr_dev *dev, union ib_gid *new_sgid); 857 858struct qlnx_cb_s { 859 struct qlnxr_dev *dev; 860 union ib_gid gid; 861}; 862 863static u_int 864qlnxr_add_ip_based_gid_cb(void *arg, struct ifaddr *ifa, u_int count) 865{ 866 struct qlnx_cb_s *cba = arg; 867 868 QL_DPRINT12(cba->dev->ha, "IP address : %x\n", ((struct sockaddr_in *) ifa->ifa_addr)->sin_addr.s_addr); 869 ipv6_addr_set_v4mapped( 870 ((struct sockaddr_in *) ifa->ifa_addr)->sin_addr.s_addr, 871 (struct in6_addr *)&cba->gid); 872 QL_DPRINT12(cba->dev->ha, "gid generated : %llx\n", cba->gid); 873 874 qlnxr_add_sgid(cba->dev, &cba->gid); 875 return (1); 876} 877 878static void 879qlnxr_add_ip_based_gid(struct qlnxr_dev *dev, if_t ifp) 880{ 881 struct qlnx_cb_s cba; 882 883 if_foreach_addr_type(ifp, AF_INET, qlnxr_add_ip_based_gid_cb, &cba); 884 for (int i = 0; i < 16; i++) { 885 QL_DPRINT12(dev->ha, "gid generated : %x\n", cba.gid.raw[i]); 886 } 887} 888 889static bool 890qlnxr_add_sgid(struct qlnxr_dev *dev, union ib_gid *new_sgid) 891{ 892 union ib_gid zero_sgid = { { 0 } }; 893 int i; 894 //unsigned long flags; 895 mtx_lock(&dev->sgid_lock); 896 for (i = 0; i < QLNXR_MAX_SGID; i++) { 897 if (!memcmp(&dev->sgid_tbl[i], &zero_sgid, 898 sizeof(union ib_gid))) { 899 /* found free entry */ 900 memcpy(&dev->sgid_tbl[i], new_sgid, 901 sizeof(union ib_gid)); 902 QL_DPRINT12(dev->ha, "copying sgid : %llx\n", 903 *new_sgid); 904 mtx_unlock(&dev->sgid_lock); 905 //TODO ib_dispatch event here? 906 return true; 907 } else if (!memcmp(&dev->sgid_tbl[i], new_sgid, 908 sizeof(union ib_gid))) { 909 /* entry already present, no addition required */ 910 mtx_unlock(&dev->sgid_lock); 911 QL_DPRINT12(dev->ha, "sgid present : %llx\n", 912 *new_sgid); 913 return false; 914 } 915 } 916 if (i == QLNXR_MAX_SGID) { 917 QL_DPRINT12(dev->ha, "didn't find an empty entry in sgid_tbl\n"); 918 } 919 mtx_unlock(&dev->sgid_lock); 920 return false; 921} 922 923static bool qlnxr_del_sgid(struct qlnxr_dev *dev, union ib_gid *gid) 924{ 925 int found = false; 926 int i; 927 //unsigned long flags; 928 929 QL_DPRINT12(dev->ha, "removing gid %llx %llx\n", 930 gid->global.interface_id, 931 gid->global.subnet_prefix); 932 mtx_lock(&dev->sgid_lock); 933 /* first is the default sgid which cannot be deleted */ 934 for (i = 1; i < QLNXR_MAX_SGID; i++) { 935 if (!memcmp(&dev->sgid_tbl[i], gid, sizeof(union ib_gid))) { 936 /* found matching entry */ 937 memset(&dev->sgid_tbl[i], 0, sizeof(union ib_gid)); 938 found = true; 939 break; 940 } 941 } 942 mtx_unlock(&dev->sgid_lock); 943 944 return found; 945} 946 947static void 948qlnxr_add_sgids(struct qlnxr_dev *dev) 949{ 950 qlnx_host_t *ha = dev->ha; 951 u16 vlan_id; 952 bool is_vlan; 953 union ib_gid vgid; 954 955 qlnxr_add_ip_based_gid(dev, ha->ifp); 956 /* MAC/VLAN base GIDs */ 957 is_vlan = is_vlan_dev(ha->ifp); 958 vlan_id = (is_vlan) ? vlan_dev_vlan_id(ha->ifp) : 0; 959 qlnxr_build_sgid_mac(&vgid, ha->primary_mac, is_vlan, vlan_id); 960 qlnxr_add_sgid(dev, &vgid); 961} 962 963static int 964qlnxr_add_default_sgid(struct qlnxr_dev *dev) 965{ 966 /* GID Index 0 - Invariant manufacturer-assigned EUI-64 */ 967 union ib_gid *sgid = &dev->sgid_tbl[0]; 968 struct ecore_rdma_device *qattr; 969 qlnx_host_t *ha; 970 ha = dev->ha; 971 972 qattr = ecore_rdma_query_device(dev->rdma_ctx); 973 if(sgid == NULL) 974 QL_DPRINT12(ha, "sgid = NULL?\n"); 975 976 sgid->global.subnet_prefix = OSAL_CPU_TO_BE64(0xfe80000000000000LL); 977 QL_DPRINT12(ha, "node_guid = %llx", dev->attr.node_guid); 978 memcpy(&sgid->raw[8], &qattr->node_guid, 979 sizeof(qattr->node_guid)); 980 //memcpy(&sgid->raw[8], &dev->attr.node_guid, 981 // sizeof(dev->attr.node_guid)); 982 QL_DPRINT12(ha, "DEFAULT sgid=[%x][%x][%x][%x][%x][%x][%x][%x][%x][%x][%x][%x][%x][%x][%x][%x]\n", 983 sgid->raw[0], sgid->raw[1], sgid->raw[2], sgid->raw[3], sgid->raw[4], sgid->raw[5], 984 sgid->raw[6], sgid->raw[7], sgid->raw[8], sgid->raw[9], sgid->raw[10], sgid->raw[11], 985 sgid->raw[12], sgid->raw[13], sgid->raw[14], sgid->raw[15]); 986 return 0; 987} 988 989static int qlnxr_addr_event (struct qlnxr_dev *dev, 990 unsigned long event, 991 if_t ifp, 992 union ib_gid *gid) 993{ 994 bool is_vlan = false; 995 union ib_gid vgid; 996 u16 vlan_id = 0xffff; 997 998 QL_DPRINT12(dev->ha, "Link event occured\n"); 999 is_vlan = is_vlan_dev(dev->ha->ifp); 1000 vlan_id = (is_vlan) ? vlan_dev_vlan_id(dev->ha->ifp) : 0; 1001 1002 switch (event) { 1003 case NETDEV_UP : 1004 qlnxr_add_sgid(dev, gid); 1005 if (is_vlan) { 1006 qlnxr_build_sgid_mac(&vgid, dev->ha->primary_mac, is_vlan, vlan_id); 1007 qlnxr_add_sgid(dev, &vgid); 1008 } 1009 break; 1010 case NETDEV_DOWN : 1011 qlnxr_del_sgid(dev, gid); 1012 if (is_vlan) { 1013 qlnxr_build_sgid_mac(&vgid, dev->ha->primary_mac, is_vlan, vlan_id); 1014 qlnxr_del_sgid(dev, &vgid); 1015 } 1016 break; 1017 default : 1018 break; 1019 } 1020 return 1; 1021} 1022 1023static int qlnxr_inetaddr_event(struct notifier_block *notifier, 1024 unsigned long event, void *ptr) 1025{ 1026 struct ifaddr *ifa = ptr; 1027 union ib_gid gid; 1028 struct qlnxr_dev *dev = container_of(notifier, struct qlnxr_dev, nb_inet); 1029 qlnx_host_t *ha = dev->ha; 1030 1031 ipv6_addr_set_v4mapped( 1032 ((struct sockaddr_in *) ifa->ifa_addr)->sin_addr.s_addr, 1033 (struct in6_addr *)&gid); 1034 return qlnxr_addr_event(dev, event, ha->ifp, &gid); 1035} 1036 1037static int 1038qlnxr_register_inet(struct qlnxr_dev *dev) 1039{ 1040 int ret; 1041 dev->nb_inet.notifier_call = qlnxr_inetaddr_event; 1042 ret = register_inetaddr_notifier(&dev->nb_inet); 1043 if (ret) { 1044 QL_DPRINT12(dev->ha, "Failed to register inetaddr\n"); 1045 return ret; 1046 } 1047 /* TODO : add for CONFIG_IPV6) */ 1048 return 0; 1049} 1050 1051static int 1052qlnxr_build_sgid_tbl(struct qlnxr_dev *dev) 1053{ 1054 qlnxr_add_default_sgid(dev); 1055 qlnxr_add_sgids(dev); 1056 return 0; 1057} 1058 1059static struct qlnx_rdma_if qlnxr_drv; 1060 1061static void * 1062qlnxr_add(void *eth_dev) 1063{ 1064 struct qlnxr_dev *dev; 1065 int ret; 1066 //device_t pci_dev; 1067 qlnx_host_t *ha; 1068 1069 ha = eth_dev; 1070 1071 QL_DPRINT12(ha, "enter [ha = %p]\n", ha); 1072 1073 dev = (struct qlnxr_dev *)ib_alloc_device(sizeof(struct qlnxr_dev)); 1074 1075 if (dev == NULL) 1076 return (NULL); 1077 1078 dev->ha = eth_dev; 1079 dev->cdev = &ha->cdev; 1080 /* Added to extend Application support */ 1081 linux_pci_attach_device(dev->ha->pci_dev, NULL, NULL, &dev->pdev); 1082 1083 dev->rdma_ctx = &ha->cdev.hwfns[0]; 1084 dev->wq_multiplier = wq_multiplier; 1085 dev->num_cnq = QLNX_NUM_CNQ; 1086 1087 QL_DPRINT12(ha, 1088 "ha = %p dev = %p ha->cdev = %p\n", 1089 ha, dev, &ha->cdev); 1090 QL_DPRINT12(ha, 1091 "dev->cdev = %p dev->rdma_ctx = %p\n", 1092 dev->cdev, dev->rdma_ctx); 1093 1094 ret = qlnxr_alloc_resources(dev); 1095 1096 if (ret) 1097 goto qlnxr_add_err; 1098 1099 ret = qlnxr_setup_irqs(dev); 1100 1101 if (ret) { 1102 qlnxr_free_resources(dev); 1103 goto qlnxr_add_err; 1104 } 1105 1106 ret = qlnxr_init_hw(dev); 1107 1108 if (ret) { 1109 qlnxr_release_irqs(dev); 1110 qlnxr_free_resources(dev); 1111 goto qlnxr_add_err; 1112 } 1113 1114 qlnxr_register_device(dev); 1115 for (int i = 0; i < ARRAY_SIZE(qlnxr_class_attributes); ++i) { 1116 if (device_create_file(&dev->ibdev.dev, qlnxr_class_attributes[i])) 1117 goto sysfs_err; 1118 } 1119 qlnxr_build_sgid_tbl(dev); 1120 //ret = qlnxr_register_inet(dev); 1121 QL_DPRINT12(ha, "exit\n"); 1122 if (!test_and_set_bit(QLNXR_ENET_STATE_BIT, &dev->enet_state)) { 1123 QL_DPRINT12(ha, "dispatching IB_PORT_ACITVE event\n"); 1124 qlnxr_ib_dispatch_event(dev, QLNXR_PORT, 1125 IB_EVENT_PORT_ACTIVE); 1126 } 1127 1128 return (dev); 1129sysfs_err: 1130 for (int i = 0; i < ARRAY_SIZE(qlnxr_class_attributes); ++i) { 1131 device_remove_file(&dev->ibdev.dev, qlnxr_class_attributes[i]); 1132 } 1133 ib_unregister_device(&dev->ibdev); 1134 1135qlnxr_add_err: 1136 ib_dealloc_device(&dev->ibdev); 1137 1138 QL_DPRINT12(ha, "exit failed\n"); 1139 return (NULL); 1140} 1141 1142static void 1143qlnxr_remove_sysfiles(struct qlnxr_dev *dev) 1144{ 1145 int i; 1146 for (i = 0; i < ARRAY_SIZE(qlnxr_class_attributes); ++i) 1147 device_remove_file(&dev->ibdev.dev, qlnxr_class_attributes[i]); 1148} 1149 1150static int 1151qlnxr_remove(void *eth_dev, void *qlnx_rdma_dev) 1152{ 1153 struct qlnxr_dev *dev; 1154 qlnx_host_t *ha; 1155 1156 dev = qlnx_rdma_dev; 1157 ha = eth_dev; 1158 1159 if ((ha == NULL) || (dev == NULL)) 1160 return (0); 1161 1162 QL_DPRINT12(ha, "enter ha = %p qlnx_rdma_dev = %p pd_count = %d\n", 1163 ha, qlnx_rdma_dev, dev->pd_count); 1164 1165 qlnxr_ib_dispatch_event(dev, QLNXR_PORT, 1166 IB_EVENT_PORT_ERR); 1167 1168 if (QLNX_IS_IWARP(dev)) { 1169 if (dev->pd_count) 1170 return (EBUSY); 1171 } 1172 1173 ib_unregister_device(&dev->ibdev); 1174 1175 if (QLNX_IS_ROCE(dev)) { 1176 if (dev->pd_count) 1177 return (EBUSY); 1178 } 1179 1180 ecore_rdma_remove_user(dev->rdma_ctx, dev->dpi); 1181 ecore_rdma_stop(dev->rdma_ctx); 1182 1183 qlnxr_release_irqs(dev); 1184 1185 qlnxr_free_resources(dev); 1186 1187 qlnxr_remove_sysfiles(dev); 1188 ib_dealloc_device(&dev->ibdev); 1189 1190 linux_pci_detach_device(&dev->pdev); 1191 1192 QL_DPRINT12(ha, "exit ha = %p qlnx_rdma_dev = %p\n", ha, qlnx_rdma_dev); 1193 return (0); 1194} 1195 1196int 1197qlnx_rdma_ll2_set_mac_filter(void *rdma_ctx, uint8_t *old_mac_address, 1198 uint8_t *new_mac_address) 1199{ 1200 struct ecore_hwfn *p_hwfn = rdma_ctx; 1201 struct qlnx_host *ha; 1202 int ret = 0; 1203 1204 ha = (struct qlnx_host *)(p_hwfn->p_dev); 1205 QL_DPRINT2(ha, "enter rdma_ctx (%p)\n", rdma_ctx); 1206 1207 if (old_mac_address) 1208 ecore_llh_remove_mac_filter(p_hwfn->p_dev, 0, old_mac_address); 1209 1210 if (new_mac_address) 1211 ret = ecore_llh_add_mac_filter(p_hwfn->p_dev, 0, new_mac_address); 1212 1213 QL_DPRINT2(ha, "exit rdma_ctx (%p)\n", rdma_ctx); 1214 return (ret); 1215} 1216 1217static void 1218qlnxr_mac_address_change(struct qlnxr_dev *dev) 1219{ 1220 qlnx_host_t *ha; 1221 1222 ha = dev->ha; 1223 1224 QL_DPRINT12(ha, "enter/exit\n"); 1225 1226 return; 1227} 1228 1229static void 1230qlnxr_notify(void *eth_dev, void *qlnx_rdma_dev, enum qlnx_rdma_event event) 1231{ 1232 struct qlnxr_dev *dev; 1233 qlnx_host_t *ha; 1234 1235 dev = qlnx_rdma_dev; 1236 1237 if (dev == NULL) 1238 return; 1239 1240 ha = dev->ha; 1241 1242 QL_DPRINT12(ha, "enter (%p, %d)\n", qlnx_rdma_dev, event); 1243 1244 switch (event) { 1245 case QLNX_ETHDEV_UP: 1246 if (!test_and_set_bit(QLNXR_ENET_STATE_BIT, &dev->enet_state)) 1247 qlnxr_ib_dispatch_event(dev, QLNXR_PORT, 1248 IB_EVENT_PORT_ACTIVE); 1249 break; 1250 1251 case QLNX_ETHDEV_CHANGE_ADDR: 1252 qlnxr_mac_address_change(dev); 1253 break; 1254 1255 case QLNX_ETHDEV_DOWN: 1256 if (test_and_set_bit(QLNXR_ENET_STATE_BIT, &dev->enet_state)) 1257 qlnxr_ib_dispatch_event(dev, QLNXR_PORT, 1258 IB_EVENT_PORT_ERR); 1259 break; 1260 } 1261 1262 QL_DPRINT12(ha, "exit (%p, %d)\n", qlnx_rdma_dev, event); 1263 return; 1264} 1265 1266static int 1267qlnxr_mod_load(void) 1268{ 1269 int ret; 1270 1271 qlnxr_drv.add = qlnxr_add; 1272 qlnxr_drv.remove = qlnxr_remove; 1273 qlnxr_drv.notify = qlnxr_notify; 1274 1275 ret = qlnx_rdma_register_if(&qlnxr_drv); 1276 1277 return (ret); 1278} 1279 1280static int 1281qlnxr_mod_unload(void) 1282{ 1283 int ret; 1284 1285 ret = qlnx_rdma_deregister_if(&qlnxr_drv); 1286 return (ret); 1287} 1288 1289static int 1290qlnxr_event_handler(module_t mod, int event, void *arg) 1291{ 1292 1293 int ret = 0; 1294 1295 switch (event) { 1296 case MOD_LOAD: 1297 ret = qlnxr_mod_load(); 1298 break; 1299 1300 case MOD_UNLOAD: 1301 ret = qlnxr_mod_unload(); 1302 break; 1303 1304 default: 1305 break; 1306 } 1307 1308 return (ret); 1309} 1310 1311static moduledata_t qlnxr_mod_info = { 1312 .name = "qlnxr", 1313 .evhand = qlnxr_event_handler, 1314}; 1315 1316MODULE_VERSION(qlnxr, 1); 1317MODULE_DEPEND(qlnxr, if_qlnxe, 1, 1, 1); 1318MODULE_DEPEND(qlnxr, ibcore, 1, 1, 1); 1319MODULE_DEPEND(qlnxr, linuxkpi, 1, 1, 1); 1320 1321DECLARE_MODULE(qlnxr, qlnxr_mod_info, SI_SUB_LAST, SI_ORDER_ANY); 1322