1/* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29#ifndef __ECORE_HSI_FCOE__ 30#define __ECORE_HSI_FCOE__ 31/****************************************/ 32/* Add include to common storage target */ 33/****************************************/ 34#include "storage_common.h" 35 36/************************************************************************/ 37/* Add include to common fcoe target for both eCore and protocol driver */ 38/************************************************************************/ 39#include "fcoe_common.h" 40 41/* 42 * The fcoe storm context of Ystorm 43 */ 44struct ystorm_fcoe_conn_st_ctx 45{ 46 u8 func_mode /* Function mode */; 47 u8 cos /* Transmission cos */; 48 u8 conf_version /* Is dcb_version or vntag_version changed */; 49 u8 eth_hdr_size /* Ethernet header size */; 50 __le16 stat_ram_addr /* Statistics ram adderss */; 51 __le16 mtu /* MTU limitation */; 52 __le16 max_fc_payload_len /* Max payload length according to target limitation and mtu. 8 bytes aligned (required for protection fast-path) */; 53 __le16 tx_max_fc_pay_len /* Max payload length according to target limitation */; 54 u8 fcp_cmd_size /* FCP cmd size. for performance reasons */; 55 u8 fcp_rsp_size /* FCP RSP size. for performance reasons */; 56 __le16 mss /* MSS for PBF (MSS we negotiate with target - protection data per segment. If we are not in perf mode it will be according to worse case) */; 57 struct regpair reserved; 58 __le16 min_frame_size /* The minimum ETH frame size required for transmission (including ETH header) */; 59 u8 protection_info_flags; 60#define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1 /* Does this connection support protection (if couple of GOS share this connection it�� ��������������s enough that one of them support protection) */ 61#define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 0 62#define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1 /* Are we in protection perf mode (there is only one protection mode for this connection and we manage to create mss that contain fixed amount of protection segment and we are only restrict by the target limitation and not line mss this is critical since if line mss restrict us we can�� ��������������t rely on this size �� �������������� it depends on vlan num) */ 63#define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 1 64#define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK 0x3F 65#define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT 2 66 u8 dst_protection_per_mss /* Destination Protection data per mss (if we are not in perf mode it will be worse case). Destination is the data add/remove from the transmitted packet (as opposed to src which is data validate by the nic they might not be identical) */; 67 u8 src_protection_per_mss /* Source Protection data per mss (if we are not in perf mode it will be worse case). Source is the data validated by the nic (as opposed to destination which is data add/remove from the transmitted packet they might not be identical) */; 68 u8 ptu_log_page_size /* 0-4K, 1-8K, 2-16K, 3-32K... */; 69 u8 flags; 70#define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 /* Inner Vlan flag */ 71#define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 0 72#define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 /* Outer Vlan flag */ 73#define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 1 74#define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x3F 75#define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 2 76 u8 fcp_xfer_size /* FCP xfer size. for performance reasons */; 77}; 78 79/* 80 * FCoE 16-bits vlan structure 81 */ 82struct fcoe_vlan_fields 83{ 84 __le16 fields; 85#define FCOE_VLAN_FIELDS_VID_MASK 0xFFF 86#define FCOE_VLAN_FIELDS_VID_SHIFT 0 87#define FCOE_VLAN_FIELDS_CLI_MASK 0x1 88#define FCOE_VLAN_FIELDS_CLI_SHIFT 12 89#define FCOE_VLAN_FIELDS_PRI_MASK 0x7 90#define FCOE_VLAN_FIELDS_PRI_SHIFT 13 91}; 92 93/* 94 * FCoE 16-bits vlan union 95 */ 96union fcoe_vlan_field_union 97{ 98 struct fcoe_vlan_fields fields /* Parameters field */; 99 __le16 val /* Global value */; 100}; 101 102/* 103 * FCoE 16-bits vlan, vif union 104 */ 105union fcoe_vlan_vif_field_union 106{ 107 union fcoe_vlan_field_union vlan /* Vlan */; 108 __le16 vif /* VIF */; 109}; 110 111/* 112 * Ethernet context section 113 */ 114struct pstorm_fcoe_eth_context_section 115{ 116 u8 remote_addr_3 /* Remote Mac Address, used in PBF Header Builder Command */; 117 u8 remote_addr_2 /* Remote Mac Address, used in PBF Header Builder Command */; 118 u8 remote_addr_1 /* Remote Mac Address, used in PBF Header Builder Command */; 119 u8 remote_addr_0 /* Remote Mac Address, used in PBF Header Builder Command */; 120 u8 local_addr_1 /* Local Mac Address, used in PBF Header Builder Command */; 121 u8 local_addr_0 /* Local Mac Address, used in PBF Header Builder Command */; 122 u8 remote_addr_5 /* Remote Mac Address, used in PBF Header Builder Command */; 123 u8 remote_addr_4 /* Remote Mac Address, used in PBF Header Builder Command */; 124 u8 local_addr_5 /* Local Mac Address, used in PBF Header Builder Command */; 125 u8 local_addr_4 /* Loca lMac Address, used in PBF Header Builder Command */; 126 u8 local_addr_3 /* Local Mac Address, used in PBF Header Builder Command */; 127 u8 local_addr_2 /* Local Mac Address, used in PBF Header Builder Command */; 128 union fcoe_vlan_vif_field_union vif_outer_vlan /* Union of VIF and outer vlan */; 129 __le16 vif_outer_eth_type /* reserved place for Ethernet type */; 130 union fcoe_vlan_vif_field_union inner_vlan /* inner vlan tag */; 131 __le16 inner_eth_type /* reserved place for Ethernet type */; 132}; 133 134/* 135 * The fcoe storm context of Pstorm 136 */ 137struct pstorm_fcoe_conn_st_ctx 138{ 139 u8 func_mode /* Function mode */; 140 u8 cos /* Transmission cos */; 141 u8 conf_version /* Is dcb_version or vntag_version changed */; 142 u8 rsrv; 143 __le16 stat_ram_addr /* Statistics ram adderss */; 144 __le16 mss /* MSS for PBF (MSS we negotiate with target - protection data per segment. If we are not in perf mode it will be according to worse case) */; 145 struct regpair abts_cleanup_addr /* Host addr of ABTS /Cleanup info. since we pass it through session context, we pass only the addr to save space */; 146 struct pstorm_fcoe_eth_context_section eth /* Source mac */; 147 u8 sid_2 /* SID FC address - Third byte that is sent to NW via PBF For example is SID is 01:02:03 then sid_2 is 0x03 */; 148 u8 sid_1 /* SID FC address - Second byte that is sent to NW via PBF */; 149 u8 sid_0 /* SID FC address - First byte that is sent to NW via PBF */; 150 u8 flags; 151#define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1 /* Is inner vlan taken from vntag default vlan (in this case I have to update inner vlan each time the default change) */ 152#define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT 0 153#define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1 /* AreSupport rec_tov timer */ 154#define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT 1 155#define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 /* Inner Vlan flag */ 156#define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 2 157#define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 /* Outer Vlan flag */ 158#define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 3 159#define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_MASK 0x1 /* Indicaiton that there should be a single vlan (for UFP mode) */ 160#define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_SHIFT 4 161#define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x7 162#define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 5 163 u8 did_2 /* DID FC address - Third byte that is sent to NW via PBF */; 164 u8 did_1 /* DID FC address - Second byte that is sent to NW via PBF */; 165 u8 did_0 /* DID FC address - First byte that is sent to NW via PBF */; 166 u8 src_mac_index; 167 __le16 rec_rr_tov_val /* REC_TOV value negotiated during PLOGI (in msec) */; 168 u8 q_relative_offset /* CQ, RQ (and CMDQ) relative offset for connection */; 169 u8 reserved1; 170}; 171 172/* 173 * The fcoe storm context of Xstorm 174 */ 175struct xstorm_fcoe_conn_st_ctx 176{ 177 u8 func_mode /* Function mode */; 178 u8 src_mac_index /* Index to the src_mac arr held in the xStorm RAM. Provided at the xStorm offload connection handler */; 179 u8 conf_version /* Advance if vntag/dcb version advance */; 180 u8 cached_wqes_avail /* Number of cached wqes available */; 181 __le16 stat_ram_addr /* Statistics ram adderss */; 182 u8 flags; 183#define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1 /* SQ deferred (happens when we wait for xfer wqe to complete cleanup/abts */ 184#define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT 0 185#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 /* Inner vlan flag ����� for calculating eth header size */ 186#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 1 187#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK 0x1 /* Original vlan configuration. used when we switch from dcb enable to dcb disabled */ 188#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT 2 189#define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3 190#define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT 3 191#define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x7 192#define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 5 193 u8 cached_wqes_offset /* Offset of first valid cached wqe */; 194 u8 reserved2; 195 u8 eth_hdr_size /* Ethernet header size */; 196 u8 seq_id /* Sequence id */; 197 u8 max_conc_seqs /* Max concurrent sequence id */; 198 __le16 num_pages_in_pbl /* Num of pages in SQ/RESPQ/XFERQ Pbl */; 199 __le16 reserved; 200 struct regpair sq_pbl_addr /* SQ address */; 201 struct regpair sq_curr_page_addr /* SQ current page address */; 202 struct regpair sq_next_page_addr /* SQ next page address */; 203 struct regpair xferq_pbl_addr /* XFERQ address */; 204 struct regpair xferq_curr_page_addr /* XFERQ current page address */; 205 struct regpair xferq_next_page_addr /* XFERQ next page address */; 206 struct regpair respq_pbl_addr /* RESPQ address */; 207 struct regpair respq_curr_page_addr /* RESPQ current page address */; 208 struct regpair respq_next_page_addr /* RESPQ next page address */; 209 __le16 mtu /* MTU limitation */; 210 __le16 tx_max_fc_pay_len /* Max payload length according to target limitation */; 211 __le16 max_fc_payload_len /* Max payload length according to target limitation and mtu. Aligned to 4 bytes. */; 212 __le16 min_frame_size /* The minimum ETH frame size required for transmission (including ETH header, excluding ETH CRC */; 213 __le16 sq_pbl_next_index /* Next index of SQ Pbl */; 214 __le16 respq_pbl_next_index /* Next index of RESPQ Pbl */; 215 u8 fcp_cmd_byte_credit /* Pre-calculated byte credit that single FCP command can consume */; 216 u8 fcp_rsp_byte_credit /* Pre-calculated byte credit that single FCP RSP can consume. */; 217 __le16 protection_info; 218#define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK 0x1 /* Intend to accelerate the protection flows */ 219#define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT 0 220#define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1 /* Does this connection support protection (if couple of GOS share this connection is enough that one of them support protection) */ 221#define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 1 222#define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1 /* Are we in protection perf mode (there is only one protection mode for this connection and we manage to create mss that contain fixed amount of protection segment and we are only restrict by the target limitation and not line mss this is critical since if line mss restrict us we can��������t rely on this size ����� it depends on vlan num) */ 223#define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 2 224#define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK 0x1 /* Is size of tx_max_pay_len_prot can be aligned to protection intervals. This means that pure data in each frame is 2k exactly, and protection intervals are no bigger than 2k */ 225#define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT 3 226#define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK 0xF 227#define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT 4 228#define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK 0xFF /* Destination Pro tection data per mss (if we are not in perf mode it will be worse case). Destination is the data add/remove from the transmitted packet (as opposed to src which is data validate by the nic they might not be identical) */ 229#define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT 8 230 __le16 xferq_pbl_next_index /* Next index of XFERQ Pbl */; 231 __le16 page_size /* Page size (in bytes) */; 232 u8 mid_seq /* Equals 1 for Middle sequence indication, otherwise 0 */; 233 u8 fcp_xfer_byte_credit /* Pre-calculated byte credit that single FCP command can consume */; 234 u8 reserved1[2]; 235 struct fcoe_wqe cached_wqes[16] /* cached wqe (8) = 8*8*8Bytes */; 236}; 237 238struct e4_xstorm_fcoe_conn_ag_ctx 239{ 240 u8 reserved0 /* cdu_validation */; 241 u8 state /* state */; 242 u8 flags0; 243#define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 244#define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 245#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 246#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT 1 247#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 248#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT 2 249#define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 250#define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 251#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 252#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT 4 253#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 254#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT 5 255#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 256#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT 6 257#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 258#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT 7 259 u8 flags1; 260#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 261#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0 262#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 263#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT 1 264#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 265#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT 2 266#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 267#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT 3 268#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 269#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT 4 270#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 271#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT 5 272#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */ 273#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT 6 274#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1 /* bit15 */ 275#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT 7 276 u8 flags2; 277#define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 278#define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0 279#define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 280#define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 2 281#define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 282#define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 4 283#define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 284#define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 6 285 u8 flags3; 286#define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 287#define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0 288#define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 289#define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 2 290#define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 291#define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 4 292#define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 293#define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 6 294 u8 flags4; 295#define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 296#define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0 297#define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 298#define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 2 299#define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 300#define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 4 301#define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 302#define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT 6 303 u8 flags5; 304#define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 305#define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0 306#define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 307#define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT 2 308#define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 309#define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT 4 310#define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 311#define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT 6 312 u8 flags6; 313#define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 314#define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0 315#define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 316#define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT 2 317#define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 318#define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT 4 319#define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf19 */ 320#define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT 6 321 u8 flags7; 322#define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 323#define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 324#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 325#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT 2 326#define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 327#define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 328#define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 329#define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 6 330#define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 331#define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 7 332 u8 flags8; 333#define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 334#define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0 335#define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 336#define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 1 337#define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 338#define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 2 339#define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 340#define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 3 341#define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 342#define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 4 343#define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 344#define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 5 345#define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 346#define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 6 347#define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 348#define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 7 349 u8 flags9; 350#define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 351#define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0 352#define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 353#define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1 354#define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 355#define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2 356#define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 357#define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3 358#define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 359#define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4 360#define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 361#define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5 362#define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 363#define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6 364#define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 365#define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7 366 u8 flags10; 367#define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 368#define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0 369#define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf19en */ 370#define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 1 371#define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 372#define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 373#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 374#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT 3 375#define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 376#define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 377#define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 378#define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT 5 379#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 380#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT 6 381#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 382#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT 7 383 u8 flags11; 384#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 385#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0 386#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 387#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT 1 388#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1 /* rule4en */ 389#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT 2 390#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 391#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 3 392#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 393#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 4 394#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 395#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 5 396#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 397#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 398#define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1 /* rule9en */ 399#define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7 400 u8 flags12; 401#define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1 /* rule10en */ 402#define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0 403#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 404#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT 1 405#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 406#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 407#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 408#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 409#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 410#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT 4 411#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 412#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT 5 413#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 414#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT 6 415#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 416#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT 7 417 u8 flags13; 418#define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1 /* rule18en */ 419#define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0 420#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 421#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT 1 422#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 423#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 424#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 425#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 426#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 427#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 428#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 429#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 430#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 431#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 432#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 433#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 434 u8 flags14; 435#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 436#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0 437#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 438#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT 1 439#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */ 440#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT 2 441#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */ 442#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT 3 443#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */ 444#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT 4 445#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */ 446#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT 5 447#define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 448#define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT 6 449 u8 byte2 /* byte2 */; 450 __le16 physical_q0 /* physical_q0 */; 451 __le16 word1 /* physical_q1 */; 452 __le16 word2 /* physical_q2 */; 453 __le16 sq_cons /* word3 */; 454 __le16 sq_prod /* word4 */; 455 __le16 xferq_prod /* word5 */; 456 __le16 xferq_cons /* conn_dpi */; 457 u8 byte3 /* byte3 */; 458 u8 byte4 /* byte4 */; 459 u8 byte5 /* byte5 */; 460 u8 byte6 /* byte6 */; 461 __le32 remain_io /* reg0 */; 462 __le32 reg1 /* reg1 */; 463 __le32 reg2 /* reg2 */; 464 __le32 reg3 /* reg3 */; 465 __le32 reg4 /* reg4 */; 466 __le32 reg5 /* cf_array0 */; 467 __le32 reg6 /* cf_array1 */; 468 __le16 respq_prod /* word7 */; 469 __le16 respq_cons /* word8 */; 470 __le16 word9 /* word9 */; 471 __le16 word10 /* word10 */; 472 __le32 reg7 /* reg7 */; 473 __le32 reg8 /* reg8 */; 474}; 475 476/* 477 * The fcoe storm context of Ustorm 478 */ 479struct ustorm_fcoe_conn_st_ctx 480{ 481 struct regpair respq_pbl_addr /* RespQ Pbl base address */; 482 __le16 num_pages_in_pbl /* Number of RespQ pbl pages (both have same wqe size) */; 483 u8 ptu_log_page_size /* 0-4K, 1-8K, 2-16K, 3-32K... */; 484 u8 log_page_size; 485 __le16 respq_prod /* RespQ producer */; 486 u8 reserved[2]; 487}; 488 489struct e4_tstorm_fcoe_conn_ag_ctx 490{ 491 u8 reserved0 /* cdu_validation */; 492 u8 state /* state */; 493 u8 flags0; 494#define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 495#define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 496#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 497#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 498#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 499#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT 2 500#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 501#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT 3 502#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 503#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT 4 504#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 505#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT 5 506#define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3 /* timer0cf */ 507#define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6 508 u8 flags1; 509#define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* timer1cf */ 510#define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0 511#define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 512#define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 2 513#define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */ 514#define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 515#define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 516#define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 6 517 u8 flags2; 518#define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 519#define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0 520#define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 521#define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 2 522#define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 523#define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 4 524#define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 525#define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 6 526 u8 flags3; 527#define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 528#define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0 529#define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 530#define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 2 531#define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1 /* cf0en */ 532#define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT 4 533#define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf1en */ 534#define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 535#define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 536#define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 6 537#define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */ 538#define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 539 u8 flags4; 540#define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 541#define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0 542#define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 543#define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 1 544#define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 545#define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 2 546#define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 547#define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 3 548#define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 549#define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 4 550#define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 551#define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 5 552#define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 553#define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 6 554#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 555#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7 556 u8 flags5; 557#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 558#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0 559#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 560#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1 561#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 562#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2 563#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 564#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3 565#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 566#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4 567#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 568#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5 569#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 570#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6 571#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 572#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7 573 __le32 reg0 /* reg0 */; 574 __le32 reg1 /* reg1 */; 575}; 576 577struct e4_ustorm_fcoe_conn_ag_ctx 578{ 579 u8 byte0 /* cdu_validation */; 580 u8 byte1 /* state */; 581 u8 flags0; 582#define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 583#define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 584#define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 585#define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 586#define E4_USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 587#define E4_USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 588#define E4_USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 589#define E4_USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 590#define E4_USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 591#define E4_USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 592 u8 flags1; 593#define E4_USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 594#define E4_USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0 595#define E4_USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 596#define E4_USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 2 597#define E4_USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 598#define E4_USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 4 599#define E4_USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 600#define E4_USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 6 601 u8 flags2; 602#define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 603#define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 604#define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 605#define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 606#define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 607#define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 608#define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 609#define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 3 610#define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 611#define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 4 612#define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 613#define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 5 614#define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 615#define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 6 616#define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 617#define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7 618 u8 flags3; 619#define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 620#define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0 621#define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 622#define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1 623#define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 624#define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2 625#define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 626#define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3 627#define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 628#define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4 629#define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 630#define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5 631#define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 632#define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6 633#define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 634#define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7 635 u8 byte2 /* byte2 */; 636 u8 byte3 /* byte3 */; 637 __le16 word0 /* conn_dpi */; 638 __le16 word1 /* word1 */; 639 __le32 reg0 /* reg0 */; 640 __le32 reg1 /* reg1 */; 641 __le32 reg2 /* reg2 */; 642 __le32 reg3 /* reg3 */; 643 __le16 word2 /* word2 */; 644 __le16 word3 /* word3 */; 645}; 646 647/* 648 * The fcoe storm context of Tstorm 649 */ 650struct tstorm_fcoe_conn_st_ctx 651{ 652 __le16 stat_ram_addr /* Statistics ram adderss */; 653 __le16 rx_max_fc_payload_len /* Max rx fc payload length. provided in ramrod */; 654 __le16 e_d_tov_val /* E_D_TOV value negotiated during PLOGI (in msec) */; 655 u8 flags; 656#define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK 0x1 /* Does the target support increment sequence counter */ 657#define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT 0 658#define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK 0x1 /* Does the connection support CONF REQ transmission */ 659#define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT 1 660#define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK 0x3F /* Default queue index the connection associated to */ 661#define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT 2 662 u8 timers_cleanup_invocation_cnt /* This variable is incremented each time the tStorm handler for timers cleanup is invoked within the same timers cleanup flow */; 663 __le32 reserved1[2]; 664 __le32 dstMacAddressBytes0To3 /* destination MAC address: Bytes 0-3. */; 665 __le16 dstMacAddressBytes4To5 /* destination MAC address: Bytes 4-5. */; 666 __le16 ramrodEcho /* Saved ramrod echo - needed for 2nd round of terminate_conn (flush Q0) */; 667 u8 flags1; 668#define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK 0x3 /* Indicate the mode of the connection: Target or Initiator, use enum fcoe_mode_type */ 669#define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT 0 670#define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x3F 671#define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 2 672 u8 cq_relative_offset /* CQ relative offset for connection */; 673 u8 cmdq_relative_offset /* CmdQ relative offset for connection */; 674 u8 bdq_resource_id /* The BDQ resource ID to which this function is mapped */; 675 u8 reserved0[4] /* Alignment to 128b */; 676}; 677 678struct e4_mstorm_fcoe_conn_ag_ctx 679{ 680 u8 byte0 /* cdu_validation */; 681 u8 byte1 /* state */; 682 u8 flags0; 683#define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 684#define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 685#define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 686#define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 687#define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 688#define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 689#define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 690#define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 691#define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 692#define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 693 u8 flags1; 694#define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 695#define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 696#define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 697#define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 698#define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 699#define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 700#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 701#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3 702#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 703#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4 704#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 705#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5 706#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 707#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6 708#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 709#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7 710 __le16 word0 /* word0 */; 711 __le16 word1 /* word1 */; 712 __le32 reg0 /* reg0 */; 713 __le32 reg1 /* reg1 */; 714}; 715 716/* 717 * Fast path part of the fcoe storm context of Mstorm 718 */ 719struct fcoe_mstorm_fcoe_conn_st_ctx_fp 720{ 721 __le16 xfer_prod /* XferQ producer */; 722 u8 num_cqs /* Number of CQs per function (internal to FW) */; 723 u8 reserved1; 724 u8 protection_info; 725#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK 0x1 /* Does this connection support protection (if couple of GOS share this connection it is enough that one of them support protection) */ 726#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0 727#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK 0x1 /* Are we in protection perf mode (there is only one protection mode for this connection and we manage to create mss that contain fixed amount of protection segment and we are only restrict by the target limitation and not line mss ����� this is critical since if line mss restrict us we can��������t rely on this size ����� it depends on vlan num) */ 728#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_SHIFT 1 729#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_MASK 0x3F 730#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_SHIFT 2 731 u8 q_relative_offset /* CQ, RQ and CMDQ relative offset for connection */; 732 u8 reserved2[2]; 733}; 734 735/* 736 * Non fast path part of the fcoe storm context of Mstorm 737 */ 738struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp 739{ 740 __le16 conn_id /* Driver connection ID. To be used by slowpaths to fill EQ placement params */; 741 __le16 stat_ram_addr /* Statistics ram adderss */; 742 __le16 num_pages_in_pbl /* Number of XferQ/RespQ pbl pages (both have same wqe size) */; 743 u8 ptu_log_page_size /* 0-4K, 1-8K, 2-16K, 3-32K... */; 744 u8 log_page_size; 745 __le16 unsolicited_cq_count /* Counts number of CQs done due to unsolicited packets on this connection */; 746 __le16 cmdq_count /* Counts number of CMDQs done on this connection */; 747 u8 bdq_resource_id /* BDQ Resource ID */; 748 u8 reserved0[3] /* Padding bytes for 2nd RegPair */; 749 struct regpair xferq_pbl_addr /* XferQ Pbl base address */; 750 struct regpair reserved1; 751 struct regpair reserved2[3]; 752}; 753 754/* 755 * The fcoe storm context of Mstorm 756 */ 757struct mstorm_fcoe_conn_st_ctx 758{ 759 struct fcoe_mstorm_fcoe_conn_st_ctx_fp fp /* Fast path part of the fcoe storm context of Mstorm */; 760 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp non_fp /* Non fast path part of the fcoe storm context of Mstorm */; 761}; 762 763/* 764 * fcoe connection context 765 */ 766struct e4_fcoe_conn_context 767{ 768 struct ystorm_fcoe_conn_st_ctx ystorm_st_context /* ystorm storm context */; 769 struct pstorm_fcoe_conn_st_ctx pstorm_st_context /* pstorm storm context */; 770 struct regpair pstorm_st_padding[2] /* padding */; 771 struct xstorm_fcoe_conn_st_ctx xstorm_st_context /* xstorm storm context */; 772 struct e4_xstorm_fcoe_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 773 struct regpair xstorm_ag_padding[6] /* padding */; 774 struct ustorm_fcoe_conn_st_ctx ustorm_st_context /* ustorm storm context */; 775 struct regpair ustorm_st_padding[2] /* padding */; 776 struct e4_tstorm_fcoe_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 777 struct regpair tstorm_ag_padding[2] /* padding */; 778 struct timers_context timer_context /* timer context */; 779 struct e4_ustorm_fcoe_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 780 struct tstorm_fcoe_conn_st_ctx tstorm_st_context /* tstorm storm context */; 781 struct e4_mstorm_fcoe_conn_ag_ctx mstorm_ag_context /* mstorm aggregative context */; 782 struct mstorm_fcoe_conn_st_ctx mstorm_st_context /* mstorm storm context */; 783}; 784 785struct e5_xstorm_fcoe_conn_ag_ctx 786{ 787 u8 reserved0 /* cdu_validation */; 788 u8 state_and_core_id /* state_and_core_id */; 789 u8 flags0; 790#define E5_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 791#define E5_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 792#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 793#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT 1 794#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 795#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT 2 796#define E5_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 797#define E5_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 798#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 799#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT 4 800#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 801#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT 5 802#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 803#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT 6 804#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 805#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT 7 806 u8 flags1; 807#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 808#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0 809#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 810#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT 1 811#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 812#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT 2 813#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 814#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT 3 815#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 816#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT 4 817#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 818#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT 5 819#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */ 820#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT 6 821#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1 /* bit15 */ 822#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT 7 823 u8 flags2; 824#define E5_XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 825#define E5_XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0 826#define E5_XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 827#define E5_XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 2 828#define E5_XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 829#define E5_XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 4 830#define E5_XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 831#define E5_XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 6 832 u8 flags3; 833#define E5_XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 834#define E5_XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0 835#define E5_XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 836#define E5_XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 2 837#define E5_XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 838#define E5_XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 4 839#define E5_XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 840#define E5_XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 6 841 u8 flags4; 842#define E5_XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 843#define E5_XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0 844#define E5_XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 845#define E5_XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 2 846#define E5_XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 847#define E5_XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 4 848#define E5_XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 849#define E5_XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT 6 850 u8 flags5; 851#define E5_XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 852#define E5_XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0 853#define E5_XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 854#define E5_XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT 2 855#define E5_XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 856#define E5_XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT 4 857#define E5_XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 858#define E5_XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT 6 859 u8 flags6; 860#define E5_XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 861#define E5_XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0 862#define E5_XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 863#define E5_XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT 2 864#define E5_XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 865#define E5_XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT 4 866#define E5_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf19 */ 867#define E5_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT 6 868 u8 flags7; 869#define E5_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 870#define E5_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 871#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 872#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT 2 873#define E5_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 874#define E5_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 875#define E5_XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 876#define E5_XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 6 877#define E5_XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 878#define E5_XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 7 879 u8 flags8; 880#define E5_XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 881#define E5_XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0 882#define E5_XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 883#define E5_XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 1 884#define E5_XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 885#define E5_XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 2 886#define E5_XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 887#define E5_XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 3 888#define E5_XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 889#define E5_XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 4 890#define E5_XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 891#define E5_XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 5 892#define E5_XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 893#define E5_XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 6 894#define E5_XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 895#define E5_XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 7 896 u8 flags9; 897#define E5_XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 898#define E5_XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0 899#define E5_XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 900#define E5_XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1 901#define E5_XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 902#define E5_XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2 903#define E5_XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 904#define E5_XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3 905#define E5_XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 906#define E5_XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4 907#define E5_XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 908#define E5_XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5 909#define E5_XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 910#define E5_XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6 911#define E5_XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 912#define E5_XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7 913 u8 flags10; 914#define E5_XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 915#define E5_XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0 916#define E5_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf19en */ 917#define E5_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 1 918#define E5_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 919#define E5_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 920#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 921#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT 3 922#define E5_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 923#define E5_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 924#define E5_XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 925#define E5_XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT 5 926#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 927#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT 6 928#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 929#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT 7 930 u8 flags11; 931#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 932#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0 933#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 934#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT 1 935#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1 /* rule4en */ 936#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT 2 937#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 938#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 3 939#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 940#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 4 941#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 942#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 5 943#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 944#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 945#define E5_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1 /* rule9en */ 946#define E5_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7 947 u8 flags12; 948#define E5_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1 /* rule10en */ 949#define E5_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0 950#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 951#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT 1 952#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 953#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 954#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 955#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 956#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 957#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT 4 958#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 959#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT 5 960#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 961#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT 6 962#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 963#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT 7 964 u8 flags13; 965#define E5_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1 /* rule18en */ 966#define E5_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0 967#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 968#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT 1 969#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 970#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 971#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 972#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 973#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 974#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 975#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 976#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 977#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 978#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 979#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 980#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 981 u8 flags14; 982#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 983#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0 984#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 985#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT 1 986#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */ 987#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT 2 988#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */ 989#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT 3 990#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */ 991#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT 4 992#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */ 993#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT 5 994#define E5_XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 995#define E5_XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT 6 996 u8 byte2 /* byte2 */; 997 __le16 physical_q0 /* physical_q0 */; 998 __le16 word1 /* physical_q1 */; 999 __le16 word2 /* physical_q2 */; 1000 __le16 sq_cons /* word3 */; 1001 __le16 sq_prod /* word4 */; 1002 __le16 xferq_prod /* word5 */; 1003 __le16 xferq_cons /* conn_dpi */; 1004 u8 byte3 /* byte3 */; 1005 u8 byte4 /* byte4 */; 1006 u8 byte5 /* byte5 */; 1007 u8 byte6 /* byte6 */; 1008 __le32 remain_io /* reg0 */; 1009 __le32 reg1 /* reg1 */; 1010 __le32 reg2 /* reg2 */; 1011 __le32 reg3 /* reg3 */; 1012 __le32 reg4 /* reg4 */; 1013 __le32 reg5 /* cf_array0 */; 1014 __le32 reg6 /* cf_array1 */; 1015 u8 flags15; 1016#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit22 */ 1017#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1018#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit23 */ 1019#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1020#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit24 */ 1021#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1022#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf24 */ 1023#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 1024#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf24en */ 1025#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 1026#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule26en */ 1027#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 1028#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule27en */ 1029#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 1030 u8 byte7 /* byte7 */; 1031 __le16 respq_prod /* word7 */; 1032 __le16 respq_cons /* word8 */; 1033 __le16 word9 /* word9 */; 1034 __le16 word10 /* word10 */; 1035 __le16 word11 /* word11 */; 1036 __le32 reg7 /* reg7 */; 1037}; 1038 1039struct e5_tstorm_fcoe_conn_ag_ctx 1040{ 1041 u8 reserved0 /* cdu_validation */; 1042 u8 state_and_core_id /* state_and_core_id */; 1043 u8 flags0; 1044#define E5_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1045#define E5_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1046#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1047#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 1048#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1049#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT 2 1050#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1051#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT 3 1052#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1053#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT 4 1054#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 1055#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT 5 1056#define E5_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3 /* timer0cf */ 1057#define E5_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6 1058 u8 flags1; 1059#define E5_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* timer1cf */ 1060#define E5_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0 1061#define E5_TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1062#define E5_TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 2 1063#define E5_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */ 1064#define E5_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 1065#define E5_TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1066#define E5_TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 6 1067 u8 flags2; 1068#define E5_TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1069#define E5_TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0 1070#define E5_TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1071#define E5_TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 2 1072#define E5_TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1073#define E5_TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 4 1074#define E5_TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1075#define E5_TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 6 1076 u8 flags3; 1077#define E5_TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1078#define E5_TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0 1079#define E5_TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1080#define E5_TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 2 1081#define E5_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1 /* cf0en */ 1082#define E5_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT 4 1083#define E5_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf1en */ 1084#define E5_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 1085#define E5_TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1086#define E5_TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 6 1087#define E5_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */ 1088#define E5_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 1089 u8 flags4; 1090#define E5_TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1091#define E5_TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0 1092#define E5_TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1093#define E5_TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 1 1094#define E5_TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1095#define E5_TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 2 1096#define E5_TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1097#define E5_TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 3 1098#define E5_TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1099#define E5_TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 4 1100#define E5_TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1101#define E5_TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 5 1102#define E5_TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1103#define E5_TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 6 1104#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1105#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7 1106 u8 flags5; 1107#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1108#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0 1109#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1110#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1 1111#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1112#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2 1113#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1114#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3 1115#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1116#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4 1117#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1118#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5 1119#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1120#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6 1121#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1122#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7 1123 u8 flags6; 1124#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */ 1125#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1126#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */ 1127#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1128#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */ 1129#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1130#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */ 1131#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 1132#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */ 1133#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 1134#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */ 1135#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 1136#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */ 1137#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 1138 u8 byte2 /* byte2 */; 1139 __le16 word0 /* word0 */; 1140 __le32 reg0 /* reg0 */; 1141}; 1142 1143struct e5_ustorm_fcoe_conn_ag_ctx 1144{ 1145 u8 byte0 /* cdu_validation */; 1146 u8 byte1 /* state_and_core_id */; 1147 u8 flags0; 1148#define E5_USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1149#define E5_USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 1150#define E5_USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1151#define E5_USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 1152#define E5_USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1153#define E5_USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 1154#define E5_USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1155#define E5_USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 1156#define E5_USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1157#define E5_USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 1158 u8 flags1; 1159#define E5_USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1160#define E5_USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0 1161#define E5_USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1162#define E5_USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 2 1163#define E5_USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1164#define E5_USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 4 1165#define E5_USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1166#define E5_USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 6 1167 u8 flags2; 1168#define E5_USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1169#define E5_USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 1170#define E5_USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1171#define E5_USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 1172#define E5_USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1173#define E5_USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 1174#define E5_USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1175#define E5_USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 3 1176#define E5_USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1177#define E5_USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 4 1178#define E5_USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1179#define E5_USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 5 1180#define E5_USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1181#define E5_USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 6 1182#define E5_USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1183#define E5_USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7 1184 u8 flags3; 1185#define E5_USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1186#define E5_USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0 1187#define E5_USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1188#define E5_USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1 1189#define E5_USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1190#define E5_USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2 1191#define E5_USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1192#define E5_USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3 1193#define E5_USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1194#define E5_USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4 1195#define E5_USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1196#define E5_USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5 1197#define E5_USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1198#define E5_USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6 1199#define E5_USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1200#define E5_USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7 1201 u8 flags4; 1202#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 1203#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1204#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 1205#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1206#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */ 1207#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1208#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */ 1209#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED4_SHIFT 4 1210#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */ 1211#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_SHIFT 6 1212#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */ 1213#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_SHIFT 7 1214 u8 byte2 /* byte2 */; 1215 __le16 word0 /* conn_dpi */; 1216 __le16 word1 /* word1 */; 1217 __le32 reg0 /* reg0 */; 1218 __le32 reg1 /* reg1 */; 1219 __le32 reg2 /* reg2 */; 1220 __le32 reg3 /* reg3 */; 1221 __le16 word2 /* word2 */; 1222 __le16 word3 /* word3 */; 1223}; 1224 1225struct e5_mstorm_fcoe_conn_ag_ctx 1226{ 1227 u8 byte0 /* cdu_validation */; 1228 u8 byte1 /* state_and_core_id */; 1229 u8 flags0; 1230#define E5_MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1231#define E5_MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 1232#define E5_MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1233#define E5_MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 1234#define E5_MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1235#define E5_MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 1236#define E5_MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1237#define E5_MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 1238#define E5_MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1239#define E5_MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 1240 u8 flags1; 1241#define E5_MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1242#define E5_MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 1243#define E5_MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1244#define E5_MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 1245#define E5_MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1246#define E5_MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 1247#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1248#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3 1249#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1250#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4 1251#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1252#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5 1253#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1254#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6 1255#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1256#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7 1257 __le16 word0 /* word0 */; 1258 __le16 word1 /* word1 */; 1259 __le32 reg0 /* reg0 */; 1260 __le32 reg1 /* reg1 */; 1261}; 1262 1263/* 1264 * fcoe connection context 1265 */ 1266struct e5_fcoe_conn_context 1267{ 1268 struct ystorm_fcoe_conn_st_ctx ystorm_st_context /* ystorm storm context */; 1269 struct pstorm_fcoe_conn_st_ctx pstorm_st_context /* pstorm storm context */; 1270 struct regpair pstorm_st_padding[2] /* padding */; 1271 struct xstorm_fcoe_conn_st_ctx xstorm_st_context /* xstorm storm context */; 1272 struct e5_xstorm_fcoe_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 1273 struct ustorm_fcoe_conn_st_ctx ustorm_st_context /* ustorm storm context */; 1274 struct regpair ustorm_st_padding[2] /* padding */; 1275 struct e5_tstorm_fcoe_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 1276 struct regpair tstorm_ag_padding[2] /* padding */; 1277 struct timers_context timer_context /* timer context */; 1278 struct e5_ustorm_fcoe_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 1279 struct tstorm_fcoe_conn_st_ctx tstorm_st_context /* tstorm storm context */; 1280 struct e5_mstorm_fcoe_conn_ag_ctx mstorm_ag_context /* mstorm aggregative context */; 1281 struct mstorm_fcoe_conn_st_ctx mstorm_st_context /* mstorm storm context */; 1282}; 1283 1284/* 1285 * FCoE connection offload params passed by driver to FW in FCoE offload ramrod 1286 */ 1287struct fcoe_conn_offload_ramrod_params 1288{ 1289 struct fcoe_conn_offload_ramrod_data offload_ramrod_data; 1290}; 1291 1292/* 1293 * FCoE connection terminate params passed by driver to FW in FCoE terminate conn ramrod 1294 */ 1295struct fcoe_conn_terminate_ramrod_params 1296{ 1297 struct fcoe_conn_terminate_ramrod_data terminate_ramrod_data; 1298}; 1299 1300/* 1301 * FCoE event type 1302 */ 1303enum fcoe_event_type 1304{ 1305 FCOE_EVENT_INIT_FUNC /* Slowpath completion on INIT_FUNC ramrod */, 1306 FCOE_EVENT_DESTROY_FUNC /* Slowpath completion on DESTROY_FUNC ramrod */, 1307 FCOE_EVENT_STAT_FUNC /* Slowpath completion on STAT_FUNC ramrod */, 1308 FCOE_EVENT_OFFLOAD_CONN /* Slowpath completion on OFFLOAD_CONN ramrod */, 1309 FCOE_EVENT_TERMINATE_CONN /* Slowpath completion on TERMINATE_CONN ramrod */, 1310 FCOE_EVENT_ERROR /* Error event */, 1311 MAX_FCOE_EVENT_TYPE 1312}; 1313 1314/* 1315 * FCoE init params passed by driver to FW in FCoE init ramrod 1316 */ 1317struct fcoe_init_ramrod_params 1318{ 1319 struct fcoe_init_func_ramrod_data init_ramrod_data; 1320}; 1321 1322/* 1323 * FCoE ramrod Command IDs 1324 */ 1325enum fcoe_ramrod_cmd_id 1326{ 1327 FCOE_RAMROD_CMD_ID_INIT_FUNC /* FCoE function init ramrod */, 1328 FCOE_RAMROD_CMD_ID_DESTROY_FUNC /* FCoE function destroy ramrod */, 1329 FCOE_RAMROD_CMD_ID_STAT_FUNC /* FCoE statistics ramrod */, 1330 FCOE_RAMROD_CMD_ID_OFFLOAD_CONN /* FCoE connection offload ramrod */, 1331 FCOE_RAMROD_CMD_ID_TERMINATE_CONN /* FCoE connection offload ramrod. Command ID known only to FW and VBD */, 1332 MAX_FCOE_RAMROD_CMD_ID 1333}; 1334 1335/* 1336 * FCoE statistics params buffer passed by driver to FW in FCoE statistics ramrod 1337 */ 1338struct fcoe_stat_ramrod_params 1339{ 1340 struct fcoe_stat_ramrod_data stat_ramrod_data; 1341}; 1342 1343struct e4_ystorm_fcoe_conn_ag_ctx 1344{ 1345 u8 byte0 /* cdu_validation */; 1346 u8 byte1 /* state */; 1347 u8 flags0; 1348#define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1349#define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 1350#define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1351#define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 1352#define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1353#define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 1354#define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1355#define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 1356#define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1357#define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 1358 u8 flags1; 1359#define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1360#define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 1361#define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1362#define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 1363#define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1364#define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 1365#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1366#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3 1367#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1368#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4 1369#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1370#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5 1371#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1372#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6 1373#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1374#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7 1375 u8 byte2 /* byte2 */; 1376 u8 byte3 /* byte3 */; 1377 __le16 word0 /* word0 */; 1378 __le32 reg0 /* reg0 */; 1379 __le32 reg1 /* reg1 */; 1380 __le16 word1 /* word1 */; 1381 __le16 word2 /* word2 */; 1382 __le16 word3 /* word3 */; 1383 __le16 word4 /* word4 */; 1384 __le32 reg2 /* reg2 */; 1385 __le32 reg3 /* reg3 */; 1386}; 1387 1388struct e5_ystorm_fcoe_conn_ag_ctx 1389{ 1390 u8 byte0 /* cdu_validation */; 1391 u8 byte1 /* state_and_core_id */; 1392 u8 flags0; 1393#define E5_YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1394#define E5_YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 1395#define E5_YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1396#define E5_YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 1397#define E5_YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1398#define E5_YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 1399#define E5_YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1400#define E5_YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 1401#define E5_YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1402#define E5_YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 1403 u8 flags1; 1404#define E5_YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1405#define E5_YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 1406#define E5_YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1407#define E5_YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 1408#define E5_YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1409#define E5_YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 1410#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1411#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3 1412#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1413#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4 1414#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1415#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5 1416#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1417#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6 1418#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1419#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7 1420 u8 byte2 /* byte2 */; 1421 u8 byte3 /* byte3 */; 1422 __le16 word0 /* word0 */; 1423 __le32 reg0 /* reg0 */; 1424 __le32 reg1 /* reg1 */; 1425 __le16 word1 /* word1 */; 1426 __le16 word2 /* word2 */; 1427 __le16 word3 /* word3 */; 1428 __le16 word4 /* word4 */; 1429 __le32 reg2 /* reg2 */; 1430 __le32 reg3 /* reg3 */; 1431}; 1432 1433#endif /* __ECORE_HSI_FCOE__ */ 1434