1/* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29#ifndef __ECORE_HSI_DEBUG_TOOLS__ 30#define __ECORE_HSI_DEBUG_TOOLS__ 31/****************************************/ 32/* Debug Tools HSI constants and macros */ 33/****************************************/ 34 35enum block_addr 36{ 37 GRCBASE_GRC = 0x50000, 38 GRCBASE_MISCS = 0x9000, 39 GRCBASE_MISC = 0x8000, 40 GRCBASE_DBU = 0xa000, 41 GRCBASE_PGLUE_B = 0x2a8000, 42 GRCBASE_CNIG = 0x218000, 43 GRCBASE_CPMU = 0x30000, 44 GRCBASE_NCSI = 0x40000, 45 GRCBASE_OPTE = 0x53000, 46 GRCBASE_BMB = 0x540000, 47 GRCBASE_PCIE = 0x54000, 48 GRCBASE_MCP = 0xe00000, 49 GRCBASE_MCP2 = 0x52000, 50 GRCBASE_PSWHST = 0x2a0000, 51 GRCBASE_PSWHST2 = 0x29e000, 52 GRCBASE_PSWRD = 0x29c000, 53 GRCBASE_PSWRD2 = 0x29d000, 54 GRCBASE_PSWWR = 0x29a000, 55 GRCBASE_PSWWR2 = 0x29b000, 56 GRCBASE_PSWRQ = 0x280000, 57 GRCBASE_PSWRQ2 = 0x240000, 58 GRCBASE_PGLCS = 0x0, 59 GRCBASE_DMAE = 0xc000, 60 GRCBASE_PTU = 0x560000, 61 GRCBASE_TCM = 0x1180000, 62 GRCBASE_MCM = 0x1200000, 63 GRCBASE_UCM = 0x1280000, 64 GRCBASE_XCM = 0x1000000, 65 GRCBASE_YCM = 0x1080000, 66 GRCBASE_PCM = 0x1100000, 67 GRCBASE_QM = 0x2f0000, 68 GRCBASE_TM = 0x2c0000, 69 GRCBASE_DORQ = 0x100000, 70 GRCBASE_BRB = 0x340000, 71 GRCBASE_SRC = 0x238000, 72 GRCBASE_PRS = 0x1f0000, 73 GRCBASE_TSDM = 0xfb0000, 74 GRCBASE_MSDM = 0xfc0000, 75 GRCBASE_USDM = 0xfd0000, 76 GRCBASE_XSDM = 0xf80000, 77 GRCBASE_YSDM = 0xf90000, 78 GRCBASE_PSDM = 0xfa0000, 79 GRCBASE_TSEM = 0x1700000, 80 GRCBASE_MSEM = 0x1800000, 81 GRCBASE_USEM = 0x1900000, 82 GRCBASE_XSEM = 0x1400000, 83 GRCBASE_YSEM = 0x1500000, 84 GRCBASE_PSEM = 0x1600000, 85 GRCBASE_RSS = 0x238800, 86 GRCBASE_TMLD = 0x4d0000, 87 GRCBASE_MULD = 0x4e0000, 88 GRCBASE_YULD = 0x4c8000, 89 GRCBASE_XYLD = 0x4c0000, 90 GRCBASE_PTLD = 0x5a0000, 91 GRCBASE_YPLD = 0x5c0000, 92 GRCBASE_PRM = 0x230000, 93 GRCBASE_PBF_PB1 = 0xda0000, 94 GRCBASE_PBF_PB2 = 0xda4000, 95 GRCBASE_RPB = 0x23c000, 96 GRCBASE_BTB = 0xdb0000, 97 GRCBASE_PBF = 0xd80000, 98 GRCBASE_RDIF = 0x300000, 99 GRCBASE_TDIF = 0x310000, 100 GRCBASE_CDU = 0x580000, 101 GRCBASE_CCFC = 0x2e0000, 102 GRCBASE_TCFC = 0x2d0000, 103 GRCBASE_IGU = 0x180000, 104 GRCBASE_CAU = 0x1c0000, 105 GRCBASE_RGFS = 0xf00000, 106 GRCBASE_RGSRC = 0x320000, 107 GRCBASE_TGFS = 0xd00000, 108 GRCBASE_TGSRC = 0x322000, 109 GRCBASE_UMAC = 0x51000, 110 GRCBASE_XMAC = 0x210000, 111 GRCBASE_DBG = 0x10000, 112 GRCBASE_NIG = 0x500000, 113 GRCBASE_WOL = 0x600000, 114 GRCBASE_BMBN = 0x610000, 115 GRCBASE_IPC = 0x20000, 116 GRCBASE_NWM = 0x800000, 117 GRCBASE_NWS = 0x700000, 118 GRCBASE_MS = 0x6a0000, 119 GRCBASE_PHY_PCIE = 0x620000, 120 GRCBASE_LED = 0x6b8000, 121 GRCBASE_AVS_WRAP = 0x6b0000, 122 GRCBASE_PXPREQBUS = 0x56000, 123 GRCBASE_MISC_AEU = 0x8000, 124 GRCBASE_BAR0_MAP = 0x1c00000, 125 MAX_BLOCK_ADDR 126}; 127 128enum block_id 129{ 130 BLOCK_GRC, 131 BLOCK_MISCS, 132 BLOCK_MISC, 133 BLOCK_DBU, 134 BLOCK_PGLUE_B, 135 BLOCK_CNIG, 136 BLOCK_CPMU, 137 BLOCK_NCSI, 138 BLOCK_OPTE, 139 BLOCK_BMB, 140 BLOCK_PCIE, 141 BLOCK_MCP, 142 BLOCK_MCP2, 143 BLOCK_PSWHST, 144 BLOCK_PSWHST2, 145 BLOCK_PSWRD, 146 BLOCK_PSWRD2, 147 BLOCK_PSWWR, 148 BLOCK_PSWWR2, 149 BLOCK_PSWRQ, 150 BLOCK_PSWRQ2, 151 BLOCK_PGLCS, 152 BLOCK_DMAE, 153 BLOCK_PTU, 154 BLOCK_TCM, 155 BLOCK_MCM, 156 BLOCK_UCM, 157 BLOCK_XCM, 158 BLOCK_YCM, 159 BLOCK_PCM, 160 BLOCK_QM, 161 BLOCK_TM, 162 BLOCK_DORQ, 163 BLOCK_BRB, 164 BLOCK_SRC, 165 BLOCK_PRS, 166 BLOCK_TSDM, 167 BLOCK_MSDM, 168 BLOCK_USDM, 169 BLOCK_XSDM, 170 BLOCK_YSDM, 171 BLOCK_PSDM, 172 BLOCK_TSEM, 173 BLOCK_MSEM, 174 BLOCK_USEM, 175 BLOCK_XSEM, 176 BLOCK_YSEM, 177 BLOCK_PSEM, 178 BLOCK_RSS, 179 BLOCK_TMLD, 180 BLOCK_MULD, 181 BLOCK_YULD, 182 BLOCK_XYLD, 183 BLOCK_PTLD, 184 BLOCK_YPLD, 185 BLOCK_PRM, 186 BLOCK_PBF_PB1, 187 BLOCK_PBF_PB2, 188 BLOCK_RPB, 189 BLOCK_BTB, 190 BLOCK_PBF, 191 BLOCK_RDIF, 192 BLOCK_TDIF, 193 BLOCK_CDU, 194 BLOCK_CCFC, 195 BLOCK_TCFC, 196 BLOCK_IGU, 197 BLOCK_CAU, 198 BLOCK_RGFS, 199 BLOCK_RGSRC, 200 BLOCK_TGFS, 201 BLOCK_TGSRC, 202 BLOCK_UMAC, 203 BLOCK_XMAC, 204 BLOCK_DBG, 205 BLOCK_NIG, 206 BLOCK_WOL, 207 BLOCK_BMBN, 208 BLOCK_IPC, 209 BLOCK_NWM, 210 BLOCK_NWS, 211 BLOCK_MS, 212 BLOCK_PHY_PCIE, 213 BLOCK_LED, 214 BLOCK_AVS_WRAP, 215 BLOCK_PXPREQBUS, 216 BLOCK_MISC_AEU, 217 BLOCK_BAR0_MAP, 218 MAX_BLOCK_ID 219}; 220 221/* 222 * binary debug buffer types 223 */ 224enum bin_dbg_buffer_type 225{ 226 BIN_BUF_DBG_MODE_TREE /* init modes tree */, 227 BIN_BUF_DBG_DUMP_REG /* GRC Dump registers */, 228 BIN_BUF_DBG_DUMP_MEM /* GRC Dump memories */, 229 BIN_BUF_DBG_IDLE_CHK_REGS /* Idle Check registers */, 230 BIN_BUF_DBG_IDLE_CHK_IMMS /* Idle Check immediates */, 231 BIN_BUF_DBG_IDLE_CHK_RULES /* Idle Check rules */, 232 BIN_BUF_DBG_IDLE_CHK_PARSING_DATA /* Idle Check parsing data */, 233 BIN_BUF_DBG_ATTN_BLOCKS /* Attention blocks */, 234 BIN_BUF_DBG_ATTN_REGS /* Attention registers */, 235 BIN_BUF_DBG_ATTN_INDEXES /* Attention indexes */, 236 BIN_BUF_DBG_ATTN_NAME_OFFSETS /* Attention name offsets */, 237 BIN_BUF_DBG_BUS_BLOCKS /* Debug Bus blocks */, 238 BIN_BUF_DBG_BUS_LINES /* Debug Bus lines */, 239 BIN_BUF_DBG_BUS_BLOCKS_USER_DATA /* Debug Bus blocks user data */, 240 BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS /* Debug Bus line name offsets */, 241 BIN_BUF_DBG_PARSING_STRINGS /* Debug Tools parsing strings */, 242 MAX_BIN_DBG_BUFFER_TYPE 243}; 244 245/* 246 * Attention bit mapping 247 */ 248struct dbg_attn_bit_mapping 249{ 250 u16 data; 251#define DBG_ATTN_BIT_MAPPING_VAL_MASK 0x7FFF /* The index of an attention in the blocks attentions list (if is_unused_bit_cnt=0), or a number of consecutive unused attention bits (if is_unused_bit_cnt=1) */ 252#define DBG_ATTN_BIT_MAPPING_VAL_SHIFT 0 253#define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK 0x1 /* if set, the val field indicates the number of consecutive unused attention bits */ 254#define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT 15 255}; 256 257/* 258 * Attention block per-type data 259 */ 260struct dbg_attn_block_type_data 261{ 262 u16 names_offset /* Offset of this block attention names in the debug attention name offsets array */; 263 u16 reserved1; 264 u8 num_regs /* Number of attention registers in this block */; 265 u8 reserved2; 266 u16 regs_offset /* Offset of this blocks attention registers in the attention registers array (in dbg_attn_reg units) */; 267}; 268 269/* 270 * Block attentions 271 */ 272struct dbg_attn_block 273{ 274 struct dbg_attn_block_type_data per_type_data[2] /* attention block per-type data. Count must match the number of elements in dbg_attn_type. */; 275}; 276 277/* 278 * Attention register result 279 */ 280struct dbg_attn_reg_result 281{ 282 u32 data; 283#define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF /* STS attention register GRC address (in dwords) */ 284#define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT 0 285#define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK 0xFF /* Number of attention indexes in this register */ 286#define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT 24 287 u16 block_attn_offset /* The offset of this registers attentions within the blocks attentions list (a value in the range 0..number of block attentions-1) */; 288 u16 reserved; 289 u32 sts_val /* Value read from the STS attention register */; 290 u32 mask_val /* Value read from the MASK attention register */; 291}; 292 293/* 294 * Attention block result 295 */ 296struct dbg_attn_block_result 297{ 298 u8 block_id /* Registers block ID */; 299 u8 data; 300#define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK 0x3 /* Value from dbg_attn_type enum */ 301#define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT 0 302#define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK 0x3F /* Number of registers in the block in which at least one attention bit is set */ 303#define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT 2 304 u16 names_offset /* Offset of this registers block attention names in the attention name offsets array */; 305 struct dbg_attn_reg_result reg_results[15] /* result data for each register in the block in which at least one attention bit is set */; 306}; 307 308/* 309 * mode header 310 */ 311struct dbg_mode_hdr 312{ 313 u16 data; 314#define DBG_MODE_HDR_EVAL_MODE_MASK 0x1 /* indicates if a mode expression should be evaluated (0/1) */ 315#define DBG_MODE_HDR_EVAL_MODE_SHIFT 0 316#define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK 0x7FFF /* offset (in bytes) in modes expression buffer. valid only if eval_mode is set. */ 317#define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT 1 318}; 319 320/* 321 * Attention register 322 */ 323struct dbg_attn_reg 324{ 325 struct dbg_mode_hdr mode /* Mode header */; 326 u16 block_attn_offset /* The offset of this registers attentions within the blocks attentions list (a value in the range 0..number of block attentions-1) */; 327 u32 data; 328#define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF /* STS attention register GRC address (in dwords) */ 329#define DBG_ATTN_REG_STS_ADDRESS_SHIFT 0 330#define DBG_ATTN_REG_NUM_REG_ATTN_MASK 0xFF /* Number of attention in this register */ 331#define DBG_ATTN_REG_NUM_REG_ATTN_SHIFT 24 332 u32 sts_clr_address /* STS_CLR attention register GRC address (in dwords) */; 333 u32 mask_address /* MASK attention register GRC address (in dwords) */; 334}; 335 336/* 337 * attention types 338 */ 339enum dbg_attn_type 340{ 341 ATTN_TYPE_INTERRUPT, 342 ATTN_TYPE_PARITY, 343 MAX_DBG_ATTN_TYPE 344}; 345 346/* 347 * Debug Bus block data 348 */ 349struct dbg_bus_block 350{ 351 u8 num_of_lines /* Number of debug lines in this block (excluding signature and latency events). */; 352 u8 has_latency_events /* Indicates if this block has a latency events debug line (0/1). */; 353 u16 lines_offset /* Offset of this blocks lines in the Debug Bus lines array. */; 354}; 355 356/* 357 * Debug Bus block user data 358 */ 359struct dbg_bus_block_user_data 360{ 361 u8 num_of_lines /* Number of debug lines in this block (excluding signature and latency events). */; 362 u8 has_latency_events /* Indicates if this block has a latency events debug line (0/1). */; 363 u16 names_offset /* Offset of this blocks lines in the debug bus line name offsets array. */; 364}; 365 366/* 367 * Block Debug line data 368 */ 369struct dbg_bus_line 370{ 371 u8 data; 372#define DBG_BUS_LINE_NUM_OF_GROUPS_MASK 0xF /* Number of groups in the line (0-3) */ 373#define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT 0 374#define DBG_BUS_LINE_IS_256B_MASK 0x1 /* Indicates if this is a 128b line (0) or a 256b line (1). */ 375#define DBG_BUS_LINE_IS_256B_SHIFT 4 376#define DBG_BUS_LINE_RESERVED_MASK 0x7 377#define DBG_BUS_LINE_RESERVED_SHIFT 5 378 u8 group_sizes /* Four 2-bit values, indicating the size of each group minus 1 (i.e. value=0 means size=1, value=1 means size=2, etc), starting from lsb. The sizes are in dwords (if is_256b=0) or in qwords (if is_256b=1). */; 379}; 380 381/* 382 * condition header for registers dump 383 */ 384struct dbg_dump_cond_hdr 385{ 386 struct dbg_mode_hdr mode /* Mode header */; 387 u8 block_id /* block ID */; 388 u8 data_size /* size in dwords of the data following this header */; 389}; 390 391/* 392 * memory data for registers dump 393 */ 394struct dbg_dump_mem 395{ 396 u32 dword0; 397#define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF /* register address (in dwords) */ 398#define DBG_DUMP_MEM_ADDRESS_SHIFT 0 399#define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF /* memory group ID */ 400#define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24 401 u32 dword1; 402#define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF /* register size (in dwords) */ 403#define DBG_DUMP_MEM_LENGTH_SHIFT 0 404#define DBG_DUMP_MEM_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 405#define DBG_DUMP_MEM_WIDE_BUS_SHIFT 24 406#define DBG_DUMP_MEM_RESERVED_MASK 0x7F 407#define DBG_DUMP_MEM_RESERVED_SHIFT 25 408}; 409 410/* 411 * register data for registers dump 412 */ 413struct dbg_dump_reg 414{ 415 u32 data; 416#define DBG_DUMP_REG_ADDRESS_MASK 0x7FFFFF /* register address (in dwords) */ 417#define DBG_DUMP_REG_ADDRESS_SHIFT 0 418#define DBG_DUMP_REG_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 419#define DBG_DUMP_REG_WIDE_BUS_SHIFT 23 420#define DBG_DUMP_REG_LENGTH_MASK 0xFF /* register size (in dwords) */ 421#define DBG_DUMP_REG_LENGTH_SHIFT 24 422}; 423 424/* 425 * split header for registers dump 426 */ 427struct dbg_dump_split_hdr 428{ 429 u32 hdr; 430#define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF /* size in dwords of the data following this header */ 431#define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0 432#define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF /* split type ID */ 433#define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24 434}; 435 436/* 437 * condition header for idle check 438 */ 439struct dbg_idle_chk_cond_hdr 440{ 441 struct dbg_mode_hdr mode /* Mode header */; 442 u16 data_size /* size in dwords of the data following this header */; 443}; 444 445/* 446 * Idle Check condition register 447 */ 448struct dbg_idle_chk_cond_reg 449{ 450 u32 data; 451#define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0x7FFFFF /* Register GRC address (in dwords) */ 452#define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0 453#define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 454#define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT 23 455#define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF /* value from block_id enum */ 456#define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24 457 u16 num_entries /* number of registers entries to check */; 458 u8 entry_size /* size of registers entry (in dwords) */; 459 u8 start_entry /* index of the first entry to check */; 460}; 461 462/* 463 * Idle Check info register 464 */ 465struct dbg_idle_chk_info_reg 466{ 467 u32 data; 468#define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0x7FFFFF /* Register GRC address (in dwords) */ 469#define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0 470#define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 471#define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT 23 472#define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF /* value from block_id enum */ 473#define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24 474 u16 size /* register size in dwords */; 475 struct dbg_mode_hdr mode /* Mode header */; 476}; 477 478/* 479 * Idle Check register 480 */ 481union dbg_idle_chk_reg 482{ 483 struct dbg_idle_chk_cond_reg cond_reg /* condition register */; 484 struct dbg_idle_chk_info_reg info_reg /* info register */; 485}; 486 487/* 488 * Idle Check result header 489 */ 490struct dbg_idle_chk_result_hdr 491{ 492 u16 rule_id /* Failing rule index */; 493 u16 mem_entry_id /* Failing memory entry index */; 494 u8 num_dumped_cond_regs /* number of dumped condition registers */; 495 u8 num_dumped_info_regs /* number of dumped condition registers */; 496 u8 severity /* from dbg_idle_chk_severity_types enum */; 497 u8 reserved; 498}; 499 500/* 501 * Idle Check result register header 502 */ 503struct dbg_idle_chk_result_reg_hdr 504{ 505 u8 data; 506#define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK 0x1 /* indicates if this register is a memory */ 507#define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0 508#define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK 0x7F /* register index within the failing rule */ 509#define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1 510 u8 start_entry /* index of the first checked entry */; 511 u16 size /* register size in dwords */; 512}; 513 514/* 515 * Idle Check rule 516 */ 517struct dbg_idle_chk_rule 518{ 519 u16 rule_id /* Idle Check rule ID */; 520 u8 severity /* value from dbg_idle_chk_severity_types enum */; 521 u8 cond_id /* Condition ID */; 522 u8 num_cond_regs /* number of condition registers */; 523 u8 num_info_regs /* number of info registers */; 524 u8 num_imms /* number of immediates in the condition */; 525 u8 reserved1; 526 u16 reg_offset /* offset of this rules registers in the idle check register array (in dbg_idle_chk_reg units) */; 527 u16 imm_offset /* offset of this rules immediate values in the immediate values array (in dwords) */; 528}; 529 530/* 531 * Idle Check rule parsing data 532 */ 533struct dbg_idle_chk_rule_parsing_data 534{ 535 u32 data; 536#define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1 /* indicates if this register has a FW message */ 537#define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0 538#define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF /* Offset of this rules strings in the debug strings array (in bytes) */ 539#define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1 540}; 541 542/* 543 * idle check severity types 544 */ 545enum dbg_idle_chk_severity_types 546{ 547 IDLE_CHK_SEVERITY_ERROR /* idle check failure should cause an error */, 548 IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC /* idle check failure should cause an error only if theres no traffic */, 549 IDLE_CHK_SEVERITY_WARNING /* idle check failure should cause a warning */, 550 MAX_DBG_IDLE_CHK_SEVERITY_TYPES 551}; 552 553/* 554 * Debug Bus block data 555 */ 556struct dbg_bus_block_data 557{ 558 u16 data; 559#define DBG_BUS_BLOCK_DATA_ENABLE_MASK_MASK 0xF /* 4-bit value: bit i set -> dword/qword i is enabled. */ 560#define DBG_BUS_BLOCK_DATA_ENABLE_MASK_SHIFT 0 561#define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_MASK 0xF /* Number of dwords/qwords to shift right the debug data (0-3) */ 562#define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_SHIFT 4 563#define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_MASK 0xF /* 4-bit value: bit i set -> dword/qword i is forced valid. */ 564#define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_SHIFT 8 565#define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_MASK 0xF /* 4-bit value: bit i set -> dword/qword i frame bit is forced. */ 566#define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_SHIFT 12 567 u8 line_num /* Debug line number to select */; 568 u8 hw_id /* HW ID associated with the block */; 569}; 570 571/* 572 * Debug Bus Clients 573 */ 574enum dbg_bus_clients 575{ 576 DBG_BUS_CLIENT_RBCN, 577 DBG_BUS_CLIENT_RBCP, 578 DBG_BUS_CLIENT_RBCR, 579 DBG_BUS_CLIENT_RBCT, 580 DBG_BUS_CLIENT_RBCU, 581 DBG_BUS_CLIENT_RBCF, 582 DBG_BUS_CLIENT_RBCX, 583 DBG_BUS_CLIENT_RBCS, 584 DBG_BUS_CLIENT_RBCH, 585 DBG_BUS_CLIENT_RBCZ, 586 DBG_BUS_CLIENT_OTHER_ENGINE, 587 DBG_BUS_CLIENT_TIMESTAMP, 588 DBG_BUS_CLIENT_CPU, 589 DBG_BUS_CLIENT_RBCY, 590 DBG_BUS_CLIENT_RBCQ, 591 DBG_BUS_CLIENT_RBCM, 592 DBG_BUS_CLIENT_RBCB, 593 DBG_BUS_CLIENT_RBCW, 594 DBG_BUS_CLIENT_RBCV, 595 MAX_DBG_BUS_CLIENTS 596}; 597 598/* 599 * Debug Bus constraint operation types 600 */ 601enum dbg_bus_constraint_ops 602{ 603 DBG_BUS_CONSTRAINT_OP_EQ /* equal */, 604 DBG_BUS_CONSTRAINT_OP_NE /* not equal */, 605 DBG_BUS_CONSTRAINT_OP_LT /* less than */, 606 DBG_BUS_CONSTRAINT_OP_LTC /* less than (cyclic) */, 607 DBG_BUS_CONSTRAINT_OP_LE /* less than or equal */, 608 DBG_BUS_CONSTRAINT_OP_LEC /* less than or equal (cyclic) */, 609 DBG_BUS_CONSTRAINT_OP_GT /* greater than */, 610 DBG_BUS_CONSTRAINT_OP_GTC /* greater than (cyclic) */, 611 DBG_BUS_CONSTRAINT_OP_GE /* greater than or equal */, 612 DBG_BUS_CONSTRAINT_OP_GEC /* greater than or equal (cyclic) */, 613 MAX_DBG_BUS_CONSTRAINT_OPS 614}; 615 616/* 617 * Debug Bus trigger state data 618 */ 619struct dbg_bus_trigger_state_data 620{ 621 u8 data; 622#define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_MASK 0xF /* 4-bit value: bit i set -> dword i of the trigger state block (after right shift) is enabled. */ 623#define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_SHIFT 0 624#define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_MASK 0xF /* 4-bit value: bit i set -> dword i is compared by a constraint */ 625#define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_SHIFT 4 626}; 627 628/* 629 * Debug Bus memory address 630 */ 631struct dbg_bus_mem_addr 632{ 633 u32 lo; 634 u32 hi; 635}; 636 637/* 638 * Debug Bus PCI buffer data 639 */ 640struct dbg_bus_pci_buf_data 641{ 642 struct dbg_bus_mem_addr phys_addr /* PCI buffer physical address */; 643 struct dbg_bus_mem_addr virt_addr /* PCI buffer virtual address */; 644 u32 size /* PCI buffer size in bytes */; 645}; 646 647/* 648 * Debug Bus Storm EID range filter params 649 */ 650struct dbg_bus_storm_eid_range_params 651{ 652 u8 min /* Minimal event ID to filter on */; 653 u8 max /* Maximal event ID to filter on */; 654}; 655 656/* 657 * Debug Bus Storm EID mask filter params 658 */ 659struct dbg_bus_storm_eid_mask_params 660{ 661 u8 val /* Event ID value */; 662 u8 mask /* Event ID mask. 1s in the mask = dont care bits. */; 663}; 664 665/* 666 * Debug Bus Storm EID filter params 667 */ 668union dbg_bus_storm_eid_params 669{ 670 struct dbg_bus_storm_eid_range_params range /* EID range filter params */; 671 struct dbg_bus_storm_eid_mask_params mask /* EID mask filter params */; 672}; 673 674/* 675 * Debug Bus Storm data 676 */ 677struct dbg_bus_storm_data 678{ 679 u8 enabled /* indicates if the Storm is enabled for recording */; 680 u8 mode /* Storm debug mode, valid only if the Storm is enabled (use enum dbg_bus_storm_modes) */; 681 u8 hw_id /* HW ID associated with the Storm */; 682 u8 eid_filter_en /* Indicates if EID filtering is performed (0/1) */; 683 u8 eid_range_not_mask /* 1 = EID range filter, 0 = EID mask filter. Valid only if eid_filter_en is set, */; 684 u8 cid_filter_en /* Indicates if CID filtering is performed (0/1) */; 685 union dbg_bus_storm_eid_params eid_filter_params /* EID filter params to filter on. Valid only if eid_filter_en is set. */; 686 u32 cid /* CID to filter on. Valid only if cid_filter_en is set. */; 687}; 688 689/* 690 * Debug Bus data 691 */ 692struct dbg_bus_data 693{ 694 u32 app_version /* The tools version number of the application */; 695 u8 state /* The current debug bus state (use enum dbg_bus_states) */; 696 u8 hw_dwords /* HW dwords per cycle */; 697 u16 hw_id_mask /* The HW IDs of the recorded HW blocks, where bits i*3..i*3+2 contain the HW ID of dword/qword i */; 698 u8 num_enabled_blocks /* Number of blocks enabled for recording */; 699 u8 num_enabled_storms /* Number of Storms enabled for recording */; 700 u8 target /* Output target (use enum dbg_bus_targets) */; 701 u8 one_shot_en /* Indicates if one-shot mode is enabled (0/1) */; 702 u8 grc_input_en /* Indicates if GRC recording is enabled (0/1) */; 703 u8 timestamp_input_en /* Indicates if timestamp recording is enabled (0/1) */; 704 u8 filter_en /* Indicates if the recording filter is enabled (0/1) */; 705 u8 adding_filter /* If true, the next added constraint belong to the filter. Otherwise, it belongs to the last added trigger state. Valid only if either filter or triggers are enabled. */; 706 u8 filter_pre_trigger /* Indicates if the recording filter should be applied before the trigger. Valid only if both filter and trigger are enabled (0/1) */; 707 u8 filter_post_trigger /* Indicates if the recording filter should be applied after the trigger. Valid only if both filter and trigger are enabled (0/1) */; 708 u16 reserved; 709 u8 trigger_en /* Indicates if the recording trigger is enabled (0/1) */; 710 struct dbg_bus_trigger_state_data trigger_states[3] /* trigger states data */; 711 u8 next_trigger_state /* ID of next trigger state to be added */; 712 u8 next_constraint_id /* ID of next filter/trigger constraint to be added */; 713 u8 unify_inputs /* If true, all inputs are associated with HW ID 0. Otherwise, each input is assigned a different HW ID (0/1) */; 714 u8 rcv_from_other_engine /* Indicates if the other engine sends it NW recording to this engine (0/1) */; 715 struct dbg_bus_pci_buf_data pci_buf /* Debug Bus PCI buffer data. Valid only when the target is DBG_BUS_TARGET_ID_PCI. */; 716 struct dbg_bus_block_data blocks[88] /* Debug Bus data for each block */; 717 struct dbg_bus_storm_data storms[6] /* Debug Bus data for each block */; 718}; 719 720/* 721 * Debug bus filter types 722 */ 723enum dbg_bus_filter_types 724{ 725 DBG_BUS_FILTER_TYPE_OFF /* filter always off */, 726 DBG_BUS_FILTER_TYPE_PRE /* filter before trigger only */, 727 DBG_BUS_FILTER_TYPE_POST /* filter after trigger only */, 728 DBG_BUS_FILTER_TYPE_ON /* filter always on */, 729 MAX_DBG_BUS_FILTER_TYPES 730}; 731 732/* 733 * Debug bus frame modes 734 */ 735enum dbg_bus_frame_modes 736{ 737 DBG_BUS_FRAME_MODE_0HW_4ST=0 /* 0 HW dwords, 4 Storm dwords */, 738 DBG_BUS_FRAME_MODE_4HW_0ST=3 /* 4 HW dwords, 0 Storm dwords */, 739 DBG_BUS_FRAME_MODE_8HW_0ST=4 /* 8 HW dwords, 0 Storm dwords */, 740 MAX_DBG_BUS_FRAME_MODES 741}; 742 743/* 744 * Debug bus other engine mode 745 */ 746enum dbg_bus_other_engine_modes 747{ 748 DBG_BUS_OTHER_ENGINE_MODE_NONE, 749 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX, 750 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX, 751 DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX, 752 DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX, 753 MAX_DBG_BUS_OTHER_ENGINE_MODES 754}; 755 756/* 757 * Debug bus post-trigger recording types 758 */ 759enum dbg_bus_post_trigger_types 760{ 761 DBG_BUS_POST_TRIGGER_RECORD /* start recording after trigger */, 762 DBG_BUS_POST_TRIGGER_DROP /* drop data after trigger */, 763 MAX_DBG_BUS_POST_TRIGGER_TYPES 764}; 765 766/* 767 * Debug bus pre-trigger recording types 768 */ 769enum dbg_bus_pre_trigger_types 770{ 771 DBG_BUS_PRE_TRIGGER_START_FROM_ZERO /* start recording from time 0 */, 772 DBG_BUS_PRE_TRIGGER_NUM_CHUNKS /* start recording some chunks before trigger */, 773 DBG_BUS_PRE_TRIGGER_DROP /* drop data before trigger */, 774 MAX_DBG_BUS_PRE_TRIGGER_TYPES 775}; 776 777/* 778 * Debug bus SEMI frame modes 779 */ 780enum dbg_bus_semi_frame_modes 781{ 782 DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST=0 /* 0 slow dwords, 4 fast dwords */, 783 DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST=3 /* 4 slow dwords, 0 fast dwords */, 784 MAX_DBG_BUS_SEMI_FRAME_MODES 785}; 786 787/* 788 * Debug bus states 789 */ 790enum dbg_bus_states 791{ 792 DBG_BUS_STATE_IDLE /* debug bus idle state (not recording) */, 793 DBG_BUS_STATE_READY /* debug bus is ready for configuration and recording */, 794 DBG_BUS_STATE_RECORDING /* debug bus is currently recording */, 795 DBG_BUS_STATE_STOPPED /* debug bus recording has stopped */, 796 MAX_DBG_BUS_STATES 797}; 798 799/* 800 * Debug Bus Storm modes 801 */ 802enum dbg_bus_storm_modes 803{ 804 DBG_BUS_STORM_MODE_PRINTF /* store data (fast debug) */, 805 DBG_BUS_STORM_MODE_PRAM_ADDR /* pram address (fast debug) */, 806 DBG_BUS_STORM_MODE_DRA_RW /* DRA read/write data (fast debug) */, 807 DBG_BUS_STORM_MODE_DRA_W /* DRA write data (fast debug) */, 808 DBG_BUS_STORM_MODE_LD_ST_ADDR /* load/store address (fast debug) */, 809 DBG_BUS_STORM_MODE_DRA_FSM /* DRA state machines (fast debug) */, 810 DBG_BUS_STORM_MODE_RH /* recording handlers (fast debug) */, 811 DBG_BUS_STORM_MODE_FOC /* FOC: FIN + DRA Rd (slow debug) */, 812 DBG_BUS_STORM_MODE_EXT_STORE /* FOC: External Store (slow) */, 813 MAX_DBG_BUS_STORM_MODES 814}; 815 816/* 817 * Debug bus target IDs 818 */ 819enum dbg_bus_targets 820{ 821 DBG_BUS_TARGET_ID_INT_BUF /* records debug bus to DBG block internal buffer */, 822 DBG_BUS_TARGET_ID_NIG /* records debug bus to the NW */, 823 DBG_BUS_TARGET_ID_PCI /* records debug bus to a PCI buffer */, 824 MAX_DBG_BUS_TARGETS 825}; 826 827/* 828 * GRC Dump data 829 */ 830struct dbg_grc_data 831{ 832 u8 params_initialized /* Indicates if the GRC parameters were initialized */; 833 u8 reserved1; 834 u16 reserved2; 835 u32 param_val[48] /* Value of each GRC parameter. Array size must match the enum dbg_grc_params. */; 836}; 837 838/* 839 * Debug GRC params 840 */ 841enum dbg_grc_params 842{ 843 DBG_GRC_PARAM_DUMP_TSTORM /* dump Tstorm memories (0/1) */, 844 DBG_GRC_PARAM_DUMP_MSTORM /* dump Mstorm memories (0/1) */, 845 DBG_GRC_PARAM_DUMP_USTORM /* dump Ustorm memories (0/1) */, 846 DBG_GRC_PARAM_DUMP_XSTORM /* dump Xstorm memories (0/1) */, 847 DBG_GRC_PARAM_DUMP_YSTORM /* dump Ystorm memories (0/1) */, 848 DBG_GRC_PARAM_DUMP_PSTORM /* dump Pstorm memories (0/1) */, 849 DBG_GRC_PARAM_DUMP_REGS /* dump non-memory registers (0/1) */, 850 DBG_GRC_PARAM_DUMP_RAM /* dump Storm internal RAMs (0/1) */, 851 DBG_GRC_PARAM_DUMP_PBUF /* dump Storm passive buffer (0/1) */, 852 DBG_GRC_PARAM_DUMP_IOR /* dump Storm IORs (0/1) */, 853 DBG_GRC_PARAM_DUMP_VFC /* dump VFC memories (0/1) */, 854 DBG_GRC_PARAM_DUMP_CM_CTX /* dump CM contexts (0/1) */, 855 DBG_GRC_PARAM_DUMP_PXP /* dump PXP memories (0/1) */, 856 DBG_GRC_PARAM_DUMP_RSS /* dump RSS memories (0/1) */, 857 DBG_GRC_PARAM_DUMP_CAU /* dump CAU memories (0/1) */, 858 DBG_GRC_PARAM_DUMP_QM /* dump QM memories (0/1) */, 859 DBG_GRC_PARAM_DUMP_MCP /* dump MCP memories (0/1) */, 860 DBG_GRC_PARAM_RESERVED /* reserved */, 861 DBG_GRC_PARAM_DUMP_CFC /* dump CFC memories (0/1) */, 862 DBG_GRC_PARAM_DUMP_IGU /* dump IGU memories (0/1) */, 863 DBG_GRC_PARAM_DUMP_BRB /* dump BRB memories (0/1) */, 864 DBG_GRC_PARAM_DUMP_BTB /* dump BTB memories (0/1) */, 865 DBG_GRC_PARAM_DUMP_BMB /* dump BMB memories (0/1) */, 866 DBG_GRC_PARAM_DUMP_NIG /* dump NIG memories (0/1) */, 867 DBG_GRC_PARAM_DUMP_MULD /* dump MULD memories (0/1) */, 868 DBG_GRC_PARAM_DUMP_PRS /* dump PRS memories (0/1) */, 869 DBG_GRC_PARAM_DUMP_DMAE /* dump PRS memories (0/1) */, 870 DBG_GRC_PARAM_DUMP_TM /* dump TM (timers) memories (0/1) */, 871 DBG_GRC_PARAM_DUMP_SDM /* dump SDM memories (0/1) */, 872 DBG_GRC_PARAM_DUMP_DIF /* dump DIF memories (0/1) */, 873 DBG_GRC_PARAM_DUMP_STATIC /* dump static debug data (0/1) */, 874 DBG_GRC_PARAM_UNSTALL /* un-stall Storms after dump (0/1) */, 875 DBG_GRC_PARAM_NUM_LCIDS /* number of LCIDs (0..320) */, 876 DBG_GRC_PARAM_NUM_LTIDS /* number of LTIDs (0..320) */, 877 DBG_GRC_PARAM_EXCLUDE_ALL /* preset: exclude all memories from dump (1 only) */, 878 DBG_GRC_PARAM_CRASH /* preset: include memories for crash dump (1 only) */, 879 DBG_GRC_PARAM_PARITY_SAFE /* perform dump only if MFW is responding (0/1) */, 880 DBG_GRC_PARAM_DUMP_CM /* dump CM memories (0/1) */, 881 DBG_GRC_PARAM_DUMP_PHY /* dump PHY memories (0/1) */, 882 DBG_GRC_PARAM_NO_MCP /* dont perform MCP commands (0/1) */, 883 DBG_GRC_PARAM_NO_FW_VER /* dont read FW/MFW version (0/1) */, 884 MAX_DBG_GRC_PARAMS 885}; 886 887/* 888 * Debug reset registers 889 */ 890enum dbg_reset_regs 891{ 892 DBG_RESET_REG_MISCS_PL_UA, 893 DBG_RESET_REG_MISCS_PL_HV, 894 DBG_RESET_REG_MISCS_PL_HV_2, 895 DBG_RESET_REG_MISC_PL_UA, 896 DBG_RESET_REG_MISC_PL_HV, 897 DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 898 DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 899 DBG_RESET_REG_MISC_PL_PDA_VAUX, 900 MAX_DBG_RESET_REGS 901}; 902 903/* 904 * Debug status codes 905 */ 906enum dbg_status 907{ 908 DBG_STATUS_OK, 909 DBG_STATUS_APP_VERSION_NOT_SET, 910 DBG_STATUS_UNSUPPORTED_APP_VERSION, 911 DBG_STATUS_DBG_BLOCK_NOT_RESET, 912 DBG_STATUS_INVALID_ARGS, 913 DBG_STATUS_OUTPUT_ALREADY_SET, 914 DBG_STATUS_INVALID_PCI_BUF_SIZE, 915 DBG_STATUS_PCI_BUF_ALLOC_FAILED, 916 DBG_STATUS_PCI_BUF_NOT_ALLOCATED, 917 DBG_STATUS_TOO_MANY_INPUTS, 918 DBG_STATUS_INPUT_OVERLAP, 919 DBG_STATUS_HW_ONLY_RECORDING, 920 DBG_STATUS_STORM_ALREADY_ENABLED, 921 DBG_STATUS_STORM_NOT_ENABLED, 922 DBG_STATUS_BLOCK_ALREADY_ENABLED, 923 DBG_STATUS_BLOCK_NOT_ENABLED, 924 DBG_STATUS_NO_INPUT_ENABLED, 925 DBG_STATUS_NO_FILTER_TRIGGER_64B, 926 DBG_STATUS_FILTER_ALREADY_ENABLED, 927 DBG_STATUS_TRIGGER_ALREADY_ENABLED, 928 DBG_STATUS_TRIGGER_NOT_ENABLED, 929 DBG_STATUS_CANT_ADD_CONSTRAINT, 930 DBG_STATUS_TOO_MANY_TRIGGER_STATES, 931 DBG_STATUS_TOO_MANY_CONSTRAINTS, 932 DBG_STATUS_RECORDING_NOT_STARTED, 933 DBG_STATUS_DATA_DIDNT_TRIGGER, 934 DBG_STATUS_NO_DATA_RECORDED, 935 DBG_STATUS_DUMP_BUF_TOO_SMALL, 936 DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED, 937 DBG_STATUS_UNKNOWN_CHIP, 938 DBG_STATUS_VIRT_MEM_ALLOC_FAILED, 939 DBG_STATUS_BLOCK_IN_RESET, 940 DBG_STATUS_INVALID_TRACE_SIGNATURE, 941 DBG_STATUS_INVALID_NVRAM_BUNDLE, 942 DBG_STATUS_NVRAM_GET_IMAGE_FAILED, 943 DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE, 944 DBG_STATUS_NVRAM_READ_FAILED, 945 DBG_STATUS_IDLE_CHK_PARSE_FAILED, 946 DBG_STATUS_MCP_TRACE_BAD_DATA, 947 DBG_STATUS_MCP_TRACE_NO_META, 948 DBG_STATUS_MCP_COULD_NOT_HALT, 949 DBG_STATUS_MCP_COULD_NOT_RESUME, 950 DBG_STATUS_RESERVED2, 951 DBG_STATUS_SEMI_FIFO_NOT_EMPTY, 952 DBG_STATUS_IGU_FIFO_BAD_DATA, 953 DBG_STATUS_MCP_COULD_NOT_MASK_PRTY, 954 DBG_STATUS_FW_ASSERTS_PARSE_FAILED, 955 DBG_STATUS_REG_FIFO_BAD_DATA, 956 DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA, 957 DBG_STATUS_DBG_ARRAY_NOT_SET, 958 DBG_STATUS_FILTER_BUG, 959 DBG_STATUS_NON_MATCHING_LINES, 960 DBG_STATUS_INVALID_TRIGGER_DWORD_OFFSET, 961 DBG_STATUS_DBG_BUS_IN_USE, 962 MAX_DBG_STATUS 963}; 964 965/* 966 * Debug Storms IDs 967 */ 968enum dbg_storms 969{ 970 DBG_TSTORM_ID, 971 DBG_MSTORM_ID, 972 DBG_USTORM_ID, 973 DBG_XSTORM_ID, 974 DBG_YSTORM_ID, 975 DBG_PSTORM_ID, 976 MAX_DBG_STORMS 977}; 978 979/* 980 * Idle Check data 981 */ 982struct idle_chk_data 983{ 984 u32 buf_size /* Idle check buffer size in dwords */; 985 u8 buf_size_set /* Indicates if the idle check buffer size was set (0/1) */; 986 u8 reserved1; 987 u16 reserved2; 988}; 989 990/* 991 * Debug Tools data (per HW function) 992 */ 993struct dbg_tools_data 994{ 995 struct dbg_grc_data grc /* GRC Dump data */; 996 struct dbg_bus_data bus /* Debug Bus data */; 997 struct idle_chk_data idle_chk /* Idle Check data */; 998 u8 mode_enable[40] /* Indicates if a mode is enabled (0/1) */; 999 u8 block_in_reset[88] /* Indicates if a block is in reset state (0/1) */; 1000 u8 chip_id /* Chip ID (from enum chip_ids) */; 1001 u8 platform_id /* Platform ID */; 1002 u8 initialized /* Indicates if the data was initialized */; 1003 u8 use_dmae /* Indicates if DMAE should be used */; 1004 u32 num_regs_read /* Numbers of registers that were read since last log */; 1005}; 1006 1007#endif /* __ECORE_HSI_DEBUG_TOOLS__ */ 1008