1/* SPDX-License-Identifier: BSD-3-Clause */ 2/* Copyright(c) 2007-2022 Intel Corporation */ 3#ifndef ADF_200XX_HW_DATA_H_ 4#define ADF_200XX_HW_DATA_H_ 5 6/* PCIe configuration space */ 7#define ADF_200XX_PMISC_BAR 0 8#define ADF_200XX_ETR_BAR 1 9#define ADF_200XX_RX_RINGS_OFFSET 8 10#define ADF_200XX_TX_RINGS_MASK 0xFF 11#define ADF_200XX_MAX_ACCELERATORS 3 12#define ADF_200XX_MAX_ACCELENGINES 6 13#define ADF_200XX_ACCELERATORS_REG_OFFSET 16 14#define ADF_200XX_ACCELERATORS_MASK 0x7 15#define ADF_200XX_ACCELENGINES_MASK 0x3F 16#define ADF_200XX_ETR_MAX_BANKS 16 17#define ADF_200XX_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28) 18#define ADF_200XX_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30) 19#define ADF_200XX_SMIA0_MASK 0xFFFF 20#define ADF_200XX_SMIA1_MASK 0x1 21#define ADF_200XX_SOFTSTRAP_CSR_OFFSET 0x2EC 22#define ADF_200XX_POWERGATE_PKE BIT(24) 23#define ADF_200XX_POWERGATE_CY BIT(23) 24 25#define ADF_200XX_PFIEERRUNCSTSR 0x280 26 27/* Error detection and correction */ 28#define ADF_200XX_AE_CTX_ENABLES(i) ((i)*0x1000 + 0x20818) 29#define ADF_200XX_AE_MISC_CONTROL(i) ((i)*0x1000 + 0x20960) 30#define ADF_200XX_ENABLE_AE_ECC_ERR BIT(28) 31#define ADF_200XX_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12)) 32#define ADF_200XX_UERRSSMSH(i) (i * 0x4000 + 0x18) 33#define ADF_200XX_CERRSSMSH(i) (i * 0x4000 + 0x10) 34#define ADF_200XX_ERRSSMSH_EN BIT(3) 35#define ADF_200XX_ERRSOU3 (0x3A000 + 0x0C) 36#define ADF_200XX_ERRSOU5 (0x3A000 + 0xD8) 37 38/* BIT(2) enables the logging of push/pull data errors. */ 39#define ADF_200XX_PPERR_EN (BIT(2)) 40 41/* Mask for VF2PF interrupts */ 42#define ADF_200XX_VF2PF1_16 (0xFFFF << 9) 43#define ADF_200XX_ERRSOU3_VF2PF(errsou3) (((errsou3)&0x01FFFE00) >> 9) 44#define ADF_200XX_ERRMSK3_VF2PF(vf_mask) (((vf_mask)&0xFFFF) << 9) 45 46/* Masks for correctable error interrupts. */ 47#define ADF_200XX_ERRMSK0_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0)) 48#define ADF_200XX_ERRMSK1_CERR (BIT(8) | BIT(0)) 49#define ADF_200XX_ERRMSK5_CERR (0) 50 51/* Masks for uncorrectable error interrupts. */ 52#define ADF_200XX_ERRMSK0_UERR (BIT(25) | BIT(17) | BIT(9) | BIT(1)) 53#define ADF_200XX_ERRMSK1_UERR (BIT(9) | BIT(1)) 54#define ADF_200XX_ERRMSK3_UERR \ 55 (BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(0)) 56#define ADF_200XX_ERRMSK5_UERR (BIT(16)) 57 58/* RI CPP control */ 59#define ADF_200XX_RICPPINTCTL (0x3A000 + 0x110) 60/* 61 * BIT(2) enables error detection and reporting on the RI Parity Error. 62 * BIT(1) enables error detection and reporting on the RI CPP Pull interface. 63 * BIT(0) enables error detection and reporting on the RI CPP Push interface. 64 */ 65#define ADF_200XX_RICPP_EN (BIT(2) | BIT(1) | BIT(0)) 66 67/* TI CPP control */ 68#define ADF_200XX_TICPPINTCTL (0x3A400 + 0x138) 69/* 70 * BIT(3) enables error detection and reporting on the ETR Parity Error. 71 * BIT(2) enables error detection and reporting on the TI Parity Error. 72 * BIT(1) enables error detection and reporting on the TI CPP Pull interface. 73 * BIT(0) enables error detection and reporting on the TI CPP Push interface. 74 */ 75#define ADF_200XX_TICPP_EN (BIT(3) | BIT(2) | BIT(1) | BIT(0)) 76 77/* CFC Uncorrectable Errors */ 78#define ADF_200XX_CPP_CFC_ERR_CTRL (0x30000 + 0xC00) 79/* 80 * BIT(1) enables interrupt. 81 * BIT(0) enables detecting and logging of push/pull data errors. 82 */ 83#define ADF_200XX_CPP_CFC_UE (BIT(1) | BIT(0)) 84 85#define ADF_200XX_SLICEPWRDOWN(i) ((i)*0x4000 + 0x2C) 86/* Enabling PKE4-PKE0. */ 87#define ADF_200XX_MMP_PWR_UP_MSK \ 88 (BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16)) 89 90/* CPM Uncorrectable Errors */ 91#define ADF_200XX_INTMASKSSM(i) ((i)*0x4000 + 0x0) 92/* Disabling interrupts for correctable errors. */ 93#define ADF_200XX_INTMASKSSM_UERR \ 94 (BIT(11) | BIT(9) | BIT(7) | BIT(5) | BIT(3) | BIT(1)) 95 96/* MMP */ 97/* BIT(3) enables correction. */ 98#define ADF_200XX_CERRSSMMMP_EN (BIT(3)) 99 100/* BIT(3) enables logging. */ 101#define ADF_200XX_UERRSSMMMP_EN (BIT(3)) 102 103#define ADF_200XX_PF2VF_OFFSET(i) (0x3A000 + 0x280 + ((i)*0x04)) 104#define ADF_200XX_VINTMSK_OFFSET(i) (0x3A000 + 0x200 + ((i)*0x04)) 105 106/* Arbiter configuration */ 107#define ADF_200XX_ARB_OFFSET 0x30000 108#define ADF_200XX_ARB_WRK_2_SER_MAP_OFFSET 0x180 109#define ADF_200XX_ARB_WQCFG_OFFSET 0x100 110 111/* Admin Interface Reg Offset */ 112#define ADF_200XX_ADMINMSGUR_OFFSET (0x3A000 + 0x574) 113#define ADF_200XX_ADMINMSGLR_OFFSET (0x3A000 + 0x578) 114#define ADF_200XX_MAILBOX_BASE_OFFSET 0x20970 115 116/* Firmware Binary */ 117#define ADF_200XX_FW "qat_200xx_fw" 118#define ADF_200XX_MMP "qat_200xx_mmp_fw" 119 120void adf_init_hw_data_200xx(struct adf_hw_device_data *hw_data); 121void adf_clean_hw_data_200xx(struct adf_hw_device_data *hw_data); 122 123#define ADF_200XX_AE_FREQ (685 * 1000000) 124#define ADF_200XX_MIN_AE_FREQ (333 * 1000000) 125#define ADF_200XX_MAX_AE_FREQ (685 * 1000000) 126 127#endif 128