1/* SPDX-License-Identifier: BSD-3-Clause */ 2/* Copyright(c) 2007-2022 Intel Corporation */ 3/** 4 ***************************************************************************** 5 * @file icp_qat_hw.h 6 * @defgroup icp_qat_hw_defs ICP QAT HW definitions 7 * @ingroup icp_qat_hw 8 * @description 9 * This file documents definitions for the QAT HW 10 * 11 *****************************************************************************/ 12 13#ifndef _ICP_QAT_HW_H_ 14#define _ICP_QAT_HW_H_ 15 16/* 17****************************************************************************** 18* Include public/global header files 19****************************************************************************** 20*/ 21 22/* ========================================================================= */ 23/* AccelerationEngine */ 24/* ========================================================================= */ 25 26typedef enum { 27 ICP_QAT_HW_AE_0 = 0, /*!< ID of AE0 */ 28 ICP_QAT_HW_AE_1 = 1, /*!< ID of AE1 */ 29 ICP_QAT_HW_AE_2 = 2, /*!< ID of AE2 */ 30 ICP_QAT_HW_AE_3 = 3, /*!< ID of AE3 */ 31 ICP_QAT_HW_AE_4 = 4, /*!< ID of AE4 */ 32 ICP_QAT_HW_AE_5 = 5, /*!< ID of AE5 */ 33 ICP_QAT_HW_AE_6 = 6, /*!< ID of AE6 */ 34 ICP_QAT_HW_AE_7 = 7, /*!< ID of AE7 */ 35 ICP_QAT_HW_AE_8 = 8, /*!< ID of AE8 */ 36 ICP_QAT_HW_AE_9 = 9, /*!< ID of AE9 */ 37 ICP_QAT_HW_AE_10 = 10, /*!< ID of AE10 */ 38 ICP_QAT_HW_AE_11 = 11, /*!< ID of AE11 */ 39 ICP_QAT_HW_AE_12 = 12, /*!< ID of AE12 */ 40 ICP_QAT_HW_AE_13 = 13, /*!< ID of AE13 */ 41 ICP_QAT_HW_AE_14 = 14, /*!< ID of AE14 */ 42 ICP_QAT_HW_AE_15 = 15, /*!< ID of AE15 */ 43 ICP_QAT_HW_AE_DELIMITER = 16 /**< Delimiter type */ 44} icp_qat_hw_ae_id_t; 45 46/* ========================================================================= */ 47/* QAT */ 48/* ========================================================================= */ 49 50typedef enum { 51 ICP_QAT_HW_QAT_0 = 0, /*!< ID of QAT0 */ 52 ICP_QAT_HW_QAT_1 = 1, /*!< ID of QAT1 */ 53 ICP_QAT_HW_QAT_2 = 2, /*!< ID of QAT2 */ 54 ICP_QAT_HW_QAT_3 = 3, /*!< ID of QAT3 */ 55 ICP_QAT_HW_QAT_4 = 4, /*!< ID of QAT4 */ 56 ICP_QAT_HW_QAT_5 = 5, /*!< ID of QAT5 */ 57 ICP_QAT_HW_QAT_DELIMITER = 6 /**< Delimiter type */ 58} icp_qat_hw_qat_id_t; 59 60/* ========================================================================= */ 61/* AUTH SLICE */ 62/* ========================================================================= */ 63 64/** 65 ***************************************************************************** 66 * @ingroup icp_qat_hw_defs 67 * Supported Authentication Algorithm types 68 * @description 69 * Enumeration which is used to define the authenticate algorithms 70 * 71 *****************************************************************************/ 72 73typedef enum { 74 ICP_QAT_HW_AUTH_ALGO_NULL = 0, /*!< Null hashing */ 75 ICP_QAT_HW_AUTH_ALGO_SHA1 = 1, /*!< SHA1 hashing */ 76 ICP_QAT_HW_AUTH_ALGO_MD5 = 2, /*!< MD5 hashing */ 77 ICP_QAT_HW_AUTH_ALGO_SHA224 = 3, /*!< SHA-224 hashing */ 78 ICP_QAT_HW_AUTH_ALGO_SHA256 = 4, /*!< SHA-256 hashing */ 79 ICP_QAT_HW_AUTH_ALGO_SHA384 = 5, /*!< SHA-384 hashing */ 80 ICP_QAT_HW_AUTH_ALGO_SHA512 = 6, /*!< SHA-512 hashing */ 81 ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC = 7, /*!< AES-XCBC-MAC hashing */ 82 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC = 8, /*!< AES-CBC-MAC hashing */ 83 ICP_QAT_HW_AUTH_ALGO_AES_F9 = 9, /*!< AES F9 hashing */ 84 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 = 10, /*!< Galois 128 bit hashing */ 85 ICP_QAT_HW_AUTH_ALGO_GALOIS_64 = 11, /*!< Galois 64 hashing */ 86 ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 = 12, /*!< Kasumi F9 hashing */ 87 ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 = 13, /*!< UIA2/SNOW_3G F9 hashing */ 88 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 = 89 14, /*!< 128_EIA3/ZUC_3G hashing */ 90 ICP_QAT_HW_AUTH_ALGO_SM3 = 15, /*!< SM3 hashing */ 91 ICP_QAT_HW_AUTH_ALGO_SHA3_224 = 16, /*!< SHA3-224 hashing */ 92 ICP_QAT_HW_AUTH_ALGO_SHA3_256 = 17, /*!< SHA3-256 hashing */ 93 ICP_QAT_HW_AUTH_ALGO_SHA3_384 = 18, /*!< SHA3-384 hashing */ 94 ICP_QAT_HW_AUTH_ALGO_SHA3_512 = 19, /*!< SHA3-512 hashing */ 95 ICP_QAT_HW_AUTH_RESERVED_4 = 20, /*!< Reserved */ 96 ICP_QAT_HW_AUTH_RESERVED_5 = 21, /*!< Reserved */ 97 ICP_QAT_HW_AUTH_ALGO_POLY = 22, /*!< POLY hashing */ 98 ICP_QAT_HW_AUTH_ALGO_DELIMITER = 23 /**< Delimiter type */ 99} icp_qat_hw_auth_algo_t; 100 101/** 102 ***************************************************************************** 103 * @ingroup icp_qat_hw_defs 104 * Definition of the supported Authentication modes 105 * @description 106 * Enumeration which is used to define the authentication slice modes. 107 * The concept of modes is very specific to the QAT implementation. Its 108 * main use is differentiate how the algorithms are used i.e. mode0 SHA1 109 * will configure the QAT Auth Slice to do plain SHA1 hashing while mode1 110 * configures it to do SHA1 HMAC with precomputes and mode2 sets up the 111 * slice to do SHA1 HMAC with no precomputes (uses key directly) 112 * 113 * @Note 114 * Only some algorithms are valid in some of the modes. If you dont know 115 * what you are doing then refer back to the HW documentation 116 * 117 *****************************************************************************/ 118 119typedef enum { 120 ICP_QAT_HW_AUTH_MODE0 = 0, /*!< QAT Auth Mode0 configuration */ 121 ICP_QAT_HW_AUTH_MODE1 = 1, /*!< QAT Auth Mode1 configuration */ 122 ICP_QAT_HW_AUTH_MODE2 = 2, /*!< QAT AuthMode2 configuration */ 123 ICP_QAT_HW_AUTH_MODE_DELIMITER = 3 /**< Delimiter type */ 124} icp_qat_hw_auth_mode_t; 125 126/** 127 ***************************************************************************** 128 * @ingroup icp_qat_hw_defs 129 * Auth configuration structure 130 * 131 * @description 132 * Definition of the format of the authentication slice configuration 133 * 134 *****************************************************************************/ 135typedef struct icp_qat_hw_auth_config_s { 136 uint32_t config; 137 /**< Configuration used for setting up the slice */ 138 139 uint32_t reserved; 140 /**< Reserved */ 141} icp_qat_hw_auth_config_t; 142 143/* Private defines */ 144 145/* Note: Bit positions have been defined for little endian ordering */ 146/* 147* AUTH CONFIG WORD BITMAP 148* + ===== + ------ + ------ + ------- + ------ + ------ + ----- + ----- + ------ + ------ + ---- + ----- + ----- + ----- + 149* | Bit | 63:56 | 55:52 | 51:48 | 47:32 | 31:24 | 23:22 | 21:18 | 17 | 16 | 15 | 14:8 | 7:4 | 3:0 | 150* + ===== + ------ + ------ + ------- + ------ + ------ + ----- + ----- + ------ + ------ + ---- + ----- + ------+ ----- + 151* | Usage | Prog | Resvd | Prog | Resvd | Resvd | Algo | Rsvrd | SHA3 | SHA3 |Rsvrd | Cmp | Mode | Algo | 152* | |padding | Bits=0 | padding | Bits=0 | Bits=0 | SHA3 | |Padding |Padding | | | | | 153* | | SHA3 | | SHA3 | | | | |Override|Disable | | | | | 154* | |(prefix)| |(postfix)| | | | | | | | | | | 155* + ===== + ------ + ------ + ------- + ------ + ------ + ----- + ----- + ------ + ------ + ---- + ----- + ----- + ------+ 156*/ 157 158/**< Flag mask & bit position */ 159 160#define QAT_AUTH_MODE_BITPOS 4 161/**< @ingroup icp_qat_hw_defs 162 * Starting bit position indicating the Auth mode */ 163 164#define QAT_AUTH_MODE_MASK 0xF 165/**< @ingroup icp_qat_hw_defs 166 * Four bit mask used for determing the Auth mode */ 167 168#define QAT_AUTH_ALGO_BITPOS 0 169/**< @ingroup icp_qat_hw_defs 170 * Starting bit position indicating the Auth Algo */ 171 172#define QAT_AUTH_ALGO_MASK 0xF 173/**< @ingroup icp_qat_hw_defs 174 * Four bit mask used for determining the Auth algo */ 175 176#define QAT_AUTH_CMP_BITPOS 8 177/**< @ingroup icp_qat_hw_defs 178 * Starting bit position indicating the Auth Compare */ 179 180#define QAT_AUTH_CMP_MASK 0x7F 181/**< @ingroup icp_qat_hw_defs 182 * Seven bit mask used to determine the Auth Compare */ 183 184#define QAT_AUTH_SHA3_PADDING_DISABLE_BITPOS 16 185/**< @ingroup icp_qat_hw_defs 186 * Starting bit position indicating the Auth h/w 187 * padding disable for SHA3. 188 * Flag set to 0 => h/w is required to pad (default) 189 * Flag set to 1 => No padding in h/w 190 */ 191 192#define QAT_AUTH_SHA3_PADDING_DISABLE_MASK 0x1 193/**< @ingroup icp_qat_hw_defs 194 * Single bit mask used to determine the Auth h/w 195 * padding disable for SHA3. 196 */ 197 198#define QAT_AUTH_SHA3_PADDING_OVERRIDE_BITPOS 17 199/**< @ingroup icp_qat_hw_defs 200 * Starting bit position indicating the Auth h/w 201 * padding override for SHA3. 202 * Flag set to 0 => default padding behaviour 203 * implemented in SHA3-256 slice will take effect 204 * (default hardware setting upon h/w reset) 205 * Flag set to 1 => SHA3-core will not use the padding 206 * sequence built into the SHA3 core. Instead, the 207 * padding sequence specified in bits 48-51 and 56-63 208 * of the 64-bit auth config word will apply 209 * (corresponds with EAS bits 32-43). 210 */ 211 212#define QAT_AUTH_SHA3_PADDING_OVERRIDE_MASK 0x1 213/**< @ingroup icp_qat_hw_defs 214 * Single bit mask used to determine the Auth h/w 215 * padding override for SHA3. 216 */ 217 218#define QAT_AUTH_ALGO_SHA3_BITPOS 22 219/**< @ingroup icp_qat_hw_defs 220 * Starting bit position for indicating the 221 * SHA3 Auth Algo 222 */ 223 224#define QAT_AUTH_ALGO_SHA3_MASK 0x3 225/**< @ingroup icp_qat_hw_defs 226 * Two bit mask used for determining the 227 * SHA3 Auth algo 228 */ 229 230/**< Flag mask & bit position */ 231 232#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_BITPOS 16 233/**< @ingroup icp_qat_hw_defs 234 * Starting bit position indicating the SHA3 235 * flexible programmable padding postfix. 236 * Note that these bits are set using macro 237 * ICP_QAT_HW_AUTH_CONFIG_BUILD_UPPER and are 238 * defined relative to the 32-bit value that 239 * this macro returns. In effect, therefore, this 240 * defines starting bit position 48 within the 241 * 64-bit auth config word. 242 */ 243 244#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_MASK 0xF 245/**< @ingroup icp_qat_hw_defs 246 * Four-bit mask used to determine the SHA3 247 * flexible programmable padding postfix 248 */ 249 250#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_BITPOS 24 251/**< @ingroup icp_qat_hw_defs 252 * Starting bit position indicating the SHA3 253 * flexible programmable padding prefix 254 * Note that these bits are set using macro 255 * ICP_QAT_HW_AUTH_CONFIG_BUILD_UPPER and are 256 * defined relative to the 32-bit value that 257 * this macro returns. In effect, therefore, this 258 * defines starting bit position 56 within the 259 * 64-bit auth config word. 260 */ 261 262#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_MASK 0xFF 263/**< @ingroup icp_qat_hw_defs 264 * Eight-bit mask used to determine the SHA3 265 * flexible programmable padding prefix 266 */ 267 268/**< Flag usage - see additional notes @description for 269 * ICP_QAT_HW_AUTH_CONFIG_BUILD and 270 * ICP_QAT_HW_AUTH_CONFIG_BUILD_UPPER macros. 271 */ 272 273#define QAT_AUTH_SHA3_HW_PADDING_ENABLE 0 274/**< @ingroup icp_qat_hw_defs 275 * This setting enables h/w padding for SHA3. 276 */ 277 278#define QAT_AUTH_SHA3_HW_PADDING_DISABLE 1 279/**< @ingroup icp_qat_hw_defs 280 * This setting disables h/w padding for SHA3. 281 */ 282 283#define QAT_AUTH_SHA3_PADDING_DISABLE_USE_DEFAULT 0 284/**< @ingroup icp_qat_hw_defs 285 * Default value for the Auth h/w padding disable. 286 * If set to 0 for SHA3-256, h/w padding is enabled. 287 * Padding_Disable is undefined for all non-SHA3-256 288 * algos and is consequently set to the default of 0. 289 */ 290 291#define QAT_AUTH_SHA3_PADDING_OVERRIDE_USE_DEFAULT 0 292/**< @ingroup icp_qat_hw_defs 293 * Value for the Auth h/w padding override for SHA3. 294 * Flag set to 0 => default padding behaviour 295 * implemented in SHA3-256 slice will take effect 296 * (default hardware setting upon h/w reset) 297 * For this setting of the override flag, all the 298 * bits of the padding sequence specified 299 * in bits 48-51 and 56-63 of the 64-bit 300 * auth config word are set to 0 (reserved). 301 */ 302 303#define QAT_AUTH_SHA3_PADDING_OVERRIDE_PROGRAMMABLE 1 304/**< @ingroup icp_qat_hw_defs 305 * Value for the Auth h/w padding override for SHA3. 306 * Flag set to 1 => SHA3-core will not use the padding 307 * sequence built into the SHA3 core. Instead, the 308 * padding sequence specified in bits 48-51 and 56-63 309 * of the 64-bit auth config word will apply 310 * (corresponds with EAS bits 32-43). 311 */ 312 313#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_RESERVED 0 314/**< @ingroup icp_qat_hw_defs 315 * All the bits of the padding sequence specified in 316 * bits 48-51 of the 64-bit auth config word are set 317 * to 0 (reserved) if the padding override bit is set 318 * to 0, indicating default padding. 319 */ 320 321#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_RESERVED 0 322/**< @ingroup icp_qat_hw_defs 323 * All the bits of the padding sequence specified in 324 * bits 56-63 of the 64-bit auth config word are set 325 * to 0 (reserved) if the padding override bit is set 326 * to 0, indicating default padding. 327 */ 328 329/** 330 *************************************************************************************** 331 * @ingroup icp_qat_hw_defs 332 * 333 * @description 334 * The derived configuration word for the auth slice is based on the inputs 335 * of mode, algorithm type and compare length. The total size of the auth 336 * config word in the setup block is 64 bits however the size of the value 337 * returned by this macro is assumed to be only 32 bits (for now) and sets 338 * the lower 32 bits of the auth config word. Unfortunately, changing the 339 * size of the returned value to 64 bits will also require changes to the 340 * shared RAM constants table so the macro size will remain at 32 bits. 341 * This means that the padding sequence bits specified in bits 48-51 and 342 * 56-63 of the 64-bit auth config word are NOT included in the 343 * ICP_QAT_HW_AUTH_CONFIG_BUILD macro and are defined in a 344 * separate macro, namely, ICP_QAT_HW_AUTH_CONFIG_BUILD_UPPER. 345 * 346 * For the digest generation case the compare length is a don't care value. 347 * Furthermore, if the client will be doing the digest validation, the 348 * compare_length will not be used. 349 * The padding and padding override bits for SHA3 are set internally 350 * by the macro. 351 * Padding_Disable is set it to 0 for SHA3-256 algo only i.e. we want to 352 * enable this to provide the ability to test with h/w padding enabled. 353 * Padding_Disable has no meaning for all non-SHA3-256 algos and is 354 * consequently set the default of 0. 355 * Padding Override is set to 0, implying that the padding behaviour 356 * implemented in the SHA3-256 slice will take effect (default hardware 357 * setting upon h/w reset). 358 * This flag has no meaning for other algos, so is also set to the default 359 * for non-SHA3-256 algos. 360 * 361 * @param mode Authentication mode to use 362 * @param algo Auth Algorithm to use 363 * @param cmp_len The length of the digest if the QAT is to the check 364 * 365 ****************************************************************************************/ 366#define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \ 367 ((((mode)&QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \ 368 (((algo)&QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \ 369 (((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) \ 370 << QAT_AUTH_ALGO_SHA3_BITPOS) | \ 371 (((QAT_AUTH_SHA3_PADDING_DISABLE_USE_DEFAULT)&QAT_AUTH_SHA3_PADDING_DISABLE_MASK) \ 372 << QAT_AUTH_SHA3_PADDING_DISABLE_BITPOS) | \ 373 (((QAT_AUTH_SHA3_PADDING_OVERRIDE_USE_DEFAULT)&QAT_AUTH_SHA3_PADDING_OVERRIDE_MASK) \ 374 << QAT_AUTH_SHA3_PADDING_OVERRIDE_BITPOS) | \ 375 (((cmp_len)&QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS)) 376 377/** 378 *************************************************************************************** 379 * @ingroup icp_qat_hw_defs 380 * 381 * @description 382 * This macro sets the upper 32 bits of the 64-bit auth config word. 383 * The sequence bits specified in bits 48-51 and 56-63 of the 64-bit auth 384 * config word are included in this macro, which is therefore assumed to 385 * return a 32-bit value. 386 * Note that the Padding Override bit is set in macro 387 * ICP_QAT_HW_AUTH_CONFIG_BUILD. 388 * Since the Padding Override is set to 0 regardless, for now, all the bits 389 * of the padding sequence specified in bits 48-51 and 56-63 of the 64-bit 390 * auth config word are set to 0 (reserved). Note that the bit positions of 391 * the padding sequence bits are defined relative to the 32-bit value that 392 * this macro returns. 393 * 394 ****************************************************************************************/ 395#define ICP_QAT_HW_AUTH_CONFIG_BUILD_UPPER \ 396 ((((QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_RESERVED)&QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_MASK) \ 397 << QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_BITPOS) | \ 398 (((QAT_AUTH_SHA3_PROG_PADDING_PREFIX_RESERVED)&QAT_AUTH_SHA3_PROG_PADDING_PREFIX_MASK) \ 399 << QAT_AUTH_SHA3_PROG_PADDING_PREFIX_BITPOS)) 400 401/** 402 ***************************************************************************** 403 * @ingroup icp_qat_hw_defs 404 * Auth Counter structure 405 * 406 * @description 407 * 32 bit counter that tracks the number of data bytes passed through 408 * the slice. This is used by the padding logic for some algorithms. Note 409 * only the upper 32 bits are set. 410 * 411 *****************************************************************************/ 412typedef struct icp_qat_hw_auth_counter_s { 413 uint32_t counter; 414 /**< Counter value */ 415 uint32_t reserved; 416 /**< Reserved */ 417} icp_qat_hw_auth_counter_t; 418 419/* Private defines */ 420#define QAT_AUTH_COUNT_MASK 0xFFFFFFFF 421/**< @ingroup icp_qat_hw_defs 422 * Thirty two bit mask used for determining the Auth count */ 423 424#define QAT_AUTH_COUNT_BITPOS 0 425/**< @ingroup icp_qat_hw_defs 426 * Starting bit position indicating the Auth count. */ 427 428/** 429 ****************************************************************************** 430 * @ingroup icp_qat_hw_defs 431 * 432 * @description 433 * Macro to build the auth counter quad word 434 * 435 * @param val Counter value to set 436 * 437 *****************************************************************************/ 438#define ICP_QAT_HW_AUTH_COUNT_BUILD(val) \ 439 (((val)&QAT_AUTH_COUNT_MASK) << QAT_AUTH_COUNT_BITPOS) 440 441/** 442 ***************************************************************************** 443 * @ingroup icp_qat_hw_defs 444 * Definition of the common auth parameters 445 * @description 446 * This part of the configuration is constant for each service 447 * 448 *****************************************************************************/ 449typedef struct icp_qat_hw_auth_setup_s { 450 icp_qat_hw_auth_config_t auth_config; 451 /**< Configuration word for the auth slice */ 452 icp_qat_hw_auth_counter_t auth_counter; 453 /**< Auth counter value for this request */ 454} icp_qat_hw_auth_setup_t; 455 456/* ************************************************************************* */ 457/* ************************************************************************* */ 458 459#define QAT_HW_DEFAULT_ALIGNMENT 8 460#define QAT_HW_ROUND_UP(val, n) (((val) + ((n)-1)) & (~(n - 1))) 461 462/* State1 */ 463#define ICP_QAT_HW_NULL_STATE1_SZ 32 464/**< @ingroup icp_qat_hw_defs 465 * State1 block size for NULL hashing */ 466#define ICP_QAT_HW_MD5_STATE1_SZ 16 467/**< @ingroup icp_qat_hw_defs 468 * State1 block size for MD5 */ 469#define ICP_QAT_HW_SHA1_STATE1_SZ 20 470/**< @ingroup icp_qat_hw_defs 471 * Define the state1 block size for SHA1 - Note that for the QAT HW the state 472 * is rounded to the nearest 8 byte multiple */ 473#define ICP_QAT_HW_SHA224_STATE1_SZ 32 474/**< @ingroup icp_qat_hw_defs 475 * State1 block size for SHA24 */ 476#define ICP_QAT_HW_SHA3_224_STATE1_SZ 28 477/**< @ingroup icp_qat_hw_defs 478 * State1 block size for SHA3_224 */ 479#define ICP_QAT_HW_SHA256_STATE1_SZ 32 480/**< @ingroup icp_qat_hw_defs 481 * State1 block size for SHA256 */ 482#define ICP_QAT_HW_SHA3_256_STATE1_SZ 32 483/**< @ingroup icp_qat_hw_defs 484 * State1 block size for SHA3_256 */ 485#define ICP_QAT_HW_SHA384_STATE1_SZ 64 486/**< @ingroup icp_qat_hw_defs 487 * State1 block size for SHA384 */ 488#define ICP_QAT_HW_SHA3_384_STATE1_SZ 48 489/**< @ingroup icp_qat_hw_defs 490 * State1 block size for SHA3_384 */ 491#define ICP_QAT_HW_SHA512_STATE1_SZ 64 492/**< @ingroup icp_qat_hw_defs 493 * State1 block size for SHA512 */ 494#define ICP_QAT_HW_SHA3_512_STATE1_SZ 64 495/**< @ingroup icp_qat_hw_defs 496 * State1 block size for SHA3_512 */ 497#define ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ 16 498/**< @ingroup icp_qat_hw_defs 499 * State1 block size for XCBC */ 500#define ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ 16 501/**< @ingroup icp_qat_hw_defs 502 * State1 block size for CBC */ 503#define ICP_QAT_HW_AES_F9_STATE1_SZ 32 504/**< @ingroup icp_qat_hw_defs 505 * State1 block size for AES F9 */ 506#define ICP_QAT_HW_KASUMI_F9_STATE1_SZ 16 507/**< @ingroup icp_qat_hw_defs 508 * State1 block size for Kasumi F9 */ 509#define ICP_QAT_HW_GALOIS_128_STATE1_SZ 16 510/**< @ingroup icp_qat_hw_defs 511 * State1 block size for Galois128 */ 512#define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8 513/**< @ingroup icp_cpm_hw_defs 514 * State1 block size for UIA2 */ 515#define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8 516/**< @ingroup icp_cpm_hw_defs 517 * State1 block size for EIA3 */ 518#define ICP_QAT_HW_SM3_STATE1_SZ 32 519/**< @ingroup icp_qat_hw_defs 520 * State1 block size for SM3 */ 521#define ICP_QAT_HW_SHA3_STATEFUL_STATE1_SZ 200 522/** <@ingroup icp_cpm_hw_defs 523 * State1 block size for stateful SHA3 processing*/ 524 525/* State2 */ 526#define ICP_QAT_HW_NULL_STATE2_SZ 32 527/**< @ingroup icp_qat_hw_defs 528 * State2 block size for NULL hashing */ 529#define ICP_QAT_HW_MD5_STATE2_SZ 16 530/**< @ingroup icp_qat_hw_defs 531 * State2 block size for MD5 */ 532#define ICP_QAT_HW_SHA1_STATE2_SZ 20 533/**< @ingroup icp_qat_hw_defs 534 * State2 block size for SHA1 - Note that for the QAT HW the state is rounded 535 * to the nearest 8 byte multiple */ 536#define ICP_QAT_HW_SHA224_STATE2_SZ 32 537/**< @ingroup icp_qat_hw_defs 538 * State2 block size for SHA224 */ 539#define ICP_QAT_HW_SHA3_224_STATE2_SZ 0 540/**< @ingroup icp_qat_hw_defs 541 * State2 block size for SHA3_224 */ 542#define ICP_QAT_HW_SHA256_STATE2_SZ 32 543/**< @ingroup icp_qat_hw_defs 544 * State2 block size for SHA256 */ 545#define ICP_QAT_HW_SHA3_256_STATE2_SZ 0 546/**< @ingroup icp_qat_hw_defs 547 * State2 block size for SHA3_256 */ 548#define ICP_QAT_HW_SHA384_STATE2_SZ 64 549/**< @ingroup icp_qat_hw_defs 550 * State2 block size for SHA384 */ 551#define ICP_QAT_HW_SHA3_384_STATE2_SZ 0 552/**< @ingroup icp_qat_hw_defs 553 * State2 block size for SHA3_384 */ 554#define ICP_QAT_HW_SHA512_STATE2_SZ 64 555/**< @ingroup icp_qat_hw_defs 556 * State2 block size for SHA512 */ 557#define ICP_QAT_HW_SHA3_512_STATE2_SZ 0 558/**< @ingroup icp_qat_hw_defs 559 * State2 block size for SHA3_512 */ 560#define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16 561/**< @ingroup icp_qat_hw_defs 562 * State2 block size for XCBC */ 563#define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16 564/**< @ingroup icp_qat_hw_defs 565 * State2 block size for CBC */ 566#define ICP_QAT_HW_AES_CCM_CBC_E_CTR0_SZ 16 567/**< @ingroup icp_qat_hw_defs 568 * State2 block size for AES Encrypted Counter 0 */ 569#define ICP_QAT_HW_F9_IK_SZ 16 570/**< @ingroup icp_qat_hw_defs 571 * State2 block size for F9 IK */ 572#define ICP_QAT_HW_F9_FK_SZ 16 573/**< @ingroup icp_qat_hw_defs 574 * State2 block size for F9 FK */ 575#define ICP_QAT_HW_KASUMI_F9_STATE2_SZ \ 576 (ICP_QAT_HW_F9_IK_SZ + ICP_QAT_HW_F9_FK_SZ) 577/**< @ingroup icp_qat_hw_defs 578 * State2 complete size for Kasumi F9 */ 579#define ICP_QAT_HW_AES_F9_STATE2_SZ ICP_QAT_HW_KASUMI_F9_STATE2_SZ 580/**< @ingroup icp_qat_hw_defs 581 * State2 complete size for AES F9 */ 582#define ICP_QAT_HW_SNOW_3G_UIA2_STATE2_SZ 24 583/**< @ingroup icp_cpm_hw_defs 584 * State2 block size for UIA2 */ 585#define ICP_QAT_HW_ZUC_3G_EIA3_STATE2_SZ 32 586/**< @ingroup icp_cpm_hw_defs 587 * State2 block size for EIA3 */ 588#define ICP_QAT_HW_GALOIS_H_SZ 16 589/**< @ingroup icp_qat_hw_defs 590 * State2 block size for Galois Multiplier H */ 591#define ICP_QAT_HW_GALOIS_LEN_A_SZ 8 592/**< @ingroup icp_qat_hw_defs 593 * State2 block size for Galois AAD length */ 594#define ICP_QAT_HW_GALOIS_E_CTR0_SZ 16 595/**< @ingroup icp_qat_hw_defs 596 * State2 block size for Galois Encrypted Counter 0 */ 597#define ICP_QAT_HW_SM3_STATE2_SZ 32 598/**< @ingroup icp_qat_hw_defs 599 * State2 block size for SM3 */ 600#define ICP_QAT_HW_SHA3_STATEFUL_STATE2_SZ 208 601/** <@ingroup icp_cpm_hw_defs 602 * State2 block size for stateful SHA3 processing*/ 603 604/* ************************************************************************* */ 605/* ************************************************************************* */ 606 607/** 608 ***************************************************************************** 609 * @ingroup icp_qat_hw_defs 610 * Definition of SHA512 auth algorithm processing struct 611 * @description 612 * This structs described the parameters to pass to the slice for 613 * configuring it for SHA512 processing. This is the largest possible 614 * setup block for authentication 615 * 616 *****************************************************************************/ 617typedef struct icp_qat_hw_auth_sha512_s { 618 icp_qat_hw_auth_setup_t inner_setup; 619 /**< Inner loop configuration word for the slice */ 620 621 uint8_t state1[ICP_QAT_HW_SHA512_STATE1_SZ]; 622 /**< Slice state1 variable */ 623 624 icp_qat_hw_auth_setup_t outer_setup; 625 /**< Outer configuration word for the slice */ 626 627 uint8_t state2[ICP_QAT_HW_SHA512_STATE2_SZ]; 628 /**< Slice state2 variable */ 629 630} icp_qat_hw_auth_sha512_t; 631 632/** 633 ***************************************************************************** 634 * @ingroup icp_qat_hw_defs 635 * Definition of SHA3_512 auth algorithm processing struct 636 * @description 637 * This structs described the parameters to pass to the slice for 638 * configuring it for SHA3_512 processing. This is the largest possible 639 * setup block for authentication 640 * 641 *****************************************************************************/ 642typedef struct icp_qat_hw_auth_sha3_512_s { 643 icp_qat_hw_auth_setup_t inner_setup; 644 /**< Inner loop configuration word for the slice */ 645 646 uint8_t state1[ICP_QAT_HW_SHA3_512_STATE1_SZ]; 647 /**< Slice state1 variable */ 648 649 icp_qat_hw_auth_setup_t outer_setup; 650 /**< Outer configuration word for the slice */ 651 652} icp_qat_hw_auth_sha3_512_t; 653 654/** 655 ***************************************************************************** 656 * @ingroup icp_qat_hw_defs 657 * Definition of stateful SHA3 auth algorithm processing struct 658 * @description 659 * This structs described the parameters to pass to the slice for 660 * configuring it for stateful SHA3 processing. This is the largest 661 * possible setup block for authentication 662 * 663 *****************************************************************************/ 664typedef struct icp_qat_hw_auth_sha3_stateful_s { 665 icp_qat_hw_auth_setup_t inner_setup; 666 /**< Inner loop configuration word for the slice */ 667 668 uint8_t inner_state1[ICP_QAT_HW_SHA3_STATEFUL_STATE1_SZ]; 669 /**< Inner hash block */ 670 671 icp_qat_hw_auth_setup_t outer_setup; 672 /**< Outer configuration word for the slice */ 673 674 uint8_t outer_state1[ICP_QAT_HW_SHA3_STATEFUL_STATE1_SZ]; 675 /**< Outer hash block */ 676 677} icp_qat_hw_auth_sha3_stateful_t; 678 679/** 680 ***************************************************************************** 681 * @ingroup icp_qat_hw_defs 682 * Supported hardware authentication algorithms 683 * @description 684 * Common grouping of the auth algorithm types supported by the QAT 685 * 686 *****************************************************************************/ 687typedef union icp_qat_hw_auth_algo_blk_u { 688 icp_qat_hw_auth_sha512_t sha512; 689 /**< SHA512 Hashing */ 690 icp_qat_hw_auth_sha3_stateful_t sha3_stateful; 691 /**< Stateful SHA3 Hashing */ 692 693} icp_qat_hw_auth_algo_blk_t; 694 695#define ICP_QAT_HW_GALOIS_LEN_A_BITPOS 0 696/**< @ingroup icp_qat_hw_defs 697 * Bit position of the 32 bit A value in the 64 bit A configuration sent to 698 * the QAT */ 699 700#define ICP_QAT_HW_GALOIS_LEN_A_MASK 0xFFFFFFFF 701/**< @ingroup icp_qat_hw_defs 702 * Mask value for A value */ 703 704/* ========================================================================= */ 705/* CIPHER SLICE */ 706/* ========================================================================= */ 707 708/** 709 ***************************************************************************** 710 * @ingroup icp_qat_hw_defs 711 * Definition of the supported Cipher Algorithm types 712 * @description 713 * Enumeration used to define the cipher algorithms 714 * 715 *****************************************************************************/ 716 717typedef enum { 718 ICP_QAT_HW_CIPHER_ALGO_NULL = 0, /*!< Null ciphering */ 719 ICP_QAT_HW_CIPHER_ALGO_DES = 1, /*!< DES ciphering */ 720 ICP_QAT_HW_CIPHER_ALGO_3DES = 2, /*!< 3DES ciphering */ 721 ICP_QAT_HW_CIPHER_ALGO_AES128 = 3, /*!< AES-128 ciphering */ 722 ICP_QAT_HW_CIPHER_ALGO_AES192 = 4, /*!< AES-192 ciphering */ 723 ICP_QAT_HW_CIPHER_ALGO_AES256 = 5, /*!< AES-256 ciphering */ 724 ICP_QAT_HW_CIPHER_ALGO_ARC4 = 6, /*!< ARC4 ciphering */ 725 ICP_QAT_HW_CIPHER_ALGO_KASUMI = 7, /*!< Kasumi */ 726 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 = 8, /*!< Snow_3G */ 727 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 = 9, /*!< ZUC_3G */ 728 ICP_QAT_HW_CIPHER_ALGO_SM4 = 10, /*!< SM4 ciphering */ 729 ICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305 = 730 11, /*!< CHACHA POLY SPC AEAD */ 731 ICP_QAT_HW_CIPHER_DELIMITER = 12 /**< Delimiter type */ 732} icp_qat_hw_cipher_algo_t; 733 734/** 735 ***************************************************************************** 736 * @ingroup icp_qat_hw_defs 737 * Definition of the supported cipher modes of operation 738 * @description 739 * Enumeration used to define the cipher slice modes. 740 * 741 * @Note 742 * Only some algorithms are valid in some of the modes. If you dont know 743 * what you are doing then refer back to the EAS 744 * 745 *****************************************************************************/ 746 747typedef enum { 748 ICP_QAT_HW_CIPHER_ECB_MODE = 0, /*!< ECB mode */ 749 ICP_QAT_HW_CIPHER_CBC_MODE = 1, /*!< CBC more */ 750 ICP_QAT_HW_CIPHER_CTR_MODE = 2, /*!< CTR mode */ 751 ICP_QAT_HW_CIPHER_F8_MODE = 3, /*!< F8 mode */ 752 ICP_QAT_HW_CIPHER_AEAD_MODE = 4, /*!< AES-GCM SPC AEAD mode */ 753 ICP_QAT_HW_CIPHER_CCM_MODE = 5, /*!< AES-CCM SPC AEAD mode */ 754 ICP_QAT_HW_CIPHER_XTS_MODE = 6, /*!< XTS mode */ 755 ICP_QAT_HW_CIPHER_MODE_DELIMITER = 7 /**< Delimiter type */ 756} icp_qat_hw_cipher_mode_t; 757 758/** 759 ***************************************************************************** 760 * @ingroup icp_qat_hw_defs 761 * Cipher Configuration Struct 762 * 763 * @description 764 * Configuration data used for setting up the QAT Cipher Slice 765 * 766 *****************************************************************************/ 767 768typedef struct icp_qat_hw_cipher_config_s { 769 uint32_t val; 770 /**< Cipher slice configuration */ 771 772 uint32_t reserved; 773 /**< Reserved */ 774} icp_qat_hw_cipher_config_t; 775 776/** 777 ***************************************************************************** 778 * @ingroup icp_qat_hw_defs 779 * Cipher Configuration Struct 780 * 781 * @description 782 * Configuration data used for setting up the QAT UCS Cipher Slice 783 * 784 *****************************************************************************/ 785typedef struct icp_qat_hw_ucs_cipher_config_s { 786 uint32_t val; 787 /**< Cipher slice configuration */ 788 789 uint32_t reserved[3]; 790 /**< Reserved */ 791} icp_qat_hw_ucs_cipher_config_t; 792 793/** 794 ***************************************************************************** 795 * @ingroup icp_qat_hw_defs 796 * Definition of the cipher direction 797 * @description 798 * Enumeration which is used to define the cipher direction to apply 799 * 800 *****************************************************************************/ 801 802typedef enum { 803 /*!< Flag to indicate that encryption is required */ 804 ICP_QAT_HW_CIPHER_ENCRYPT = 0, 805 /*!< Flag to indicate that decryption is required */ 806 ICP_QAT_HW_CIPHER_DECRYPT = 1, 807 808} icp_qat_hw_cipher_dir_t; 809 810/** 811 ***************************************************************************** 812 * @ingroup icp_qat_hw_defs 813 * Definition of the cipher key conversion modes 814 * @description 815 * Enumeration which is used to define if cipher key conversion is needed 816 * 817 *****************************************************************************/ 818 819typedef enum { 820 /*!< Flag to indicate that no key convert is required */ 821 ICP_QAT_HW_CIPHER_NO_CONVERT = 0, 822 /*!< Flag to indicate that key conversion is required */ 823 ICP_QAT_HW_CIPHER_KEY_CONVERT = 1, 824} icp_qat_hw_cipher_convert_t; 825 826/* Private defines */ 827 828/* Note: Bit positions have been arranged for little endian ordering */ 829 830#define QAT_CIPHER_MODE_BITPOS 4 831/**< @ingroup icp_qat_hw_defs 832 * Define for the cipher mode bit position */ 833 834#define QAT_CIPHER_MODE_MASK 0xF 835/**< @ingroup icp_qat_hw_defs 836 * Define for the cipher mode mask (four bits) */ 837 838#define QAT_CIPHER_ALGO_BITPOS 0 839/**< @ingroup icp_qat_hw_defs 840 * Define for the cipher algo bit position */ 841 842#define QAT_CIPHER_ALGO_MASK 0xF 843/**< @ingroup icp_qat_hw_defs 844 * Define for the cipher algo mask (four bits) */ 845 846#define QAT_CIPHER_CONVERT_BITPOS 9 847/**< @ingroup icp_qat_hw_defs 848 * Define the cipher convert key bit position */ 849 850#define QAT_CIPHER_CONVERT_MASK 0x1 851/**< @ingroup icp_qat_hw_defs 852 * Define for the cipher convert key mask (one bit)*/ 853 854#define QAT_CIPHER_DIR_BITPOS 8 855/**< @ingroup icp_qat_hw_defs 856 * Define for the cipher direction bit position */ 857 858#define QAT_CIPHER_DIR_MASK 0x1 859/**< @ingroup icp_qat_hw_defs 860 * Define for the cipher direction mask (one bit) */ 861 862#define QAT_CIPHER_AEAD_HASH_CMP_LEN_MASK 0x1F 863/**< @ingroup icp_qat_hw_defs 864 * Define for the cipher AEAD Hash compare length mask (5 bits)*/ 865 866#define QAT_CIPHER_AEAD_HASH_CMP_LEN_BITPOS 10 867/**< @ingroup icp_qat_hw_defs 868 * Define for the cipher AEAD Hash compare length (5 bits)*/ 869 870#define QAT_CIPHER_AEAD_AAD_SIZE_LOWER_MASK 0xFF 871/**< @ingroup icp_qat_hw_defs 872 * Define for the cipher AEAD AAD size lower byte mask */ 873 874#define QAT_CIPHER_AEAD_AAD_SIZE_UPPER_MASK 0x3F 875/**< @ingroup icp_qat_hw_defs 876 * Define for the cipher AEAD AAD size upper 6 bits mask */ 877 878#define QAT_CIPHER_AEAD_AAD_UPPER_SHIFT 8 879/**< @ingroup icp_qat_hw_defs 880 * Define for the cipher AEAD AAD size Upper byte shift */ 881 882#define QAT_CIPHER_AEAD_AAD_LOWER_SHIFT 24 883/**< @ingroup icp_qat_hw_defs 884 * Define for the cipher AEAD AAD size Lower byte shift */ 885 886#define QAT_CIPHER_AEAD_AAD_SIZE_BITPOS 16 887/**< @ingroup icp_qat_hw_defs 888 * Define for the cipher AEAD AAD size (14 bits)*/ 889 890#define QAT_CIPHER_MODE_F8_KEY_SZ_MULT 2 891/**< @ingroup icp_qat_hw_defs 892 * Define for the cipher mode F8 key size */ 893 894#define QAT_CIPHER_MODE_XTS_KEY_SZ_MULT 2 895/**< @ingroup icp_qat_hw_defs 896 * Define for the cipher XTS mode key size */ 897 898#define QAT_CIPHER_MODE_UCS_XTS_KEY_SZ_MULT 1 899/**< @ingroup icp_qat_hw_defs 900 * Define for the UCS cipher XTS mode key size */ 901 902/** 903 ****************************************************************************** 904 * @ingroup icp_qat_hw_defs 905 * 906 * @description 907 * Build the cipher configuration field 908 * 909 * @param mode Cipher Mode to use 910 * @param algo Cipher Algorithm to use 911 * @param convert Specify if the key is to be converted 912 * @param dir Specify the cipher direction either encrypt or decrypt 913 * 914 *****************************************************************************/ 915#define ICP_QAT_HW_CIPHER_CONFIG_BUILD( \ 916 mode, algo, convert, dir, aead_hash_cmp_len) \ 917 ((((mode)&QAT_CIPHER_MODE_MASK) << QAT_CIPHER_MODE_BITPOS) | \ 918 (((algo)&QAT_CIPHER_ALGO_MASK) << QAT_CIPHER_ALGO_BITPOS) | \ 919 (((convert)&QAT_CIPHER_CONVERT_MASK) << QAT_CIPHER_CONVERT_BITPOS) | \ 920 (((dir)&QAT_CIPHER_DIR_MASK) << QAT_CIPHER_DIR_BITPOS) | \ 921 (((aead_hash_cmp_len)&QAT_CIPHER_AEAD_HASH_CMP_LEN_MASK) \ 922 << QAT_CIPHER_AEAD_HASH_CMP_LEN_BITPOS)) 923 924/** 925 ****************************************************************************** 926 * @ingroup icp_qat_hw_defs 927 * 928 * @description 929 * Build the second QW of cipher slice config 930 * 931 * @param aad_size Specify the size of associated authentication data 932 * for AEAD processing 933 * 934 ******************************************************************************/ 935#define ICP_QAT_HW_CIPHER_CONFIG_BUILD_UPPER(aad_size) \ 936 (((((aad_size) >> QAT_CIPHER_AEAD_AAD_UPPER_SHIFT) & \ 937 QAT_CIPHER_AEAD_AAD_SIZE_UPPER_MASK) \ 938 << QAT_CIPHER_AEAD_AAD_SIZE_BITPOS) | \ 939 (((aad_size)&QAT_CIPHER_AEAD_AAD_SIZE_LOWER_MASK) \ 940 << QAT_CIPHER_AEAD_AAD_LOWER_SHIFT)) 941 942#define ICP_QAT_HW_DES_BLK_SZ 8 943/**< @ingroup icp_qat_hw_defs 944 * Define the block size for DES. 945 * This used as either the size of the IV or CTR input value */ 946#define ICP_QAT_HW_3DES_BLK_SZ 8 947/**< @ingroup icp_qat_hw_defs 948 * Define the processing block size for 3DES */ 949#define ICP_QAT_HW_NULL_BLK_SZ 8 950/**< @ingroup icp_qat_hw_defs 951 * Define the processing block size for NULL */ 952#define ICP_QAT_HW_AES_BLK_SZ 16 953/**< @ingroup icp_qat_hw_defs 954 * Define the processing block size for AES 128, 192 and 256 */ 955#define ICP_QAT_HW_KASUMI_BLK_SZ 8 956/**< @ingroup icp_qat_hw_defs 957 * Define the processing block size for KASUMI */ 958#define ICP_QAT_HW_SNOW_3G_BLK_SZ 8 959/**< @ingroup icp_qat_hw_defs 960 * Define the processing block size for SNOW_3G */ 961#define ICP_QAT_HW_ZUC_3G_BLK_SZ 8 962/**< @ingroup icp_qat_hw_defs 963 * Define the processing block size for ZUC_3G */ 964#define ICP_QAT_HW_NULL_KEY_SZ 256 965/**< @ingroup icp_qat_hw_defs 966 * Define the key size for NULL */ 967#define ICP_QAT_HW_DES_KEY_SZ 8 968/**< @ingroup icp_qat_hw_defs 969 * Define the key size for DES */ 970#define ICP_QAT_HW_3DES_KEY_SZ 24 971/**< @ingroup icp_qat_hw_defs 972 * Define the key size for 3DES */ 973#define ICP_QAT_HW_AES_128_KEY_SZ 16 974/**< @ingroup icp_qat_hw_defs 975 * Define the key size for AES128 */ 976#define ICP_QAT_HW_AES_192_KEY_SZ 24 977/**< @ingroup icp_qat_hw_defs 978 * Define the key size for AES192 */ 979#define ICP_QAT_HW_AES_256_KEY_SZ 32 980/**< @ingroup icp_qat_hw_defs 981 * Define the key size for AES256 */ 982/* AES UCS */ 983#define ICP_QAT_HW_UCS_AES_128_KEY_SZ ICP_QAT_HW_AES_128_KEY_SZ 984/**< @ingroup icp_qat_hw_defs 985 * Define the key size for AES128 for UCS slice*/ 986#define ICP_QAT_HW_UCS_AES_192_KEY_SZ 32 987/**< @ingroup icp_qat_hw_defs 988 * Define the key size for AES192 for UCS slice*/ 989#define ICP_QAT_HW_UCS_AES_256_KEY_SZ ICP_QAT_HW_AES_256_KEY_SZ 990/**< @ingroup icp_qat_hw_defs 991 * Define the key size for AES256 for UCS slice*/ 992#define ICP_QAT_HW_AES_128_F8_KEY_SZ \ 993 (ICP_QAT_HW_AES_128_KEY_SZ * QAT_CIPHER_MODE_F8_KEY_SZ_MULT) 994/**< @ingroup icp_qat_hw_defs 995 * Define the key size for AES128 F8 */ 996#define ICP_QAT_HW_AES_192_F8_KEY_SZ \ 997 (ICP_QAT_HW_AES_192_KEY_SZ * QAT_CIPHER_MODE_F8_KEY_SZ_MULT) 998/**< @ingroup icp_qat_hw_defs 999 * Define the key size for AES192 F8 */ 1000#define ICP_QAT_HW_AES_256_F8_KEY_SZ \ 1001 (ICP_QAT_HW_AES_256_KEY_SZ * QAT_CIPHER_MODE_F8_KEY_SZ_MULT) 1002/**< @ingroup icp_qat_hw_defs 1003 * Define the key size for AES256 F8 */ 1004#define ICP_QAT_HW_AES_128_XTS_KEY_SZ \ 1005 (ICP_QAT_HW_AES_128_KEY_SZ * QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) 1006/**< @ingroup icp_qat_hw_defs 1007 * Define the key size for AES128 XTS */ 1008#define ICP_QAT_HW_AES_256_XTS_KEY_SZ \ 1009 (ICP_QAT_HW_AES_256_KEY_SZ * QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) 1010/**< @ingroup icp_qat_hw_defs 1011 * Define the key size for AES256 XTS */ 1012#define ICP_QAT_HW_UCS_AES_128_XTS_KEY_SZ \ 1013 (ICP_QAT_HW_UCS_AES_128_KEY_SZ * QAT_CIPHER_MODE_UCS_XTS_KEY_SZ_MULT) 1014/**< @ingroup icp_qat_hw_defs 1015 * Define the key size for AES128 XTS for the UCS Slice*/ 1016#define ICP_QAT_HW_UCS_AES_256_XTS_KEY_SZ \ 1017 (ICP_QAT_HW_UCS_AES_256_KEY_SZ * QAT_CIPHER_MODE_UCS_XTS_KEY_SZ_MULT) 1018/**< @ingroup icp_qat_hw_defs 1019 * Define the key size for AES256 XTS for the UCS Slice*/ 1020#define ICP_QAT_HW_KASUMI_KEY_SZ 16 1021/**< @ingroup icp_qat_hw_defs 1022 * Define the key size for Kasumi */ 1023#define ICP_QAT_HW_KASUMI_F8_KEY_SZ \ 1024 (ICP_QAT_HW_KASUMI_KEY_SZ * QAT_CIPHER_MODE_F8_KEY_SZ_MULT) 1025/**< @ingroup icp_qat_hw_defs 1026 * Define the key size for Kasumi F8 */ 1027#define ICP_QAT_HW_AES_128_XTS_KEY_SZ \ 1028 (ICP_QAT_HW_AES_128_KEY_SZ * QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) 1029/**< @ingroup icp_qat_hw_defs 1030 * Define the key size for AES128 XTS */ 1031#define ICP_QAT_HW_AES_256_XTS_KEY_SZ \ 1032 (ICP_QAT_HW_AES_256_KEY_SZ * QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) 1033/**< @ingroup icp_qat_hw_defs 1034 * Define the key size for AES256 XTS */ 1035#define ICP_QAT_HW_ARC4_KEY_SZ 256 1036/**< @ingroup icp_qat_hw_defs 1037 * Define the key size for ARC4 */ 1038#define ICP_QAT_HW_SNOW_3G_UEA2_KEY_SZ 16 1039/**< @ingroup icp_cpm_hw_defs 1040 * Define the key size for SNOW_3G_UEA2 */ 1041#define ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ 16 1042/**< @ingroup icp_cpm_hw_defs 1043 * Define the iv size for SNOW_3G_UEA2 */ 1044#define ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ 16 1045/**< @ingroup icp_cpm_hw_defs 1046 * Define the key size for ZUC_3G_EEA3 */ 1047#define ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ 16 1048/**< @ingroup icp_cpm_hw_defs 1049 * Define the iv size for ZUC_3G_EEA3 */ 1050#define ICP_QAT_HW_MODE_F8_NUM_REG_TO_CLEAR 2 1051/**< @ingroup icp_cpm_hw_defs 1052 * Number of the HW register to clear in F8 mode */ 1053/**< @ingroup icp_qat_hw_defs 1054 * Define the State/ Initialization Vector size for CHACHAPOLY */ 1055#define ICP_QAT_HW_CHACHAPOLY_KEY_SZ 32 1056/**< @ingroup icp_qat_hw_defs 1057 * Define the key size for CHACHA20-Poly1305*/ 1058#define ICP_QAT_HW_CHACHAPOLY_IV_SZ 12 1059/**< @ingroup icp_qat_hw_defs 1060 * Define the block size for CHACHA20-Poly1305*/ 1061#define ICP_QAT_HW_CHACHAPOLY_BLK_SZ 64 1062/**< @ingroup icp_qat_hw_defs 1063 * Define the State/ Initialization Vector size for CHACHA20-Poly1305 */ 1064#define ICP_QAT_HW_CHACHAPOLY_CTR_SZ 16 1065/**< @ingroup icp_qat_hw_defs 1066 * Define the key size for CHACHA20-Poly1305*/ 1067#define ICP_QAT_HW_SPC_CTR_SZ 16 1068/**< @ingroup icp_qat_hw_defs 1069 * Define the Single Pass tag size*/ 1070#define ICP_QAT_HW_CHACHAPOLY_ICV__SZ 16 1071/**< @ingroup icp_qat_hw_defs 1072 * Define the key size for CHACHA20-Poly1305*/ 1073#define ICP_QAT_HW_CHACHAPOLY_AAD_MAX_LOG 14 1074/**< @ingroup icp_qat_hw_defs 1075 * Define the key size for CHACHA20-Poly1305*/ 1076#define ICP_QAT_HW_SM4_BLK_SZ 16 1077/**< @ingroup icp_qat_hw_defs 1078 * Define the processing block size for SM4 */ 1079#define ICP_QAT_HW_SM4_KEY_SZ 16 1080/**< @ingroup icp_qat_hw_defs 1081 * Number of the HW register to clear in F8 mode */ 1082#define ICP_QAT_HW_SM4_IV_SZ 16 1083/**< @ingroup icp_qat_hw_defs 1084 * Define the key size for SM4 */ 1085 1086/* 1087 * SHRAM constants definitions 1088 */ 1089#define INIT_SHRAM_CONSTANTS_TABLE_SZ (1024) 1090#define SHRAM_CONSTANTS_TABLE_SIZE_QWS (INIT_SHRAM_CONSTANTS_TABLE_SZ / 4 / 2) 1091 1092/** 1093 ***************************************************************************** 1094 * @ingroup icp_qat_hw_defs 1095 * Definition of AES-256 F8 cipher algorithm processing struct 1096 * @description 1097 * This structs described the parameters to pass to the slice for 1098 * configuring it for AES-256 F8 processing 1099 * 1100 *****************************************************************************/ 1101typedef struct icp_qat_hw_cipher_aes256_f8_s { 1102 icp_qat_hw_cipher_config_t cipher_config; 1103 /**< Cipher configuration word for the slice set to 1104 * AES-256 and the F8 mode */ 1105 1106 uint8_t key[ICP_QAT_HW_AES_256_F8_KEY_SZ]; 1107 /**< Cipher key */ 1108 1109} icp_qat_hw_cipher_aes256_f8_t; 1110 1111/** 1112 ***************************************************************************** 1113 * @ingroup icp_qat_hw_defs 1114 * Supported hardware cipher algorithms 1115 * @description 1116 * Common grouping of the cipher algorithm types supported by the QAT. 1117 * This is the largest possible cipher setup block size 1118 * 1119 *****************************************************************************/ 1120typedef union icp_qat_hw_cipher_algo_blk_u { 1121 1122 icp_qat_hw_cipher_aes256_f8_t aes256_f8; 1123 /**< AES-256 F8 Cipher */ 1124 1125} icp_qat_hw_cipher_algo_blk_t; 1126 1127/* ========================================================================= */ 1128/* TRNG SLICE */ 1129/* ========================================================================= */ 1130 1131/** 1132 ***************************************************************************** 1133 * @ingroup icp_qat_hw_defs 1134 * Definition of the supported TRNG configuration modes 1135 * @description 1136 * Enumeration used to define the TRNG modes. Used by clients when 1137 * configuring the TRNG for use 1138 * 1139 *****************************************************************************/ 1140 1141typedef enum { 1142 ICP_QAT_HW_TRNG_DBL = 0, /*!< TRNG Disabled mode */ 1143 ICP_QAT_HW_TRNG_NHT = 1, /*!< TRNG Normal Health Test mode */ 1144 ICP_QAT_HW_TRNG_KAT = 4, /*!< TRNG Known Answer Test mode */ 1145 ICP_QAT_HW_TRNG_DELIMITER = 8 /**< Delimiter type */ 1146} icp_qat_hw_trng_cfg_mode_t; 1147 1148/** 1149 ***************************************************************************** 1150 * @ingroup icp_qat_hw_defs 1151 * Definition of the supported TRNG KAT (known answer test) modes 1152 * @description 1153 * Enumeration which is used to define the TRNG KAT modes. Used by clients 1154 * when configuring the TRNG for testing 1155 * 1156 *****************************************************************************/ 1157 1158typedef enum { 1159 ICP_QAT_HW_TRNG_NEG_0 = 0, /*!< TRNG Neg Zero Test */ 1160 ICP_QAT_HW_TRNG_NEG_1 = 1, /*!< TRNG Neg One Test */ 1161 ICP_QAT_HW_TRNG_POS = 2, /*!< TRNG POS Test */ 1162 ICP_QAT_HW_TRNG_POS_VNC = 3, /*!< TRNG POS VNC Test */ 1163 ICP_QAT_HW_TRNG_KAT_DELIMITER = 4 /**< Delimiter type */ 1164} icp_qat_hw_trng_kat_mode_t; 1165 1166/** 1167 ***************************************************************************** 1168 * @ingroup icp_qat_hw_defs 1169 * TRNG mode configuration structure. 1170 * 1171 * @description 1172 * Definition of the format of the TRNG slice configuration. Used 1173 * internally by the QAT FW for configuration of the KAT unit or the 1174 * TRNG depending on the slice command i.e. either a set_slice_config or 1175 * slice_wr_KAT_type 1176 * 1177 *****************************************************************************/ 1178 1179typedef struct icp_qat_hw_trng_config_s { 1180 uint32_t val; 1181 /**< Configuration used for setting up the TRNG slice */ 1182 1183 uint32_t reserved; 1184 /**< Reserved */ 1185} icp_qat_hw_trng_config_t; 1186 1187/* Private Defines */ 1188 1189/* Note: Bit positions have been arranged for little endian ordering */ 1190 1191#define QAT_TRNG_CONFIG_MODE_MASK 0x7 1192/**< @ingroup icp_qat_hw_defs 1193 * Mask for the TRNG configuration mode. (Three bits) */ 1194 1195#define QAT_TRNG_CONFIG_MODE_BITPOS 5 1196/**< @ingroup icp_qat_hw_defs 1197 * TRNG configuration mode bit positions start */ 1198 1199#define QAT_TRNG_KAT_MODE_MASK 0x3 1200/**< @ingroup icp_qat_hw_defs 1201 * Mask of two bits for the TRNG known answer test mode */ 1202 1203#define QAT_TRNG_KAT_MODE_BITPOS 6 1204/**< @ingroup icp_qat_hw_defs 1205 * TRNG known answer test mode bit positions start */ 1206 1207/** 1208 ****************************************************************************** 1209 * @ingroup icp_qat_hw_defs 1210 * 1211 * @description 1212 * Build the configuration byte for the TRNG slice based on the mode 1213 * 1214 * @param mode Configuration mode parameter 1215 * 1216 *****************************************************************************/ 1217#define ICP_QAT_HW_TRNG_CONFIG_MODE_BUILD(mode) \ 1218 (((mode)&QAT_TRNG_CONFIG_MODE_MASK) << QAT_TRNG_CONFIG_MODE_BITPOS) 1219 1220/** 1221 ****************************************************************************** 1222 * @ingroup icp_qat_hw_defs 1223 * 1224 * @description 1225 * Build the configuration byte for the TRNG KAT based on the mode 1226 * 1227 * @param mode Configuration mode parameter 1228 * 1229 *****************************************************************************/ 1230#define ICP_QAT_HW_TRNG_KAT_MODE_BUILD(mode) \ 1231 ((((mode)&QAT_TRNG_KAT_MODE_MASK) << QAT_TRNG_KAT_MODE_BITPOS)) 1232 1233/** 1234 ***************************************************************************** 1235 * @ingroup icp_qat_hw_defs 1236 * TRNG test status structure. 1237 * 1238 * @description 1239 * Definition of the format of the TRNG slice test status structure. Used 1240 * internally by the QAT FW. 1241 * 1242 *****************************************************************************/ 1243 1244typedef struct icp_qat_hw_trng_test_status_s { 1245 1246 uint32_t status; 1247 /**< Status used for setting up the TRNG slice */ 1248 1249 uint32_t fail_count; 1250 /**< Comparator fail count */ 1251} icp_qat_hw_trng_test_status_t; 1252 1253#define ICP_QAT_HW_TRNG_TEST_NO_FAILURES 1 1254/**< @ingroup icp_qat_hw_defs 1255 * Flag to indicate that there were no Test Failures */ 1256 1257#define ICP_QAT_HW_TRNG_TEST_FAILURES_FOUND 0 1258/**< @ingroup icp_qat_hw_defs 1259 * Flag to indicate that there were Test Failures */ 1260 1261#define ICP_QAT_HW_TRNG_TEST_STATUS_VALID 1 1262/**< @ingroup icp_qat_hw_defs 1263 * Flag to indicate that there is no valid Test output */ 1264 1265#define ICP_QAT_HW_TRNG_TEST_STATUS_INVALID 0 1266/**< @ingroup icp_qat_hw_defs 1267 * Flag to indicate that the Test output is still invalid */ 1268 1269/* Private defines */ 1270#define QAT_TRNG_TEST_FAILURE_FLAG_MASK 0x1 1271/**< @ingroup icp_qat_hw_defs 1272 * Mask of one bit used to determine the TRNG Test pass/fail */ 1273 1274#define QAT_TRNG_TEST_FAILURE_FLAG_BITPOS 4 1275/**< @ingroup icp_qat_hw_defs 1276 * Flag position to indicate that the TRNG Test status is pass of fail */ 1277 1278#define QAT_TRNG_TEST_STATUS_MASK 0x1 1279/**< @ingroup icp_qat_hw_defs 1280 * Mask of one bit used to determine the TRNG Test staus */ 1281 1282#define QAT_TRNG_TEST_STATUS_BITPOS 1 1283/**< @ingroup icp_qat_hw_defs 1284 * Flag position to indicate the TRNG Test status */ 1285 1286/** 1287 ****************************************************************************** 1288 * @ingroup icp_qat_hw_defs 1289 * 1290 * @description 1291 * Extract the fail bit for the TRNG slice 1292 * 1293 * @param status TRNG status value 1294 * 1295 *****************************************************************************/ 1296 1297#define ICP_QAT_HW_TRNG_FAIL_FLAG_GET(status) \ 1298 (((status) >> QAT_TRNG_TEST_FAILURE_FLAG_BITPOS) & \ 1299 QAT_TRNG_TEST_FAILURE_FLAG_MASK) 1300 1301/** 1302 ****************************************************************************** 1303 * @ingroup icp_qat_hw_defs 1304 * 1305 * @description 1306 * Extract the status valid bit for the TRNG slice 1307 * 1308 * @param status TRNG status value 1309 * 1310 *****************************************************************************/ 1311#define ICP_QAT_HW_TRNG_STATUS_VALID_GET(status) \ 1312 (((status) >> QAT_TRNG_TEST_STATUS_BITPOS) & QAT_TRNG_TEST_STATUS_MASK) 1313 1314/** 1315 ***************************************************************************** 1316 * @ingroup icp_qat_hw_defs 1317 * TRNG entropy counters 1318 * 1319 * @description 1320 * Definition of the format of the TRNG entropy counters. Used internally 1321 * by the QAT FW. 1322 * 1323 *****************************************************************************/ 1324 1325typedef struct icp_qat_hw_trng_entropy_counts_s { 1326 uint64_t raw_ones_count; 1327 /**< Count of raw ones of entropy */ 1328 1329 uint64_t raw_zeros_count; 1330 /**< Count of raw zeros of entropy */ 1331 1332 uint64_t cond_ones_count; 1333 /**< Count of conditioned ones entropy */ 1334 1335 uint64_t cond_zeros_count; 1336 /**< Count of conditioned zeros entropy */ 1337} icp_qat_hw_trng_entropy_counts_t; 1338 1339/* Private defines */ 1340#define QAT_HW_TRNG_ENTROPY_STS_RSVD_SZ 4 1341/**< @ingroup icp_qat_hw_defs 1342 * TRNG entropy status reserved size in bytes */ 1343 1344/** 1345 ***************************************************************************** 1346 * @ingroup icp_qat_hw_defs 1347 * TRNG entropy available status. 1348 * 1349 * @description 1350 * Definition of the format of the TRNG slice entropy status available. 1351 * struct. Used internally by the QAT FW. 1352 * 1353 *****************************************************************************/ 1354typedef struct icp_qat_hw_trng_entropy_status_s { 1355 uint32_t status; 1356 /**< Entropy status in the TRNG */ 1357 1358 uint8_t reserved[QAT_HW_TRNG_ENTROPY_STS_RSVD_SZ]; 1359 /**< Reserved */ 1360} icp_qat_hw_trng_entropy_status_t; 1361 1362#define ICP_QAT_HW_TRNG_ENTROPY_AVAIL 1 1363/**< @ingroup icp_qat_hw_defs 1364 * Flag indicating that entropy data is available in the QAT TRNG slice */ 1365 1366#define ICP_QAT_HW_TRNG_ENTROPY_NOT_AVAIL 0 1367/**< @ingroup icp_qat_hw_defs 1368 * Flag indicating that no entropy data is available in the QAT TRNG slice */ 1369 1370/* Private defines */ 1371#define QAT_TRNG_ENTROPY_STATUS_MASK 1 1372/**< @ingroup icp_qat_hw_defs 1373 * Mask of one bit used to determine the TRNG Entropy status */ 1374 1375#define QAT_TRNG_ENTROPY_STATUS_BITPOS 0 1376/**< @ingroup icp_qat_hw_defs 1377 * Starting bit position for TRNG Entropy status. */ 1378 1379/** 1380 ****************************************************************************** 1381 * @ingroup icp_qat_hw_defs 1382 * 1383 * @description 1384 * Extract the entropy available status bit 1385 * 1386 * @param status TRNG status value 1387 * 1388 *****************************************************************************/ 1389#define ICP_QAT_HW_TRNG_ENTROPY_STATUS_GET(status) \ 1390 (((status) >> QAT_TRNG_ENTROPY_STATUS_BITPOS) & \ 1391 QAT_TRNG_ENTROPY_STATUS_MASK) 1392 1393/** 1394 ***************************************************************************** 1395 * @ingroup icp_qat_hw_defs 1396 * Entropy seed data 1397 * 1398 * @description 1399 * This type is used for the definition of the entropy generated by a read 1400 * of the TRNG slice 1401 * 1402 *****************************************************************************/ 1403typedef uint64_t icp_qat_hw_trng_entropy; 1404 1405/* ========================================================================= */ 1406/* COMPRESSION SLICE */ 1407/* ========================================================================= */ 1408 1409/** 1410 ***************************************************************************** 1411 * @ingroup icp_qat_hw_defs 1412 * Definition of the supported compression directions 1413 * @description 1414 * Enumeration used to define the compression directions 1415 * 1416 *****************************************************************************/ 1417 1418typedef enum { 1419 ICP_QAT_HW_COMPRESSION_DIR_COMPRESS = 0, /*!< Compression */ 1420 ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS = 1, /*!< Decompression */ 1421 ICP_QAT_HW_COMPRESSION_DIR_DELIMITER = 2 /**< Delimiter type */ 1422} icp_qat_hw_compression_direction_t; 1423 1424/** 1425 ***************************************************************************** 1426 * @ingroup icp_qat_hw_defs 1427 * Definition of the supported delayed match modes 1428 * @description 1429 * Enumeration used to define whether delayed match is enabled 1430 * 1431 *****************************************************************************/ 1432 1433typedef enum { 1434 ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DISABLED = 0, 1435 /*!< Delayed match disabled */ 1436 1437 ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_ENABLED = 1, 1438 /*!< Delayed match enabled 1439 Note: This is the only valid mode - refer to CPM1.6 SAS */ 1440 1441 ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DELIMITER = 2 1442 /**< Delimiter type */ 1443 1444} icp_qat_hw_compression_delayed_match_t; 1445 1446/** 1447 ***************************************************************************** 1448 * @ingroup icp_qat_hw_defs 1449 * Definition of the supported compression algorithms 1450 * @description 1451 * Enumeration used to define the compression algorithms 1452 * 1453 *****************************************************************************/ 1454 1455typedef enum { 1456 ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE = 0, /*!< Deflate compression */ 1457 ICP_QAT_HW_COMPRESSION_DEPRECATED = 1, /*!< Deprecated */ 1458 ICP_QAT_HW_COMPRESSION_ALGO_DELIMITER = 2 /**< Delimiter type */ 1459} icp_qat_hw_compression_algo_t; 1460 1461/** 1462 ***************************************************************************** 1463 * @ingroup icp_qat_hw_defs 1464 * Definition of the supported compression depths 1465 * @description 1466 * Enumeration used to define the compression slice depths. 1467 * 1468 *****************************************************************************/ 1469 1470typedef enum { 1471 ICP_QAT_HW_COMPRESSION_DEPTH_1 = 0, 1472 /*!< Search depth 1 (Fastest least exhaustive) */ 1473 1474 ICP_QAT_HW_COMPRESSION_DEPTH_4 = 1, 1475 /*!< Search depth 4 */ 1476 1477 ICP_QAT_HW_COMPRESSION_DEPTH_8 = 2, 1478 /*!< Search depth 8 */ 1479 1480 ICP_QAT_HW_COMPRESSION_DEPTH_16 = 3, 1481 /*!< Search depth 16 */ 1482 1483 ICP_QAT_HW_COMPRESSION_DEPTH_128 = 4, 1484 /*!< Search depth 128 (Slowest, most exhaustive) */ 1485 1486 ICP_QAT_HW_COMPRESSION_DEPTH_DELIMITER = 5 1487 /**< Delimiter type */ 1488 1489} icp_qat_hw_compression_depth_t; 1490 1491/** 1492 ***************************************************************************** 1493 * @ingroup icp_qat_hw_defs 1494 * Definition of the supported file types 1495 * @description 1496 * Enumeration used to define the compression file types. 1497 * 1498 *****************************************************************************/ 1499 1500typedef enum { 1501 ICP_QAT_HW_COMPRESSION_FILE_TYPE_0 = 0, 1502 /*!< Use Static Trees */ 1503 1504 ICP_QAT_HW_COMPRESSION_FILE_TYPE_1 = 1, 1505 /*!< Use Semi-Dynamic Trees at offset 0 */ 1506 1507 ICP_QAT_HW_COMPRESSION_FILE_TYPE_2 = 2, 1508 /*!< Use Semi-Dynamic Trees at offset 320 */ 1509 1510 ICP_QAT_HW_COMPRESSION_FILE_TYPE_3 = 3, 1511 /*!< Use Semi-Dynamic Trees at offset 640 */ 1512 1513 ICP_QAT_HW_COMPRESSION_FILE_TYPE_4 = 4, 1514 /*!< Use Semi-Dynamic Trees at offset 960 */ 1515 1516 ICP_QAT_HW_COMPRESSION_FILE_TYPE_DELIMITER = 5 1517 /**< Delimiter type */ 1518 1519} icp_qat_hw_compression_file_type_t; 1520 1521typedef enum { 1522 BNP_SKIP_MODE_DISABLED = 0, 1523 BNP_SKIP_MODE_AT_START = 1, 1524 BNP_SKIP_MODE_AT_END = 2, 1525 BNP_SKIP_MODE_STRIDE = 3 1526} icp_qat_bnp_skip_mode_t; 1527 1528/** 1529 ***************************************************************************** 1530 * @ingroup icp_qat_hw_defs 1531 * Compression Configuration Struct 1532 * 1533 * @description 1534 * Configuration data used for setting up the QAT Compression Slice 1535 * 1536 *****************************************************************************/ 1537 1538typedef struct icp_qat_hw_compression_config_s { 1539 uint32_t lower_val; 1540 /**< Compression slice configuration lower LW */ 1541 1542 uint32_t upper_val; 1543 /**< Compression slice configuration upper LW */ 1544} icp_qat_hw_compression_config_t; 1545 1546/* Private defines */ 1547#define QAT_COMPRESSION_DIR_BITPOS 4 1548/**< @ingroup icp_qat_hw_defs 1549 * Define for the compression direction bit position */ 1550 1551#define QAT_COMPRESSION_DIR_MASK 0x7 1552/**< @ingroup icp_qat_hw_defs 1553 * Define for the compression direction mask (three bits) */ 1554 1555#define QAT_COMPRESSION_DELAYED_MATCH_BITPOS 16 1556/**< @ingroup icp_qat_hw_defs 1557 * Define for the compression delayed match bit position */ 1558 1559#define QAT_COMPRESSION_DELAYED_MATCH_MASK 0x1 1560/**< @ingroup icp_qat_hw_defs 1561 * Define for the delayed match mask (one bit) */ 1562 1563#define QAT_COMPRESSION_ALGO_BITPOS 31 1564/**< @ingroup icp_qat_hw_defs 1565 * Define for the compression algorithm bit position */ 1566 1567#define QAT_COMPRESSION_ALGO_MASK 0x1 1568/**< @ingroup icp_qat_hw_defs 1569 * Define for the compression algorithm mask (one bit) */ 1570 1571#define QAT_COMPRESSION_DEPTH_BITPOS 28 1572/**< @ingroup icp_qat_hw_defs 1573 * Define for the compression depth bit position */ 1574 1575#define QAT_COMPRESSION_DEPTH_MASK 0x7 1576/**< @ingroup icp_qat_hw_defs 1577 * Define for the compression depth mask (three bits) */ 1578 1579#define QAT_COMPRESSION_FILE_TYPE_BITPOS 24 1580/**< @ingroup icp_qat_hw_defs 1581 * Define for the compression file type bit position */ 1582 1583#define QAT_COMPRESSION_FILE_TYPE_MASK 0xF 1584/**< @ingroup icp_qat_hw_defs 1585 * Define for the compression file type mask (four bits) */ 1586 1587/** 1588 ****************************************************************************** 1589 * @ingroup icp_qat_hw_defs 1590 * 1591 * @description 1592 * Build the compression slice configuration field 1593 * 1594 * @param dir Compression Direction to use, compress or decompress 1595 * @param delayed Specify if delayed match should be enabled 1596 * @param algo Compression algorithm to use 1597 * @param depth Compression search depth to use 1598 * @param filetype Compression file type to use, static or semi dynamic trees 1599 * 1600 *****************************************************************************/ 1601#define ICP_QAT_HW_COMPRESSION_CONFIG_BUILD( \ 1602 dir, delayed, algo, depth, filetype) \ 1603 ((((dir)&QAT_COMPRESSION_DIR_MASK) << QAT_COMPRESSION_DIR_BITPOS) | \ 1604 (((delayed)&QAT_COMPRESSION_DELAYED_MATCH_MASK) \ 1605 << QAT_COMPRESSION_DELAYED_MATCH_BITPOS) | \ 1606 (((algo)&QAT_COMPRESSION_ALGO_MASK) << QAT_COMPRESSION_ALGO_BITPOS) | \ 1607 (((depth)&QAT_COMPRESSION_DEPTH_MASK) \ 1608 << QAT_COMPRESSION_DEPTH_BITPOS) | \ 1609 (((filetype)&QAT_COMPRESSION_FILE_TYPE_MASK) \ 1610 << QAT_COMPRESSION_FILE_TYPE_BITPOS)) 1611 1612/* ========================================================================= */ 1613/* TRANSLATOR SLICE */ 1614/* ========================================================================= */ 1615 1616/**< Translator slice configuration is set internally by the firmware */ 1617 1618#endif /* _ICP_QAT_HW_H_ */ 1619