1/******************************************************************************* 2*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3* 4*Redistribution and use in source and binary forms, with or without modification, are permitted provided 5*that the following conditions are met: 6*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7*following disclaimer. 8*2. Redistributions in binary form must reproduce the above copyright notice, 9*this list of conditions and the following disclaimer in the documentation and/or other materials provided 10*with the distribution. 11* 12*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20 21********************************************************************************/ 22/*******************************************************************************/ 23/*! \file saint.c 24 * \brief The file implements the functions to handle/enable/disable interrupt 25 * 26 */ 27/*******************************************************************************/ 28#include <sys/cdefs.h> 29#include <dev/pms/config.h> 30 31#include <dev/pms/RefTisa/sallsdk/spc/saglobal.h> 32#define SA_CLEAR_ODCR_IN_INTERRUPT 33 34//#define SA_TEST_FW_SPURIOUS_INT 35 36#ifdef SA_TEST_FW_SPURIOUS_INT 37bit32 gOurIntCount = 0; 38bit32 gSpuriousIntCount = 0; 39bit32 gSpuriousInt[64]= 40{ 410,0,0,0,0,0,0,0, 420,0,0,0,0,0,0,0, 430,0,0,0,0,0,0,0, 440,0,0,0,0,0,0,0, 450,0,0,0,0,0,0,0, 460,0,0,0,0,0,0,0, 470,0,0,0,0,0,0,0, 480,0,0,0,0,0,0,0 49}; 50bit32 gSpuriousInt1[64]= 51{ 520,0,0,0,0,0,0,0, 530,0,0,0,0,0,0,0, 540,0,0,0,0,0,0,0, 550,0,0,0,0,0,0,0, 560,0,0,0,0,0,0,0, 570,0,0,0,0,0,0,0, 580,0,0,0,0,0,0,0, 590,0,0,0,0,0,0,0 60}; 61#endif /* SA_TEST_FW_SPURIOUS_INT */ 62 63#ifdef SA_ENABLE_TRACE_FUNCTIONS 64#ifdef siTraceFileID 65#undef siTraceFileID 66#endif /* siTraceFileID */ 67#define siTraceFileID 'G' 68#endif /* SA_ENABLE_TRACE_FUNCTIONS */ 69 70LOCAL FORCEINLINE bit32 siProcessOBMsg( 71 agsaRoot_t *agRoot, 72 bit32 count, 73 bit32 queueNum 74 ); 75 76LOCAL bit32 siFatalInterruptHandler( 77 agsaRoot_t *agRoot, 78 bit32 interruptVectorIndex 79 ) 80{ 81 agsaLLRoot_t *saRoot = agNULL; 82 agsaFatalErrorInfo_t fatal_error; 83 bit32 value; 84 bit32 ret = AGSA_RC_FAILURE; 85 bit32 Sendfatal = agTRUE; 86 87 SA_ASSERT((agNULL != agRoot), ""); 88 if (agRoot == agNULL) 89 { 90 SA_DBG1(("siFatalInterruptHandler: agRoot == agNULL\n")); 91 return AGSA_RC_FAILURE; 92 } 93 saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 94 SA_ASSERT((agNULL != saRoot), ""); 95 if (saRoot == agNULL) 96 { 97 SA_DBG1(("siFatalInterruptHandler: saRoot == agNULL\n")); 98 return AGSA_RC_FAILURE; 99 } 100 101 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); 102 if (saRoot->ResetFailed) 103 { 104 SA_DBG1(("siFatalInterruptHandler: ResetFailed\n")); 105 ossaDisableInterrupts(agRoot, interruptVectorIndex); 106 return AGSA_RC_FAILURE; 107 } 108 109 if(SCRATCH_PAD1_V_ERROR_STATE( value ) ) 110 { 111 si_memset(&fatal_error, 0, sizeof(agsaFatalErrorInfo_t)); 112 /* read detail fatal errors */ 113 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0, MSGU_SCRATCH_PAD_0); 114 fatal_error.errorInfo0 = value; 115 SA_DBG1(("siFatalInterruptHandler: ScratchPad0 AAP error 0x%x code 0x%x\n",SCRATCH_PAD1_V_ERROR_STATE( value ), value)); 116 117 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); 118 fatal_error.errorInfo1 = value; 119 /* AAP error state */ 120 SA_DBG1(("siFatalInterruptHandler: AAP error state and error code 0x%x\n", value)); 121 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2); 122 fatal_error.errorInfo2 = value; 123 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2 0x%08x\n", fatal_error.errorInfo2 )); 124 125#if defined(SALLSDK_DEBUG) 126 if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_ILA_ERR) 127 { 128 SA_DBG1(("siFatalInterruptHandler:SCRATCH_PAD1_V_ERROR_STATE SCRATCH_PAD2_FW_ILA_ERR 0x%08x\n", SCRATCH_PAD2_FW_ILA_ERR)); 129 } 130 if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_FLM_ERR) 131 { 132 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_FLM_ERR 0x%08x\n", SCRATCH_PAD2_FW_FLM_ERR)); 133 } 134 if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_FW_ASRT_ERR) 135 { 136 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_FW_ASRT_ERR 0x%08x\n", SCRATCH_PAD2_FW_FW_ASRT_ERR)); 137 } 138 if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_WDG_ERR) 139 { 140 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_HW_WDG_ERR 0x%08x\n", SCRATCH_PAD2_FW_HW_WDG_ERR)); 141 } 142 if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_GEN_EXCEPTION_ERR) 143 { 144 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_GEN_EXCEPTION_ERR 0x%08x\n", SCRATCH_PAD2_FW_GEN_EXCEPTION_ERR)); 145 } 146 if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_UNDTMN_ERR) 147 { 148 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_UNDTMN_ERR 0x%08x\n",SCRATCH_PAD2_FW_UNDTMN_ERR )); 149 } 150 if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_FATAL_ERR) 151 { 152 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_HW_FATAL_ERR 0x%08x\n", SCRATCH_PAD2_FW_HW_FATAL_ERR)); 153 } 154 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_PCS_ERR ) 155 { 156 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_PCS_ERR 0x%08x\n", value)); 157 } 158 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_GSM_ERR ) 159 { 160 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_GSM_ERR 0x%08x\n", value)); 161 } 162 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP0_ERR ) 163 { 164 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP0_ERR 0x%08x\n", value)); 165 } 166 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) ==SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP1_ERR ) 167 { 168 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP1_ERR 0x%08x\n", value)); 169 } 170 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP2_ERR ) 171 { 172 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP2_ERR 0x%08x\n", value)); 173 } 174 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_ERAAE_ERR ) 175 { 176 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_ERAAE_ERR 0x%08x\n", value)); 177 } 178 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_SDS_ERR ) 179 { 180 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_SDS_ERR 0x%08x\n", value)); 181 } 182 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_CORE_ERR ) 183 { 184 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_CORE_ERR 0x%08x\n", value)); 185 } 186 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_AL_ERR ) 187 { 188 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_AL_ERR 0x%08x\n", value)); 189 } 190 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_MSGU_ERR ) 191 { 192 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_MSGU_ERR 0x%08x\n", value)); 193 } 194 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_SPBC_ERR ) 195 { 196 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_SPBC_ERR 0x%08x\n", value)); 197 } 198 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_BDMA_ERR ) 199 { 200 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_BDMA_ERR 0x%08x\n", value)); 201 } 202 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSL2B_ERR) 203 { 204 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSL2B_ERR 0x%08x\n", value)); 205 } 206 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSDC_ERR ) 207 { 208 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSDC_ERR 0x%08x\n", value)); 209 } 210 if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_UNDETERMINED_ERROR_OCCURRED ) 211 { 212 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_UNDETERMINED_ERROR_OCCURRED 0x%08x\n", value)); 213 } 214#endif /* SALLSDK_DEBUG */ 215 216 if( fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_NON_FATAL_ERR && 217 !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_ILA_ERR) && 218 !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_FLM_ERR) && 219 !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_FW_ASRT_ERR) && 220 !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_WDG_ERR) && 221 !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_GEN_EXCEPTION_ERR) && 222 !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_UNDTMN_ERR) && 223 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_PCS_ERR) && 224 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_GSM_ERR) && 225 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP0_ERR) && 226 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP2_ERR) && 227 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_ERAAE_ERR) && 228 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_SDS_ERR) && 229 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_CORE_ERR) && 230 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_AL_ERR) && 231 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_MSGU_ERR) && 232 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_SPBC_ERR) && 233 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_BDMA_ERR) && 234 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSL2B_ERR) && 235 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSDC_ERR) && 236 !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_UNDETERMINED_ERROR_OCCURRED) && 237 !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_FATAL_ERR) ) 238 { 239 SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_HW_NON_FATAL_ERR 0x%08x\n", value)); 240 Sendfatal = agFALSE; 241 } 242 243 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3, MSGU_SCRATCH_PAD_3); 244 SA_DBG1(("siFatalInterruptHandler: ScratchPad3 IOP error code 0x%08x\n", value)); 245 fatal_error.errorInfo3 = value; 246 247 if (agNULL != saRoot) 248 { 249 fatal_error.regDumpBusBaseNum0 = saRoot->mainConfigTable.regDumpPCIBAR; 250 fatal_error.regDumpOffset0 = saRoot->mainConfigTable.FatalErrorDumpOffset0; 251 fatal_error.regDumpLen0 = saRoot->mainConfigTable.FatalErrorDumpLength0; 252 fatal_error.regDumpBusBaseNum1 = saRoot->mainConfigTable.regDumpPCIBAR; 253 fatal_error.regDumpOffset1 = saRoot->mainConfigTable.FatalErrorDumpOffset1; 254 fatal_error.regDumpLen1 = saRoot->mainConfigTable.FatalErrorDumpLength1; 255 } 256 else 257 { 258 fatal_error.regDumpBusBaseNum0 = 0; 259 fatal_error.regDumpOffset0 = 0; 260 fatal_error.regDumpLen0 = 0; 261 fatal_error.regDumpBusBaseNum1 = 0; 262 fatal_error.regDumpOffset1 = 0; 263 fatal_error.regDumpLen1 = 0; 264 } 265 /* Call Back with error */ 266 SA_DBG1(("siFatalInterruptHandler: Sendfatal %x HostR0 0x%x\n",Sendfatal ,ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_Rsvd_0_Register ) )); 267 SA_DBG1(("siFatalInterruptHandler: ScratchPad2 0x%x ScratchPad3 0x%x\n", 268 ossaHwRegReadExt(agRoot, PCIBAR0,V_Host_Scratchpad_2_Register), 269 ossaHwRegReadExt(agRoot, PCIBAR0,V_Host_Scratchpad_3_Register) )); 270 271 ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_MALFUNCTION, Sendfatal, (void *)&fatal_error, agNULL); 272 ret = AGSA_RC_SUCCESS; 273 } 274 else 275 { 276 bit32 host_reg0; 277 host_reg0 = ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_Rsvd_0_Register ); 278 if( host_reg0 == 0x2) 279 { 280 Sendfatal = agFALSE; 281 282 SA_DBG1(("siFatalInterruptHandler: Non fatal ScratchPad1 0x%x HostR0 0x%x\n", value,host_reg0)); 283 SA_DBG1(("siFatalInterruptHandler: ScratchPad0 0x%x ScratchPad1 0x%x\n", 284 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register), 285 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_1_Register) )); 286 SA_DBG1(("siFatalInterruptHandler: ScratchPad2 0x%x ScratchPad3 0x%x\n", 287 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_2_Register), 288 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_3_Register) )); 289 290 ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_MALFUNCTION, Sendfatal, (void *)&fatal_error, agNULL); 291 ret = AGSA_RC_SUCCESS; 292 } 293 else if( host_reg0 == HDA_AES_DIF_FUNC) 294 { 295 SA_DBG1(("siFatalInterruptHandler: HDA_AES_DIF_FUNC 0x%x\n", 296 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_Rsvd_0_Register))); 297 Sendfatal = agFALSE; 298 ret = AGSA_RC_SUCCESS; 299 } 300 else 301 { 302 SA_DBG1(("siFatalInterruptHandler: No error detected ScratchPad1 0x%x HostR0 0x%x\n", value,host_reg0)); 303 SA_DBG1(("siFatalInterruptHandler: ScratchPad0 0x%x ScratchPad1 0x%x\n", 304 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register), 305 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_1_Register) )); 306 SA_DBG1(("siFatalInterruptHandler: ScratchPad2 0x%x ScratchPad3 0x%x\n", 307 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_2_Register), 308 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_3_Register) )); 309 310 SA_DBG1(("siFatalInterruptHandler: Doorbell_Set %08X U %08X\n", 311 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_Register), 312 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_RegisterU))); 313 SA_DBG1(("siFatalInterruptHandler: Doorbell_Mask %08X U %08X\n", 314 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register ), 315 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU ))); 316 317 ret = AGSA_RC_FAILURE; 318 } 319 } 320 return ret; 321 322} 323 324GLOBAL bit32 saFatalInterruptHandler( 325 agsaRoot_t *agRoot, 326 bit32 interruptVectorIndex 327 ) 328{ 329 agsaLLRoot_t *saRoot = agNULL; 330 bit32 ret = AGSA_RC_FAILURE; 331 332 /* sanity check */ 333 SA_ASSERT((agNULL != agRoot), ""); 334 saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 335 SA_ASSERT((agNULL != saRoot), ""); 336 337 if (saRoot->ResetFailed) 338 { 339 SA_DBG1(("saFatalInterruptHandler: ResetFailed\n")); 340 ossaDisableInterrupts(agRoot, interruptVectorIndex); 341 return AGSA_RC_FAILURE; 342 } 343 if (saRoot->swConfig.fatalErrorInterruptEnable != 1) 344 { 345 SA_DBG1(("saFatalInterruptHandler: fatalErrorInterrtupt is NOT enabled\n")); 346 ossaDisableInterrupts(agRoot, interruptVectorIndex); 347 return AGSA_RC_FAILURE; 348 } 349 350 if (saRoot->swConfig.fatalErrorInterruptVector != interruptVectorIndex) 351 { 352 SA_DBG1(("saFatalInterruptHandler: interruptVectorIndex does not match 0x%x 0x%x\n", 353 saRoot->swConfig.fatalErrorInterruptVector, interruptVectorIndex)); 354 SA_DBG1(("saFatalInterruptHandler: ScratchPad0 0x%x ScratchPad1 0x%x\n", 355 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register), 356 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_1_Register) )); 357 SA_DBG1(("saFatalInterruptHandler: ScratchPad2 0x%x ScratchPad3 0x%x\n", 358 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_2_Register), 359 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_3_Register) )); 360 ossaDisableInterrupts(agRoot, interruptVectorIndex); 361 return AGSA_RC_FAILURE; 362 } 363 364 ret = siFatalInterruptHandler(agRoot,interruptVectorIndex); 365 366 367 ossaDisableInterrupts(agRoot, interruptVectorIndex); 368 369 return ret; 370} 371/******************************************************************************/ 372/*! \brief Function to process the interrupts 373 * 374 * The saInterruptHandler() function is called after an interrupts has 375 * been received 376 * This function disables interrupts 377 * 378 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 379 * instance of SAS/SATA hardware 380 * \param interruptVectorIndex message that caused MSI message 381 * 382 * \return TRUE if we caused interrupt 383 * 384 */ 385/*******************************************************************************/ 386FORCEINLINE bit32 387saInterruptHandler( 388 agsaRoot_t *agRoot, 389 bit32 interruptVectorIndex 390 ) 391{ 392 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 393 bit32 ToBeProcessedCount = 0; 394 bit32 our_int = 0; 395#ifdef SA_TEST_FW_SPURIOUS_INT 396 bit8 i; 397#endif/* SA_TEST_FW_SPURIOUS_INT */ 398 399 if( agNULL == saRoot ) 400 { 401 /* Can be called before initialize is completed in a shared 402 interrupt environment like windows 2003 403 */ 404 return(ToBeProcessedCount); 405 } 406 407 if( (our_int = saRoot->OurInterrupt(agRoot,interruptVectorIndex)) == FALSE ) 408 { 409#ifdef SA_TEST_FW_SPURIOUS_INT 410 gSpuriousIntCount++; 411 smTrace(hpDBG_REGISTERS,"S1",gSpuriousIntCount); 412 /* TP:S1 gSpuriousIntCount */ 413#endif /* SA_TEST_FW_SPURIOUS_INT */ 414 return(ToBeProcessedCount); 415 } 416 417 smTraceFuncEnter(hpDBG_TICK_INT, "5q"); 418 419 smTrace(hpDBG_TICK_INT,"VI",interruptVectorIndex); 420 /* TP:Vi interrupt VectorIndex */ 421 422 if ( agFALSE == saRoot->sysIntsActive ) 423 { 424 // SA_ASSERT(0, "saInterruptHandler sysIntsActive not set"); 425 426#ifdef SA_PRINTOUT_IN_WINDBG 427#ifndef DBG 428 DbgPrint("saInterruptHandler: sysIntsActive not set Doorbell_Mask_Set %08X U %08X\n", 429 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register), 430 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU) ); 431#endif /* DBG */ 432#endif /* SA_PRINTOUT_IN_WINDBG */ 433 434 435 SA_DBG1(("saInterruptHandler: Doorbell_Mask_Set %08X U %08X\n", 436 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register), 437 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU))); 438 ossaDisableInterrupts(agRoot, interruptVectorIndex); 439 return(ToBeProcessedCount); 440 441 } 442 443 /* Allow replacement of disable interrupt */ 444 ossaDisableInterrupts(agRoot, interruptVectorIndex); 445 446 447#ifdef SA_TEST_FW_SPURIOUS_INT 448 449 /* count for my interrupt */ 450 gOurIntCount++; 451 452 smTrace(hpDBG_REGISTERS,"S4",gOurIntCount); 453 /* TP:S4 gOurIntCount */ 454#endif /* SA_TEST_FW_SPURIOUS_INT */ 455 456 smTraceFuncExit(hpDBG_TICK_INT, 'a', "5q"); 457 return(TRUE); 458 459} 460 461/******************************************************************************/ 462/*! \brief Function to disable MSIX interrupts 463 * 464 * siDisableMSIXInterrupts disables interrupts 465 * called thru macro ossaDisableInterrupts 466 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 467 * instance of SAS/SATA hardware 468 * \param interruptVectorIndex - vector index for message 469 * 470 */ 471/*******************************************************************************/ 472GLOBAL void siDisableMSIXInterrupts( 473 agsaRoot_t *agRoot, 474 bit32 interruptVectorIndex 475 ) 476{ 477 bit32 msi_index; 478#ifndef SA_CLEAR_ODCR_IN_INTERRUPT 479 bit32 value; 480#endif /* SA_CLEAR_ODCR_IN_INTERRUPT */ 481 msi_index = interruptVectorIndex * MSIX_TABLE_ELEMENT_SIZE; 482 msi_index += MSIX_TABLE_BASE; 483 ossaHwRegWrite(agRoot,msi_index , MSIX_INTERRUPT_DISABLE); 484 ossaHwRegRead(agRoot, msi_index); /* Dummy read */ 485#ifndef SA_CLEAR_ODCR_IN_INTERRUPT 486 value = (1 << interruptVectorIndex); 487 ossaHwRegWrite(agRoot, MSGU_ODCR, value); 488#endif /* SA_CLEAR_ODCR_IN_INTERRUPT */ 489} 490 491/******************************************************************************/ 492/*! \brief Function to disable MSIX V interrupts 493 * 494 * siDisableMSIXInterrupts disables interrupts 495 * called thru macro ossaDisableInterrupts 496 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 497 * instance of SAS/SATA hardware 498 * \param interruptVectorIndex - vector index for message 499 * 500 */ 501/*******************************************************************************/ 502void siDisableMSIX_V_Interrupts( 503 agsaRoot_t *agRoot, 504 bit32 interruptVectorIndex 505 ) 506{ 507 bit64 mask; 508 agsabit32bit64 u64; 509 mask =( (bit64)1 << interruptVectorIndex); 510 u64.B64 = mask; 511 if(smIS64bInt(agRoot)) 512 { 513 SA_DBG4(("siDisableMSIX_V_Interrupts: VI %d U 0x%08X L 0x%08X\n",interruptVectorIndex,u64.S32[1],u64.S32[0])); 514 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_RegisterU,u64.S32[1]); 515 } 516 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_Register, u64.S32[0]); 517 518} 519/******************************************************************************/ 520/*! \brief Function to disable MSI interrupts 521 * 522 * siDisableMSIInterrupts disables interrupts 523 * called thru macro ossaDisableInterrupts 524 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 525 * instance of SAS/SATA hardware 526 * \param interruptVectorIndex - vector index for message 527 * 528 */ 529/*******************************************************************************/ 530GLOBAL void siDisableMSIInterrupts( 531 agsaRoot_t *agRoot, 532 bit32 interruptVectorIndex 533 ) 534{ 535 bit32 ODMRValue; 536 bit32 mask; 537 mask = 1 << interruptVectorIndex; 538 539 /*Must be protected for interuption */ 540 ODMRValue = ossaHwRegRead(agRoot, MSGU_ODMR); 541 ODMRValue |= mask; 542 543 ossaHwRegWrite(agRoot, MSGU_ODMR, ODMRValue); 544 ossaHwRegWrite(agRoot, MSGU_ODCR, mask); 545} 546 547/******************************************************************************/ 548/*! \brief Function to disable MSI V interrupts 549 * 550 * siDisableMSIInterrupts disables interrupts 551 * called thru macro ossaDisableInterrupts 552 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 553 * instance of SAS/SATA hardware 554 * \param interruptVectorIndex - vector index for message 555 * 556 */ 557/*******************************************************************************/ 558GLOBAL void siDisableMSI_V_Interrupts( 559 agsaRoot_t *agRoot, 560 bit32 interruptVectorIndex 561 ) 562{ 563 SA_ASSERT(0, "Should not be called"); 564 SA_DBG4(("siDisableMSI_V_Interrupts:\n")); 565} 566 567/******************************************************************************/ 568/*! \brief Function to process Legacy interrupts 569 * 570 * siDisableLegacyInterrupts disables interrupts 571 * called thru macro ossaDisableInterrupts 572 * 573 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 574 * instance of SAS/SATA hardware 575 * \param interruptVectorIndex not used in legacy case 576 * 577 */ 578/*******************************************************************************/ 579GLOBAL void siDisableLegacyInterrupts( 580 agsaRoot_t *agRoot, 581 bit32 interruptVectorIndex 582 ) 583{ 584 ossaHwRegWrite(agRoot, MSGU_ODMR, ODMR_MASK_ALL); 585#ifndef SA_CLEAR_ODCR_IN_INTERRUPT 586 ossaHwRegWrite(agRoot, MSGU_ODCR, ODCR_CLEAR_ALL); 587#endif /* SA_CLEAR_ODCR_IN_INTERRUPT */ 588} 589 590/******************************************************************************/ 591/*! \brief Function to process Legacy V interrupts 592 * 593 * siDisableLegacyInterrupts disables interrupts 594 * called thru macro ossaDisableInterrupts 595 * 596 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 597 * instance of SAS/SATA hardware 598 * \param interruptVectorIndex not used in legacy case 599 * 600 */ 601/*******************************************************************************/ 602GLOBAL void siDisableLegacy_V_Interrupts( 603 agsaRoot_t *agRoot, 604 bit32 interruptVectorIndex 605 ) 606{ 607 608 bit64 mask; 609 agsabit32bit64 u64; 610 mask =( (bit64)1 << interruptVectorIndex); 611 u64.B64 = mask; 612 613 SA_DBG4(("siDisableLegacy_V_Interrupts:IN MSGU_READ_ODR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODR, V_Outbound_Doorbell_Set_Register))); 614 SA_DBG4(("siDisableLegacy_V_Interrupts:IN MSGU_READ_ODMR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODMR, V_Outbound_Doorbell_Mask_Set_Register ))); 615 if(smIS64bInt(agRoot)) 616 { 617 SA_DBG4(("siDisableLegacy_V_Interrupts: VI %d U 0x%08X L 0x%08X\n",interruptVectorIndex,u64.S32[1],u64.S32[0])); 618 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_Register,u64.S32[1] ); 619 } 620 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_RegisterU,u64.S32[0]); 621 622} 623/******************************************************************************/ 624/*! \brief Function to process MSIX interrupts 625 * 626 * siOurMSIXInterrupt checks if we generated interrupt 627 * called thru function pointer saRoot->OurInterrupt 628 * 629 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 630 * instance of SAS/SATA hardware 631 * \return always true 632 */ 633/*******************************************************************************/ 634GLOBAL bit32 siOurMSIXInterrupt( 635 agsaRoot_t *agRoot, 636 bit32 interruptVectorIndex 637 ) 638{ 639 return(TRUE); 640} 641 642/******************************************************************************/ 643/*! \brief Function to process MSIX V interrupts 644 * 645 * siOurMSIXInterrupt checks if we generated interrupt 646 * called thru function pointer saRoot->OurInterrupt 647 * 648 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 649 * instance of SAS/SATA hardware 650 * \return always true 651 */ 652/*******************************************************************************/ 653GLOBAL bit32 siOurMSIX_V_Interrupt( 654 agsaRoot_t *agRoot, 655 bit32 interruptVectorIndex 656 ) 657{ 658 return(TRUE); 659} 660/******************************************************************************/ 661/*! \brief Function to process MSI interrupts 662 * 663 * siOurMSIInterrupt checks if we generated interrupt 664 * called thru function pointer saRoot->OurInterrupt 665 * 666 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 667 * instance of SAS/SATA hardware 668 * \return always true 669 */ 670/*******************************************************************************/ 671bit32 siOurMSIInterrupt( 672 agsaRoot_t *agRoot, 673 bit32 interruptVectorIndex 674 ) 675{ 676 return(TRUE); 677} 678 679/******************************************************************************/ 680/*! \brief Function to process MSI V interrupts 681 * 682 * siOurMSIInterrupt checks if we generated interrupt 683 * called thru function pointer saRoot->OurInterrupt 684 * 685 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 686 * instance of SAS/SATA hardware 687 * \return always true 688 */ 689/*******************************************************************************/ 690bit32 siOurMSI_V_Interrupt( 691 agsaRoot_t *agRoot, 692 bit32 interruptVectorIndex 693 ) 694{ 695 SA_DBG4((":siOurMSI_V_Interrupt\n")); 696 return(TRUE); 697} 698 699/******************************************************************************/ 700/*! \brief Function to process Legacy interrupts 701 * 702 * siOurLegacyInterrupt checks if we generated interrupt 703 * called thru function pointer saRoot->OurInterrupt 704 * 705 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 706 * instance of SAS/SATA hardware 707 * \return true if we claim interrupt 708 */ 709/*******************************************************************************/ 710bit32 siOurLegacyInterrupt( 711 agsaRoot_t *agRoot, 712 bit32 interruptVectorIndex 713 ) 714{ 715 bit32 Int_masked; 716 bit32 Int_active; 717 Int_masked = MSGU_READ_ODMR; 718 Int_active = MSGU_READ_ODR; 719 720 if(Int_masked & 1 ) 721 { 722 return(FALSE); 723 } 724 if(Int_active & 1 ) 725 { 726 727 return(TRUE); 728 } 729 return(FALSE); 730} 731 732/******************************************************************************/ 733/*! \brief Function to process Legacy V interrupts 734 * 735 * siOurLegacyInterrupt checks if we generated interrupt 736 * called thru function pointer saRoot->OurInterrupt 737 * 738 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 739 * instance of SAS/SATA hardware 740 * \return true if we claim interrupt 741 */ 742/*******************************************************************************/ 743bit32 siOurLegacy_V_Interrupt( 744 agsaRoot_t *agRoot, 745 bit32 interruptVectorIndex 746 ) 747{ 748 bit32 Int_active; 749 Int_active = siHalRegReadExt(agRoot, GEN_MSGU_ODR, V_Outbound_Doorbell_Set_Register ); 750 751 return(Int_active ? TRUE : FALSE); 752} 753 754 755/******************************************************************************/ 756/*! \brief Function to process the cause of interrupt 757 * 758 * The saDelayedInterruptHandler() function is called after an interrupt messages has 759 * been received it may be called by a deferred procedure call 760 * 761 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 762 * instance of SAS/SATA hardware 763 * \param interruptVectorIndex - vector index for message 764 * \param count Number of completion queue entries to consume 765 * 766 * \return number of messages processed 767 * 768 */ 769/*******************************************************************************/ 770FORCEINLINE bit32 771saDelayedInterruptHandler( 772 agsaRoot_t *agRoot, 773 bit32 interruptVectorIndex, 774 bit32 count 775 ) 776{ 777 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 778 bit32 processedMsgCount = 0; 779 bit32 pad1 = 0; 780 bit32 host_reg0 = 0; 781#if defined(SALLSDK_DEBUG) 782 bit32 host_reg1 = 0; 783#endif 784 bit8 i = 0; 785 786 OSSA_OUT_ENTER(agRoot); 787 788 smTraceFuncEnter(hpDBG_VERY_LOUD,"5p"); 789 790 smTrace(hpDBG_VERY_LOUD,"Vd",interruptVectorIndex); 791 /* TP:Vd delayed VectorIndex */ 792 smTrace(hpDBG_VERY_LOUD,"Vc",count); 793 /* TP:Vc IOMB count*/ 794 795 if( saRoot->swConfig.fatalErrorInterruptEnable && 796 saRoot->swConfig.fatalErrorInterruptVector == interruptVectorIndex ) 797 { 798 pad1 = siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); 799 host_reg0 = ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_Rsvd_0_Register ); 800 801 802 if(saRoot->swConfig.hostDirectAccessMode & 2 ) 803 { 804 if( host_reg0 == HDA_AES_DIF_FUNC) 805 { 806 host_reg0 = 0; 807 } 808 } 809 810 811#if defined(SALLSDK_DEBUG) 812 host_reg1 = ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_Rsvd_1_Register ); 813#endif 814 if( (SCRATCH_PAD1_V_ERROR_STATE( pad1 ) != 0 ) && host_reg0 ) 815 { 816 817 SA_DBG1(("saDelayedInterruptHandler: vi %d Error %08X\n",interruptVectorIndex, SCRATCH_PAD1_V_ERROR_STATE( pad1 ))); 818 SA_DBG1(("saDelayedInterruptHandler: Sp 1 %08X Hr0 %08X Hr1 %08X\n",pad1,host_reg0,host_reg1 )); 819 SA_DBG1(("saDelayedInterruptHandler: SCRATCH_PAD1_V_ERROR_STATE %08X\n", SCRATCH_PAD1_V_ERROR_STATE( pad1 ))); 820 SA_DBG1(("saDelayedInterruptHandler: SCRATCH_PAD1_V_ILA_ERROR_STATE %08X\n", SCRATCH_PAD1_V_ILA_ERROR_STATE( pad1 ))); 821 SA_DBG1(("saDelayedInterruptHandler: SCRATCH_PAD1_V_RAAE_ERROR_STATE %08X\n", SCRATCH_PAD1_V_RAAE_ERROR_STATE( pad1 ))); 822 SA_DBG1(("saDelayedInterruptHandler: SCRATCH_PAD1_V_IOP0_ERROR_STATE %08X\n", SCRATCH_PAD1_V_IOP0_ERROR_STATE( pad1 ))); 823 SA_DBG1(("saDelayedInterruptHandler: SCRATCH_PAD1_V_IOP1_ERROR_STATE %08X\n", SCRATCH_PAD1_V_IOP1_ERROR_STATE( pad1 ))); 824 825 siFatalInterruptHandler( agRoot, interruptVectorIndex ); 826 ossaDisableInterrupts(agRoot, interruptVectorIndex); 827 828 } 829 else 830 { 831 SA_DBG2(("saDelayedInterruptHandler: Fatal Check VI %d SCRATCH_PAD1 %08X host_reg0 %08X host_reg1 %08X\n",interruptVectorIndex, pad1,host_reg0,host_reg1)); 832 SA_DBG2(("saDelayedInterruptHandler: ScratchPad0 0x%x ScratchPad1 0x%x\n", 833 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register), 834 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_1_Register) )); 835 SA_DBG2(("saDelayedInterruptHandler: ScratchPad2 0x%x ScratchPad3 0x%x\n", 836 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_2_Register), 837 ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_3_Register) )); 838 839 SA_DBG2(("saDelayedInterruptHandler: Doorbell_Set %08X U %08X\n", 840 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_Register), 841 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_RegisterU))); 842 SA_DBG2(("saDelayedInterruptHandler: Doorbell_Mask %08X U %08X\n", 843 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register ), 844 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU ))); 845 } 846 847 } 848 849 850#ifdef SA_LNX_PERF_MODE 851 return siProcessOBMsg(agRoot, count, interruptVectorIndex); 852#endif 853 854 /* check all the configuration outbound queues within a vector bitmap */ 855 SA_ASSERT((saRoot->QueueConfig.numOutboundQueues < 65), "numOutboundQueue"); 856 857 for ( i = 0; i < saRoot->QueueConfig.numOutboundQueues; i++ ) 858 { 859 /* process IOMB in the outbound queue 0 to 31 if bit set in the vector bitmap */ 860 if (i < OQ_NUM_32) 861 { 862 if (saRoot->interruptVecIndexBitMap[interruptVectorIndex] & (1 << i)) 863 { 864 processedMsgCount += siProcessOBMsg(agRoot, count, i); 865 } 866 else if (saRoot->QueueConfig.outboundQueues[i].interruptEnable == 0) 867 { 868 /* polling mode - interruptVectorIndex = 0 only and no bit set */ 869 processedMsgCount += siProcessOBMsg(agRoot, count, i); 870 } 871#ifdef SA_FW_TEST_INTERRUPT_REASSERT 872 else if (saRoot->CheckAll) 873 { 874 /* polling mode - interruptVectorIndex = 0 only and no bit set */ 875 processedMsgCount += siProcessOBMsg(agRoot, count, i); 876 } 877#endif /* SA_FW_TEST_INTERRUPT_REASSERT */ 878 879 } 880 else 881 { 882 /* process IOMB in the outbound queue 32 to 63 if bit set in the vector bitmap */ 883 if (saRoot->interruptVecIndexBitMap1[interruptVectorIndex] & (1 << (i - OQ_NUM_32))) 884 { 885 processedMsgCount += siProcessOBMsg(agRoot, count, i); 886 } 887 /* check interruptEnable bit for polling mode of OQ */ 888 /* the following code can be removed, we do not care about the bit */ 889 else if (saRoot->QueueConfig.outboundQueues[i].interruptEnable == 0) 890 { 891 /* polling mode - interruptVectorIndex = 0 only and no bit set */ 892 processedMsgCount += siProcessOBMsg(agRoot, count, i); 893 } 894#ifdef SA_FW_TEST_INTERRUPT_REASSERT 895 else if (saRoot->CheckAll) 896 { 897 /* polling mode - interruptVectorIndex = 0 only and no bit set */ 898 processedMsgCount += siProcessOBMsg(agRoot, count, i); 899 } 900#endif /* SA_FW_TEST_INTERRUPT_REASSERT */ 901 } 902 } 903 904#ifdef SA_FW_TEST_INTERRUPT_REASSERT 905 saRoot->CheckAll = 0; 906#endif /* SA_FW_TEST_INTERRUPT_REASSERT */ 907 908#ifndef SA_RENABLE_IN_OSLAYER 909 if ( agTRUE == saRoot->sysIntsActive ) 910 { 911 /* Allow replacement of enable interrupt */ 912 ossaReenableInterrupts(agRoot, interruptVectorIndex); 913 } 914#endif /* SA_RENABLE_IN_OSLAYER */ 915 916 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5p"); 917 918 OSSA_OUT_LEAVE(agRoot); 919 return processedMsgCount; 920} 921 922/******************************************************************************/ 923/*! \brief Function to reenable MSIX interrupts 924 * 925 * siReenableMSIXInterrupts reenableinterrupts 926 * called thru macro ossaReenableInterrupts 927 * 928 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 929 * instance of SAS/SATA hardware 930 * \param interruptVectorIndex - vector index for message 931 * 932 */ 933/*******************************************************************************/ 934void siReenableMSIXInterrupts( 935 agsaRoot_t *agRoot, 936 bit32 interruptVectorIndex 937 ) 938{ 939 bit32 msi_index; 940#ifdef SA_CLEAR_ODCR_IN_INTERRUPT 941 bit32 value; 942#endif /* SA_CLEAR_ODCR_IN_INTERRUPT */ 943 msi_index = interruptVectorIndex * MSIX_TABLE_ELEMENT_SIZE; 944 msi_index += MSIX_TABLE_BASE; 945 ossaHwRegWriteExt(agRoot, PCIBAR0,msi_index, MSIX_INTERRUPT_ENABLE); 946 947 SA_DBG4(("siReenableMSIXInterrupts:interruptVectorIndex %d\n",interruptVectorIndex)); 948 949#ifdef SA_CLEAR_ODCR_IN_INTERRUPT 950 value = (1 << interruptVectorIndex); 951 siHalRegWriteExt(agRoot, GEN_MSGU_ODCR, MSGU_ODCR, value); 952#endif /* SA_CLEAR_ODCR_IN_INTERRUPT */ 953} 954/******************************************************************************/ 955/*! \brief Function to reenable MSIX interrupts 956 * 957 * siReenableMSIXInterrupts reenableinterrupts 958 * called thru macro ossaReenableInterrupts 959 * 960 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 961 * instance of SAS/SATA hardware 962 * \param interruptVectorIndex - vector index for message 963 * 964 */ 965/*******************************************************************************/ 966void siReenableMSIX_V_Interrupts( 967 agsaRoot_t *agRoot, 968 bit32 interruptVectorIndex 969 ) 970{ 971 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 972 bit64 mask; 973 agsabit32bit64 u64; 974 mask =( (bit64)1 << interruptVectorIndex); 975 u64.B64 = mask; 976 977 SA_DBG4(("siReenableMSIX_V_Interrupts:\n")); 978 979 if(saRoot->sysIntsActive) 980 { 981 if(smIS64bInt(agRoot)) 982 { 983 SA_DBG4(("siReenableMSIX_V_Interrupts: VI %d U 0x%08X L 0x%08X\n",interruptVectorIndex,u64.S32[1],u64.S32[0])); 984 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Clear_RegisterU,u64.S32[1] ); 985 } 986 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Clear_Register,u64.S32[0]); 987 } 988 else 989 { 990 SA_DBG1(("siReenableMSIX_V_Interrupts: VI %d sysIntsActive off\n",interruptVectorIndex)); 991 } 992 993} 994 995/******************************************************************************/ 996/*! \brief Function to reenable MSI interrupts 997 * 998 * siReenableMSIXInterrupts reenableinterrupts 999 * called thru macro ossaReenableInterrupts 1000 * 1001 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 1002 * instance of SAS/SATA hardware 1003 * \param interruptVectorIndex - vector index for message 1004 * 1005 */ 1006/*******************************************************************************/ 1007GLOBAL void siReenableMSIInterrupts( 1008 agsaRoot_t *agRoot, 1009 bit32 interruptVectorIndex 1010 ) 1011{ 1012 bit32 ODMRValue; 1013 1014 ODMRValue = siHalRegReadExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR); 1015 ODMRValue &= ~(1 << interruptVectorIndex); 1016 1017 siHalRegWriteExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR, ODMRValue); 1018} 1019 1020/******************************************************************************/ 1021/*! \brief Function to reenable MSI V interrupts 1022 * 1023 * siReenableMSIXInterrupts reenableinterrupts 1024 * called thru macro ossaReenableInterrupts 1025 * 1026 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 1027 * instance of SAS/SATA hardware 1028 * \param interruptVectorIndex - vector index for message 1029 * 1030 */ 1031/*******************************************************************************/ 1032GLOBAL void siReenableMSI_V_Interrupts( 1033 agsaRoot_t *agRoot, 1034 bit32 interruptVectorIndex 1035 ) 1036{ 1037 SA_ASSERT(0, "Should not be called"); 1038 1039 SA_DBG4(("siReenableMSI_V_Interrupts:\n")); 1040 1041} 1042/******************************************************************************/ 1043/*! \brief Function to reenable Legacy interrupts 1044 * 1045 * siReenableLegacyInterrupts reenableinterrupts 1046 * called thru macro ossaReenableInterrupts 1047 * 1048 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 1049 * instance of SAS/SATA hardware 1050 * \param interruptVectorIndex always zero 1051 * 1052 */ 1053/*******************************************************************************/ 1054GLOBAL void siReenableLegacyInterrupts( 1055 agsaRoot_t *agRoot, 1056 bit32 interruptVectorIndex 1057 ) 1058{ 1059 siHalRegWriteExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR, ODMR_CLEAR_ALL); 1060 1061#ifdef SA_CLEAR_ODCR_IN_INTERRUPT 1062 siHalRegWriteExt(agRoot, GEN_MSGU_ODCR, MSGU_ODCR, ODCR_CLEAR_ALL); 1063#endif /* SA_CLEAR_ODCR_IN_INTERRUPT */ 1064} 1065 1066/******************************************************************************/ 1067/*! \brief Function to reenable Legacy V interrupts 1068 * 1069 * siReenableLegacyInterrupts reenableinterrupts 1070 * called thru macro ossaReenableInterrupts 1071 * 1072 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 1073 * instance of SAS/SATA hardware 1074 * \param interruptVectorIndex always zero 1075 * 1076 */ 1077/*******************************************************************************/ 1078GLOBAL void siReenableLegacy_V_Interrupts( 1079 agsaRoot_t *agRoot, 1080 bit32 interruptVectorIndex 1081 ) 1082{ 1083 1084 bit32 mask; 1085 mask = 1 << interruptVectorIndex; 1086 1087 SA_DBG5(("siReenableLegacy_V_Interrupts:IN MSGU_READ_ODR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODR, V_Outbound_Doorbell_Set_Register))); 1088 SA_DBG5(("siReenableLegacy_V_Interrupts:IN MSGU_READ_ODMR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODMR, V_Outbound_Doorbell_Mask_Set_Register ))); 1089 1090 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Clear_Register, mask); 1091 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Clear_Register, mask ); 1092 1093 1094 SA_DBG5(("siReenableLegacy_V_Interrupts:OUT MSGU_READ_ODMR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODMR, V_Outbound_Doorbell_Mask_Set_Register ))); 1095 1096} 1097 1098/******************************************************************************/ 1099/*! \brief Function to enable a single interrupt vector 1100 * 1101 * 1102 * 1103 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 1104 * instance of SAS/SATA hardware 1105 * \param interruptVectorIndex Interrupt vector to enable 1106 * 1107 */ 1108/*******************************************************************************/ 1109/******************************************************************************/ 1110/*! \brief saSystemInterruptsEnable 1111 * Function to enable a single interrupt vector 1112 * 1113 * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 1114 * instance of SAS/SATA hardware 1115 * \param interruptVectorIndex Interrupt vector to enable 1116 * 1117 */ 1118/*******************************************************************************/ 1119GLOBAL FORCEINLINE 1120void saSystemInterruptsEnable( 1121 agsaRoot_t *agRoot, 1122 bit32 interruptVectorIndex 1123 ) 1124{ 1125 ossaReenableInterrupts(agRoot, interruptVectorIndex); 1126} 1127/******************************************************************************/ 1128/*! \brief Routine to handle Outbound Message 1129 * 1130 * The handle for outbound message 1131 * 1132 * \param agRoot handles for this instance of SAS/SATA hardware 1133 * \param count interrupt message count 1134 * \param queueNum outbound queue 1135 * 1136 * \return 1137 */ 1138/*******************************************************************************/ 1139LOCAL FORCEINLINE bit32 1140siProcessOBMsg( 1141 agsaRoot_t *agRoot, 1142 bit32 count, 1143 bit32 queueNum 1144 ) 1145{ 1146 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1147 mpiOCQueue_t *circularQ = agNULL; 1148 void *pMsg1 = agNULL; 1149 bit32 ret, processedMsgCount = 0; 1150 bit32 ParseOBIombStatus = 0; 1151#ifdef SA_ENABLE_TRACE_FUNCTIONS 1152 bit32 i = 0; 1153#endif 1154 bit16 opcode = 0; 1155 mpiMsgCategory_t category; 1156 bit8 bc = 0; 1157 1158 smTraceFuncEnter(hpDBG_VERY_LOUD,"5r"); 1159 1160 1161 SA_DBG3(("siProcessOBMsg: queueNum 0x%x\n", queueNum)); 1162 1163 ossaSingleThreadedEnter(agRoot, LL_IOREQ_OBQ_LOCK + queueNum); 1164 1165 circularQ = &saRoot->outboundQueue[queueNum]; 1166 OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0); 1167 1168 if (circularQ->producerIdx == circularQ->consumerIdx) 1169 { 1170 ossaSingleThreadedLeave(agRoot, LL_IOREQ_OBQ_LOCK + queueNum); 1171 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5r"); 1172 return processedMsgCount; 1173 } 1174 1175 ossaSingleThreadedLeave(agRoot, LL_IOREQ_OBQ_LOCK + queueNum); 1176 1177 do 1178 { 1179 /* ossaSingleThreadedEnter(agRoot, LL_IOREQ_OBQ_LOCK + queueNum); */ 1180 ret = mpiMsgConsume(circularQ, &pMsg1, &category, &opcode, &bc); 1181 /* ossaSingleThreadedLeave(agRoot, LL_IOREQ_OBQ_LOCK + queueNum); */ 1182 1183 if (AGSA_RC_SUCCESS == ret) 1184 { 1185 smTrace(hpDBG_IOMB,"M0",queueNum); 1186 /* TP:M0 queueNum */ 1187 smTrace(hpDBG_VERY_LOUD,"MA",opcode); 1188 /* TP:MA opcode */ 1189 smTrace(hpDBG_IOMB,"MB",category); 1190 /* TP:MB category */ 1191 1192#ifdef SA_ENABLE_TRACE_FUNCTIONS 1193 for (i=0; i<((bit32)bc*(circularQ->elementSize/4)); i++) 1194 { 1195 /* The -sizeof(mpiMsgHeader_t) is to account for mpiMsgConsume incrementing the pointer past the header*/ 1196 smTrace(hpDBG_IOMB,"MC",*( ((bit32*)((bit8 *)pMsg1 - sizeof(mpiMsgHeader_t))) + i)); 1197 /* TP:MC Outbound IOMB Dword */ 1198 } 1199#endif 1200 1201 MPI_DEBUG_TRACE( circularQ->qNumber,((circularQ->producerIdx << 16 ) | circularQ->consumerIdx),MPI_DEBUG_TRACE_OBQ, (void *)(((bit8*)pMsg1) - sizeof(mpiMsgHeader_t)), circularQ->elementSize); 1202 1203 ossaLogIomb(circularQ->agRoot, 1204 circularQ->qNumber, 1205 FALSE, 1206 (void *)(((bit8*)pMsg1) - sizeof(mpiMsgHeader_t)), 1207 bc*circularQ->elementSize); 1208 1209 ossaQueueProcessed(agRoot, queueNum, circularQ->producerIdx, circularQ->consumerIdx); 1210 /* process the outbound message */ 1211 ParseOBIombStatus = mpiParseOBIomb(agRoot, (bit32 *)pMsg1, category, opcode); 1212 if (ParseOBIombStatus == AGSA_RC_FAILURE) 1213 { 1214 SA_DBG1(("siProcessOBMsg, Failed Q %2d PI 0x%03x CI 0x%03x\n", queueNum, circularQ->producerIdx, circularQ->consumerIdx)); 1215#if defined(SALLSDK_DEBUG) 1216 /* free the message for debug: this is a hang! */ 1217 1218 mpiMsgFreeSet(circularQ, pMsg1, bc); 1219 processedMsgCount ++; 1220#endif /**/ 1221 break; 1222 } 1223 1224 /* free the message from the outbound circular buffer */ 1225 mpiMsgFreeSet(circularQ, pMsg1, bc); 1226 processedMsgCount ++; 1227 } 1228 else 1229 //if (AGSA_RC_BUSY == ret) // always (circularQ->producerIdx == circularQ->consumerIdx) 1230 // || (AGSA_RC_FAILURE == ret) 1231 { 1232 break; 1233 } 1234 } 1235 /* end of message processing if hit the count */ 1236 while(count > processedMsgCount); 1237 1238/* #define SALLSDK_FATAL_ERROR_DETECT 1 */ 1239/* 1240 this comments are to be removed 1241 fill in 0x1D 0x1e 0x1f 0x20 in MPI table for 1242 bit32 regDumpBusBaseNum0; 1243 bit32 regDumpOffset0; 1244 bit32 regDumpLen0; 1245 bit32 regDumpBusBaseNum1; 1246 bit32 regDumpOffset1; 1247 bit32 regDumpLen1; 1248 in agsaFatalErrorInfo_t 1249 1250 ??? regDumpBusBaseNum0 and regDumpBusBaseNum1 1251 saRoot->mainConfigTable.regDumpPCIBAR = pcibar; 1252 saRoot->mainConfigTable.FatalErrorDumpOffset0 = config->FatalErrorDumpOffset0; 1253 saRoot->mainConfigTable.FatalErrorDumpLength0 = config->FatalErrorDumpLength0; 1254 saRoot->mainConfigTable.FatalErrorDumpOffset1 = config->FatalErrorDumpOffset1; 1255 saRoot->mainConfigTable.FatalErrorDumpLength1 = config->FatalErrorDumpLength1; 1256 1257 1258 1259*/ 1260#if defined(SALLSDK_FATAL_ERROR_DETECT) 1261 1262 if( smIS_SPC(agRoot) ) /* SPC only */ 1263 { 1264 1265 /* any fatal error happened */ 1266 /* executing this code impacts performance by 1% when no error is detected */ 1267 { 1268 agsaFatalErrorInfo_t fatal_error; 1269 bit32 value; 1270 bit32 value1; 1271 1272 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); 1273 value1 = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2); 1274 1275 if( (value & SA_FATAL_ERROR_SP1_AAP1_ERR_MASK) == SA_FATAL_ERROR_FATAL_ERROR || 1276 (value1 & SA_FATAL_ERROR_SP2_IOP_ERR_MASK) == SA_FATAL_ERROR_FATAL_ERROR ) 1277 { 1278 si_memset(&fatal_error, 0, sizeof(agsaFatalErrorInfo_t)); 1279 /* read detail fatal errors */ 1280 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0, MSGU_SCRATCH_PAD_0); 1281 fatal_error.errorInfo0 = value; 1282 SA_DBG1(("siProcessOBMsg: ScratchPad0 AAP error code 0x%x\n", value)); 1283 1284 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); 1285 fatal_error.errorInfo1 = value; 1286 /* AAP error state */ 1287 SA_DBG1(("siProcessOBMsg: AAP error state and error code 0x%x\n", value)); 1288 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2); 1289 fatal_error.errorInfo2 = value; 1290 /* IOP error state */ 1291 SA_DBG1(("siProcessOBMsg: IOP error state and error code 0x%x\n", value)); 1292 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3, MSGU_SCRATCH_PAD_3); 1293 SA_DBG1(("siProcessOBMsg: ScratchPad3 IOP error code 0x%x\n", value)); 1294 fatal_error.errorInfo3 = value; 1295 1296 if (agNULL != saRoot) 1297 { 1298 fatal_error.regDumpBusBaseNum0 = saRoot->mainConfigTable.regDumpPCIBAR; 1299 fatal_error.regDumpOffset0 = saRoot->mainConfigTable.FatalErrorDumpOffset0; 1300 fatal_error.regDumpLen0 = saRoot->mainConfigTable.FatalErrorDumpLength0; 1301 fatal_error.regDumpBusBaseNum1 = saRoot->mainConfigTable.regDumpPCIBAR; 1302 fatal_error.regDumpOffset1 = saRoot->mainConfigTable.FatalErrorDumpOffset1; 1303 fatal_error.regDumpLen1 = saRoot->mainConfigTable.FatalErrorDumpLength1; 1304 } 1305 else 1306 { 1307 fatal_error.regDumpBusBaseNum0 = 0; 1308 fatal_error.regDumpOffset0 = 0; 1309 fatal_error.regDumpLen0 = 0; 1310 fatal_error.regDumpBusBaseNum1 = 0; 1311 fatal_error.regDumpOffset1 = 0; 1312 fatal_error.regDumpLen1 = 0; 1313 } 1314 /* Call Back with error */ 1315 SA_DBG1(("siProcessOBMsg: SALLSDK_FATAL_ERROR_DETECT \n")); 1316 ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_MALFUNCTION, 0, (void *)&fatal_error, agNULL); 1317 } 1318 } 1319 } 1320#endif /* SALLSDK_FATAL_ERROR_DETECT */ 1321 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5r"); 1322 return processedMsgCount; 1323} 1324 1325/******************************************************************************/ 1326/*! \brief Function to enable/disable interrupts 1327 * 1328 * The saSystemInterruptsActive() function is called to indicate to the LL Layer 1329 * whether interrupts are available. The parameter sysIntsActive indicates whether 1330 * interrupts are available at this time. 1331 * 1332 * \param agRoot handles for this instance of SAS/SATA hardware 1333 * \param sysIntsActive flag for enable/disable interrupt 1334 * 1335 * \return -void- 1336 * 1337 */ 1338/*******************************************************************************/ 1339GLOBAL void saSystemInterruptsActive( 1340 agsaRoot_t *agRoot, 1341 agBOOLEAN sysIntsActive 1342 ) 1343{ 1344 bit32 x; 1345 agsaLLRoot_t *saRoot; 1346 1347 SA_ASSERT((agNULL != agRoot), ""); 1348 if (agRoot == agNULL) 1349 { 1350 SA_DBG1(("saSystemInterruptsActive: agRoot == agNULL\n")); 1351 return; 1352 } 1353 saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1354 SA_ASSERT((agNULL != saRoot), ""); 1355 if (saRoot == agNULL) 1356 { 1357 SA_DBG1(("saSystemInterruptsActive: saRoot == agNULL\n")); 1358 return; 1359 } 1360 1361 smTraceFuncEnter(hpDBG_TICK_INT,"5s"); 1362 SA_DBG1(("saSystemInterruptsActive: now 0x%X new 0x%x\n",saRoot->sysIntsActive,sysIntsActive)); 1363 SA_DBG3(("saSystemInterruptsActive: Doorbell_Set %08X U %08X\n", 1364 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_Register), 1365 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_RegisterU))); 1366 SA_DBG3(("saSystemInterruptsActive: Doorbell_Mask %08X U %08X\n", 1367 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register ), 1368 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU ))); 1369 1370 if( saRoot->sysIntsActive && sysIntsActive ) 1371 { 1372 SA_DBG1(("saSystemInterruptsActive: Already active 0x%X new 0x%x\n",saRoot->sysIntsActive,sysIntsActive)); 1373 smTraceFuncExit(hpDBG_TICK_INT, 'a', "5s"); 1374 return; 1375 } 1376 1377 if( !saRoot->sysIntsActive && !sysIntsActive ) 1378 { 1379 if(smIS_SPC(agRoot)) 1380 { 1381 siHalRegWriteExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR,AGSA_INTERRUPT_HANDLE_ALL_CHANNELS ); 1382 } 1383 else 1384 { 1385 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_Register, AGSA_INTERRUPT_HANDLE_ALL_CHANNELS); 1386 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_RegisterU, AGSA_INTERRUPT_HANDLE_ALL_CHANNELS); 1387 } 1388 SA_DBG1(("saSystemInterruptsActive: Already disabled 0x%X new 0x%x\n",saRoot->sysIntsActive,sysIntsActive)); 1389 smTraceFuncExit(hpDBG_TICK_INT, 'b', "5s"); 1390 return; 1391 } 1392 1393 /* Set the flag is sdkData */ 1394 saRoot->sysIntsActive = (bit8)sysIntsActive; 1395 1396 1397 smTrace(hpDBG_TICK_INT,"Vq",sysIntsActive); 1398 /* TP:Vq sysIntsActive */ 1399 /* If sysIntsActive is true */ 1400 if ( agTRUE == sysIntsActive ) 1401 { 1402 1403 SA_DBG1(("saSystemInterruptsActive: Doorbell_Set %08X U %08X\n", 1404 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_Register), 1405 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_RegisterU))); 1406 SA_DBG1(("saSystemInterruptsActive: Doorbell_Mask_Set %08X U %08X\n", 1407 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register), 1408 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU))); 1409 if(smIS_SPCV(agRoot)) 1410 { 1411 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Clear_Register, 0xFFFFFFFF); 1412 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Clear_RegisterU, 0xFFFFFFFF); 1413 } 1414 /* enable interrupt */ 1415 for(x=0; x < saRoot->numInterruptVectors; x++) 1416 { 1417 ossaReenableInterrupts(agRoot,x ); 1418 } 1419 1420 if(saRoot->swConfig.fatalErrorInterruptEnable) 1421 { 1422 ossaReenableInterrupts(agRoot,saRoot->swConfig.fatalErrorInterruptVector ); 1423 } 1424 1425 siHalRegWriteExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR, 0); 1426 } 1427 /* If sysIntsActive is false */ 1428 else 1429 { 1430 /* disable interrupt */ 1431 if(smIS_SPC(agRoot)) 1432 { 1433 siHalRegWriteExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR,AGSA_INTERRUPT_HANDLE_ALL_CHANNELS ); 1434 } 1435 else 1436 { 1437 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_Register, AGSA_INTERRUPT_HANDLE_ALL_CHANNELS); 1438 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_RegisterU, AGSA_INTERRUPT_HANDLE_ALL_CHANNELS); 1439 } 1440 } 1441 1442 SA_DBG3(("saSystemInterruptsActive: Doorbell_Set %08X U %08X\n", 1443 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_Register), 1444 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_RegisterU))); 1445 SA_DBG3(("saSystemInterruptsActive: Doorbell_Mask %08X U %08X\n", 1446 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register ), 1447 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU ))); 1448 1449 1450 smTraceFuncExit(hpDBG_TICK_INT, 'c', "5s"); 1451} 1452 1453/******************************************************************************/ 1454/*! \brief Routine to handle for received SAS with data payload event 1455 * 1456 * The handle for received SAS with data payload event 1457 * 1458 * \param agRoot handles for this instance of SAS/SATA hardware 1459 * \param pRequest handles for the IOrequest 1460 * \param pRespIU the pointer to the Response IU 1461 * \param param Payload Length 1462 * 1463 * \return -void- 1464 */ 1465/*******************************************************************************/ 1466GLOBAL void siEventSSPResponseWtDataRcvd( 1467 agsaRoot_t *agRoot, 1468 agsaIORequestDesc_t *pRequest, 1469 agsaSSPResponseInfoUnit_t *pRespIU, 1470 bit32 param, 1471 bit32 sspTag 1472 ) 1473{ 1474 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1475 agsaDeviceDesc_t *pDevice; 1476 bit32 count = 0; 1477 bit32 padCount; 1478 1479 smTraceFuncEnter(hpDBG_VERY_LOUD,"5g"); 1480 1481 /* get frame handle */ 1482 1483 /* If the request is still valid */ 1484 if ( agTRUE == pRequest->valid ) 1485 { 1486 /* get device */ 1487 pDevice = pRequest->pDevice; 1488 1489 /* Delete the request from the pendingIORequests */ 1490 ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1491 saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 1492 ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1493 1494 if (sspTag & SSP_RESCV_BIT) 1495 { 1496 /* get the pad count, bit 17 and 18 of sspTag */ 1497 padCount = (sspTag >> SSP_RESCV_PAD_SHIFT) & 0x3; 1498 /* get Residual Count */ 1499 count = *(bit32 *)((bit8 *)pRespIU + param + padCount); 1500 } 1501 1502 (*(ossaSSPCompletedCB_t)(pRequest->completionCB))(agRoot, 1503 pRequest->pIORequestContext, 1504 OSSA_IO_SUCCESS, 1505 param, 1506 (void *)pRespIU, 1507 (bit16)(sspTag & SSPTAG_BITS), 1508 count); 1509 1510 ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1511 pRequest->valid = agFALSE; 1512 /* return the request to free pool */ 1513 if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) 1514 { 1515 SA_DBG1(("siEventSSPResponseWtDataRcvd: saving pRequest (%p) for later use\n", pRequest)); 1516 saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); 1517 } 1518 else 1519 { 1520 /* return the request to free pool */ 1521 saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 1522 } 1523 ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1524 1525 } 1526 else 1527 { 1528 SA_DBG1(("siEventSSPResponseWtDataRcvd: pRequest->Valid not TRUE\n")); 1529 } 1530 1531 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5g"); 1532 1533 return; 1534} 1535 1536/******************************************************************************/ 1537/*! \brief Routine to handle successfully completed IO event 1538 * 1539 * Handle successfully completed IO 1540 * 1541 * \param agRoot handles for this instance of SAS/SATA hardware 1542 * \param pRequest Pointer of IO request of the IO 1543 * \param status status of the IO 1544 * 1545 * \return -void- 1546 */ 1547/*******************************************************************************/ 1548GLOBAL FORCEINLINE void siIODone( 1549 agsaRoot_t *agRoot, 1550 agsaIORequestDesc_t *pRequest, 1551 bit32 status, 1552 bit32 sspTag 1553 ) 1554{ 1555 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1556 agsaDeviceDesc_t *pDevice = agNULL; 1557 1558 smTraceFuncEnter(hpDBG_VERY_LOUD,"5h"); 1559 1560 SA_ASSERT(NULL != pRequest, "pRequest cannot be null"); 1561 1562 /* If the request is still valid */ 1563 if ( agTRUE == pRequest->valid ) 1564 { 1565 /* get device */ 1566 pDevice = pRequest->pDevice; 1567 1568 /* process different request type */ 1569 switch (pRequest->requestType & AGSA_REQTYPE_MASK) 1570 { 1571 case AGSA_SSP_REQTYPE: 1572 { 1573 SA_ASSERT(pRequest->valid, "pRequest not valid"); 1574 pRequest->completionCB(agRoot, 1575 pRequest->pIORequestContext, 1576 OSSA_IO_SUCCESS, 1577 0, 1578 agNULL, 1579 (bit16)(sspTag & SSPTAG_BITS), 1580 0); 1581 ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1582 /* Delete the request from the pendingIORequests */ 1583 saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 1584 /* return the request to free pool */ 1585 pRequest->valid = agFALSE; 1586 saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 1587 ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1588 1589 1590 break; 1591 } 1592 case AGSA_SATA_REQTYPE: 1593 { 1594 SA_DBG5(("siIODone: SATA complete\n")); 1595 1596 if ( agNULL != pRequest->pIORequestContext ) 1597 { 1598 SA_DBG5(("siIODone: Complete Request\n")); 1599 1600 (*(ossaSATACompletedCB_t)(pRequest->completionCB))(agRoot, 1601 pRequest->pIORequestContext, 1602 OSSA_IO_SUCCESS, 1603 agNULL, 1604 0, 1605 agNULL); 1606 } 1607 ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1608 /* Delete the request from the pendingIORequests */ 1609 saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 1610 /* return the request to free pool */ 1611 saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 1612 ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1613 1614 pRequest->valid = agFALSE; 1615 1616 break; 1617 } 1618 case AGSA_SMP_REQTYPE: 1619 { 1620 if ( agNULL != pRequest->pIORequestContext ) 1621 { 1622 (*(ossaSMPCompletedCB_t)(pRequest->completionCB))(agRoot, 1623 pRequest->pIORequestContext, 1624 OSSA_IO_SUCCESS, 1625 0, 1626 agNULL); 1627 } 1628 1629 ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1630 /* Delete the request from the pendingSMPRequests */ 1631 saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 1632 /* return the request to free pool */ 1633 if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) 1634 { 1635 SA_DBG1(("siIODone: saving pRequest (%p) for later use\n", pRequest)); 1636 saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); 1637 } 1638 else 1639 { 1640 saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 1641 } 1642 ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1643 1644 pRequest->valid = agFALSE; 1645 1646 break; 1647 } 1648 default: 1649 { 1650 SA_DBG1(("siIODone: unknown request type (%x) is completed. HTag=0x%x\n", pRequest->requestType, pRequest->HTag)); 1651 break; 1652 } 1653 } 1654 } 1655 else 1656 { 1657 SA_DBG1(("siIODone: The request is not valid any more. HTag=0x%x requestType=0x%x\n", pRequest->HTag, pRequest->requestType)); 1658 } 1659 1660 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5h"); 1661 1662} 1663 1664/******************************************************************************/ 1665/*! \brief Routine to handle abnormal completed IO/SMP event 1666 * 1667 * Handle abnormal completed IO/SMP 1668 * 1669 * \param agRoot handles for this instance of SAS/SATA hardware 1670 * \param pRequest Pointer of IO request of the IO 1671 * \param status status of the IO 1672 * \param param Length 1673 * 1674 * \return -void- 1675 */ 1676/*******************************************************************************/ 1677GLOBAL void siAbnormal( 1678 agsaRoot_t *agRoot, 1679 agsaIORequestDesc_t *pRequest, 1680 bit32 status, 1681 bit32 param, 1682 bit32 sspTag 1683 ) 1684{ 1685 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1686 agsaDeviceDesc_t *pDevice; 1687 1688 smTraceFuncEnter(hpDBG_VERY_LOUD,"5i"); 1689 1690 if (agNULL == pRequest) 1691 { 1692 SA_DBG1(("siAbnormal: pRequest is NULL.\n")); 1693 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5i"); 1694 return; 1695 } 1696 1697 /* If the request is still valid */ 1698 if ( agTRUE == pRequest->valid ) 1699 { 1700 /* get device */ 1701 1702 SA_ASSERT((pRequest->pIORequestContext->osData != pRequest->pIORequestContext->sdkData), "pIORequestContext"); 1703 1704 pDevice = pRequest->pDevice; 1705 1706 /* remove the IO request from IOMap */ 1707 saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; 1708 saRoot->IOMap[pRequest->HTag].IORequest = agNULL; 1709 saRoot->IOMap[pRequest->HTag].agContext = agNULL; 1710 1711 smTrace(hpDBG_VERY_LOUD,"P6",status ); 1712 /* TP:P6 siAbnormal status */ 1713 smTrace(hpDBG_VERY_LOUD,"P7",param ); 1714 /* TP:P7 siAbnormal param */ 1715 /* process different request type */ 1716 switch (pRequest->requestType & AGSA_REQTYPE_MASK) 1717 { 1718 case AGSA_SSP_REQTYPE: 1719 { 1720 (*(ossaSSPCompletedCB_t)(pRequest->completionCB))(agRoot, 1721 pRequest->pIORequestContext, 1722 status, 1723 param, 1724 agNULL, 1725 (bit16)(sspTag & SSPTAG_BITS), 1726 ((sspTag & SSP_AGR_S_BIT)? (1 << 0) : 0)); 1727 1728 ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1729 /* Delete the request from the pendingIORequests */ 1730 saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 1731 pRequest->valid = agFALSE; 1732 /* return the request to free pool */ 1733 if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) 1734 { 1735 SA_DBG1(("siAbnormal: saving pRequest (%p) for later use\n", pRequest)); 1736 saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); 1737 } 1738 else 1739 { 1740 /* return the request to free pool */ 1741 saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 1742 } 1743 ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1744 1745 break; 1746 } 1747 case AGSA_SATA_REQTYPE: 1748 { 1749 SA_DBG5(("siAbnormal: SATA \n")); 1750 1751 if ( agNULL != pRequest->pIORequestContext ) 1752 { 1753 SA_DBG5(("siAbnormal: Calling SATACompletedCB\n")); 1754 1755 (*(ossaSATACompletedCB_t)(pRequest->completionCB))(agRoot, 1756 pRequest->pIORequestContext, 1757 status, 1758 agNULL, 1759 param, 1760 agNULL); 1761 } 1762 1763 ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1764 /* Delete the request from the pendingIORequests */ 1765 saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 1766 /* return the request to free pool */ 1767 pRequest->valid = agFALSE; 1768 if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) 1769 { 1770 SA_DBG1(("siAbnormal: saving pRequest (%p) for later use\n", pRequest)); 1771 saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); 1772 } 1773 else 1774 { 1775 /* return the request to free pool */ 1776 saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 1777 } 1778 ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1779 1780 break; 1781 } 1782 case AGSA_SMP_REQTYPE: 1783 { 1784 if ( agNULL != pRequest->pIORequestContext ) 1785 { 1786 (*(ossaSMPCompletedCB_t)(pRequest->completionCB))(agRoot, 1787 pRequest->pIORequestContext, 1788 status, 1789 param, 1790 agNULL); 1791 } 1792 1793 ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1794 /* Delete the request from the pendingSMPRequests */ 1795 saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 1796 /* return the request to free pool */ 1797 pRequest->valid = agFALSE; 1798 if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) 1799 { 1800 SA_DBG1(("siAbnormal: saving pRequest (%p) for later use\n", pRequest)); 1801 saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); 1802 } 1803 else 1804 { 1805 /* return the request to free pool */ 1806 saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 1807 } 1808 ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1809 1810 break; 1811 } 1812 default: 1813 { 1814 SA_DBG1(("siAbnormal: unknown request type (%x) is completed. Tag=0x%x\n", pRequest->requestType, pRequest->HTag)); 1815 break; 1816 } 1817 } 1818 1819 } 1820 else 1821 { 1822 SA_DBG1(("siAbnormal: The request is not valid any more. Tag=0x%x\n", pRequest->HTag)); 1823 } 1824 1825 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5i"); 1826 1827 return; 1828} 1829 1830 1831/******************************************************************************/ 1832/*! \brief Routine to handle abnormal DIF completed IO/SMP event 1833 * 1834 * Handle abnormal completed IO/SMP 1835 * 1836 * \param agRoot handles for this instance of SAS/SATA hardware 1837 * \param pRequest Pointer of IO request of the IO 1838 * \param status status of the IO 1839 * \param param Length 1840 * 1841 * \return -void- 1842 */ 1843/*******************************************************************************/ 1844GLOBAL void siDifAbnormal( 1845 agsaRoot_t *agRoot, 1846 agsaIORequestDesc_t *pRequest, 1847 bit32 status, 1848 bit32 param, 1849 bit32 sspTag, 1850 bit32 *pMsg1 1851 ) 1852{ 1853 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1854 agsaDeviceDesc_t *pDevice; 1855 1856 smTraceFuncEnter(hpDBG_VERY_LOUD,"2S"); 1857 1858 if (agNULL == pRequest) 1859 { 1860 SA_DBG1(("siDifAbnormal: pRequest is NULL.\n")); 1861 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2S"); 1862 return; 1863 } 1864 1865 /* If the request is still valid */ 1866 if ( agTRUE == pRequest->valid ) 1867 { 1868 /* get device */ 1869 pDevice = pRequest->pDevice; 1870 1871 /* remove the IO request from IOMap */ 1872 saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; 1873 saRoot->IOMap[pRequest->HTag].IORequest = agNULL; 1874 saRoot->IOMap[pRequest->HTag].agContext = agNULL; 1875 1876 smTrace(hpDBG_VERY_LOUD,"P6",status ); 1877 /* TP:P6 siDifAbnormal status */ 1878 /* process different request type */ 1879 switch (pRequest->requestType & AGSA_REQTYPE_MASK) 1880 { 1881 case AGSA_SSP_REQTYPE: 1882 { 1883 agsaDifDetails_t agDifDetails; 1884 agsaSSPCompletionDifRsp_t *pIomb; 1885 pIomb = (agsaSSPCompletionDifRsp_t *)pMsg1; 1886 si_memset(&agDifDetails, 0, sizeof(agDifDetails)); 1887 1888 OSSA_READ_LE_32(agRoot, &agDifDetails.UpperLBA, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,UpperLBA )); 1889 OSSA_READ_LE_32(agRoot, &agDifDetails.LowerLBA, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,LowerLBA )); 1890 OSSA_READ_LE_32(agRoot, &agDifDetails.sasAddressHi, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,sasAddressHi )); 1891 OSSA_READ_LE_32(agRoot, &agDifDetails.sasAddressLo, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,sasAddressLo)); 1892 OSSA_READ_LE_32(agRoot, &agDifDetails.ExpectedCRCUDT01, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,ExpectedCRCUDT01 )); 1893 OSSA_READ_LE_32(agRoot, &agDifDetails.ExpectedUDT2345, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,ExpectedUDT2345)); 1894 OSSA_READ_LE_32(agRoot, &agDifDetails.ActualCRCUDT01, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,ActualCRCUDT01 )); 1895 OSSA_READ_LE_32(agRoot, &agDifDetails.ActualUDT2345, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,ActualUDT2345)); 1896 OSSA_READ_LE_32(agRoot, &agDifDetails.DIFErrDevID, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,DIFErrDevID )); 1897 OSSA_READ_LE_32(agRoot, &agDifDetails.ErrBoffsetEDataLen, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,ErrBoffsetEDataLen )); 1898 agDifDetails.frame = (void *)(bit8*)(pIomb+ OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t, EDATA_FRM)); 1899 1900 (*(ossaSSPCompletedCB_t)(pRequest->completionCB))(agRoot, 1901 pRequest->pIORequestContext, 1902 status, 1903 param, 1904 &agDifDetails, 1905 (bit16)(sspTag & SSPTAG_BITS), 1906 ((sspTag & SSP_AGR_S_BIT)? (1 << 0) : 0)); 1907 1908 ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1909 pRequest->valid = agFALSE; 1910 /* Delete the request from the pendingIORequests */ 1911 saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 1912 1913 /* return the request to free pool */ 1914 if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) 1915 { 1916 SA_DBG1(("siDifAbnormal: saving pRequest (%p) for later use\n", pRequest)); 1917 saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); 1918 } 1919 else 1920 { 1921 /* return the request to free pool */ 1922 saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 1923 } 1924 ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1925 1926 break; 1927 } 1928 default: 1929 { 1930 SA_DBG1(("siDifAbnormal: unknown request type (%x) is completed. Tag=0x%x\n", pRequest->requestType, pRequest->HTag)); 1931 break; 1932 } 1933 } 1934 1935 } 1936 else 1937 { 1938 SA_DBG1(("siDifAbnormal: The request is not valid any more. Tag=0x%x\n", pRequest->HTag)); 1939 } 1940 1941 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2S"); 1942 1943 return; 1944} 1945 1946 1947/******************************************************************************/ 1948/*! \brief Routine to handle for received SMP response event 1949 * 1950 * The handle for received SMP response event 1951 * 1952 * \param agRoot handles for this instance of SAS/SATA hardware 1953 * \param pIomb Pointer of payload of IOMB 1954 * \param payloadSize size of the payload 1955 * \param tag the tag of the request SMP 1956 * 1957 * \return -void- 1958 */ 1959/*******************************************************************************/ 1960GLOBAL void siSMPRespRcvd( 1961 agsaRoot_t *agRoot, 1962 agsaSMPCompletionRsp_t *pIomb, 1963 bit32 payloadSize, 1964 bit32 tag 1965 ) 1966{ 1967 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1968 agsaFrameHandle_t frameHandle; 1969 agsaIORequestDesc_t *pRequest; 1970 agsaDeviceDesc_t *pDevice; 1971 agsaPort_t *pPort; 1972 1973 smTraceFuncEnter(hpDBG_VERY_LOUD,"5j"); 1974 1975 /* get the request */ 1976 pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; 1977 SA_ASSERT(pRequest, "pRequest"); 1978 1979 /* get the port */ 1980 pPort = pRequest->pPort; 1981 SA_ASSERT(pPort, "pPort"); 1982 1983 if (pRequest->IRmode == 0) 1984 { 1985 /* get frame handle - direct response mode */ 1986 frameHandle = (agsaFrameHandle_t)(&(pIomb->SMPrsp[0])); 1987#if defined(SALLSDK_DEBUG) 1988 SA_DBG3(("saSMPRespRcvd(direct): smpRspPtr=0x%p - len=0x%x\n", 1989 frameHandle, 1990 payloadSize 1991 )); 1992#endif /* SALLSDK_DEBUG */ 1993 } 1994 else 1995 { 1996 /* indirect response mode */ 1997 frameHandle = agNULL; 1998 } 1999 2000 /* If the request is still valid */ 2001 if ( agTRUE == pRequest->valid ) 2002 { 2003 /* get device */ 2004 pDevice = pRequest->pDevice; 2005 SA_ASSERT(pDevice, "pDevice"); 2006 2007 /* Delete the request from the pendingSMPRequests */ 2008 ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 2009 saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 2010 ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 2011 2012 /* If the request is from OS layer */ 2013 if ( agNULL != pRequest->pIORequestContext ) 2014 { 2015 if (agNULL == frameHandle) 2016 { 2017 /* indirect mode */ 2018 /* call back with success */ 2019 (*(ossaSMPCompletedCB_t)(pRequest->completionCB))(agRoot, pRequest->pIORequestContext, OSSA_IO_SUCCESS, payloadSize, frameHandle); 2020 } 2021 else 2022 { 2023 /* direct mode */ 2024 /* call back with success */ 2025 (*(ossaSMPCompletedCB_t)(pRequest->completionCB))(agRoot, pRequest->pIORequestContext, OSSA_IO_SUCCESS, payloadSize, frameHandle); 2026 } 2027 } 2028 2029 /* remove the IO request from IOMap */ 2030 saRoot->IOMap[tag].Tag = MARK_OFF; 2031 saRoot->IOMap[tag].IORequest = agNULL; 2032 saRoot->IOMap[tag].agContext = agNULL; 2033 ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 2034 pRequest->valid = agFALSE; 2035 if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) 2036 { 2037 SA_DBG1(("siSMPRespRcvd: saving pRequest (%p) for later use\n", pRequest)); 2038 saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); 2039 } 2040 else 2041 { 2042 /* return the request to free pool */ 2043 saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 2044 } 2045 ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 2046 } 2047 2048 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5j"); 2049 2050 return; 2051} 2052 2053/******************************************************************************/ 2054/*! \brief Routine to handle for received Phy Up event 2055 * 2056 * The handle for received Phy Up event 2057 * 2058 * \param agRoot handles for this instance of SAS/SATA hardware 2059 * \param phyId for the Phy Up event happened 2060 * \param agSASIdentify is the remote phy Identify 2061 * \param portId is the port context index of the phy up event 2062 * \param deviceId is the device context index 2063 * \param linkRate link up rate from SPC 2064 * 2065 * \return -void- 2066 */ 2067/*******************************************************************************/ 2068GLOBAL void siEventPhyUpRcvd( 2069 agsaRoot_t *agRoot, 2070 bit32 phyId, 2071 agsaSASIdentify_t *agSASIdentify, 2072 bit32 portId, 2073 bit32 npipps, 2074 bit8 linkRate 2075 ) 2076{ 2077 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 2078 agsaPhy_t *pPhy = &(saRoot->phys[phyId]); 2079 agsaPort_t *pPort; 2080 agsaSASIdentify_t remoteIdentify; 2081 agsaPortContext_t *agPortContext; 2082 2083 smTraceFuncEnter(hpDBG_VERY_LOUD,"5k"); 2084 2085 /* Read remote SAS Identify from response message and save it */ 2086 remoteIdentify = *agSASIdentify; 2087 2088 /* get port context from portMap */ 2089 SA_DBG2(("siEventPhyUpRcvd:PortID 0x%x PortStatus 0x%x PortContext %p\n",saRoot->PortMap[portId & PORTID_MASK].PortID,saRoot->PortMap[portId & PORTID_MASK].PortStatus,saRoot->PortMap[portId & PORTID_MASK].PortContext)); 2090 agPortContext = (agsaPortContext_t *)saRoot->PortMap[portId].PortContext; 2091 2092 SA_DBG2(("siEventPhyUpRcvd: portID %d PortContext %p linkRate 0x%X\n", portId, agPortContext,linkRate)); 2093 if (smIS_SPCV8006(agRoot)) 2094 { 2095 SA_DBG1(("siEventPhyUpRcvd: SAS_PHY_UP received for SATA Controller\n")); 2096 return; 2097 } 2098 2099 if (agNULL != agPortContext) 2100 { 2101 /* existing port */ 2102 pPort = (agsaPort_t *) (agPortContext->sdkData); 2103 pPort->portId = portId; 2104 2105 /* include the phy to the port */ 2106 pPort->phyMap[phyId] = agTRUE; 2107 /* Set the port for the phy */ 2108 saRoot->phys[phyId].pPort = pPort; 2109 2110 /* Update port state */ 2111 if (OSSA_PORT_VALID == (npipps & PORT_STATE_MASK)) 2112 { 2113 pPort->status &= ~PORT_INVALIDATING; 2114 saRoot->PortMap[portId].PortStatus &= ~PORT_INVALIDATING; 2115 SA_DBG1(("siEventPhyUpRcvd: portID %d PortContext %p, hitting workaround\n", portId, agPortContext)); 2116 } 2117 } 2118 else 2119 { 2120 ossaSingleThreadedEnter(agRoot, LL_PORT_LOCK); 2121 /* new port */ 2122 /* Allocate a free port */ 2123 pPort = (agsaPort_t *) saLlistGetHead(&(saRoot->freePorts)); 2124 if (agNULL != pPort) 2125 { 2126 /* Acquire port list lock */ 2127 saLlistRemove(&(saRoot->freePorts), &(pPort->linkNode)); 2128 2129 /* setup the port data structure */ 2130 pPort->portContext.osData = agNULL; 2131 pPort->portContext.sdkData = pPort; 2132 2133 /* Add to valid port list */ 2134 saLlistAdd(&(saRoot->validPorts), &(pPort->linkNode)); 2135 /* Release port list lock */ 2136 ossaSingleThreadedLeave(agRoot, LL_PORT_LOCK); 2137 2138 /* include the phy to the port */ 2139 pPort->phyMap[phyId] = agTRUE; 2140 /* Set the port for the phy */ 2141 saRoot->phys[phyId].pPort = pPort; 2142 2143 /* Setup portMap based on portId */ 2144 saRoot->PortMap[portId].PortID = portId; 2145 saRoot->PortMap[portId].PortContext = &(pPort->portContext); 2146 pPort->portId = portId; 2147 2148 SA_DBG3(("siEventPhyUpRcvd: NewPort portID %d PortContext %p\n", portId, saRoot->PortMap[portId].PortContext)); 2149 } 2150 else 2151 { 2152 ossaSingleThreadedLeave(agRoot, LL_PORT_LOCK); 2153 /* pPort is agNULL*/ 2154 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5k"); 2155 return; 2156 } 2157 2158 if (OSSA_PORT_VALID == (npipps & PORT_STATE_MASK)) 2159 { 2160 pPort->status &= ~PORT_INVALIDATING; 2161 saRoot->PortMap[portId].PortStatus &= ~PORT_INVALIDATING; 2162 } 2163 else 2164 { 2165 SA_DBG1(("siEventPhyUpRcvd: PortInvalid portID %d PortContext %p\n", portId, saRoot->PortMap[portId].PortContext)); 2166 } 2167 } 2168 2169 /* adjust the bit fields before callback */ 2170 phyId = (linkRate << SHIFT8) | phyId; 2171 /* report PhyId, NPIP, PortState */ 2172 phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16); 2173 ossaHwCB(agRoot, &(pPort->portContext), OSSA_HW_EVENT_SAS_PHY_UP, phyId, agNULL, &remoteIdentify); 2174 2175 /* set PHY_UP status */ 2176 PHY_STATUS_SET(pPhy, PHY_UP); 2177 2178 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5k"); 2179 2180 /* return */ 2181 return; 2182} 2183 2184/******************************************************************************/ 2185/*! \brief Routine to handle for received SATA signature event 2186 * 2187 * The handle for received SATA signature event 2188 * 2189 * \param agRoot handles for this instance of SAS/SATA hardware 2190 * \param phyId the phy id of the phy received the frame 2191 * \param pMsg the pointer to the message payload 2192 * \param portId the port context index of the phy up event 2193 * \param deviceId the device context index 2194 * \param linkRate link up rate from SPC 2195 * 2196 * \return -void- 2197 */ 2198/*******************************************************************************/ 2199GLOBAL void siEventSATASignatureRcvd( 2200 agsaRoot_t *agRoot, 2201 bit32 phyId, 2202 void *pMsg, 2203 bit32 portId, 2204 bit32 npipps, 2205 bit8 linkRate 2206 ) 2207{ 2208 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 2209 agsaPhy_t *pPhy = &(saRoot->phys[phyId]); 2210 agsaPort_t *pPort = agNULL; 2211 agsaPortContext_t *agPortContext; 2212#if defined(SALLSDK_DEBUG) 2213 agsaFisRegDeviceToHost_t *fisD2H; 2214 /* Read the D2H FIS */ 2215 fisD2H = (agsaFisRegDeviceToHost_t *)pMsg; 2216#endif /* SALLSDK_DEBUG */ 2217 2218 smTraceFuncEnter(hpDBG_VERY_LOUD,"5m"); 2219 2220 SA_DBG5(("siEventSATASignatureRcvd: About to read the signatureFIS data\n")); 2221 2222 2223 SA_DBG5(("agsaFisRegDeviceToHost_t:\n")); 2224 SA_DBG5((" fisType = %x\n", fisD2H->h.fisType)); 2225 SA_DBG5((" i_pmPort = %x\n", fisD2H->h.i_pmPort)); 2226 SA_DBG5((" status = %x\n", fisD2H->h.status)); 2227 SA_DBG5((" error = %x\n", fisD2H->h.error)); 2228 2229 SA_DBG5((" lbaLow = %x\n", fisD2H->d.lbaLow)); 2230 SA_DBG5((" lbaMid = %x\n", fisD2H->d.lbaMid)); 2231 SA_DBG5((" lbaHigh = %x\n", fisD2H->d.lbaHigh)); 2232 SA_DBG5((" device = %x\n", fisD2H->d.device)); 2233 2234 SA_DBG5((" lbaLowExp = %x\n", fisD2H->d.lbaLowExp)); 2235 SA_DBG5((" lbaMidExp = %x\n", fisD2H->d.lbaMidExp)); 2236 SA_DBG5((" lbaHighExp = %x\n", fisD2H->d.lbaHighExp)); 2237 SA_DBG5((" reserved4 = %x\n", fisD2H->d.reserved4)); 2238 2239 SA_DBG5((" sectorCount = %x\n", fisD2H->d.sectorCount)); 2240 SA_DBG5((" sectorCountExp = %x\n", fisD2H->d.sectorCountExp)); 2241 SA_DBG5((" reserved5 = %x\n", fisD2H->d.reserved5)); 2242 SA_DBG5((" reserved6 = %x\n", fisD2H->d.reserved6)); 2243 2244 SA_DBG5((" reserved7 (32) = %08X\n", fisD2H->d.reserved7)); 2245 2246 SA_DBG5(("siEventSATASignatureRcvd: GOOD signatureFIS data\n")); 2247 2248#if defined(SALLSDK_DEBUG) 2249 /* read signature */ 2250 pPhy->remoteSignature[0] = (bit8) fisD2H->d.sectorCount; 2251 pPhy->remoteSignature[1] = (bit8) fisD2H->d.lbaLow; 2252 pPhy->remoteSignature[2] = (bit8) fisD2H->d.lbaMid; 2253 pPhy->remoteSignature[3] = (bit8) fisD2H->d.lbaHigh; 2254 pPhy->remoteSignature[4] = (bit8) fisD2H->d.device; 2255#endif 2256 2257 /* get port context from portMap */ 2258 SA_DBG2(("siEventSATASignatureRcvd:PortID 0x%x PortStatus 0x%x PortContext %p\n",saRoot->PortMap[portId & PORTID_MASK].PortID,saRoot->PortMap[portId & PORTID_MASK].PortStatus,saRoot->PortMap[portId & PORTID_MASK].PortContext)); 2259 agPortContext = (agsaPortContext_t *)saRoot->PortMap[portId].PortContext; 2260 2261 SA_DBG2(("siEventSATASignatureRcvd: portID %d PortContext %p\n", portId, agPortContext)); 2262 2263 if (agNULL != agPortContext) 2264 { 2265 /* exist port */ 2266 pPort = (agsaPort_t *) (agPortContext->sdkData); 2267 pPort->portId = portId; 2268 2269 /* include the phy to the port */ 2270 pPort->phyMap[phyId] = agTRUE; 2271 /* Set the port for the phy */ 2272 saRoot->phys[phyId].pPort = pPort; 2273 } 2274 else 2275 { 2276 ossaSingleThreadedEnter(agRoot, LL_PORT_LOCK); 2277 /* new port */ 2278 /* Allocate a free port */ 2279 pPort = (agsaPort_t *) saLlistGetHead(&(saRoot->freePorts)); 2280 if (agNULL != pPort) 2281 { 2282 /* Acquire port list lock */ 2283 saLlistRemove(&(saRoot->freePorts), &(pPort->linkNode)); 2284 2285 /* setup the port data structure */ 2286 pPort->portContext.osData = agNULL; 2287 pPort->portContext.sdkData = pPort; 2288 2289 /* Add to valid port list */ 2290 saLlistAdd(&(saRoot->validPorts), &(pPort->linkNode)); 2291 /* Release port list lock */ 2292 ossaSingleThreadedLeave(agRoot, LL_PORT_LOCK); 2293 2294 /* include the phy to the port */ 2295 pPort->phyMap[phyId] = agTRUE; 2296 /* Set the port for the phy */ 2297 saRoot->phys[phyId].pPort = pPort; 2298 2299 /* Setup portMap based on portId */ 2300 saRoot->PortMap[portId].PortID = portId; 2301 saRoot->PortMap[portId].PortContext = &(pPort->portContext); 2302 pPort->portId = portId; 2303 SA_DBG3(("siEventSATASignatureRcvd: NewPort portID %d portContect %p\n", portId, saRoot->PortMap[portId].PortContext)); 2304 } 2305 else 2306 { 2307 ossaSingleThreadedLeave(agRoot, LL_PORT_LOCK); 2308 /* pPort is agNULL*/ 2309 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5m"); 2310 return; 2311 } 2312 2313 if (OSSA_PORT_VALID == (npipps & PORT_STATE_MASK)) 2314 { 2315 pPort->status &= ~PORT_INVALIDATING; 2316 saRoot->PortMap[portId].PortStatus &= ~PORT_INVALIDATING; 2317 } 2318 else 2319 { 2320 SA_DBG1(("siEventSATASignatureRcvd: PortInvalid portID %d PortContext %p\n", portId, saRoot->PortMap[portId].PortContext)); 2321 } 2322 } 2323 2324 /* adjust the bit fields before callback */ 2325 phyId = (linkRate << SHIFT8) | phyId; 2326 /* report PhyId, NPIP, PortState */ 2327 phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16); 2328 ossaHwCB(agRoot, &(pPort->portContext), OSSA_HW_EVENT_SATA_PHY_UP, phyId, agNULL, pMsg); 2329 2330 /* set PHY_UP status */ 2331 PHY_STATUS_SET(pPhy, PHY_UP); 2332 2333 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5m"); 2334 2335 /* return */ 2336 return; 2337} 2338 2339 2340/******************************************************************************/ 2341/*! \brief Process Outbound IOMB Message 2342 * 2343 * Process Outbound IOMB from SPC 2344 * 2345 * \param agRoot Handles for this instance of SAS/SATA LL Layer 2346 * \param pMsg1 Pointer of Response IOMB message 1 2347 * \param category category of outbpond IOMB header 2348 * \param opcode Opcode of Outbound IOMB header 2349 * \param bc buffer count of IOMB header 2350 * 2351 * \return success or fail 2352 * 2353 */ 2354/*******************************************************************************/ 2355GLOBAL bit32 mpiParseOBIomb( 2356 agsaRoot_t *agRoot, 2357 bit32 *pMsg1, 2358 mpiMsgCategory_t category, 2359 bit16 opcode 2360 ) 2361{ 2362 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 2363 bit32 ret = AGSA_RC_SUCCESS; 2364 bit32 parserStatus = AGSA_RC_SUCCESS; 2365 2366 smTraceFuncEnter(hpDBG_VERY_LOUD, "2f"); 2367 2368 switch (opcode) 2369 { 2370 case OPC_OUB_COMBINED_SSP_COMP: 2371 { 2372 agsaSSPCoalescedCompletionRsp_t *pIomb = (agsaSSPCoalescedCompletionRsp_t *)pMsg1; 2373 agsaIORequestDesc_t *pRequest = agNULL; 2374 bit32 tag = 0; 2375 bit32 sspTag = 0; 2376 bit32 count = 0; 2377 2378#ifdef SALL_API_TEST 2379 saRoot->LLCounters.IOCounter.numSSPCompleted++; 2380 SA_DBG3(("mpiParseOBIomb, SSP_COMP Response received IOMB=%p %d\n", 2381 pMsg1, saRoot->LLCounters.IOCounter.numSSPCompleted)); 2382#else 2383 SA_DBG3(("mpiParseOBIomb, OPC_OUB_COMBINED_SSP_COMP Response received IOMB=%p\n", pMsg1)); 2384#endif 2385 /* get Tag */ 2386 for (count = 0; count < pIomb->coalescedCount; count++) 2387 { 2388 tag = pIomb->sspComplCxt[count].tag; 2389 sspTag = pIomb->sspComplCxt[count].SSPTag; 2390 pRequest = (agsaIORequestDesc_t *)saRoot->IOMap[tag].IORequest; 2391 SA_ASSERT((pRequest), "pRequest"); 2392 2393 if(pRequest == agNULL) 2394 { 2395 SA_DBG1(("mpiParseOBIomb,OPC_OUB_COMBINED_SSP_COMP Resp IOMB tag=0x%x, status=0x%x, param=0x%x, SSPTag=0x%x\n", tag, OSSA_IO_SUCCESS, 0, sspTag)); 2396#ifdef SA_ENABLE_PCI_TRIGGER 2397 if( saRoot->swConfig.PCI_trigger & PCI_TRIGGER_COAL_IOMB_ERROR ) 2398 { 2399 siPCITriger(agRoot); 2400 } 2401#endif /* SA_ENABLE_PCI_TRIGGER */ 2402 return(AGSA_RC_FAILURE); 2403 } 2404 SA_ASSERT((pRequest->valid), "pRequest->valid"); 2405 2406#ifdef SA_ENABLE_PCI_TRIGGER 2407 if(!pRequest->valid) 2408 { 2409 if( saRoot->swConfig.PCI_trigger & PCI_TRIGGER_COAL_INVALID ) 2410 { 2411 siPCITriger(agRoot); 2412 } 2413 } 2414#endif /* SA_ENABLE_PCI_TRIGGER */ 2415 2416 2417 SA_DBG3(("mpiParseOBIomb, OPC_OUB_COMBINED_SSP_COMP IOMB tag=0x%x, status=0x%x, param=0x%x, SSPTag=0x%x\n", tag, OSSA_IO_SUCCESS, 0, sspTag)); 2418 2419 /* Completion of SSP without Response Data */ 2420 siIODone( agRoot, pRequest, OSSA_IO_SUCCESS, sspTag); 2421 } 2422 } 2423 break; 2424 2425 case OPC_OUB_SSP_COMP: 2426 { 2427#ifdef SALL_API_TEST 2428 saRoot->LLCounters.IOCounter.numSSPCompleted++; 2429 SA_DBG3(("mpiParseOBIomb, SSP_COMP Response received IOMB=%p %d\n", 2430 pMsg1, saRoot->LLCounters.IOCounter.numSSPCompleted)); 2431#else 2432 SA_DBG3(("mpiParseOBIomb, SSP_COMP Response received IOMB=%p\n", pMsg1)); 2433#endif 2434 /* process the SSP IO Completed response message */ 2435 mpiSSPCompletion(agRoot, pMsg1); 2436 break; 2437 } 2438 case OPC_OUB_COMBINED_SATA_COMP: 2439 { 2440 agsaSATACoalescedCompletionRsp_t *pIomb; 2441 agsaIORequestDesc_t *pRequest; 2442 bit32 tag; 2443 bit32 count; 2444 2445 #ifdef SALL_API_TEST 2446 saRoot->LLCounters.IOCounter.numSSPCompleted++; 2447 SA_DBG3(("mpiParseOBIomb, OPC_OUB_COMBINED_SATA_COMP Response received IOMB=%p %d\n", 2448 pMsg1, saRoot->LLCounters.IOCounter.numSSPCompleted)); 2449 #else 2450 SA_DBG3(("mpiParseOBIomb, OPC_OUB_COMBINED_SATA_COMP Response received IOMB=%p\n", pMsg1)); 2451 #endif 2452 2453 pIomb = (agsaSATACoalescedCompletionRsp_t *)pMsg1; 2454 /* get Tag */ 2455 for (count = 0; count < pIomb->coalescedCount; count++) 2456 { 2457 tag = pIomb->stpComplCxt[count].tag; 2458 pRequest = (agsaIORequestDesc_t *)saRoot->IOMap[tag].IORequest; 2459 SA_ASSERT((pRequest), "pRequest"); 2460 2461 if(pRequest == agNULL) 2462 { 2463 SA_DBG1(("mpiParseOBIomb,OPC_OUB_COMBINED_SATA_COMP Resp IOMB tag=0x%x, status=0x%x, param=0x%x\n", tag, OSSA_IO_SUCCESS, 0)); 2464 return(AGSA_RC_FAILURE); 2465 } 2466 SA_ASSERT((pRequest->valid), "pRequest->valid"); 2467 2468 SA_DBG3(("mpiParseOBIomb, OPC_OUB_COMBINED_SATA_COMP IOMB tag=0x%x, status=0x%x, param=0x%x\n", tag, OSSA_IO_SUCCESS, 0)); 2469 2470 /* Completion of SATA without Response Data */ 2471 siIODone( agRoot, pRequest, OSSA_IO_SUCCESS, 0); 2472 } 2473 break; 2474 } 2475 case OPC_OUB_SATA_COMP: 2476 { 2477#ifdef SALL_API_TEST 2478 saRoot->LLCounters.IOCounter.numSataCompleted++; 2479 SA_DBG3(("mpiParseOBIomb, SATA_COMP Response received IOMB=%p %d\n", 2480 pMsg1, saRoot->LLCounters.IOCounter.numSataCompleted)); 2481#else 2482 SA_DBG3(("mpiParseOBIomb, SATA_COMP Response received IOMB=%p\n", pMsg1)); 2483#endif 2484 /* process the response message */ 2485 mpiSATACompletion(agRoot, pMsg1); 2486 break; 2487 } 2488 case OPC_OUB_SSP_ABORT_RSP: 2489 { 2490#ifdef SALL_API_TEST 2491 saRoot->LLCounters.IOCounter.numSSPAbortedCB++; 2492#else 2493 SA_DBG3(("mpiParseOBIomb, SSP_ABORT Response received IOMB=%p\n", pMsg1)); 2494#endif 2495 /* process the response message */ 2496 parserStatus = mpiSSPAbortRsp(agRoot, (agsaSSPAbortRsp_t *)pMsg1); 2497 if(parserStatus != AGSA_RC_SUCCESS) 2498 { 2499 SA_DBG3(("mpiParseOBIomb, mpiSSPAbortRsp FAIL IOMB=%p\n", pMsg1)); 2500 } 2501 2502 break; 2503 } 2504 case OPC_OUB_SATA_ABORT_RSP: 2505 { 2506#ifdef SALL_API_TEST 2507 saRoot->LLCounters.IOCounter.numSataAbortedCB++; 2508#else 2509 SA_DBG3(("mpiParseOBIomb, SATA_ABORT Response received IOMB=%p\n", pMsg1)); 2510#endif 2511 /* process the response message */ 2512 mpiSATAAbortRsp(agRoot, (agsaSATAAbortRsp_t *)pMsg1); 2513 break; 2514 } 2515 case OPC_OUB_SATA_EVENT: 2516 { 2517 SA_DBG3(("mpiParseOBIomb, SATA_EVENT Response received IOMB=%p\n", pMsg1)); 2518 /* process the response message */ 2519 mpiSATAEvent(agRoot, (agsaSATAEventRsp_t *)pMsg1); 2520 break; 2521 } 2522 case OPC_OUB_SSP_EVENT: 2523 { 2524 SA_DBG3(("mpiParseOBIomb, SSP_EVENT Response received IOMB=%p\n", pMsg1)); 2525 /* process the response message */ 2526 mpiSSPEvent(agRoot, (agsaSSPEventRsp_t *)pMsg1); 2527 break; 2528 } 2529 case OPC_OUB_SMP_COMP: 2530 { 2531#ifdef SALL_API_TEST 2532 saRoot->LLCounters.IOCounter.numSMPCompleted++; 2533 SA_DBG3(("mpiParseOBIomb, SMP_COMP Response received IOMB=%p, %d\n", 2534 pMsg1, saRoot->LLCounters.IOCounter.numSMPCompleted)); 2535#else 2536 SA_DBG3(("mpiParseOBIomb, SMP_COMP Response received IOMB=%p\n", pMsg1)); 2537#endif 2538 /* process the response message */ 2539 mpiSMPCompletion(agRoot, (agsaSMPCompletionRsp_t *)pMsg1); 2540 break; 2541 } 2542 case OPC_OUB_ECHO: 2543 { 2544#ifdef SALL_API_TEST 2545 saRoot->LLCounters.IOCounter.numEchoCB++; 2546 SA_DBG3(("mpiParseOBIomb, ECHO Response received %d\n", saRoot->LLCounters.IOCounter.numEchoCB)); 2547#else 2548 SA_DBG3(("mpiParseOBIomb, ECHO Response received\n")); 2549#endif 2550 /* process the response message */ 2551 mpiEchoRsp(agRoot, (agsaEchoRsp_t *)pMsg1); 2552 break; 2553 } 2554 case OPC_OUB_GET_NVMD_DATA: 2555 { 2556 SA_DBG3(("mpiParseOBIomb, OPC_OUB_GET_NVMD_DATA received IOMB=%p\n", pMsg1)); 2557 /* process the response message */ 2558 mpiGetNVMDataRsp(agRoot, (agsaGetNVMDataRsp_t *)pMsg1); 2559 break; 2560 } 2561 case OPC_OUB_SPC_HW_EVENT: 2562 { 2563 SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); 2564 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SPC_HW_EVENT Response received IOMB=%p\n", pMsg1)); 2565 /* process the response message */ 2566 mpiHWevent(agRoot, (agsaHWEvent_SPC_OUB_t *)pMsg1); 2567 break; 2568 } 2569 case OPC_OUB_HW_EVENT: 2570 { 2571 SA_DBG3(("mpiParseOBIomb, HW_EVENT Response received IOMB=%p\n", pMsg1)); 2572 /* process the response message */ 2573 mpiHWevent(agRoot, (agsaHWEvent_SPC_OUB_t *)pMsg1); 2574 break; 2575 } 2576 case OPC_OUB_PHY_START_RESPONSE: 2577 { 2578 SA_DBG1(("mpiParseOBIomb, OPC_OUB_PHY_START_RESPONSE Response received IOMB=%p\n", pMsg1)); 2579 /* process the response message */ 2580 mpiPhyStartEvent( agRoot, (agsaHWEvent_Phy_OUB_t *)pMsg1 ); 2581 2582 break; 2583 } 2584 case OPC_OUB_PHY_STOP_RESPONSE: 2585 { 2586 SA_DBG1(("mpiParseOBIomb, OPC_OUB_PHY_STOP_RESPONSE Response received IOMB=%p\n", pMsg1)); 2587 /* process the response message */ 2588 mpiPhyStopEvent( agRoot, (agsaHWEvent_Phy_OUB_t *)pMsg1 ); 2589 break; 2590 } 2591 2592 case OPC_OUB_LOCAL_PHY_CNTRL: 2593 { 2594 SA_DBG3(("mpiParseOBIomb, PHY CONTROL Response received IOMB=%p\n", pMsg1)); 2595 /* process the response message */ 2596 mpiPhyCntrlRsp(agRoot, (agsaLocalPhyCntrlRsp_t *)pMsg1); 2597 break; 2598 } 2599 case OPC_OUB_SPC_DEV_REGIST: 2600 { 2601 SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); 2602 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SPC_DEV_REGIST Response received IOMB=%p\n", pMsg1)); 2603 /* process the response message */ 2604 mpiDeviceRegRsp(agRoot, (agsaDeviceRegistrationRsp_t *)pMsg1); 2605 break; 2606 } 2607 case OPC_OUB_DEV_REGIST: 2608 { 2609 SA_DBG2(("mpiParseOBIomb, DEV_REGISTRATION Response received IOMB=%p\n", pMsg1)); 2610 /* process the response message */ 2611 mpiDeviceRegRsp(agRoot, (agsaDeviceRegistrationRsp_t *)pMsg1); 2612 break; 2613 } 2614 case OPC_OUB_DEREG_DEV: 2615 { 2616 SA_DBG3(("mpiParseOBIomb, DEREGISTRATION DEVICE Response received IOMB=%p\n", pMsg1)); 2617 /* process the response message */ 2618 mpiDeregDevHandleRsp(agRoot, (agsaDeregDevHandleRsp_t *)pMsg1); 2619 break; 2620 } 2621 case OPC_OUB_GET_DEV_HANDLE: 2622 { 2623 SA_DBG3(("mpiParseOBIomb, GET_DEV_HANDLE Response received IOMB=%p\n", pMsg1)); 2624 /* process the response message */ 2625 mpiGetDevHandleRsp(agRoot, (agsaGetDevHandleRsp_t *)pMsg1); 2626 break; 2627 } 2628 case OPC_OUB_SPC_DEV_HANDLE_ARRIV: 2629 { 2630 SA_DBG3(("mpiParseOBIomb, SPC_DEV_HANDLE_ARRIV Response received IOMB=%p\n", pMsg1)); 2631 /* process the response message */ 2632 mpiDeviceHandleArrived(agRoot, (agsaDeviceHandleArrivedNotify_t *)pMsg1); 2633 break; 2634 } 2635 case OPC_OUB_DEV_HANDLE_ARRIV: 2636 { 2637 SA_DBG3(("mpiParseOBIomb, DEV_HANDLE_ARRIV Response received IOMB=%p\n", pMsg1)); 2638 /* process the response message */ 2639 mpiDeviceHandleArrived(agRoot, (agsaDeviceHandleArrivedNotify_t *)pMsg1); 2640 break; 2641 } 2642 case OPC_OUB_SSP_RECV_EVENT: 2643 { 2644 SA_DBG3(("mpiParseOBIomb, SSP_RECV_EVENT Response received IOMB=%p\n", pMsg1)); 2645 /* process the response message */ 2646 mpiSSPReqReceivedNotify(agRoot, (agsaSSPReqReceivedNotify_t *)pMsg1); 2647 break; 2648 } 2649 case OPC_OUB_DEV_INFO: 2650 { 2651 SA_ASSERT((smIS_SPCV(agRoot)), "smIS_SPCV"); 2652 SA_DBG3(("mpiParseOBIomb, DEV_INFO Response received IOMB=%p\n", pMsg1)); 2653 /* process the response message */ 2654 mpiGetDevInfoRsp(agRoot, (agsaGetDevInfoRspV_t *)pMsg1); 2655 break; 2656 } 2657 case OPC_OUB_GET_PHY_PROFILE_RSP: 2658 { 2659 SA_ASSERT((smIS_SPCV(agRoot)), "smIS_SPCV"); 2660 SA_DBG2(("mpiParseOBIomb, OPC_OUB_GET_PHY_PROFILE_RSP Response received IOMB=%p\n", pMsg1)); 2661 /* process the response message */ 2662 mpiGetPhyProfileRsp(agRoot, (agsaGetPhyProfileRspV_t *)pMsg1); 2663 break; 2664 } 2665 case OPC_OUB_SET_PHY_PROFILE_RSP: 2666 { 2667 SA_ASSERT((smIS_SPCV(agRoot)), "smIS_SPCV"); 2668 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_PHY_PROFILE_RSP Response received IOMB=%p\n", pMsg1)); 2669 /* process the response message */ 2670 mpiSetPhyProfileRsp(agRoot, (agsaSetPhyProfileRspV_t *)pMsg1); 2671 break; 2672 } 2673 case OPC_OUB_SPC_DEV_INFO: 2674 { 2675 SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); 2676 SA_DBG3(("mpiParseOBIomb, DEV_INFO Response received IOMB=%p\n", pMsg1)); 2677 /* process the response message */ 2678 mpiGetDevInfoRspSpc(agRoot, (agsaGetDevInfoRsp_t *)pMsg1); 2679 break; 2680 } 2681 case OPC_OUB_FW_FLASH_UPDATE: 2682 { 2683 SA_DBG3(("mpiParseOBIomb, OPC_OUB_FW_FLASH_UPDATE Response received IOMB=%p\n", pMsg1)); 2684 /* process the response message */ 2685 mpiFwFlashUpdateRsp(agRoot, (agsaFwFlashUpdateRsp_t *)pMsg1); 2686 break; 2687 } 2688 case OPC_OUB_FLASH_OP_EXT_RSP: 2689 { 2690 SA_DBG3(("mpiParseOBIomb, OPC_OUB_FLASH_OP_EXT_RSP Response received IOMB=%p\n", pMsg1)); 2691 /* process the response message */ 2692 mpiFwExtFlashUpdateRsp(agRoot, (agsaFwFlashOpExtRsp_t *)pMsg1); 2693 break; 2694 } 2695#ifdef SPC_ENABLE_PROFILE 2696 case OPC_OUB_FW_PROFILE: 2697 { 2698 SA_DBG3(("mpiParseOBIomb, OPC_OUB_FW_PROFILE Response received IOMB=%p\n", pMsg1)); 2699 /* process the response message */ 2700 mpiFwProfileRsp(agRoot, (agsaFwProfileRsp_t *)pMsg1); 2701 break; 2702 } 2703#endif 2704 case OPC_OUB_SET_NVMD_DATA: 2705 { 2706 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_NVMD_DATA received IOMB=%p\n", pMsg1)); 2707 /* process the response message */ 2708 mpiSetNVMDataRsp(agRoot, (agsaSetNVMDataRsp_t *)pMsg1); 2709 break; 2710 } 2711 case OPC_OUB_GPIO_RESPONSE: 2712 { 2713 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_GPIO_RESPONSE Response received IOMB=%p\n", pMsg1)); 2714 /* process the response message */ 2715 mpiGPIORsp(agRoot, (agsaGPIORsp_t *)pMsg1); 2716 break; 2717 } 2718 case OPC_OUB_GPIO_EVENT: 2719 { 2720 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_GPIO_RESPONSE Response received IOMB=%p\n", pMsg1)); 2721 /* process the response message */ 2722 mpiGPIOEventRsp(agRoot, (agsaGPIOEvent_t *)pMsg1); 2723 break; 2724 } 2725 case OPC_OUB_GENERAL_EVENT: 2726 { 2727 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_GENERAL_EVENT Response received IOMB=%p\n", pMsg1)); 2728 /* process the response message */ 2729 mpiGeneralEventRsp(agRoot, (agsaGeneralEventRsp_t *)pMsg1); 2730 break; 2731 } 2732 case OPC_OUB_SAS_DIAG_MODE_START_END: 2733 { 2734 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SAS_DIAG_MODE_START_END Response received IOMB=%p\n", pMsg1)); 2735 /* process the response message */ 2736 mpiSASDiagStartEndRsp(agRoot, (agsaSASDiagStartEndRsp_t *)pMsg1); 2737 break; 2738 } 2739 case OPC_OUB_SAS_DIAG_EXECUTE: 2740 { 2741 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SAS_DIAG_EXECUTE_RSP Response received IOMB=%p\n", pMsg1)); 2742 /* process the response message */ 2743 mpiSASDiagExecuteRsp(agRoot, (agsaSASDiagExecuteRsp_t *)pMsg1); 2744 break; 2745 } 2746 case OPC_OUB_GET_TIME_STAMP: 2747 { 2748 SA_DBG3(("mpiParseOBIomb, OPC_OUB_GET_TIME_STAMP Response received IOMB=%p\n", pMsg1)); 2749 /* process the response message */ 2750 mpiGetTimeStampRsp(agRoot, (agsaGetTimeStampRsp_t *)pMsg1); 2751 break; 2752 } 2753 2754 case OPC_OUB_SPC_SAS_HW_EVENT_ACK: 2755 { 2756 SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); 2757 SA_DBG3(("mpiParseOBIomb,OPC_OUB_SPC_SAS_HW_EVENT_ACK Response received IOMB=%p\n", pMsg1)); 2758 /* process the response message */ 2759 mpiSASHwEventAckRsp(agRoot, (agsaSASHwEventAckRsp_t *)pMsg1); 2760 break; 2761 } 2762 2763 case OPC_OUB_SAS_HW_EVENT_ACK: 2764 { 2765 SA_ASSERT((smIS_SPCV(agRoot)), "smIS_SPCV"); 2766 SA_DBG1(("mpiParseOBIomb, OPC_OUB_SAS_HW_EVENT_ACK Response received IOMB=%p\n", pMsg1)); 2767 /* process the response message */ 2768 mpiSASHwEventAckRsp(agRoot, (agsaSASHwEventAckRsp_t *)pMsg1); 2769 break; 2770 } 2771 case OPC_OUB_PORT_CONTROL: 2772 { 2773 SA_DBG1(("mpiParseOBIomb, OPC_OUB_PORT_CONTROL Response received IOMB=%p\n", pMsg1)); 2774 /* process the response message */ 2775 mpiPortControlRsp(agRoot, (agsaPortControlRsp_t *)pMsg1); 2776 break; 2777 } 2778 case OPC_OUB_SMP_ABORT_RSP: 2779 { 2780#ifdef SALL_API_TEST 2781 saRoot->LLCounters.IOCounter.numSMPAbortedCB++; 2782 SA_DBG3(("mpiParseOBIomb, SMP_ABORT Response received IOMB=%p, %d\n", 2783 pMsg1, saRoot->LLCounters.IOCounter.numSMPAbortedCB)); 2784#else 2785 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SMP_ABORT_RSP Response received IOMB=%p\n", pMsg1)); 2786#endif 2787 /* process the response message */ 2788 mpiSMPAbortRsp(agRoot, (agsaSMPAbortRsp_t *)pMsg1); 2789 break; 2790 } 2791 case OPC_OUB_DEVICE_HANDLE_REMOVAL: 2792 { 2793 SA_DBG3(("mpiParseOBIomb, OPC_OUB_DEVICE_HANDLE_REMOVAL received IOMB=%p\n", pMsg1)); 2794 /* process the response message */ 2795 mpiDeviceHandleRemoval(agRoot, (agsaDeviceHandleRemoval_t *)pMsg1); 2796 break; 2797 } 2798 case OPC_OUB_SET_DEVICE_STATE: 2799 { 2800 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_DEVICE_STATE received IOMB=%p\n", pMsg1)); 2801 /* process the response message */ 2802 mpiSetDeviceStateRsp(agRoot, (agsaSetDeviceStateRsp_t *)pMsg1); 2803 break; 2804 } 2805 case OPC_OUB_GET_DEVICE_STATE: 2806 { 2807 SA_DBG3(("mpiParseOBIomb, OPC_OUB_GET_DEVICE_STATE received IOMB=%p\n", pMsg1)); 2808 /* process the response message */ 2809 mpiGetDeviceStateRsp(agRoot, (agsaGetDeviceStateRsp_t *)pMsg1); 2810 break; 2811 } 2812 case OPC_OUB_SET_DEV_INFO: 2813 { 2814 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_DEV_INFO received IOMB=%p\n", pMsg1)); 2815 /* process the response message */ 2816 mpiSetDevInfoRsp(agRoot, (agsaSetDeviceInfoRsp_t *)pMsg1); 2817 break; 2818 } 2819 case OPC_OUB_SAS_RE_INITIALIZE: 2820 { 2821 SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); 2822 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SAS_RE_INITIALIZE received IOMB=%p\n", pMsg1)); 2823 /* process the response message */ 2824 mpiSasReInitializeRsp(agRoot, (agsaSasReInitializeRsp_t *)pMsg1); 2825 break; 2826 } 2827 2828 case OPC_OUB_SGPIO_RESPONSE: 2829 { 2830 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SGPIO_RESPONSE Response received IOMB=%p\n", pMsg1)); 2831 /* process the response message */ 2832 mpiSGpioRsp(agRoot, (agsaSGpioRsp_t *)pMsg1); 2833 break; 2834 } 2835 2836 case OPC_OUB_PCIE_DIAG_EXECUTE: 2837 { 2838 SA_DBG3(("mpiParseOBIomb, OPC_OUB_PCIE_DIAG_EXECUTE Response received IOMB=%p\n", pMsg1)); 2839 /* process the response message */ 2840 mpiPCIeDiagExecuteRsp(agRoot, (agsaPCIeDiagExecuteRsp_t *)pMsg1); 2841 break; 2842 } 2843 2844 case OPC_OUB_GET_VIST_CAP_RSP: 2845 { 2846 SA_DBG3(("mpiParseOBIomb, OPC_INB_GET_VIST_CAP Response received IOMB=%p\n", pMsg1)); 2847 /* process the response message */ 2848 mpiGetVHistRsp(agRoot, (agsaGetVHistCapRsp_t *)pMsg1); 2849 break; 2850 } 2851 case 2104: 2852 { 2853 if(smIS_SPC6V(agRoot)) 2854 { 2855 SA_DBG3(("mpiParseOBIomb, OPC_OUB_GET_DFE_DATA_RSP Response received IOMB=%p\n", pMsg1)); 2856 /* process the response message */ 2857 mpiGetDFEDataRsp(agRoot, (agsaGetDDEFDataRsp_t *)pMsg1); 2858 } 2859 if(smIS_SPC12V(agRoot)) 2860 { 2861 SA_DBG3(("mpiParseOBIomb, OPC_INB_GET_VIST_CAP Response received IOMB=%p\n", pMsg1)); 2862 /* process the response message */ 2863 mpiGetVHistRsp(agRoot, (agsaGetVHistCapRsp_t *)pMsg1); 2864 } 2865 else 2866 { 2867 SA_DBG1(("mpiParseOBIomb, 2104 Response received IOMB=%p\n", pMsg1)); 2868 /* process the response message */ 2869 } 2870 break; 2871 } 2872 case OPC_OUB_SET_CONTROLLER_CONFIG: 2873 { 2874 SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_CONTROLLER_CONFIG Response received IOMB=%p\n", pMsg1)); 2875 mpiSetControllerConfigRsp(agRoot, (agsaSetControllerConfigRsp_t *)pMsg1); 2876 break; 2877 } 2878 case OPC_OUB_GET_CONTROLLER_CONFIG: 2879 { 2880 SA_DBG3(("mpiParseOBIomb, OPC_OUB_GET_CONTROLLER_CONFIG Response received IOMB=%p\n", pMsg1)); 2881 mpiGetControllerConfigRsp(agRoot, (agsaGetControllerConfigRsp_t *)pMsg1); 2882 break; 2883 } 2884 case OPC_OUB_KEK_MANAGEMENT: 2885 { 2886 SA_DBG3(("mpiParseOBIomb, OPC_OUB_KEK_MANAGEMENT Response received IOMB=%p\n", pMsg1)); 2887 mpiKekManagementRsp(agRoot, (agsaKekManagementRsp_t *)pMsg1); 2888 break; 2889 } 2890 case OPC_OUB_DEK_MANAGEMENT: 2891 { 2892 SA_DBG3(("mpiParseOBIomb, OPC_OUB_DEK_MANAGEMENT Response received IOMB=%p\n", pMsg1)); 2893 mpiDekManagementRsp(agRoot, (agsaDekManagementRsp_t *)pMsg1); 2894 break; 2895 } 2896 case OPC_OUB_OPR_MGMT: 2897 { 2898 SA_DBG1(("mpiParseOBIomb, OPC_OUB_OPR_MGMT Response received IOMB=%p\n", pMsg1)); 2899 mpiOperatorManagementRsp(agRoot, (agsaOperatorMangmenRsp_t *)pMsg1); 2900 break; 2901 } 2902 case OPC_OUB_ENC_TEST_EXECUTE: 2903 { 2904 SA_DBG1(("mpiParseOBIomb, OPC_OUB_ENC_TEST_EXECUTE Response received IOMB=%p\n", pMsg1)); 2905 mpiBistRsp(agRoot, (agsaEncryptBistRsp_t *)pMsg1); 2906 break; 2907 } 2908 case OPC_OUB_SET_OPERATOR: 2909 { 2910 SA_DBG1(("mpiParseOBIomb, OPC_OUB_SET_OPERATOR Response received IOMB=%p\n", pMsg1)); 2911 mpiSetOperatorRsp(agRoot, (agsaSetOperatorRsp_t *)pMsg1); 2912 break; 2913 } 2914 case OPC_OUB_GET_OPERATOR: 2915 { 2916 SA_DBG1(("mpiParseOBIomb, OPC_OUB_GET_OPERATOR Response received IOMB=%p\n", pMsg1)); 2917 mpiGetOperatorRsp(agRoot, (agsaGetOperatorRsp_t *)pMsg1); 2918 break; 2919 } 2920 case OPC_OUB_DIF_ENC_OFFLOAD_RSP: 2921 { 2922 SA_ASSERT((smIS_SPCV(agRoot)), "smIS_SPCV"); 2923 SA_DBG1(("mpiParseOBIomb, OPC_OUB_DIF_ENC_OFFLOAD_RSP Response received IOMB=%p\n", pMsg1)); 2924 /* process the response message */ 2925 mpiDifEncOffloadRsp(agRoot, (agsaDifEncOffloadRspV_t *)pMsg1); 2926 break; 2927 } 2928 default: 2929 { 2930#ifdef SALL_API_TEST 2931 saRoot->LLCounters.IOCounter.numUNKNWRespIOMB++; 2932 SA_DBG1(("mpiParseOBIomb, UnKnown Response received IOMB=%p, %d\n", 2933 pMsg1, saRoot->LLCounters.IOCounter.numUNKNWRespIOMB)); 2934#else 2935 SA_DBG1(("mpiParseOBIomb, Unknown IOMB Response received opcode 0x%X IOMB=%p\n",opcode, pMsg1)); 2936#endif 2937 break; 2938 } 2939 } /* switch */ 2940 2941 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2f"); 2942 2943 return ret; 2944 2945} 2946 2947 2948/******************************************************************************/ 2949/*! \brief SPC MPI SATA Completion 2950 * 2951 * This function handles the SATA completion. 2952 * 2953 * \param agRoot Handles for this instance of SAS/SATA LLL 2954 * \param pIomb1 Pointer of Message1 2955 * \param bc buffer count 2956 * 2957 * \return The read value 2958 * 2959 */ 2960/*******************************************************************************/ 2961GLOBAL FORCEINLINE 2962bit32 mpiSATACompletion( 2963 agsaRoot_t *agRoot, 2964 bit32 *pIomb1 2965 ) 2966{ 2967 bit32 ret = AGSA_RC_SUCCESS; 2968 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 2969 bit32 status; 2970 bit32 tag; 2971 bit32 param; 2972 agsaIORequestDesc_t *pRequest; 2973 bit32 *agFirstDword; 2974 bit32 *pResp; 2975 2976 smTraceFuncEnter(hpDBG_VERY_LOUD,"2s"); 2977 2978 OSSA_READ_LE_32(AGROOT, &tag, pIomb1, OSSA_OFFSET_OF(agsaSATACompletionRsp_t, tag)) ; 2979 OSSA_READ_LE_32(AGROOT, &status, pIomb1, OSSA_OFFSET_OF(agsaSATACompletionRsp_t, status)) ; 2980 OSSA_READ_LE_32(AGROOT, ¶m, pIomb1, OSSA_OFFSET_OF(agsaSATACompletionRsp_t, param)) ; 2981 2982 SA_DBG3(("mpiSATACompletion: start, HTAG=0x%x\n", tag)); 2983 2984 /* get IOrequest from IOMap */ 2985 pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; 2986 SA_ASSERT((pRequest), "pRequest"); 2987 2988 if(agNULL == pRequest) 2989 { 2990 SA_DBG1(("mpiSATACompletion: agNULL == pRequest tag 0x%X status 0x%X\n",tag, status )); 2991 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2s"); 2992 return AGSA_RC_FAILURE; 2993 } 2994 2995 SA_ASSERT((pRequest->valid), "pRequest->valid"); 2996 if(!pRequest->valid) 2997 { 2998 SA_DBG1(("mpiSATACompletion: not valid IOMB tag=0x%x status=0x%x param=0x%x Device =0x%x\n", tag, status, param, 2999 pRequest->pDevice ? pRequest->pDevice->DeviceMapIndex : -1)); 3000 } 3001 3002 switch (status) 3003 { 3004 case OSSA_IO_SUCCESS: 3005 { 3006 SA_DBG3(("mpiSATACompletion: OSSA_IO_SUCCESS, param=0x%x\n", param)); 3007 if (!param) 3008 { 3009 /* SATA request completion */ 3010 siIODone( agRoot, pRequest, OSSA_IO_SUCCESS, 0); 3011 } 3012 else 3013 { 3014 /* param number bytes of SATA Rsp */ 3015 agFirstDword = &pIomb1[3]; 3016 pResp = &pIomb1[4]; 3017 3018 /* CB function to the up layer */ 3019 /* Response Length not include firstDW */ 3020 saRoot->IoErrorCount.agOSSA_IO_COMPLETED_ERROR_SCSI_STATUS++; 3021 SA_DBG2(("mpiSATACompletion: param 0x%x agFirstDwordResp 0x%x Resp 0x%x tag 0x%x\n",param,*agFirstDword,*pResp ,tag)); 3022 siEventSATAResponseWtDataRcvd(agRoot, pRequest, agFirstDword, pResp, (param - 4)); 3023 } 3024 3025 break; 3026 } 3027 case OSSA_IO_ABORTED: 3028 { 3029 SA_DBG2(("mpiSATACompletion: OSSA_IO_ABORTED tag 0x%X\n", tag)); 3030 saRoot->IoErrorCount.agOSSA_IO_ABORTED++; 3031 siAbnormal(agRoot, pRequest, status, param, 0); 3032 break; 3033 } 3034 case OSSA_IO_UNDERFLOW: 3035 { 3036 /* SATA Completion with error */ 3037 SA_DBG1(("mpiSATACompletion, OSSA_IO_UNDERFLOW tag 0x%X\n", tag)); 3038 /*underflow means underrun, treat it as success*/ 3039 saRoot->IoErrorCount.agOSSA_IO_UNDERFLOW++; 3040 siAbnormal(agRoot, pRequest, status, param, 0); 3041 break; 3042 } 3043 case OSSA_IO_NO_DEVICE: 3044 { 3045 SA_DBG1(("mpiSATACompletion, OSSA_IO_NO_DEVICE tag 0x%X\n", tag)); 3046 saRoot->IoErrorCount.agOSSA_IO_NO_DEVICE++; 3047 siAbnormal(agRoot, pRequest, status, 0, 0); 3048 break; 3049 } 3050 case OSSA_IO_XFER_ERROR_BREAK: 3051 { 3052 SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_ERROR_BREAK SPC tag 0x%X\n", tag)); 3053 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_BREAK++; 3054 siAbnormal(agRoot, pRequest, status, 0, 0); 3055 break; 3056 } 3057 case OSSA_IO_XFER_ERROR_PHY_NOT_READY: 3058 { 3059 SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_ERROR_PHY_NOT_READY tag 0x%X\n", tag)); 3060 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_PHY_NOT_READY++; 3061 siAbnormal(agRoot, pRequest, status, 0, 0); 3062 break; 3063 } 3064 case OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 3065 { 3066 SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED tag 0x%X\n", tag)); 3067 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED++; 3068 siAbnormal(agRoot, pRequest, status, 0, 0); 3069 break; 3070 } 3071 case OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 3072 { 3073 SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION tag 0x%X\n", tag)); 3074 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION++; 3075 siAbnormal(agRoot, pRequest, status, 0, 0); 3076 break; 3077 } 3078 case OSSA_IO_OPEN_CNX_ERROR_BREAK: 3079 { 3080 SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_BREAK SPC tag 0x%X\n", tag)); 3081 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_BREAK++; 3082 siAbnormal(agRoot, pRequest, status, 0, 0); 3083 break; 3084 } 3085 case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 3086 { 3087 SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS tag 0x%X\n", tag)); 3088 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS++; 3089 siAbnormal(agRoot, pRequest, status, 0, 0); 3090 break; 3091 } 3092 case OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION: 3093 { 3094 SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION tag 0x%X\n", tag)); 3095 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION++; 3096 siAbnormal(agRoot, pRequest, status, 0, 0); 3097 break; 3098 } 3099 case OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 3100 { 3101 SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED tag 0x%X\n", tag)); 3102 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED++; 3103 siAbnormal(agRoot, pRequest, status, 0, 0); 3104 break; 3105 } 3106 case OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 3107 { 3108 SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY tag 0x%X\n", tag)); 3109 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY++; 3110 siAbnormal(agRoot, pRequest, status, 0, 0); 3111 break; 3112 } 3113 case OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 3114 { 3115 SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION tag 0x%X\n", tag)); 3116 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION++; 3117 siAbnormal(agRoot, pRequest, status, 0, 0); 3118 break; 3119 } 3120 case OSSA_IO_XFER_ERROR_NAK_RECEIVED: 3121 { 3122 SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_ERROR_NAK_RECEIVED tag 0x%X\n", tag)); 3123 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_NAK_RECEIVED++; 3124 siAbnormal(agRoot, pRequest, status, 0, 0); 3125 break; 3126 } 3127 case OSSA_IO_XFER_ERROR_DMA: 3128 { 3129 SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_ERROR_DMA tag 0x%X\n", tag)); 3130 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_DMA++; 3131 siAbnormal(agRoot, pRequest, status, 0, 0); 3132 break; 3133 } 3134 case OSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT: 3135 { 3136 SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT tag 0x%X\n", tag)); 3137 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT++; 3138 siAbnormal(agRoot, pRequest, status, 0, 0); 3139 break; 3140 } 3141 case OSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE: 3142 { 3143 SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE tag 0x%X\n", tag)); 3144 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE++; 3145 siAbnormal(agRoot, pRequest, status, 0, 0); 3146 break; 3147 } 3148 case OSSA_IO_XFER_OPEN_RETRY_TIMEOUT: 3149 { 3150 SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_OPEN_RETRY_TIMEOUT tag 0x%X\n", tag)); 3151 saRoot->IoErrorCount.agOSSA_IO_XFER_OPEN_RETRY_TIMEOUT++; 3152 siAbnormal(agRoot, pRequest, status, 0, 0); 3153 break; 3154 } 3155 case OSSA_IO_PORT_IN_RESET: 3156 { 3157 SA_DBG1(("mpiSATACompletion: OSSA_IO_PORT_IN_RESET tag 0x%X\n", tag)); 3158 saRoot->IoErrorCount.agOSSA_IO_PORT_IN_RESET++; 3159 siAbnormal(agRoot, pRequest, status, 0, 0); 3160 break; 3161 } 3162 case OSSA_IO_DS_NON_OPERATIONAL: 3163 { 3164 SA_DBG1(("mpiSATACompletion: OSSA_IO_DS_NON_OPERATIONAL tag 0x%X\n", tag)); 3165 saRoot->IoErrorCount.agOSSA_IO_DS_NON_OPERATIONAL++; 3166 siAbnormal(agRoot, pRequest, status, 0, 0); 3167 break; 3168 } 3169 case OSSA_IO_DS_IN_RECOVERY: 3170 { 3171 SA_DBG1(("mpiSATACompletion: OSSA_IO_DS_IN_RECOVERY tag 0x%X\n", tag)); 3172 saRoot->IoErrorCount.agOSSA_IO_DS_IN_RECOVERY++; 3173 siAbnormal(agRoot, pRequest, status, 0, 0); 3174 break; 3175 } 3176 case OSSA_IO_DS_IN_ERROR: 3177 { 3178 SA_DBG1(("mpiSATACompletion: OSSA_IO_DS_IN_ERROR tag 0x%X\n", tag)); 3179 saRoot->IoErrorCount.agOSSA_IO_DS_IN_ERROR++; 3180 siAbnormal(agRoot, pRequest, status, 0, 0); 3181 break; 3182 } 3183 3184 case OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 3185 { 3186 SA_DBG1(("mpiSATACompletion: OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY tag 0x%X\n", tag)); 3187 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY++; 3188 siAbnormal(agRoot, pRequest, status, 0, 0); 3189 break; 3190 } 3191 case OSSA_IO_ABORT_IN_PROGRESS: 3192 { 3193 SA_DBG1(("mpiSATACompletion: OSSA_IO_ABORT_IN_PROGRESS tag 0x%X\n", tag)); 3194 saRoot->IoErrorCount.agOSSA_IO_ABORT_IN_PROGRESS++; 3195 siAbnormal(agRoot, pRequest, status, 0, 0); 3196 break; 3197 } 3198 case OSSA_IO_ABORT_DELAYED: 3199 { 3200 SA_DBG1(("mpiSATACompletion: OSSA_IO_ABORT_DELAYED tag 0x%X\n", tag)); 3201 saRoot->IoErrorCount.agOSSA_IO_ABORT_DELAYED++; 3202 siAbnormal(agRoot, pRequest, status, 0, 0); 3203 break; 3204 } 3205 case OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT: 3206 { 3207 SA_DBG1(("mpiSATACompletion: OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT tag 0x%X\n", tag)); 3208 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT++; 3209 siAbnormal(agRoot, pRequest, status, 0, 0); 3210 break; 3211 } 3212 case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 3213 { 3214 SA_DBG1(("mpiSATACompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED HTAG = 0x%x\n", tag)); 3215 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED++; 3216 siAbnormal(agRoot, pRequest, status, 0, 0); 3217 break; 3218 } 3219 case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 3220 { 3221 SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO tag 0x%x\n", tag)); 3222 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO++; 3223 siAbnormal(agRoot, pRequest, status, 0, 0 ); 3224 break; 3225 } 3226 case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 3227 { 3228 SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST tag 0x%x\n", tag)); 3229 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST++; 3230 siAbnormal(agRoot, pRequest, status, 0, 0 ); 3231 break; 3232 } 3233 case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 3234 { 3235 SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE tag 0x%x\n", tag)); 3236 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE++; 3237 siAbnormal(agRoot, pRequest, status, 0, 0 ); 3238 break; 3239 } 3240 case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 3241 { 3242 SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED tag 0x%x\n", tag)); 3243 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED++; 3244 siAbnormal(agRoot, pRequest, status, 0, 0 ); 3245 break; 3246 } 3247 case OSSA_IO_DS_INVALID: 3248 { 3249 SA_DBG1(("mpiSATACompletion: OSSA_IO_DS_INVALID tag 0x%X\n", tag)); 3250 saRoot->IoErrorCount.agOSSA_IO_DS_INVALID++; 3251 siAbnormal(agRoot, pRequest, status, 0, 0); 3252 break; 3253 } 3254 case OSSA_IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR: 3255 { 3256 SA_DBG1(("mpiSATACompletion: OSSA_IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR tag 0x%X\n", tag)); 3257 saRoot->IoErrorCount.agOSSA_IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR++; 3258 siAbnormal(agRoot, pRequest, status, 0, 0); 3259 break; 3260 } 3261 case OSSA_MPI_IO_RQE_BUSY_FULL: 3262 { 3263 SA_DBG1(("mpiSATACompletion: OSSA_MPI_IO_RQE_BUSY_FULL tag 0x%X\n", tag)); 3264 saRoot->IoErrorCount.agOSSA_MPI_IO_RQE_BUSY_FULL++; 3265 siAbnormal(agRoot, pRequest, status, 0, 0); 3266 break; 3267 } 3268#ifdef REMOVED 3269 case OSSA_IO_XFER_ERR_EOB_DATA_OVERRUN: 3270 { 3271 SA_DBG1(("mpiSATACompletion: OSSA_IO_XFER_ERR_EOB_DATA_OVERRUN tag 0x%x\n", tag)); 3272 saRoot->IoErrorCount.agOSSA_IO_XFER_ERR_EOB_DATA_OVERRUN++; 3273 siAbnormal(agRoot, pRequest, status, 0, 0); 3274 break; 3275 } 3276#endif 3277 case OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE: 3278 { 3279 SA_DBG1(("mpiSATACompletion: OPC_OUB_SATA_COMP:OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE \n")); 3280 saRoot->IoErrorCount.agOSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE++; 3281 siAbnormal(agRoot, pRequest, status, 0, 0); 3282 break; 3283 } 3284 case OSSA_MPI_ERR_ATAPI_DEVICE_BUSY: 3285 { 3286 SA_DBG1(("mpiSATACompletion: OSSA_MPI_ERR_ATAPI_DEVICE_BUSY tag 0x%X\n", tag)); 3287 saRoot->IoErrorCount.agOSSA_MPI_ERR_ATAPI_DEVICE_BUSY++; 3288 siAbnormal(agRoot, pRequest, status, param, 0 ); 3289 break; 3290 } 3291 case OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS: 3292 { 3293 SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS tag 0x%X\n", tag)); 3294 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS++; 3295 siAbnormal(agRoot, pRequest, status, 0, 0); 3296 break; 3297 } 3298 case OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID: 3299 { 3300 SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID tag 0x%X\n", tag)); 3301 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS++; 3302 siAbnormal(agRoot, pRequest, status, 0, 0); 3303 break; 3304 } 3305 case OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH: 3306 { 3307 SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH tag 0x%X\n", tag)); 3308 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_IV_MISMATCH++; 3309 siAbnormal(agRoot, pRequest, status, 0, 0); 3310 break; 3311 } 3312 case OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR: 3313 { 3314 SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR tag 0x%X\n", tag)); 3315 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR++; 3316 siAbnormal(agRoot, pRequest, status, 0, 0); 3317 break; 3318 } 3319 case OSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED: 3320 { 3321 SA_DBG1(("mpiSATACompletion: OSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED tag 0x%X\n", tag)); 3322 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED++; 3323 siAbnormal(agRoot, pRequest, status, 0, 0); 3324 break; 3325 } 3326 3327 case OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH: 3328 { 3329 SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH tag 0x%X\n", tag)); 3330 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH++; 3331 siAbnormal(agRoot, pRequest, status, 0, 0); 3332 break; 3333 } 3334 case OSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS: 3335 { 3336 SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS tag 0x%X\n", tag)); 3337 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS++; 3338 siAbnormal(agRoot, pRequest, status, 0, 0); 3339 break; 3340 } 3341 case OSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE: 3342 { 3343 SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE tag 0x%X\n", tag)); 3344 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS++; 3345 siAbnormal(agRoot, pRequest, status, 0, 0); 3346 break; 3347 } 3348 3349 default: 3350 { 3351 SA_DBG1(("mpiSATACompletion: Unknown status 0x%x tag 0x%x\n", status, tag)); 3352 saRoot->IoErrorCount.agOSSA_IO_UNKNOWN_ERROR++; 3353 siAbnormal(agRoot, pRequest, status, param, 0); 3354 break; 3355 } 3356 } 3357 3358 /* The HTag should equal to the IOMB tag */ 3359 if (pRequest->HTag != tag) 3360 { 3361 SA_DBG1(("mpiSATACompletion: Error Htag %d not equal IOMBtag %d\n", pRequest->HTag, tag)); 3362 } 3363 3364 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2s"); 3365 return ret; 3366} 3367 3368/******************************************************************************/ 3369/*! \brief SPC MPI SSP Completion 3370 * 3371 * This function handles the SSP completion. 3372 * 3373 * \param agRoot Handles for this instance of SAS/SATA LLL 3374 * \param pIomb1 Pointer of Message1 3375 * \param bc buffer count 3376 * 3377 * \return The read value 3378 * 3379 */ 3380/*******************************************************************************/ 3381GLOBAL FORCEINLINE 3382bit32 mpiSSPCompletion( 3383 agsaRoot_t *agRoot, 3384 bit32 *pIomb1 3385 ) 3386{ 3387 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 3388 agsaSSPCompletionRsp_t *pIomb = (agsaSSPCompletionRsp_t *)pIomb1; 3389 agsaIORequestDesc_t *pRequest = agNULL; 3390 agsaSSPResponseInfoUnit_t *pRespIU = agNULL; 3391 bit32 tag = 0; 3392 bit32 sspTag = 0; 3393 bit32 status, param = 0; 3394 bit32 ret = AGSA_RC_SUCCESS; 3395 3396 smTraceFuncEnter(hpDBG_VERY_LOUD, "5A"); 3397 3398 /* get Tag */ 3399 OSSA_READ_LE_32(agRoot, &tag, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionRsp_t, tag)); 3400 OSSA_READ_LE_32(agRoot, &status, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionRsp_t, status)); 3401 OSSA_READ_LE_32(agRoot, ¶m, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionRsp_t, param)); 3402 OSSA_READ_LE_32(agRoot, &sspTag, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionRsp_t, SSPTag)); 3403 /* get SSP_START IOrequest from IOMap */ 3404 pRequest = (agsaIORequestDesc_t *)saRoot->IOMap[tag].IORequest; 3405 SA_ASSERT((pRequest), "pRequest"); 3406 3407 if(pRequest == agNULL) 3408 { 3409 SA_DBG1(("mpiSSPCompletion,AGSA_RC_FAILURE SSP Resp IOMB tag=0x%x, status=0x%x, param=0x%x, SSPTag=0x%x\n", tag, status, param, sspTag)); 3410 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5A"); 3411 return(AGSA_RC_FAILURE); 3412 } 3413 SA_ASSERT((pRequest->valid), "pRequest->valid"); 3414 3415 if(!pRequest->valid) 3416 { 3417 SA_DBG1(("mpiSSPCompletion, SSP Resp IOMB tag=0x%x, status=0x%x, param=0x%x, SSPTag=0x%x Device =0x%x\n", tag, status, param, sspTag, 3418 pRequest->pDevice ? pRequest->pDevice->DeviceMapIndex : -1)); 3419 } 3420 3421 switch (status) 3422 { 3423 case OSSA_IO_SUCCESS: 3424 { 3425 if (!param) 3426 { 3427 /* Completion of SSP without Response Data */ 3428 siIODone( agRoot, pRequest, OSSA_IO_SUCCESS, sspTag); 3429 } 3430 else 3431 { 3432 /* Get SSP Response with Response Data */ 3433 pRespIU = (agsaSSPResponseInfoUnit_t *)&(pIomb->SSPrsp); 3434 if (pRespIU->status == 0x02 || pRespIU->status == 0x18 || 3435 pRespIU->status == 0x30 || pRespIU->status == 0x40 ) 3436 { 3437 /* SCSI status is CHECK_CONDITION, RESV_CONFLICT, ACA_ACTIVE, TASK_ABORTED */ 3438 saRoot->IoErrorCount.agOSSA_IO_COMPLETED_ERROR_SCSI_STATUS++; 3439 SA_DBG2(("mpiSSPCompletion: pRespIU->status 0x%x tag 0x%x\n", pRespIU->status,tag)); 3440 } 3441 siEventSSPResponseWtDataRcvd(agRoot, pRequest, pRespIU, param, sspTag); 3442 } 3443 3444 break; 3445 } 3446 3447 case OSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME: 3448 { 3449 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3450 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME++; 3451 /* Get SSP Response with Response Data */ 3452 pRespIU = (agsaSSPResponseInfoUnit_t *)&(pIomb->SSPrsp); 3453 if (pRespIU->status == 0x02 || pRespIU->status == 0x18 || 3454 pRespIU->status == 0x30 || pRespIU->status == 0x40 ) 3455 { 3456 /* SCSI status is CHECK_CONDITION, RESV_CONFLICT, ACA_ACTIVE, TASK_ABORTED */ 3457 saRoot->IoErrorCount.agOSSA_IO_COMPLETED_ERROR_SCSI_STATUS++; 3458 SA_DBG2(("mpiSSPCompletion: pRespIU->status 0x%x tag 0x%x\n", pRespIU->status,tag)); 3459 } 3460 siEventSSPResponseWtDataRcvd(agRoot, pRequest, pRespIU, param, sspTag); 3461 3462 break; 3463 } 3464 3465 case OSSA_IO_ABORTED: 3466 { 3467#ifdef SALL_API_TEST 3468 saRoot->LLCounters.IOCounter.numSSPAborted++; 3469 SA_DBG3(("mpiSSPCompletion, OSSA_IO_ABORTED Response received IOMB=%p %d\n", 3470 pIomb1, saRoot->LLCounters.IOCounter.numSSPAborted)); 3471#endif 3472 SA_DBG2(("mpiSSPCompletion, OSSA_IO_ABORTED IOMB tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3473 saRoot->IoErrorCount.agOSSA_IO_ABORTED++; 3474 /* SSP Abort CB */ 3475 siAbnormal(agRoot, pRequest, status, param, sspTag); 3476 break; 3477 } 3478 case OSSA_IO_UNDERFLOW: 3479 { 3480 /* SSP Completion with error */ 3481 SA_DBG2(("mpiSSPCompletion, OSSA_IO_UNDERFLOW tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3482 /*saRoot->IoErrorCount.agOSSA_IO_UNDERFLOW++;*/ 3483 siAbnormal(agRoot, pRequest, status, param, sspTag); 3484 break; 3485 } 3486 case OSSA_IO_NO_DEVICE: 3487 { 3488 SA_DBG1(("mpiSSPCompletion: OSSA_IO_NO_DEVICE tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3489 saRoot->IoErrorCount.agOSSA_IO_NO_DEVICE++; 3490 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3491 break; 3492 } 3493 case OSSA_IO_XFER_ERROR_BREAK: 3494 { 3495 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_BREAK tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3496 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_BREAK++; 3497 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3498 break; 3499 } 3500 case OSSA_IO_XFER_ERROR_PHY_NOT_READY: 3501 { 3502 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_PHY_NOT_READY tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3503 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_PHY_NOT_READY++; 3504 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3505 break; 3506 } 3507 case OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 3508 { 3509 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3510 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED++; 3511 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3512 break; 3513 } 3514 case OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 3515 { 3516 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION++; 3517 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3518 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3519 break; 3520 } 3521 case OSSA_IO_OPEN_CNX_ERROR_BREAK: 3522 { 3523 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_BREAK tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3524 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_BREAK++; 3525 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3526 break; 3527 } 3528 case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 3529 { 3530 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3531 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS++; 3532 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3533 break; 3534 } 3535 case OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION: 3536 { 3537 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3538 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION++; 3539 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3540 break; 3541 } 3542 case OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 3543 { 3544 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3545 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED++; 3546 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3547 break; 3548 } 3549 case OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 3550 { 3551 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3552 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION++; 3553 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3554 break; 3555 } 3556 case OSSA_IO_XFER_ERROR_NAK_RECEIVED: 3557 { 3558 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_NAK_RECEIVED tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3559 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_NAK_RECEIVED++; 3560 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3561 break; 3562 } 3563 case OSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT: 3564 { 3565 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3566 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT++; 3567 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3568 break; 3569 } 3570 case OSSA_IO_XFER_ERROR_DMA: 3571 { 3572 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_DMA tag 0x%x ssptag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3573 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_DMA++; 3574 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3575 break; 3576 } 3577 case OSSA_IO_XFER_OPEN_RETRY_TIMEOUT: 3578 { 3579 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_OPEN_RETRY_TIMEOUT tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3580 saRoot->IoErrorCount.agOSSA_IO_XFER_OPEN_RETRY_TIMEOUT++; 3581 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3582 break; 3583 } 3584 case OSSA_IO_XFER_ERROR_UNEXPECTED_PHASE: 3585 { 3586 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_UNEXPECTED_PHASE tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3587 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_UNEXPECTED_PHASE++; 3588 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3589 break; 3590 } 3591 case OSSA_IO_XFER_ERROR_OFFSET_MISMATCH: 3592 { 3593 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_OFFSET_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3594 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_OFFSET_MISMATCH++; 3595 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3596 break; 3597 } 3598 case OSSA_IO_PORT_IN_RESET: 3599 { 3600 SA_DBG1(("mpiSSPCompletion: OSSA_IO_PORT_IN_RESET tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3601 saRoot->IoErrorCount.agOSSA_IO_PORT_IN_RESET++; 3602 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3603 break; 3604 } 3605 case OSSA_IO_DS_NON_OPERATIONAL: 3606 { 3607 SA_DBG1(("mpiSSPCompletion: OSSA_IO_DS_NON_OPERATIONAL tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3608 saRoot->IoErrorCount.agOSSA_IO_DS_NON_OPERATIONAL++; 3609 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3610 break; 3611 } 3612 case OSSA_IO_DS_IN_RECOVERY: 3613 { 3614 SA_DBG1(("mpiSSPCompletion: OSSA_IO_DS_IN_RECOVERY tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3615 saRoot->IoErrorCount.agOSSA_IO_DS_IN_RECOVERY++; 3616 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3617 break; 3618 } 3619 case OSSA_IO_TM_TAG_NOT_FOUND: 3620 { 3621 SA_DBG1(("mpiSSPCompletion: OSSA_IO_TM_TAG_NOT_FOUND tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3622 saRoot->IoErrorCount.agOSSA_IO_TM_TAG_NOT_FOUND++; 3623 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3624 break; 3625 } 3626 case OSSA_IO_XFER_PIO_SETUP_ERROR: 3627 { 3628 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_PIO_SETUP_ERROR tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3629 saRoot->IoErrorCount.agOSSA_IO_XFER_PIO_SETUP_ERROR++; 3630 /* not allowed case. Therefore, return failed status */ 3631 siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); 3632 break; 3633 } 3634 case OSSA_IO_SSP_EXT_IU_ZERO_LEN_ERROR: 3635 { 3636 SA_DBG1(("mpiSSPCompletion: OSSA_IO_SSP_IU_ZERO_LEN_ERROR tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3637 saRoot->IoErrorCount.agOSSA_IO_SSP_EXT_IU_ZERO_LEN_ERROR++; 3638 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3639 break; 3640 } 3641 case OSSA_IO_DS_IN_ERROR: 3642 { 3643 SA_DBG1(("mpiSSPCompletion: OSSA_IO_DS_IN_ERROR tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3644 saRoot->IoErrorCount.agOSSA_IO_DS_IN_ERROR++; 3645 /* not allowed case. Therefore, return failed status */ 3646 siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); 3647 break; 3648 } 3649 case OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 3650 { 3651 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3652 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY++; 3653 /* not allowed case. Therefore, return failed status */ 3654 siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); 3655 break; 3656 } 3657 case OSSA_IO_ABORT_IN_PROGRESS: 3658 { 3659 SA_DBG1(("mpiSSPCompletion: OSSA_IO_ABORT_IN_PROGRESS tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3660 saRoot->IoErrorCount.agOSSA_IO_ABORT_IN_PROGRESS++; 3661 /* not allowed case. Therefore, return failed status */ 3662 siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); 3663 break; 3664 } 3665 case OSSA_IO_ABORT_DELAYED: 3666 { 3667 SA_DBG1(("mpiSSPCompletion: OSSA_IO_ABORT_DELAYED tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3668 saRoot->IoErrorCount.agOSSA_IO_ABORT_DELAYED++; 3669 /* not allowed case. Therefore, return failed status */ 3670 siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); 3671 break; 3672 } 3673 case OSSA_IO_INVALID_LENGTH: 3674 { 3675 SA_DBG1(("mpiSSPCompletion: OSSA_IO_INVALID_LENGTH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3676 saRoot->IoErrorCount.agOSSA_IO_INVALID_LENGTH++; 3677 /* not allowed case. Therefore, return failed status */ 3678 siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); 3679 break; 3680 } 3681 case OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT: 3682 { 3683 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3684 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT++; 3685 /* not allowed case. Therefore, return failed status */ 3686 siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); 3687 break; 3688 } 3689 case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 3690 { 3691 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED HTAG = 0x%x ssptag = 0x%x\n", tag, sspTag)); 3692 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED++; 3693 siAbnormal(agRoot, pRequest, status, 0, sspTag); 3694 break; 3695 } 3696 case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 3697 { 3698 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3699 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO++; 3700 siAbnormal(agRoot, pRequest, status, param, sspTag); 3701 break; 3702 } 3703 case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 3704 { 3705 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3706 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST++; 3707 siAbnormal(agRoot, pRequest, status, param, sspTag); 3708 break; 3709 } 3710 case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 3711 { 3712 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3713 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE++; 3714 siAbnormal(agRoot, pRequest, status, param, sspTag); 3715 break; 3716 } 3717 case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 3718 { 3719 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3720 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED++; 3721 siAbnormal(agRoot, pRequest, status, param, sspTag); 3722 break; 3723 } 3724 case OSSA_IO_DS_INVALID: 3725 { 3726 SA_DBG1(("mpiSSPCompletion: OSSA_IO_DS_INVALID tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3727 saRoot->IoErrorCount.agOSSA_IO_DS_INVALID++; 3728 siAbnormal(agRoot, pRequest, status, param, sspTag); 3729 break; 3730 } 3731 case OSSA_MPI_IO_RQE_BUSY_FULL: 3732 { 3733 SA_DBG1(("mpiSSPCompletion: OSSA_MPI_IO_RQE_BUSY_FULL tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3734 saRoot->IoErrorCount.agOSSA_MPI_IO_RQE_BUSY_FULL++; 3735 siAbnormal(agRoot, pRequest, status, param, sspTag); 3736 break; 3737 } 3738 case OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE: 3739 { 3740 SA_DBG1(("mpiSSPCompletion: OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3741 saRoot->IoErrorCount.agOSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE++; 3742 siAbnormal(agRoot, pRequest, status, param, sspTag); 3743 break; 3744 } 3745 case OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS: 3746 { 3747 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3748 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS++; 3749 siAbnormal(agRoot, pRequest, status, param, sspTag); 3750 break; 3751 } 3752 case OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH: 3753 { 3754 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3755 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH++; 3756 siAbnormal(agRoot, pRequest, status, param, sspTag); 3757 break; 3758 } 3759 case OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID: 3760 { 3761 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3762 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID++; 3763 siAbnormal(agRoot, pRequest, status, param, sspTag); 3764 break; 3765 } 3766 case OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH: 3767 { 3768 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3769 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_IV_MISMATCH++; 3770 siAbnormal(agRoot, pRequest, status, param, sspTag); 3771 break; 3772 } 3773 case OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR: 3774 { 3775 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3776 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR++; 3777 siAbnormal(agRoot, pRequest, status, param, sspTag); 3778 break; 3779 } 3780 case OSSA_IO_XFR_ERROR_INTERNAL_RAM: 3781 { 3782 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_INTERNAL_RAM tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3783 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_INTERNAL_RAM++; 3784 siAbnormal(agRoot, pRequest, status, param, sspTag); 3785 break; 3786 } 3787 case OSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS: 3788 { 3789 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3790 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS++; 3791 siAbnormal(agRoot, pRequest, status, param, sspTag); 3792 break; 3793 } 3794 case OSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE: 3795 { 3796 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3797 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE++; 3798 siAbnormal(agRoot, pRequest, status, param, sspTag); 3799 break; 3800 } 3801#ifdef SA_TESTBASE_EXTRA 3802 /* TestBase */ 3803 case OSSA_IO_HOST_BST_INVALID: 3804 { 3805 SA_DBG1(("mpiParseOBIomb, OPC_OUB_SSP_COMP: OSSA_IO_HOST_BST_INVALID 0x%x\n", status)); 3806 siAbnormal(agRoot, pRequest, status, param, sspTag); 3807 break; 3808 } 3809#endif /* SA_TESTBASE_EXTRA */ 3810 case OSSA_IO_XFR_ERROR_DIF_MISMATCH: 3811 { 3812 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DIF_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3813 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DIF_MISMATCH++; 3814 siDifAbnormal(agRoot, pRequest, status, param, sspTag, pIomb1); 3815 break; 3816 } 3817 case OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH: 3818 { 3819 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3820 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH++; 3821 siDifAbnormal(agRoot, pRequest, status, param, sspTag, pIomb1); 3822 break; 3823 } 3824 case OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH: 3825 { 3826 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3827 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH++; 3828 siDifAbnormal(agRoot, pRequest, status, param, sspTag, pIomb1); 3829 break; 3830 } 3831 case OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH: 3832 { 3833 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3834 saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH++; 3835 siDifAbnormal(agRoot, pRequest, status, param, sspTag, pIomb1); 3836 break; 3837 } 3838 case OSSA_IO_XFER_ERROR_DIF_INTERNAL_ERROR: 3839 { 3840 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_DIF_INTERNAL_ERROR tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3841 saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_DIF_INTERNAL_ERROR++; 3842 siDifAbnormal(agRoot, pRequest, status, param, sspTag, pIomb1); 3843 break; 3844 } 3845 case OSSA_IO_XFER_ERR_EOB_DATA_OVERRUN: 3846 { 3847 SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERR_EOB_DATA_OVERRUN tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3848 saRoot->IoErrorCount.agOSSA_IO_XFER_ERR_EOB_DATA_OVERRUN++; 3849 siAbnormal(agRoot, pRequest, status, param, sspTag); 3850 break; 3851 } 3852 case OSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED: 3853 { 3854 SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3855 saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED++; 3856 siAbnormal(agRoot, pRequest, status, param, sspTag); 3857 break; 3858 } 3859 default: 3860 { 3861 SA_DBG1(("mpiSSPCompletion: Unknown tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3862 /* not allowed case. Therefore, return failed status */ 3863 saRoot->IoErrorCount.agOSSA_IO_UNKNOWN_ERROR++; 3864 siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); 3865 break; 3866 } 3867 } 3868 3869 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5A"); 3870 return ret; 3871} 3872