1/*
2 * Copyright (c) 2015, 2020 Ruslan Bukin <br@bsdpad.com>
3 * Copyright (c) 2015 The FreeBSD Foundation
4 * All rights reserved.
5 *
6 * This software was developed by Semihalf.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 *
30 */
31
32#ifndef __PCI_HOST_GENERIC_H_
33#define	__PCI_HOST_GENERIC_H_
34
35#include "pci_if.h"
36
37/* Assembling ECAM Configuration Address */
38#define	PCIE_BUS_SHIFT		20
39#define	PCIE_SLOT_SHIFT		15
40#define	PCIE_FUNC_SHIFT		12
41#define	PCIE_BUS_MASK		0xFF
42#define	PCIE_SLOT_MASK		0x1F
43#define	PCIE_FUNC_MASK		0x07
44#define	PCIE_REG_MASK		0xFFF
45
46#define	PCIE_ADDR_OFFSET(bus, slot, func, reg)			\
47	((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT)	|	\
48	(((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT)	|	\
49	(((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT)	|	\
50	((reg) & PCIE_REG_MASK))
51
52#define	MAX_RANGES_TUPLES	16
53#define	MIN_RANGES_TUPLES	2
54
55struct pcie_range {
56	uint64_t	pci_base;
57	uint64_t	phys_base;
58	uint64_t	size;
59	uint64_t	flags;
60#define	FLAG_TYPE(x)		((x) & FLAG_TYPE_MASK)
61#define	FLAG_TYPE_MASK		0x3
62#define	FLAG_TYPE_INVALID	0x0
63#define	FLAG_TYPE_IO		0x1
64#define	FLAG_TYPE_MEM		0x2
65#define	FLAG_TYPE_PMEM		0x3
66	struct resource *res;
67};
68
69struct generic_pcie_core_softc {
70	struct pcie_range	ranges[MAX_RANGES_TUPLES];
71	int			nranges;
72	int			coherent;
73	bool			has_pmem;
74	struct rman		pmem_rman;
75	struct rman		mem_rman;
76	struct rman		io_rman;
77	struct resource		*res;
78	int			bus_start;
79	int			bus_end;
80	int			ecam;
81	device_t		dev;
82	bus_space_handle_t	ioh;
83	bus_dma_tag_t		dmat;
84	uint32_t		quirks;
85};
86
87/* Quirks */
88#define PCIE_ECAM_DESIGNWARE_QUIRK	(1 << 0)
89/* Child will map resources to access config registers */
90#define PCIE_CUSTOM_CONFIG_SPACE_QUIRK	(1 << 1)
91
92DECLARE_CLASS(generic_pcie_core_driver);
93
94int pci_host_generic_core_attach(device_t);
95int pci_host_generic_core_detach(device_t);
96struct resource *pci_host_generic_core_alloc_resource(device_t, device_t, int,
97    int *, rman_res_t, rman_res_t, rman_res_t, u_int);
98int pci_host_generic_core_release_resource(device_t, device_t,
99    struct resource *);
100
101#endif /* __PCI_HOST_GENERIC_H_ */
102