1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2000,2001 Jonathan Chen. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Copyright (c) 1998, 1999 and 2000 31 * HAYAKAWA Koichi. All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. All advertising materials mentioning features or use of this software 42 * must display the following acknowledgement: 43 * This product includes software developed by HAYAKAWA Koichi. 44 * 4. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59/* 60 * Register definitions for PCI to Cardbus Bridge chips 61 */ 62 63/* PCI header registers */ 64#define CBBR_SOCKBASE 0x10 /* len=4 */ 65 66#define CBBR_MEMBASE0 0x1c /* len=4 */ 67#define CBBR_MEMLIMIT0 0x20 /* len=4 */ 68#define CBBR_MEMBASE1 0x24 /* len=4 */ 69#define CBBR_MEMLIMIT1 0x28 /* len=4 */ 70#define CBBR_IOBASE0 0x2c /* len=4 */ 71#define CBBR_IOLIMIT0 0x30 /* len=4 */ 72#define CBBR_IOBASE1 0x34 /* len=4 */ 73#define CBBR_IOLIMIT1 0x38 /* len=4 */ 74#define CBB_MEMALIGN 4096 75#define CBB_MEMALIGN_BITS 12 76#define CBB_IOALIGN 4 77#define CBB_IOALIGN_BITS 2 78 79#define CBBR_INTRLINE 0x3c /* len=1 */ 80#define CBBR_INTRPIN 0x3d /* len=1 */ 81#define CBBR_BRIDGECTRL 0x3e /* len=2 */ 82# define CBBM_BRIDGECTRL_MASTER_ABORT 0x0020 83# define CBBM_BRIDGECTRL_RESET 0x0040 84# define CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN 0x0080 85# define CBBM_BRIDGECTRL_PREFETCH_0 0x0100 86# define CBBM_BRIDGECTRL_PREFETCH_1 0x0200 87# define CBBM_BRIDGECTRL_WRITE_POST_EN 0x0400 88 /* additional bit for RF5C46[567] */ 89# define CBBM_BRIDGECTRL_RL_3E0_EN 0x0800 90# define CBBM_BRIDGECTRL_RL_3E2_EN 0x1000 91 92#define CBBR_LEGACY 0x44 /* len=4 */ 93 94/* TI */ 95#define CBBR_SYSCTRL 0x80 /* len=4 */ 96# define CBBM_SYSCTRL_INTRTIE 0x20000000u 97 98/* TI [14][245]xx */ 99#define CBBR_MMCTRL 0x84 /* len=4 */ 100 101/* TI 12xx/14xx/15xx (except 1250/1251/1251B/1450) */ 102#define CBBR_MFUNC 0x8c /* len=4 */ 103# define CBBM_MFUNC_PIN0 0x0000000f 104# define CBBM_MFUNC_PIN0_INTA 0x02 105# define CBBM_MFUNC_PIN1 0x000000f0 106# define CBBM_MFUNC_PIN1_INTB 0x20 107# define CBBM_MFUNC_PIN2 0x00000f00 108# define CBBM_MFUNC_PIN3 0x0000f000 109# define CBBM_MFUNC_PIN4 0x000f0000 110# define CBBM_MFUNC_PIN5 0x00f00000 111# define CBBM_MFUNC_PIN6 0x0f000000 112 113#define CBBR_CBCTRL 0x91 /* len=1 */ 114 /* bits for TI 113X */ 115# define CBBM_CBCTRL_113X_RI_EN 0x80 116# define CBBM_CBCTRL_113X_ZV_EN 0x40 117# define CBBM_CBCTRL_113X_PCI_IRQ_EN 0x20 118# define CBBM_CBCTRL_113X_PCI_INTR 0x10 119# define CBBM_CBCTRL_113X_PCI_CSC 0x08 120# define CBBM_CBCTRL_113X_PCI_CSC_D 0x04 121# define CBBM_CBCTRL_113X_SPEAKER_EN 0x02 122# define CBBM_CBCTRL_113X_INTR_DET 0x01 123 /* TI [14][245]xx */ 124# define CBBM_CBCTRL_12XX_RI_EN 0x80 125# define CBBM_CBCTRL_12XX_ZV_EN 0x40 126# define CBBM_CBCTRL_12XX_AUD2MUX 0x04 127# define CBBM_CBCTRL_12XX_SPEAKER_EN 0x02 128# define CBBM_CBCTRL_12XX_INTR_DET 0x01 129#define CBBR_DEVCTRL 0x92 /* len=1 */ 130# define CBBM_DEVCTRL_INT_SERIAL 0x04 131# define CBBM_DEVCTRL_INT_PCI 0x02 132 133/* ToPIC 95 ONLY */ 134#define TOPIC95_SOCKETCTRL 0x90 135# define TOPIC95_SOCKETCTRL_SCR_IRQSEL 0x00000001 /* PCI intr */ 136/* ToPIC 97, 100 */ 137#define TOPIC97_ZV_CONTROL 0x9c /* 1 byte */ 138# define TOPIC97_ZVC_ENABLE 0x1 139 140/* TOPIC 95+ */ 141#define TOPIC_SLOTCTRL 0xa0 /* 1 byte */ 142# define TOPIC_SLOTCTRL_SLOTON 0x80 143# define TOPIC_SLOTCTRL_SLOTEN 0x40 144# define TOPIC_SLOTCTRL_ID_LOCK 0x20 145# define TOPIC_SLOTCTRL_ID_WP 0x10 146# define TOPIC_SLOTCTRL_PORT_MASK 0x0c 147# define TOPIC_SLOTCTRL_PORT_SHIFT 2 148# define TOPIC_SLOTCTRL_OSF_MASK 0x03 149# define TOPIC_SLOTCTRL_OSF_SHIFT 0 150 151/* TOPIC 95+ */ 152#define TOPIC_INTCTRL 0xa1 /* 1 byte */ 153# define TOPIC_INTCTRL_INTB 0x20 154# define TOPIC_INTCTRL_INTA 0x10 155# define TOPIC_INTCTRL_INT_MASK 0x30 156/* The following bits may be for ToPIC 95 only */ 157# define TOPIC95_INTCTRL_CLOCK_MASK 0x0c 158# define TOPIC95_INTCTRL_CLOCK_2 0x08 /* PCI Clk/2 */ 159# define TOPIC95_INTCTRL_CLOCK_1 0x04 /* PCI Clk */ 160# define TOPIC95_INTCTRL_CLOCK_0 0x00 /* no clock */ 161/* ToPIC97, 100 defines the following bits */ 162# define TOPIC97_INTCTRL_STSIRQNP 0x04 163# define TOPIC97_INTCTRL_IRQNP 0x02 164# define TOPIC97_INTCTRL_INTIRQSEL 0x01 165 166/* TOPIC 95+ */ 167#define TOPIC_CDC 0xa3 /* 1 byte */ 168# define TOPIC_CDC_CARDBUS 0x80 169# define TOPIC_CDC_VS1 0x04 170# define TOPIC_CDC_VS2 0x02 171# define TOPIC_CDC_SWDETECT 0x01 172 173/* TOPIC97+? */ 174#define TOPIC_REG_CTRL 0xa4 /* 4 bytes */ 175# define TOPIC_REG_CTRL_RESUME_RESET 0x80000000 176# define TOPIC_REG_CTRL_REMOVE_RESET 0x40000000 177# define TOPIC97_REG_CTRL_CLKRUN_ENA 0x20000000 178# define TOPIC97_REG_CTRL_TESTMODE 0x10000000 179# define TOPIC97_REG_CTRL_IOPLUP 0x08000000 180# define TOPIC_REG_CTRL_BUFOFF_PWROFF 0x02000000 181# define TOPIC_REG_CTRL_BUFOFF_SIGOFF 0x01000000 182# define TOPIC97_REG_CTRL_CB_DEV_MASK 0x0000f800 183# define TOPIC97_REG_CTRL_CB_DEV_SHIFT 11 184# define TOPIC97_REG_CTRL_RI_DISABLE 0x00000004 185# define TOPIC97_REG_CTRL_CAUDIO_OFF 0x00000002 186# define TOPIC_REG_CTRL_CAUDIO_INVERT 0x00000001 187 188/* Socket definitions */ 189#define CBB_SOCKET_EVENT_CSTS 0x01 /* Card Status Change */ 190#define CBB_SOCKET_EVENT_CD1 0x02 /* Card Detect 1 */ 191#define CBB_SOCKET_EVENT_CD2 0x04 /* Card Detect 2 */ 192#define CBB_SOCKET_EVENT_CD 0x06 /* Card Detect all */ 193#define CBB_SOCKET_EVENT_POWER 0x08 /* Power Cycle */ 194#define CBB_SOCKET_EVENT_VALID_MASK 0x0f /* All socket events */ 195 196#define CBB_SOCKET_MASK_CSTS 0x01 /* Card Status Change */ 197#define CBB_SOCKET_MASK_CD 0x06 /* Card Detect */ 198#define CBB_SOCKET_MASK_POWER 0x08 /* Power Cycle */ 199#define CBB_SOCKET_MASK_ALL 0x0F /* all of the above */ 200 201#define CBB_STATE_CSTCHG (1UL << 0) /* Card Status Change */ 202#define CBB_STATE_CD1_CHANGE (1UL << 1) /* Card Detect 1 */ 203#define CBB_STATE_CD2_CHANGE (1UL << 2) /* Card Detect 2 */ 204#define CBB_STATE_CD (3UL << 1) /* Card Detect all */ 205#define CBB_STATE_POWER_CYCLE (1UL << 3) /* Power Cycle */ 206#define CBB_STATE_R2_CARD (1UL << 4) /* 16-bit Card */ 207#define CBB_STATE_CB_CARD (1UL << 5) /* Cardbus Card */ 208#define CBB_STATE_IREQ (1UL << 6) /* Ready */ 209#define CBB_STATE_NOT_A_CARD (1UL << 7) /* Unrecognized Card */ 210#define CBB_STATE_DATA_LOST (1UL << 8) /* Data Lost */ 211#define CBB_STATE_BAD_VCC_REQ (1UL << 9) /* Bad VccRequest */ 212#define CBB_STATE_5VCARD (1UL << 10) /* 5 V Card */ 213#define CBB_STATE_3VCARD (1UL << 11) /* 3.3 V Card */ 214#define CBB_STATE_XVCARD (1UL << 12) /* X.X V Card */ 215#define CBB_STATE_YVCARD (1UL << 13) /* Y.Y V Card */ 216#define CBB_STATE_5VSOCK (1UL << 28) /* 5 V Socket */ 217#define CBB_STATE_3VSOCK (1UL << 29) /* 3.3 V Socket */ 218#define CBB_STATE_XVSOCK (1UL << 30) /* X.X V Socket */ 219#define CBB_STATE_YVSOCK (1UL << 31) /* Y.Y V Socket */ 220 221#define CBB_SOCKET_CTRL_VPPMASK 0x07 222#define CBB_SOCKET_CTRL_VPP_OFF 0x00 223#define CBB_SOCKET_CTRL_VPP_12V 0x01 224#define CBB_SOCKET_CTRL_VPP_5V 0x02 225#define CBB_SOCKET_CTRL_VPP_3V 0x03 226#define CBB_SOCKET_CTRL_VPP_XV 0x04 227#define CBB_SOCKET_CTRL_VPP_YV 0x05 228 229#define CBB_SOCKET_CTRL_VCCMASK 0x70 230#define CBB_SOCKET_CTRL_VCC_OFF 0x00 231#define CBB_SOCKET_CTRL_VCC_5V 0x20 232#define CBB_SOCKET_CTRL_VCC_3V 0x30 233#define CBB_SOCKET_CTRL_VCC_XV 0x40 234#define CBB_SOCKET_CTRL_VCC_YV 0x50 235 236#define CBB_SOCKET_CTRL_STOPCLK 0x80 237 238#define CBB_FORCE_CV_TEST (1UL << 14) 239#define CBB_FORCE_3VCARD (1UL << 11) 240#define CBB_FORCE_5VCARD (1UL << 10) 241#define CBB_FORCE_BAD_VCC_REQ (1UL << 9) 242#define CBB_FORCE_DATA_LOST (1UL << 8) 243#define CBB_FORCE_NOT_A_CARD (1UL << 7) 244#define CBB_FORCE_CB_CARD (1UL << 5) 245#define CBB_FORCE_R2_CARD (1UL << 4) 246#define CBB_FORCE_POWER_CYCLE (1UL << 3) 247#define CBB_FORCE_CD2_CHANGE (1UL << 2) 248#define CBB_FORCE_CD1_CHANGE (1UL << 1) 249#define CBB_FORCE_CSTCHG (1UL << 0) 250 251#include <dev/pccbb/pccbbdevid.h> 252 253#define CBB_SOCKET_EVENT 0x00 254#define CBB_SOCKET_MASK 0x04 255#define CBB_SOCKET_STATE 0x08 256#define CBB_SOCKET_FORCE 0x0c 257#define CBB_SOCKET_CONTROL 0x10 258#define CBB_SOCKET_POWER 0x14 259 260#define CBB_EXCA_OFFSET 0x800 /* offset for exca regs */ 261