1/*- 2 * Copyright (c) 2017 Broadcom. All rights reserved. 3 * The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the copyright holder nor the names of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32/** 33 * @file 34 * Define common SLI-4 structures and function prototypes. 35 */ 36 37#ifndef _SLI4_H 38#define _SLI4_H 39 40#include "ocs_os.h" 41 42#define SLI_PAGE_SIZE (4096) 43#define SLI_SUB_PAGE_MASK (SLI_PAGE_SIZE - 1) 44#define SLI_PAGE_SHIFT 12 45#define SLI_ROUND_PAGE(b) (((b) + SLI_SUB_PAGE_MASK) & ~SLI_SUB_PAGE_MASK) 46 47#define SLI4_BMBX_TIMEOUT_MSEC 30000 48#define SLI4_FW_READY_TIMEOUT_MSEC 30000 49 50static inline uint32_t 51sli_page_count(size_t bytes, uint32_t page_size) 52{ 53 uint32_t mask = page_size - 1; 54 uint32_t shift = 0; 55 56 switch (page_size) { 57 case 4096: 58 shift = 12; 59 break; 60 case 8192: 61 shift = 13; 62 break; 63 case 16384: 64 shift = 14; 65 break; 66 case 32768: 67 shift = 15; 68 break; 69 case 65536: 70 shift = 16; 71 break; 72 default: 73 return 0; 74 } 75 76 return (bytes + mask) >> shift; 77} 78 79/************************************************************************* 80 * Common PCI configuration space register definitions 81 */ 82 83#define SLI4_PCI_CLASS_REVISION 0x0008 /** register offset */ 84#define SLI4_PCI_REV_ID_SHIFT 0 85#define SLI4_PCI_REV_ID_MASK 0xff 86#define SLI4_PCI_CLASS_SHIFT 8 87#define SLI4_PCI_CLASS_MASK 0xfff 88 89#define SLI4_PCI_SOFT_RESET_CSR 0x005c /** register offset */ 90#define SLI4_PCI_SOFT_RESET_MASK 0x0080 91 92/************************************************************************* 93 * Common SLI-4 register offsets and field definitions 94 */ 95 96/** 97 * @brief SLI_INTF - SLI Interface Definition Register 98 */ 99#define SLI4_INTF_REG 0x0058 /** register offset */ 100#define SLI4_INTF_VALID_SHIFT 29 101#define SLI4_INTF_VALID_MASK 0x7 102#define SLI4_INTF_VALID 0x6 103#define SLI4_INTF_IF_TYPE_SHIFT 12 104#define SLI4_INTF_IF_TYPE_MASK 0xf 105#define SLI4_INTF_SLI_FAMILY_SHIFT 8 106#define SLI4_INTF_SLI_FAMILY_MASK 0xf 107#define SLI4_INTF_SLI_REVISION_SHIFT 4 108#define SLI4_INTF_SLI_REVISION_MASK 0xf 109#define SLI4_FAMILY_CHECK_ASIC_TYPE 0xf 110 111#define SLI4_IF_TYPE_BE3_SKH_PF 0 112#define SLI4_IF_TYPE_BE3_SKH_VF 1 113#define SLI4_IF_TYPE_LANCER_FC_ETH 2 114#define SLI4_IF_TYPE_LANCER_RDMA 3 115#define SLI4_IF_TYPE_LANCER_G7 6 116#define SLI4_MAX_IF_TYPES 7 117 118/** 119 * @brief ASIC_ID - SLI ASIC Type and Revision Register 120 */ 121#define SLI4_ASIC_ID_REG 0x009c /* register offset */ 122#define SLI4_ASIC_REV_SHIFT 0 123#define SLI4_ASIC_REV_MASK 0xf 124#define SLI4_ASIC_VER_SHIFT 4 125#define SLI4_ASIC_VER_MASK 0xf 126#define SLI4_ASIC_GEN_SHIFT 8 127#define SLI4_ASIC_GEN_MASK 0xff 128#define SLI4_ASIC_GEN_BE2 0x00 129#define SLI4_ASIC_GEN_BE3 0x03 130#define SLI4_ASIC_GEN_SKYHAWK 0x04 131#define SLI4_ASIC_GEN_CORSAIR 0x05 132#define SLI4_ASIC_GEN_LANCER 0x0b 133 134/** 135 * @brief BMBX - Bootstrap Mailbox Register 136 */ 137#define SLI4_BMBX_REG 0x0160 /* register offset */ 138#define SLI4_BMBX_MASK_HI 0x3 139#define SLI4_BMBX_MASK_LO 0xf 140#define SLI4_BMBX_RDY BIT(0) 141#define SLI4_BMBX_HI BIT(1) 142#define SLI4_BMBX_WRITE_HI(r) ((ocs_addr32_hi(r) & ~SLI4_BMBX_MASK_HI) | \ 143 SLI4_BMBX_HI) 144#define SLI4_BMBX_WRITE_LO(r) (((ocs_addr32_hi(r) & SLI4_BMBX_MASK_HI) << 30) | \ 145 (((r) & ~SLI4_BMBX_MASK_LO) >> 2)) 146 147#define SLI4_BMBX_SIZE 256 148 149/** 150 * @brief EQCQ_DOORBELL - EQ and CQ Doorbell Register 151 */ 152#define SLI4_EQCQ_DOORBELL_REG 0x120 153#define SLI4_EQCQ_DOORBELL_CI BIT(9) 154#define SLI4_EQCQ_DOORBELL_QT BIT(10) 155#define SLI4_EQCQ_DOORBELL_ARM BIT(29) 156#define SLI4_EQCQ_DOORBELL_SE BIT(31) 157#define SLI4_EQCQ_NUM_SHIFT 16 158#define SLI4_EQCQ_NUM_MASK 0x01ff 159#define SLI4_EQCQ_EQ_ID_MASK 0x3fff 160#define SLI4_EQCQ_CQ_ID_MASK 0x7fff 161#define SLI4_EQCQ_EQ_ID_MASK_LO 0x01ff 162#define SLI4_EQCQ_CQ_ID_MASK_LO 0x03ff 163#define SLI4_EQCQ_EQCQ_ID_MASK_HI 0xf800 164#define SLI4_IF6_EQ_DOORBELL_REG 0x120 165#define SLI4_IF6_CQ_DOORBELL_REG 0xC0 166 167/** 168 * @brief SLIPORT_CONTROL - SLI Port Control Register 169 */ 170#define SLI4_SLIPORT_CONTROL_REG 0x0408 171#define SLI4_SLIPORT_CONTROL_END BIT(30) 172#define SLI4_SLIPORT_CONTROL_LITTLE_ENDIAN (0) 173#define SLI4_SLIPORT_CONTROL_BIG_ENDIAN BIT(30) 174#define SLI4_SLIPORT_CONTROL_IP BIT(27) 175#define SLI4_SLIPORT_CONTROL_IDIS BIT(22) 176#define SLI4_SLIPORT_CONTROL_FDD BIT(31) 177 178/** 179 * @brief SLI4_SLIPORT_ERROR1 - SLI Port Error Register 180 */ 181#define SLI4_SLIPORT_ERROR1 0x040c 182 183/** 184 * @brief SLI4_SLIPORT_ERROR2 - SLI Port Error Register 185 */ 186#define SLI4_SLIPORT_ERROR2 0x0410 187 188/** 189 * @brief User error registers 190 */ 191#define SLI4_UERR_STATUS_LOW_REG 0xA0 192#define SLI4_UERR_STATUS_HIGH_REG 0xA4 193#define SLI4_UERR_MASK_LOW_REG 0xA8 194#define SLI4_UERR_MASK_HIGH_REG 0xAC 195 196/** 197 * @brief Registers for generating software UE (BE3) 198 */ 199#define SLI4_SW_UE_CSR1 0x138 200#define SLI4_SW_UE_CSR2 0x1FFFC 201 202/** 203 * @brief Registers for generating software UE (Skyhawk) 204 */ 205#define SLI4_SW_UE_REG 0x5C /* register offset */ 206 207static inline uint32_t sli_eq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm) 208{ 209 uint32_t reg = 0; 210#if BYTE_ORDER == LITTLE_ENDIAN 211 struct { 212 uint32_t eq_id_lo:9, 213 ci:1, /* clear interrupt */ 214 qt:1, /* queue type */ 215 eq_id_hi:5, 216 number_popped:13, 217 arm:1, 218 :1, 219 se:1; 220 } * eq_doorbell = (void *)® 221#else 222#error big endian version not defined 223#endif 224 225 eq_doorbell->eq_id_lo = id & SLI4_EQCQ_EQ_ID_MASK_LO; 226 eq_doorbell->qt = 1; /* EQ is type 1 (section 2.2.3.3 SLI Arch) */ 227 eq_doorbell->eq_id_hi = (id >> 9) & 0x1f; 228 eq_doorbell->number_popped = n_popped; 229 eq_doorbell->arm = arm; 230 eq_doorbell->ci = TRUE; 231 232 return reg; 233} 234 235static inline uint32_t sli_cq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm) 236{ 237 uint32_t reg = 0; 238#if BYTE_ORDER == LITTLE_ENDIAN 239 struct { 240 uint32_t cq_id_lo:10, 241 qt:1, /* queue type */ 242 cq_id_hi:5, 243 number_popped:13, 244 arm:1, 245 :1, 246 se:1; 247 } * cq_doorbell = (void *)® 248#else 249#error big endian version not defined 250#endif 251 252 cq_doorbell->cq_id_lo = id & SLI4_EQCQ_CQ_ID_MASK_LO; 253 cq_doorbell->qt = 0; /* CQ is type 0 (section 2.2.3.3 SLI Arch) */ 254 cq_doorbell->cq_id_hi = (id >> 10) & 0x1f; 255 cq_doorbell->number_popped = n_popped; 256 cq_doorbell->arm = arm; 257 258 return reg; 259} 260 261static inline uint32_t sli_iftype6_eq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm) 262{ 263 uint32_t reg = 0; 264#if BYTE_ORDER == LITTLE_ENDIAN 265 struct { 266 uint32_t eq_id:12, 267 :4, /* clear interrupt */ 268 number_popped:13, 269 arm:1, 270 :1, 271 io:1; 272 } * eq_doorbell = (void *)® 273#else 274#error big endian version not defined 275#endif 276 277 eq_doorbell->eq_id = id; 278 eq_doorbell->number_popped = n_popped; 279 eq_doorbell->arm = arm; 280 281 return reg; 282} 283 284static inline uint32_t sli_iftype6_cq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm) 285{ 286 uint32_t reg = 0; 287#if BYTE_ORDER == LITTLE_ENDIAN 288 struct { 289 uint32_t cq_id:16, 290 number_popped:13, 291 arm:1, 292 :1, 293 se:1; 294 } * cq_doorbell = (void *)® 295#else 296#error big endian version not defined 297#endif 298 299 cq_doorbell->cq_id = id; 300 cq_doorbell->number_popped = n_popped; 301 cq_doorbell->arm = arm; 302 303 return reg; 304} 305 306/** 307 * @brief MQ_DOORBELL - MQ Doorbell Register 308 */ 309#define SLI4_MQ_DOORBELL_REG 0x0140 /* register offset */ 310#define SLI4_IF6_MQ_DOORBELL_REG 0x0160 /* register offset if_type = 6 */ 311#define SLI4_MQ_DOORBELL_NUM_SHIFT 16 312#define SLI4_MQ_DOORBELL_NUM_MASK 0x3fff 313#define SLI4_MQ_DOORBELL_ID_MASK 0xffff 314#define SLI4_MQ_DOORBELL(n, i) ((((n) & SLI4_MQ_DOORBELL_NUM_MASK) << SLI4_MQ_DOORBELL_NUM_SHIFT) | \ 315 ((i) & SLI4_MQ_DOORBELL_ID_MASK)) 316 317/** 318 * @brief RQ_DOORBELL - RQ Doorbell Register 319 */ 320#define SLI4_RQ_DOORBELL_REG 0x0a0 /* register offset */ 321#define SLI4_IF6_RQ_DOORBELL_REG 0x0080 /* register offset of if_type = 6 */ 322#define SLI4_RQ_DOORBELL_NUM_SHIFT 16 323#define SLI4_RQ_DOORBELL_NUM_MASK 0x3fff 324#define SLI4_RQ_DOORBELL_ID_MASK 0xffff 325#define SLI4_RQ_DOORBELL(n, i) ((((n) & SLI4_RQ_DOORBELL_NUM_MASK) << SLI4_RQ_DOORBELL_NUM_SHIFT) | \ 326 ((i) & SLI4_RQ_DOORBELL_ID_MASK)) 327 328/** 329 * @brief WQ_DOORBELL - WQ Doorbell Register 330 */ 331#define SLI4_IO_WQ_DOORBELL_REG 0x040 /* register offset */ 332#define SLI4_IF6_WQ_DOORBELL_REG 0x040 /* register offset for if_type = 6 */ 333#define SLI4_WQ_DOORBELL_IDX_SHIFT 16 334#define SLI4_WQ_DOORBELL_IDX_MASK 0x00ff 335#define SLI4_WQ_DOORBELL_NUM_SHIFT 24 336#define SLI4_WQ_DOORBELL_NUM_MASK 0x00ff 337#define SLI4_WQ_DOORBELL_ID_MASK 0xffff 338#define SLI4_WQ_DOORBELL(n, x, i) ((((n) & SLI4_WQ_DOORBELL_NUM_MASK) << SLI4_WQ_DOORBELL_NUM_SHIFT) | \ 339 (((x) & SLI4_WQ_DOORBELL_IDX_MASK) << SLI4_WQ_DOORBELL_IDX_SHIFT) | \ 340 ((i) & SLI4_WQ_DOORBELL_ID_MASK)) 341 342/** 343 * @brief SLIPORT_SEMAPHORE - SLI Port Host and Port Status Register 344 */ 345#define SLI4_PORT_SEMAPHORE_REG_0 0x00ac /** register offset Interface Type 0 + 1 */ 346#define SLI4_PORT_SEMAPHORE_REG_1 0x0180 /** register offset Interface Type 0 + 1 */ 347#define SLI4_PORT_SEMAPHORE_REG_236 0x0400 /** register offset Interface Type 2 + 3 + 6*/ 348#define SLI4_PORT_SEMAPHORE_PORT_MASK 0x0000ffff 349#define SLI4_PORT_SEMAPHORE_PORT(r) ((r) & SLI4_PORT_SEMAPHORE_PORT_MASK) 350#define SLI4_PORT_SEMAPHORE_HOST_MASK 0x00ff0000 351#define SLI4_PORT_SEMAPHORE_HOST_SHIFT 16 352#define SLI4_PORT_SEMAPHORE_HOST(r) (((r) & SLI4_PORT_SEMAPHORE_HOST_MASK) >> \ 353 SLI4_PORT_SEMAPHORE_HOST_SHIFT) 354#define SLI4_PORT_SEMAPHORE_SCR2 BIT(26) /** scratch area 2 */ 355#define SLI4_PORT_SEMAPHORE_SCR1 BIT(27) /** scratch area 1 */ 356#define SLI4_PORT_SEMAPHORE_IPC BIT(28) /** IP conflict */ 357#define SLI4_PORT_SEMAPHORE_NIP BIT(29) /** no IP address */ 358#define SLI4_PORT_SEMAPHORE_SFI BIT(30) /** secondary firmware image used */ 359#define SLI4_PORT_SEMAPHORE_PERR BIT(31) /** POST fatal error */ 360 361#define SLI4_PORT_SEMAPHORE_STATUS_POST_READY 0xc000 362#define SLI4_PORT_SEMAPHORE_STATUS_UNRECOV_ERR 0xf000 363#define SLI4_PORT_SEMAPHORE_STATUS_ERR_MASK 0xf000 364#define SLI4_PORT_SEMAPHORE_IN_ERR(r) (SLI4_PORT_SEMAPHORE_STATUS_UNRECOV_ERR == ((r) & \ 365 SLI4_PORT_SEMAPHORE_STATUS_ERR_MASK)) 366 367/** 368 * @brief SLIPORT_STATUS - SLI Port Status Register 369 */ 370 371#define SLI4_PORT_STATUS_REG_236 0x0404 /** register offset Interface Type 2 + 3 + 6*/ 372#define SLI4_PORT_STATUS_FDP BIT(21) /** function specific dump present */ 373#define SLI4_PORT_STATUS_RDY BIT(23) /** ready */ 374#define SLI4_PORT_STATUS_RN BIT(24) /** reset needed */ 375#define SLI4_PORT_STATUS_DIP BIT(25) /** dump present */ 376#define SLI4_PORT_STATUS_OTI BIT(29) /** over temp indicator */ 377#define SLI4_PORT_STATUS_END BIT(30) /** endianness */ 378#define SLI4_PORT_STATUS_ERR BIT(31) /** SLI port error */ 379#define SLI4_PORT_STATUS_READY(r) ((r) & SLI4_PORT_STATUS_RDY) 380#define SLI4_PORT_STATUS_ERROR(r) ((r) & SLI4_PORT_STATUS_ERR) 381#define SLI4_PORT_STATUS_DUMP_PRESENT(r) ((r) & SLI4_PORT_STATUS_DIP) 382#define SLI4_PORT_STATUS_FDP_PRESENT(r) ((r) & SLI4_PORT_STATUS_FDP) 383 384#define SLI4_PHSDEV_CONTROL_REG_236 0x0414 /** register offset Interface Type 2 + 3 + 6*/ 385#define SLI4_PHYDEV_CONTROL_DRST BIT(0) /** physical device reset */ 386#define SLI4_PHYDEV_CONTROL_FRST BIT(1) /** firmware reset */ 387#define SLI4_PHYDEV_CONTROL_DD BIT(2) /** diagnostic dump */ 388#define SLI4_PHYDEV_CONTROL_FRL_MASK 0x000000f0 389#define SLI4_PHYDEV_CONTROL_FRL_SHIFT 4 390#define SLI4_PHYDEV_CONTROL_FRL(r) (((r) & SLI4_PHYDEV_CONTROL_FRL_MASK) >> \ 391 SLI4_PHYDEV_CONTROL_FRL_SHIFT_SHIFT) 392 393/************************************************************************* 394 * SLI-4 mailbox command formats and definitions 395 */ 396 397typedef struct sli4_mbox_command_header_s { 398#if BYTE_ORDER == LITTLE_ENDIAN 399 uint32_t :8, 400 command:8, 401 status:16; /** Port writes to indicate success / fail */ 402#else 403#error big endian version not defined 404#endif 405} sli4_mbox_command_header_t; 406 407#define SLI4_MBOX_COMMAND_CONFIG_LINK 0x07 408#define SLI4_MBOX_COMMAND_DUMP 0x17 409#define SLI4_MBOX_COMMAND_DOWN_LINK 0x06 410#define SLI4_MBOX_COMMAND_INIT_LINK 0x05 411#define SLI4_MBOX_COMMAND_INIT_VFI 0xa3 412#define SLI4_MBOX_COMMAND_INIT_VPI 0xa4 413#define SLI4_MBOX_COMMAND_POST_XRI 0xa7 414#define SLI4_MBOX_COMMAND_RELEASE_XRI 0xac 415#define SLI4_MBOX_COMMAND_READ_CONFIG 0x0b 416#define SLI4_MBOX_COMMAND_READ_STATUS 0x0e 417#define SLI4_MBOX_COMMAND_READ_NVPARMS 0x02 418#define SLI4_MBOX_COMMAND_READ_REV 0x11 419#define SLI4_MBOX_COMMAND_READ_LNK_STAT 0x12 420#define SLI4_MBOX_COMMAND_READ_SPARM64 0x8d 421#define SLI4_MBOX_COMMAND_READ_TOPOLOGY 0x95 422#define SLI4_MBOX_COMMAND_REG_FCFI 0xa0 423#define SLI4_MBOX_COMMAND_REG_FCFI_MRQ 0xaf 424#define SLI4_MBOX_COMMAND_REG_RPI 0x93 425#define SLI4_MBOX_COMMAND_REG_RX_RQ 0xa6 426#define SLI4_MBOX_COMMAND_REG_VFI 0x9f 427#define SLI4_MBOX_COMMAND_REG_VPI 0x96 428#define SLI4_MBOX_COMMAND_REQUEST_FEATURES 0x9d 429#define SLI4_MBOX_COMMAND_SLI_CONFIG 0x9b 430#define SLI4_MBOX_COMMAND_UNREG_FCFI 0xa2 431#define SLI4_MBOX_COMMAND_UNREG_RPI 0x14 432#define SLI4_MBOX_COMMAND_UNREG_VFI 0xa1 433#define SLI4_MBOX_COMMAND_UNREG_VPI 0x97 434#define SLI4_MBOX_COMMAND_WRITE_NVPARMS 0x03 435#define SLI4_MBOX_COMMAND_CONFIG_AUTO_XFER_RDY 0xAD 436#define SLI4_MBOX_COMMAND_CONFIG_AUTO_XFER_RDY_HP 0xAE 437 438#define SLI4_MBOX_STATUS_SUCCESS 0x0000 439#define SLI4_MBOX_STATUS_FAILURE 0x0001 440#define SLI4_MBOX_STATUS_RPI_NOT_REG 0x1400 441 442/** 443 * @brief Buffer Descriptor Entry (BDE) 444 */ 445typedef struct sli4_bde_s { 446#if BYTE_ORDER == LITTLE_ENDIAN 447 uint32_t buffer_length:24, 448 bde_type:8; 449 union { 450 struct { 451 uint32_t buffer_address_low; 452 uint32_t buffer_address_high; 453 } data; 454 struct { 455 uint32_t offset; 456 uint32_t rsvd2; 457 } imm; 458 struct { 459 uint32_t sgl_segment_address_low; 460 uint32_t sgl_segment_address_high; 461 } blp; 462 } u; 463#else 464#error big endian version not defined 465#endif 466} sli4_bde_t; 467 468#define SLI4_BDE_TYPE_BDE_64 0x00 /** Generic 64-bit data */ 469#define SLI4_BDE_TYPE_BDE_IMM 0x01 /** Immediate data */ 470#define SLI4_BDE_TYPE_BLP 0x40 /** Buffer List Pointer */ 471 472/** 473 * @brief Scatter-Gather Entry (SGE) 474 */ 475typedef struct sli4_sge_s { 476#if BYTE_ORDER == LITTLE_ENDIAN 477 uint32_t buffer_address_high; 478 uint32_t buffer_address_low; 479 uint32_t data_offset:27, 480 sge_type:4, 481 last:1; 482 uint32_t buffer_length; 483#else 484#error big endian version not defined 485#endif 486} sli4_sge_t; 487 488/** 489 * @brief T10 DIF Scatter-Gather Entry (SGE) 490 */ 491typedef struct sli4_dif_sge_s { 492#if BYTE_ORDER == LITTLE_ENDIAN 493 uint32_t buffer_address_high; 494 uint32_t buffer_address_low; 495 uint32_t :27, 496 sge_type:4, 497 last:1; 498 uint32_t :32; 499#else 500#error big endian version not defined 501#endif 502} sli4_dif_sge_t; 503 504/** 505 * @brief T10 DIF Seed Scatter-Gather Entry (SGE) 506 */ 507typedef struct sli4_diseed_sge_s { 508#if BYTE_ORDER == LITTLE_ENDIAN 509 uint32_t ref_tag_cmp; 510 uint32_t ref_tag_repl; 511 uint32_t app_tag_repl:16, 512 :2, 513 hs:1, 514 ws:1, 515 ic:1, 516 ics:1, 517 atrt:1, 518 at:1, 519 fwd_app_tag:1, 520 repl_app_tag:1, 521 head_insert:1, 522 sge_type:4, 523 last:1; 524 uint32_t app_tag_cmp:16, 525 dif_blk_size:3, 526 auto_incr_ref_tag:1, 527 check_app_tag:1, 528 check_ref_tag:1, 529 check_crc:1, 530 new_ref_tag:1, 531 dif_op_rx:4, 532 dif_op_tx:4; 533#else 534#error big endian version not defined 535#endif 536} sli4_diseed_sge_t; 537 538/** 539 * @brief List Segment Pointer Scatter-Gather Entry (SGE) 540 */ 541typedef struct sli4_lsp_sge_s { 542#if BYTE_ORDER == LITTLE_ENDIAN 543 uint32_t buffer_address_high; 544 uint32_t buffer_address_low; 545 uint32_t :27, 546 sge_type:4, 547 last:1; 548 uint32_t segment_length:24, 549 :8; 550#else 551#error big endian version not defined 552#endif 553} sli4_lsp_sge_t; 554 555#define SLI4_SGE_MAX_RESERVED 3 556 557#define SLI4_SGE_DIF_OP_IN_NODIF_OUT_CRC 0x00 558#define SLI4_SGE_DIF_OP_IN_CRC_OUT_NODIF 0x01 559#define SLI4_SGE_DIF_OP_IN_NODIF_OUT_CHKSUM 0x02 560#define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_NODIF 0x03 561#define SLI4_SGE_DIF_OP_IN_CRC_OUT_CRC 0x04 562#define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_CHKSUM 0x05 563#define SLI4_SGE_DIF_OP_IN_CRC_OUT_CHKSUM 0x06 564#define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_CRC 0x07 565#define SLI4_SGE_DIF_OP_IN_RAW_OUT_RAW 0x08 566 567#define SLI4_SGE_TYPE_DATA 0x00 568#define SLI4_SGE_TYPE_CHAIN 0x03 /** Skyhawk only */ 569#define SLI4_SGE_TYPE_DIF 0x04 /** Data Integrity Field */ 570#define SLI4_SGE_TYPE_LSP 0x05 /** List Segment Pointer */ 571#define SLI4_SGE_TYPE_PEDIF 0x06 /** Post Encryption Engine DIF */ 572#define SLI4_SGE_TYPE_PESEED 0x07 /** Post Encryption Engine DIF Seed */ 573#define SLI4_SGE_TYPE_DISEED 0x08 /** DIF Seed */ 574#define SLI4_SGE_TYPE_ENC 0x09 /** Encryption */ 575#define SLI4_SGE_TYPE_ATM 0x0a /** DIF Application Tag Mask */ 576#define SLI4_SGE_TYPE_SKIP 0x0c /** SKIP */ 577 578#define OCS_MAX_SGE_SIZE 0x80000000 /* Maximum data allowed in a SGE */ 579 580/** 581 * @brief CONFIG_LINK 582 */ 583typedef struct sli4_cmd_config_link_s { 584 sli4_mbox_command_header_t hdr; 585#if BYTE_ORDER == LITTLE_ENDIAN 586 uint32_t maxbbc:8, /** Max buffer-to-buffer credit */ 587 :24; 588 uint32_t alpa:8, 589 n_port_id:16, 590 :8; 591 uint32_t rsvd3; 592 uint32_t e_d_tov; 593 uint32_t lp_tov; 594 uint32_t r_a_tov; 595 uint32_t r_t_tov; 596 uint32_t al_tov; 597 uint32_t rsvd9; 598 uint32_t :8, 599 bbscn:4, /** buffer-to-buffer state change number */ 600 cscn:1, /** configure BBSCN */ 601 :19; 602#else 603#error big endian version not defined 604#endif 605} sli4_cmd_config_link_t; 606 607/** 608 * @brief DUMP Type 4 609 */ 610#define SLI4_WKI_TAG_SAT_TEM 0x1040 611typedef struct sli4_cmd_dump4_s { 612 sli4_mbox_command_header_t hdr; 613#if BYTE_ORDER == LITTLE_ENDIAN 614 uint32_t type:4, 615 :28; 616 uint32_t wki_selection:16, 617 :16; 618 uint32_t resv; 619 uint32_t returned_byte_cnt; 620 uint32_t resp_data[59]; 621#else 622#error big endian version not defined 623#endif 624} sli4_cmd_dump4_t; 625 626/** 627 * @brief FW_INITIALIZE - initialize a SLI port 628 * 629 * @note This command uses a different format than all others. 630 */ 631 632extern const uint8_t sli4_fw_initialize[8]; 633 634/** 635 * @brief FW_DEINITIALIZE - deinitialize a SLI port 636 * 637 * @note This command uses a different format than all others. 638 */ 639 640extern const uint8_t sli4_fw_deinitialize[8]; 641 642/** 643 * @brief INIT_LINK - initialize the link for a FC/FCoE port 644 */ 645typedef struct sli4_cmd_init_link_flags_s { 646 uint32_t loopback:1, 647 topology:2, 648 #define FC_TOPOLOGY_FCAL 0 649 #define FC_TOPOLOGY_P2P 1 650 :3, 651 unfair:1, 652 skip_lirp_lilp:1, 653 gen_loop_validity_check:1, 654 skip_lisa:1, 655 enable_topology_failover:1, 656 fixed_speed:1, 657 :3, 658 select_hightest_al_pa:1, 659 :16; /* pad to 32 bits */ 660} sli4_cmd_init_link_flags_t; 661 662#define SLI4_INIT_LINK_F_LOOP_BACK BIT(0) 663#define SLI4_INIT_LINK_F_UNFAIR BIT(6) 664#define SLI4_INIT_LINK_F_NO_LIRP BIT(7) 665#define SLI4_INIT_LINK_F_LOOP_VALID_CHK BIT(8) 666#define SLI4_INIT_LINK_F_NO_LISA BIT(9) 667#define SLI4_INIT_LINK_F_FAIL_OVER BIT(10) 668#define SLI4_INIT_LINK_F_NO_AUTOSPEED BIT(11) 669#define SLI4_INIT_LINK_F_PICK_HI_ALPA BIT(15) 670 671#define SLI4_INIT_LINK_F_P2P_ONLY 1 672#define SLI4_INIT_LINK_F_FCAL_ONLY 2 673 674#define SLI4_INIT_LINK_F_FCAL_FAIL_OVER 0 675#define SLI4_INIT_LINK_F_P2P_FAIL_OVER 1 676 677typedef struct sli4_cmd_init_link_s { 678 sli4_mbox_command_header_t hdr; 679#if BYTE_ORDER == LITTLE_ENDIAN 680 uint32_t selective_reset_al_pa:8, 681 :24; 682 sli4_cmd_init_link_flags_t link_flags; 683 uint32_t link_speed_selection_code; 684 #define FC_LINK_SPEED_1G 1 685 #define FC_LINK_SPEED_2G 2 686 #define FC_LINK_SPEED_AUTO_1_2 3 687 #define FC_LINK_SPEED_4G 4 688 #define FC_LINK_SPEED_AUTO_4_1 5 689 #define FC_LINK_SPEED_AUTO_4_2 6 690 #define FC_LINK_SPEED_AUTO_4_2_1 7 691 #define FC_LINK_SPEED_8G 8 692 #define FC_LINK_SPEED_AUTO_8_1 9 693 #define FC_LINK_SPEED_AUTO_8_2 10 694 #define FC_LINK_SPEED_AUTO_8_2_1 11 695 #define FC_LINK_SPEED_AUTO_8_4 12 696 #define FC_LINK_SPEED_AUTO_8_4_1 13 697 #define FC_LINK_SPEED_AUTO_8_4_2 14 698 #define FC_LINK_SPEED_10G 16 699 #define FC_LINK_SPEED_16G 17 700 #define FC_LINK_SPEED_AUTO_16_8_4 18 701 #define FC_LINK_SPEED_AUTO_16_8 19 702 #define FC_LINK_SPEED_32G 20 703 #define FC_LINK_SPEED_AUTO_32_16_8 21 704 #define FC_LINK_SPEED_AUTO_32_16 22 705#else 706#error big endian version not defined 707#endif 708} sli4_cmd_init_link_t; 709 710/** 711 * @brief INIT_VFI - initialize the VFI resource 712 */ 713typedef struct sli4_cmd_init_vfi_s { 714 sli4_mbox_command_header_t hdr; 715#if BYTE_ORDER == LITTLE_ENDIAN 716 uint32_t vfi:16, 717 :12, 718 vp:1, 719 vf:1, 720 vt:1, 721 vr:1; 722 uint32_t fcfi:16, 723 vpi:16; 724 uint32_t vf_id:13, 725 pri:3, 726 :16; 727 uint32_t :24, 728 hop_count:8; 729#else 730#error big endian version not defined 731#endif 732} sli4_cmd_init_vfi_t; 733 734/** 735 * @brief INIT_VPI - initialize the VPI resource 736 */ 737typedef struct sli4_cmd_init_vpi_s { 738 sli4_mbox_command_header_t hdr; 739#if BYTE_ORDER == LITTLE_ENDIAN 740 uint32_t vpi:16, 741 vfi:16; 742#else 743#error big endian version not defined 744#endif 745} sli4_cmd_init_vpi_t; 746 747/** 748 * @brief POST_XRI - post XRI resources to the SLI Port 749 */ 750typedef struct sli4_cmd_post_xri_s { 751 sli4_mbox_command_header_t hdr; 752#if BYTE_ORDER == LITTLE_ENDIAN 753 uint32_t xri_base:16, 754 xri_count:12, 755 enx:1, 756 dl:1, 757 di:1, 758 val:1; 759#else 760#error big endian version not defined 761#endif 762} sli4_cmd_post_xri_t; 763 764/** 765 * @brief RELEASE_XRI - Release XRI resources from the SLI Port 766 */ 767typedef struct sli4_cmd_release_xri_s { 768 sli4_mbox_command_header_t hdr; 769#if BYTE_ORDER == LITTLE_ENDIAN 770 uint32_t released_xri_count:5, 771 :11, 772 xri_count:5, 773 :11; 774 struct { 775 uint32_t xri_tag0:16, 776 xri_tag1:16; 777 } xri_tbl[62]; 778#else 779#error big endian version not defined 780#endif 781} sli4_cmd_release_xri_t; 782 783/** 784 * @brief READ_CONFIG - read SLI port configuration parameters 785 */ 786typedef struct sli4_cmd_read_config_s { 787 sli4_mbox_command_header_t hdr; 788} sli4_cmd_read_config_t; 789 790typedef struct sli4_res_read_config_s { 791 sli4_mbox_command_header_t hdr; 792#if BYTE_ORDER == LITTLE_ENDIAN 793 uint32_t :31, 794 ext:1; /** Resource Extents */ 795 uint32_t :20, 796 pt:2, 797 tf:1, 798 ptv:1, 799 topology:8; 800 uint32_t rsvd3; 801 uint32_t e_d_tov:16, 802 :16; 803 uint32_t rsvd5; 804 uint32_t r_a_tov:16, 805 :16; 806 uint32_t rsvd7; 807 uint32_t rsvd8; 808 uint32_t lmt:16, /** Link Module Type */ 809 :16; 810 uint32_t rsvd10; 811 uint32_t rsvd11; 812 uint32_t xri_base:16, 813 xri_count:16; 814 uint32_t rpi_base:16, 815 rpi_count:16; 816 uint32_t vpi_base:16, 817 vpi_count:16; 818 uint32_t vfi_base:16, 819 vfi_count:16; 820 uint32_t :16, 821 fcfi_count:16; 822 uint32_t rq_count:16, 823 eq_count:16; 824 uint32_t wq_count:16, 825 cq_count:16; 826 uint32_t pad[45]; 827#else 828#error big endian version not defined 829#endif 830} sli4_res_read_config_t; 831 832#define SLI4_READ_CFG_TOPO_FCOE 0x0 /** FCoE topology */ 833#define SLI4_READ_CFG_TOPO_FC 0x1 /** FC topology unknown */ 834#define SLI4_READ_CFG_TOPO_FC_DA 0x2 /** FC Direct Attach (non FC-AL) topology */ 835#define SLI4_READ_CFG_TOPO_FC_AL 0x3 /** FC-AL topology */ 836 837/** 838 * @brief READ_NVPARMS - read SLI port configuration parameters 839 */ 840typedef struct sli4_cmd_read_nvparms_s { 841 sli4_mbox_command_header_t hdr; 842#if BYTE_ORDER == LITTLE_ENDIAN 843 uint32_t rsvd1; 844 uint32_t rsvd2; 845 uint32_t rsvd3; 846 uint32_t rsvd4; 847 uint8_t wwpn[8]; 848 uint8_t wwnn[8]; 849 uint32_t hard_alpa:8, 850 preferred_d_id:24; 851#else 852#error big endian version not defined 853#endif 854} sli4_cmd_read_nvparms_t; 855 856/** 857 * @brief WRITE_NVPARMS - write SLI port configuration parameters 858 */ 859typedef struct sli4_cmd_write_nvparms_s { 860 sli4_mbox_command_header_t hdr; 861#if BYTE_ORDER == LITTLE_ENDIAN 862 uint32_t rsvd1; 863 uint32_t rsvd2; 864 uint32_t rsvd3; 865 uint32_t rsvd4; 866 uint8_t wwpn[8]; 867 uint8_t wwnn[8]; 868 uint32_t hard_alpa:8, 869 preferred_d_id:24; 870#else 871#error big endian version not defined 872#endif 873} sli4_cmd_write_nvparms_t; 874 875/** 876 * @brief READ_REV - read the Port revision levels 877 */ 878typedef struct sli4_cmd_read_rev_s { 879 sli4_mbox_command_header_t hdr; 880#if BYTE_ORDER == LITTLE_ENDIAN 881 uint32_t :16, 882 sli_level:4, 883 fcoem:1, 884 ceev:2, 885 :6, 886 vpd:1, 887 :2; 888 uint32_t first_hw_revision; 889 uint32_t second_hw_revision; 890 uint32_t rsvd4; 891 uint32_t third_hw_revision; 892 uint32_t fc_ph_low:8, 893 fc_ph_high:8, 894 feature_level_low:8, 895 feature_level_high:8; 896 uint32_t rsvd7; 897 uint32_t first_fw_id; 898 char first_fw_name[16]; 899 uint32_t second_fw_id; 900 char second_fw_name[16]; 901 uint32_t rsvd18[30]; 902 uint32_t available_length:24, 903 :8; 904 uint32_t physical_address_low; 905 uint32_t physical_address_high; 906 uint32_t returned_vpd_length; 907 uint32_t actual_vpd_length; 908#else 909#error big endian version not defined 910#endif 911} sli4_cmd_read_rev_t; 912 913/** 914 * @brief READ_SPARM64 - read the Port service parameters 915 */ 916typedef struct sli4_cmd_read_sparm64_s { 917 sli4_mbox_command_header_t hdr; 918#if BYTE_ORDER == LITTLE_ENDIAN 919 uint32_t rsvd1; 920 uint32_t rsvd2; 921 sli4_bde_t bde_64; 922 uint32_t vpi:16, 923 :16; 924 uint32_t port_name_start:16, 925 port_name_length:16; 926 uint32_t node_name_start:16, 927 node_name_length:16; 928#else 929#error big endian version not defined 930#endif 931} sli4_cmd_read_sparm64_t; 932 933#define SLI4_READ_SPARM64_VPI_DEFAULT 0 934#define SLI4_READ_SPARM64_VPI_SPECIAL UINT16_MAX 935 936#define SLI4_READ_SPARM64_WWPN_OFFSET (4 * sizeof(uint32_t)) 937#define SLI4_READ_SPARM64_WWNN_OFFSET (SLI4_READ_SPARM64_WWPN_OFFSET + sizeof(uint64_t)) 938 939typedef struct sli4_port_state_s { 940#if BYTE_ORDER == LITTLE_ENDIAN 941 uint32_t nx_port_recv_state:2, 942 nx_port_trans_state:2, 943 nx_port_state_machine:4, 944 link_speed:8, 945 :14, 946 tf:1, 947 lu:1; 948#else 949#error big endian version not defined 950#endif 951} sli4_port_state_t; 952 953/** 954 * @brief READ_TOPOLOGY - read the link event information 955 */ 956typedef struct sli4_cmd_read_topology_s { 957 sli4_mbox_command_header_t hdr; 958#if BYTE_ORDER == LITTLE_ENDIAN 959 uint32_t event_tag; 960 uint32_t attention_type:8, 961 il:1, 962 pb_recvd:1, 963 :22; 964 uint32_t topology:8, 965 lip_type:8, 966 lip_al_ps:8, 967 al_pa_granted:8; 968 sli4_bde_t bde_loop_map; 969 sli4_port_state_t link_down; 970 sli4_port_state_t link_current; 971 uint32_t max_bbc:8, 972 init_bbc:8, 973 bbscn:4, 974 cbbscn:4, 975 :8; 976 uint32_t r_t_tov:9, 977 :3, 978 al_tov:4, 979 lp_tov:16; 980 uint32_t acquired_al_pa:8, 981 :7, 982 pb:1, 983 specified_al_pa:16; 984 uint32_t initial_n_port_id:24, 985 :8; 986#else 987#error big endian version not defined 988#endif 989} sli4_cmd_read_topology_t; 990 991#define SLI4_MIN_LOOP_MAP_BYTES 128 992 993#define SLI4_READ_TOPOLOGY_LINK_UP 0x1 994#define SLI4_READ_TOPOLOGY_LINK_DOWN 0x2 995#define SLI4_READ_TOPOLOGY_LINK_NO_ALPA 0x3 996 997#define SLI4_READ_TOPOLOGY_UNKNOWN 0x0 998#define SLI4_READ_TOPOLOGY_NPORT 0x1 999#define SLI4_READ_TOPOLOGY_FC_AL 0x2 1000 1001#define SLI4_READ_TOPOLOGY_SPEED_NONE 0x00 1002#define SLI4_READ_TOPOLOGY_SPEED_1G 0x04 1003#define SLI4_READ_TOPOLOGY_SPEED_2G 0x08 1004#define SLI4_READ_TOPOLOGY_SPEED_4G 0x10 1005#define SLI4_READ_TOPOLOGY_SPEED_8G 0x20 1006#define SLI4_READ_TOPOLOGY_SPEED_10G 0x40 1007#define SLI4_READ_TOPOLOGY_SPEED_16G 0x80 1008#define SLI4_READ_TOPOLOGY_SPEED_32G 0x90 1009 1010/** 1011 * @brief REG_FCFI - activate a FC Forwarder 1012 */ 1013#define SLI4_CMD_REG_FCFI_NUM_RQ_CFG 4 1014typedef struct sli4_cmd_reg_fcfi_s { 1015 sli4_mbox_command_header_t hdr; 1016#if BYTE_ORDER == LITTLE_ENDIAN 1017 uint32_t fcf_index:16, 1018 fcfi:16; 1019 uint32_t rq_id_1:16, 1020 rq_id_0:16; 1021 uint32_t rq_id_3:16, 1022 rq_id_2:16; 1023 struct { 1024 uint32_t r_ctl_mask:8, 1025 r_ctl_match:8, 1026 type_mask:8, 1027 type_match:8; 1028 } rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG]; 1029 uint32_t vlan_tag:12, 1030 vv:1, 1031 :19; 1032#else 1033#error big endian version not defined 1034#endif 1035} sli4_cmd_reg_fcfi_t; 1036 1037#define SLI4_CMD_REG_FCFI_MRQ_NUM_RQ_CFG 4 1038#define SLI4_CMD_REG_FCFI_MRQ_MAX_NUM_RQ 32 1039#define SLI4_CMD_REG_FCFI_SET_FCFI_MODE 0 1040#define SLI4_CMD_REG_FCFI_SET_MRQ_MODE 1 1041 1042typedef struct sli4_cmd_reg_fcfi_mrq_s { 1043 sli4_mbox_command_header_t hdr; 1044#if BYTE_ORDER == LITTLE_ENDIAN 1045 uint32_t fcf_index:16, 1046 fcfi:16; 1047 1048 uint32_t rq_id_1:16, 1049 rq_id_0:16; 1050 1051 uint32_t rq_id_3:16, 1052 rq_id_2:16; 1053 1054 struct { 1055 uint32_t r_ctl_mask:8, 1056 r_ctl_match:8, 1057 type_mask:8, 1058 type_match:8; 1059 } rq_cfg[SLI4_CMD_REG_FCFI_MRQ_NUM_RQ_CFG]; 1060 1061 uint32_t vlan_tag:12, 1062 vv:1, 1063 mode:1, 1064 :18; 1065 1066 uint32_t num_mrq_pairs:8, 1067 mrq_filter_bitmask:4, 1068 rq_selection_policy:4, 1069 :16; 1070#endif 1071} sli4_cmd_reg_fcfi_mrq_t; 1072 1073/** 1074 * @brief REG_RPI - register a Remote Port Indicator 1075 */ 1076typedef struct sli4_cmd_reg_rpi_s { 1077 sli4_mbox_command_header_t hdr; 1078#if BYTE_ORDER == LITTLE_ENDIAN 1079 uint32_t rpi:16, 1080 :16; 1081 uint32_t remote_n_port_id:24, 1082 upd:1, 1083 :2, 1084 etow:1, 1085 :1, 1086 terp:1, 1087 :1, 1088 ci:1; 1089 sli4_bde_t bde_64; 1090 uint32_t vpi:16, 1091 :16; 1092#else 1093#error big endian version not defined 1094#endif 1095} sli4_cmd_reg_rpi_t; 1096#define SLI4_REG_RPI_BUF_LEN 0x70 1097 1098/** 1099 * @brief REG_VFI - register a Virtual Fabric Indicator 1100 */ 1101typedef struct sli4_cmd_reg_vfi_s { 1102 sli4_mbox_command_header_t hdr; 1103#if BYTE_ORDER == LITTLE_ENDIAN 1104 uint32_t vfi:16, 1105 :12, 1106 vp:1, 1107 upd:1, 1108 :2; 1109 uint32_t fcfi:16, 1110 vpi:16; /* vp=TRUE */ 1111 uint8_t wwpn[8]; /* vp=TRUE */ 1112 sli4_bde_t sparm; /* either FLOGI or PLOGI */ 1113 uint32_t e_d_tov; 1114 uint32_t r_a_tov; 1115 uint32_t local_n_port_id:24, /* vp=TRUE */ 1116 :8; 1117#else 1118#error big endian version not defined 1119#endif 1120} sli4_cmd_reg_vfi_t; 1121 1122/** 1123 * @brief REG_VPI - register a Virtual Port Indicator 1124 */ 1125typedef struct sli4_cmd_reg_vpi_s { 1126 sli4_mbox_command_header_t hdr; 1127#if BYTE_ORDER == LITTLE_ENDIAN 1128 uint32_t rsvd1; 1129 uint32_t local_n_port_id:24, 1130 upd:1, 1131 :7; 1132 uint8_t wwpn[8]; 1133 uint32_t rsvd5; 1134 uint32_t vpi:16, 1135 vfi:16; 1136#else 1137#error big endian version not defined 1138#endif 1139} sli4_cmd_reg_vpi_t; 1140 1141/** 1142 * @brief REQUEST_FEATURES - request / query SLI features 1143 */ 1144typedef union { 1145#if BYTE_ORDER == LITTLE_ENDIAN 1146 struct { 1147 uint32_t iaab:1, /** inhibit auto-ABTS originator */ 1148 npiv:1, /** NPIV support */ 1149 dif:1, /** DIF/DIX support */ 1150 vf:1, /** virtual fabric support */ 1151 fcpi:1, /** FCP initiator support */ 1152 fcpt:1, /** FCP target support */ 1153 fcpc:1, /** combined FCP initiator/target */ 1154 :1, 1155 rqd:1, /** recovery qualified delay */ 1156 iaar:1, /** inhibit auto-ABTS responder */ 1157 hlm:1, /** High Login Mode */ 1158 perfh:1, /** performance hints */ 1159 rxseq:1, /** RX Sequence Coalescing */ 1160 rxri:1, /** Release XRI variant of Coalescing */ 1161 dcl2:1, /** Disable Class 2 */ 1162 rsco:1, /** Receive Sequence Coalescing Optimizations */ 1163 mrqp:1, /** Multi RQ Pair Mode Support */ 1164 :15; 1165 } flag; 1166 uint32_t dword; 1167#else 1168#error big endian version not defined 1169#endif 1170} sli4_features_t; 1171 1172typedef struct sli4_cmd_request_features_s { 1173 sli4_mbox_command_header_t hdr; 1174#if BYTE_ORDER == LITTLE_ENDIAN 1175 uint32_t qry:1, 1176 :31; 1177#else 1178#error big endian version not defined 1179#endif 1180 sli4_features_t command; 1181 sli4_features_t response; 1182} sli4_cmd_request_features_t; 1183 1184/** 1185 * @brief SLI_CONFIG - submit a configuration command to Port 1186 * 1187 * Command is either embedded as part of the payload (embed) or located 1188 * in a separate memory buffer (mem) 1189 */ 1190 1191typedef struct sli4_sli_config_pmd_s { 1192 uint32_t address_low; 1193 uint32_t address_high; 1194 uint32_t length:24, 1195 :8; 1196} sli4_sli_config_pmd_t; 1197 1198typedef struct sli4_cmd_sli_config_s { 1199 sli4_mbox_command_header_t hdr; 1200#if BYTE_ORDER == LITTLE_ENDIAN 1201 uint32_t emb:1, 1202 :2, 1203 pmd_count:5, 1204 :24; 1205 uint32_t payload_length; 1206 uint32_t rsvd3; 1207 uint32_t rsvd4; 1208 uint32_t rsvd5; 1209 union { 1210 uint8_t embed[58 * sizeof(uint32_t)]; 1211 sli4_sli_config_pmd_t mem; 1212 } payload; 1213#else 1214#error big endian version not defined 1215#endif 1216} sli4_cmd_sli_config_t; 1217 1218/** 1219 * @brief READ_STATUS - read tx/rx status of a particular port 1220 * 1221 */ 1222 1223typedef struct sli4_cmd_read_status_s { 1224 sli4_mbox_command_header_t hdr; 1225#if BYTE_ORDER == LITTLE_ENDIAN 1226 uint32_t cc:1, 1227 :31; 1228 uint32_t rsvd2; 1229 uint32_t transmit_kbyte_count; 1230 uint32_t receive_kbyte_count; 1231 uint32_t transmit_frame_count; 1232 uint32_t receive_frame_count; 1233 uint32_t transmit_sequence_count; 1234 uint32_t receive_sequence_count; 1235 uint32_t total_exchanges_originator; 1236 uint32_t total_exchanges_responder; 1237 uint32_t receive_p_bsy_count; 1238 uint32_t receive_f_bsy_count; 1239 uint32_t dropped_frames_due_to_no_rq_buffer_count; 1240 uint32_t empty_rq_timeout_count; 1241 uint32_t dropped_frames_due_to_no_xri_count; 1242 uint32_t empty_xri_pool_count; 1243 1244#else 1245#error big endian version not defined 1246#endif 1247} sli4_cmd_read_status_t; 1248 1249/** 1250 * @brief READ_LNK_STAT - read link status of a particular port 1251 * 1252 */ 1253 1254typedef struct sli4_cmd_read_link_stats_s { 1255 sli4_mbox_command_header_t hdr; 1256#if BYTE_ORDER == LITTLE_ENDIAN 1257 uint32_t rec:1, 1258 gec:1, 1259 w02of:1, 1260 w03of:1, 1261 w04of:1, 1262 w05of:1, 1263 w06of:1, 1264 w07of:1, 1265 w08of:1, 1266 w09of:1, 1267 w10of:1, 1268 w11of:1, 1269 w12of:1, 1270 w13of:1, 1271 w14of:1, 1272 w15of:1, 1273 w16of:1, 1274 w17of:1, 1275 w18of:1, 1276 w19of:1, 1277 w20of:1, 1278 w21of:1, 1279 resv0:8, 1280 clrc:1, 1281 clof:1; 1282 uint32_t link_failure_error_count; 1283 uint32_t loss_of_sync_error_count; 1284 uint32_t loss_of_signal_error_count; 1285 uint32_t primitive_sequence_error_count; 1286 uint32_t invalid_transmission_word_error_count; 1287 uint32_t crc_error_count; 1288 uint32_t primitive_sequence_event_timeout_count; 1289 uint32_t elastic_buffer_overrun_error_count; 1290 uint32_t arbitration_fc_al_timout_count; 1291 uint32_t advertised_receive_bufftor_to_buffer_credit; 1292 uint32_t current_receive_buffer_to_buffer_credit; 1293 uint32_t advertised_transmit_buffer_to_buffer_credit; 1294 uint32_t current_transmit_buffer_to_buffer_credit; 1295 uint32_t received_eofa_count; 1296 uint32_t received_eofdti_count; 1297 uint32_t received_eofni_count; 1298 uint32_t received_soff_count; 1299 uint32_t received_dropped_no_aer_count; 1300 uint32_t received_dropped_no_available_rpi_resources_count; 1301 uint32_t received_dropped_no_available_xri_resources_count; 1302 1303#else 1304#error big endian version not defined 1305#endif 1306} sli4_cmd_read_link_stats_t; 1307 1308/** 1309 * @brief Format a WQE with WQ_ID Association performance hint 1310 * 1311 * @par Description 1312 * PHWQ works by over-writing part of Word 10 in the WQE with the WQ ID. 1313 * 1314 * @param entry Pointer to the WQE. 1315 * @param q_id Queue ID. 1316 * 1317 * @return None. 1318 */ 1319static inline void 1320sli_set_wq_id_association(void *entry, uint16_t q_id) 1321{ 1322 uint32_t *wqe = entry; 1323 1324 /* 1325 * Set Word 10, bit 0 to zero 1326 * Set Word 10, bits 15:1 to the WQ ID 1327 */ 1328#if BYTE_ORDER == LITTLE_ENDIAN 1329 wqe[10] &= ~0xffff; 1330 wqe[10] |= q_id << 1; 1331#else 1332#error big endian version not defined 1333#endif 1334} 1335 1336/** 1337 * @brief UNREG_FCFI - unregister a FCFI 1338 */ 1339typedef struct sli4_cmd_unreg_fcfi_s { 1340 sli4_mbox_command_header_t hdr; 1341 uint32_t rsvd1; 1342#if BYTE_ORDER == LITTLE_ENDIAN 1343 uint32_t fcfi:16, 1344 :16; 1345#else 1346#error big endian version not defined 1347#endif 1348} sli4_cmd_unreg_fcfi_t; 1349 1350/** 1351 * @brief UNREG_RPI - unregister one or more RPI 1352 */ 1353typedef struct sli4_cmd_unreg_rpi_s { 1354 sli4_mbox_command_header_t hdr; 1355#if BYTE_ORDER == LITTLE_ENDIAN 1356 uint32_t index:16, 1357 :13, 1358 dp:1, 1359 ii:2; 1360 uint32_t destination_n_port_id:24, 1361 :8; 1362#else 1363#error big endian version not defined 1364#endif 1365} sli4_cmd_unreg_rpi_t; 1366 1367#define SLI4_UNREG_RPI_II_RPI 0x0 1368#define SLI4_UNREG_RPI_II_VPI 0x1 1369#define SLI4_UNREG_RPI_II_VFI 0x2 1370#define SLI4_UNREG_RPI_II_FCFI 0x3 1371 1372/** 1373 * @brief UNREG_VFI - unregister one or more VFI 1374 */ 1375typedef struct sli4_cmd_unreg_vfi_s { 1376 sli4_mbox_command_header_t hdr; 1377#if BYTE_ORDER == LITTLE_ENDIAN 1378 uint32_t rsvd1; 1379 uint32_t index:16, 1380 :14, 1381 ii:2; 1382#else 1383#error big endian version not defined 1384#endif 1385} sli4_cmd_unreg_vfi_t; 1386 1387#define SLI4_UNREG_VFI_II_VFI 0x0 1388#define SLI4_UNREG_VFI_II_FCFI 0x3 1389 1390enum { 1391 SLI4_UNREG_TYPE_PORT, 1392 SLI4_UNREG_TYPE_DOMAIN, 1393 SLI4_UNREG_TYPE_FCF, 1394 SLI4_UNREG_TYPE_ALL 1395}; 1396 1397/** 1398 * @brief UNREG_VPI - unregister one or more VPI 1399 */ 1400typedef struct sli4_cmd_unreg_vpi_s { 1401 sli4_mbox_command_header_t hdr; 1402#if BYTE_ORDER == LITTLE_ENDIAN 1403 uint32_t rsvd1; 1404 uint32_t index:16, 1405 :14, 1406 ii:2; 1407#else 1408#error big endian version not defined 1409#endif 1410} sli4_cmd_unreg_vpi_t; 1411 1412#define SLI4_UNREG_VPI_II_VPI 0x0 1413#define SLI4_UNREG_VPI_II_VFI 0x2 1414#define SLI4_UNREG_VPI_II_FCFI 0x3 1415 1416/** 1417 * @brief AUTO_XFER_RDY - Configure the auto-generate XFER-RDY feature. 1418 */ 1419typedef struct sli4_cmd_config_auto_xfer_rdy_s { 1420 sli4_mbox_command_header_t hdr; 1421#if BYTE_ORDER == LITTLE_ENDIAN 1422 uint32_t resv; 1423 uint32_t max_burst_len; 1424#else 1425#error big endian version not defined 1426#endif 1427} sli4_cmd_config_auto_xfer_rdy_t; 1428 1429typedef struct sli4_cmd_config_auto_xfer_rdy_hp_s { 1430 sli4_mbox_command_header_t hdr; 1431#if BYTE_ORDER == LITTLE_ENDIAN 1432 uint32_t resv; 1433 uint32_t max_burst_len; 1434 uint32_t esoc:1, 1435 :31; 1436 uint32_t block_size:16, 1437 :16; 1438#else 1439#error big endian version not defined 1440#endif 1441} sli4_cmd_config_auto_xfer_rdy_hp_t; 1442 1443/************************************************************************* 1444 * SLI-4 common configuration command formats and definitions 1445 */ 1446 1447#define SLI4_CFG_STATUS_SUCCESS 0x00 1448#define SLI4_CFG_STATUS_FAILED 0x01 1449#define SLI4_CFG_STATUS_ILLEGAL_REQUEST 0x02 1450#define SLI4_CFG_STATUS_ILLEGAL_FIELD 0x03 1451 1452#define SLI4_MGMT_STATUS_FLASHROM_READ_FAILED 0xcb 1453 1454#define SLI4_CFG_ADD_STATUS_NO_STATUS 0x00 1455#define SLI4_CFG_ADD_STATUS_INVALID_OPCODE 0x1e 1456 1457/** 1458 * Subsystem values. 1459 */ 1460#define SLI4_SUBSYSTEM_COMMON 0x01 1461#define SLI4_SUBSYSTEM_LOWLEVEL 0x0B 1462#define SLI4_SUBSYSTEM_FCFCOE 0x0c 1463#define SLI4_SUBSYSTEM_DMTF 0x11 1464 1465#define SLI4_OPC_LOWLEVEL_SET_WATCHDOG 0X36 1466 1467/** 1468 * Common opcode (OPC) values. 1469 */ 1470#define SLI4_OPC_COMMON_FUNCTION_RESET 0x3d 1471#define SLI4_OPC_COMMON_CREATE_CQ 0x0c 1472#define SLI4_OPC_COMMON_CREATE_CQ_SET 0x1d 1473#define SLI4_OPC_COMMON_DESTROY_CQ 0x36 1474#define SLI4_OPC_COMMON_MODIFY_EQ_DELAY 0x29 1475#define SLI4_OPC_COMMON_CREATE_EQ 0x0d 1476#define SLI4_OPC_COMMON_DESTROY_EQ 0x37 1477#define SLI4_OPC_COMMON_CREATE_MQ_EXT 0x5a 1478#define SLI4_OPC_COMMON_DESTROY_MQ 0x35 1479#define SLI4_OPC_COMMON_GET_CNTL_ATTRIBUTES 0x20 1480#define SLI4_OPC_COMMON_NOP 0x21 1481#define SLI4_OPC_COMMON_GET_RESOURCE_EXTENT_INFO 0x9a 1482#define SLI4_OPC_COMMON_GET_SLI4_PARAMETERS 0xb5 1483#define SLI4_OPC_COMMON_QUERY_FW_CONFIG 0x3a 1484#define SLI4_OPC_COMMON_GET_PORT_NAME 0x4d 1485 1486#define SLI4_OPC_COMMON_WRITE_FLASHROM 0x07 1487#define SLI4_OPC_COMMON_MANAGE_FAT 0x44 1488#define SLI4_OPC_COMMON_READ_TRANSCEIVER_DATA 0x49 1489#define SLI4_OPC_COMMON_GET_CNTL_ADDL_ATTRIBUTES 0x79 1490#define SLI4_OPC_COMMON_GET_EXT_FAT_CAPABILITIES 0x7d 1491#define SLI4_OPC_COMMON_SET_EXT_FAT_CAPABILITIES 0x7e 1492#define SLI4_OPC_COMMON_EXT_FAT_CONFIGURE_SNAPSHOT 0x7f 1493#define SLI4_OPC_COMMON_EXT_FAT_RETRIEVE_SNAPSHOT 0x80 1494#define SLI4_OPC_COMMON_EXT_FAT_READ_STRING_TABLE 0x82 1495#define SLI4_OPC_COMMON_GET_FUNCTION_CONFIG 0xa0 1496#define SLI4_OPC_COMMON_GET_PROFILE_CONFIG 0xa4 1497#define SLI4_OPC_COMMON_SET_PROFILE_CONFIG 0xa5 1498#define SLI4_OPC_COMMON_GET_PROFILE_LIST 0xa6 1499#define SLI4_OPC_COMMON_GET_ACTIVE_PROFILE 0xa7 1500#define SLI4_OPC_COMMON_SET_ACTIVE_PROFILE 0xa8 1501#define SLI4_OPC_COMMON_READ_OBJECT 0xab 1502#define SLI4_OPC_COMMON_WRITE_OBJECT 0xac 1503#define SLI4_OPC_COMMON_DELETE_OBJECT 0xae 1504#define SLI4_OPC_COMMON_READ_OBJECT_LIST 0xad 1505#define SLI4_OPC_COMMON_SET_DUMP_LOCATION 0xb8 1506#define SLI4_OPC_COMMON_SET_FEATURES 0xbf 1507#define SLI4_OPC_COMMON_GET_RECONFIG_LINK_INFO 0xc9 1508#define SLI4_OPC_COMMON_SET_RECONFIG_LINK_ID 0xca 1509 1510/** 1511 * DMTF opcode (OPC) values. 1512 */ 1513#define SLI4_OPC_DMTF_EXEC_CLP_CMD 0x01 1514 1515/** 1516 * @brief Generic Command Request header 1517 */ 1518typedef struct sli4_req_hdr_s { 1519#if BYTE_ORDER == LITTLE_ENDIAN 1520 uint32_t opcode:8, 1521 subsystem:8, 1522 :16; 1523 uint32_t timeout; 1524 uint32_t request_length; 1525 uint32_t version:8, 1526 :24; 1527#else 1528#error big endian version not defined 1529#endif 1530} sli4_req_hdr_t; 1531 1532/** 1533 * @brief Generic Command Response header 1534 */ 1535typedef struct sli4_res_hdr_s { 1536#if BYTE_ORDER == LITTLE_ENDIAN 1537 uint32_t opcode:8, 1538 subsystem:8, 1539 :16; 1540 uint32_t status:8, 1541 additional_status:8, 1542 :16; 1543 uint32_t response_length; 1544 uint32_t actual_response_length; 1545#else 1546#error big endian version not defined 1547#endif 1548} sli4_res_hdr_t; 1549 1550/** 1551 * @brief COMMON_FUNCTION_RESET 1552 * 1553 * Resets the Port, returning it to a power-on state. This configuration 1554 * command does not have a payload and should set/expect the lengths to 1555 * be zero. 1556 */ 1557typedef struct sli4_req_common_function_reset_s { 1558 sli4_req_hdr_t hdr; 1559} sli4_req_common_function_reset_t; 1560 1561typedef struct sli4_res_common_function_reset_s { 1562 sli4_res_hdr_t hdr; 1563} sli4_res_common_function_reset_t; 1564 1565/** 1566 * @brief COMMON_CREATE_CQ_V0 1567 * 1568 * Create a Completion Queue. 1569 */ 1570typedef struct sli4_req_common_create_cq_v0_s { 1571 sli4_req_hdr_t hdr; 1572#if BYTE_ORDER == LITTLE_ENDIAN 1573 uint32_t num_pages:16, 1574 :16; 1575 uint32_t :12, 1576 clswm:2, 1577 nodelay:1, 1578 :12, 1579 cqecnt:2, 1580 valid:1, 1581 :1, 1582 evt:1; 1583 uint32_t :22, 1584 eq_id:8, 1585 :1, 1586 arm:1; 1587 uint32_t rsvd[2]; 1588 struct { 1589 uint32_t low; 1590 uint32_t high; 1591 } page_physical_address[0]; 1592#else 1593#error big endian version not defined 1594#endif 1595} sli4_req_common_create_cq_v0_t; 1596 1597/** 1598 * @brief COMMON_CREATE_CQ_V2 1599 * 1600 * Create a Completion Queue. 1601 */ 1602typedef struct sli4_req_common_create_cq_v2_s { 1603 sli4_req_hdr_t hdr; 1604#if BYTE_ORDER == LITTLE_ENDIAN 1605 uint32_t num_pages:16, 1606 page_size:8, 1607 :8, 1608 uint32_t :12, 1609 clswm:2, 1610 nodelay:1, 1611 autovalid:1, 1612 :9, 1613 cqe_size:2, 1614 cqecnt:2, 1615 valid:1, 1616 :1, 1617 evt:1; 1618 uint32_t eq_id:16, 1619 :15, 1620 arm:1; 1621 uint32_t cqe_count:16, 1622 :16; 1623 uint32_t rsvd[1]; 1624 struct { 1625 uint32_t low; 1626 uint32_t high; 1627 } page_physical_address[0]; 1628#else 1629#error big endian version not defined 1630#endif 1631} sli4_req_common_create_cq_v2_t; 1632 1633/** 1634 * @brief COMMON_CREATE_CQ_SET_V0 1635 * 1636 * Create a set of Completion Queues. 1637 */ 1638typedef struct sli4_req_common_create_cq_set_v0_s { 1639 sli4_req_hdr_t hdr; 1640#if BYTE_ORDER == LITTLE_ENDIAN 1641 uint32_t num_pages:16, 1642 page_size:8, 1643 :8; 1644 uint32_t :12, 1645 clswm:2, 1646 nodelay:1, 1647 autovalid:1, 1648 rsvd:11, 1649 cqecnt:2, 1650 valid:1, 1651 :1, 1652 evt:1; 1653 uint32_t num_cq_req:16, 1654 cqe_count:15, 1655 arm:1; 1656 uint16_t eq_id[16]; 1657 struct { 1658 uint32_t low; 1659 uint32_t high; 1660 } page_physical_address[0]; 1661#else 1662#error big endian version not defined 1663#endif 1664} sli4_req_common_create_cq_set_v0_t; 1665 1666/** 1667 * CQE count. 1668 */ 1669#define SLI4_CQ_CNT_256 0 1670#define SLI4_CQ_CNT_512 1 1671#define SLI4_CQ_CNT_1024 2 1672#define SLI4_CQ_CNT_LARGE 3 1673 1674#define SLI4_CQE_BYTES (4 * sizeof(uint32_t)) 1675 1676#define SLI4_COMMON_CREATE_CQ_V2_MAX_PAGES 8 1677 1678/** 1679 * @brief Generic Common Create EQ/CQ/MQ/WQ/RQ Queue completion 1680 */ 1681typedef struct sli4_res_common_create_queue_s { 1682 sli4_res_hdr_t hdr; 1683#if BYTE_ORDER == LITTLE_ENDIAN 1684 uint32_t q_id:16, 1685 :8, 1686 ulp:8; 1687 uint32_t db_offset; 1688 uint32_t db_rs:16, 1689 db_fmt:16; 1690#else 1691#error big endian version not defined 1692#endif 1693} sli4_res_common_create_queue_t; 1694 1695typedef struct sli4_res_common_create_queue_set_s { 1696 sli4_res_hdr_t hdr; 1697#if BYTE_ORDER == LITTLE_ENDIAN 1698 uint32_t q_id:16, 1699 num_q_allocated:16; 1700#else 1701#error big endian version not defined 1702#endif 1703} sli4_res_common_create_queue_set_t; 1704 1705/** 1706 * @brief Common Destroy CQ 1707 */ 1708typedef struct sli4_req_common_destroy_cq_s { 1709 sli4_req_hdr_t hdr; 1710#if BYTE_ORDER == LITTLE_ENDIAN 1711 uint32_t cq_id:16, 1712 :16; 1713#else 1714#error big endian version not defined 1715#endif 1716} sli4_req_common_destroy_cq_t; 1717 1718/** 1719 * @brief COMMON_MODIFY_EQ_DELAY 1720 * 1721 * Modify the delay multiplier for EQs 1722 */ 1723typedef struct sli4_req_common_modify_eq_delay_s { 1724 sli4_req_hdr_t hdr; 1725#if BYTE_ORDER == LITTLE_ENDIAN 1726 uint32_t num_eq; 1727 struct { 1728 uint32_t eq_id; 1729 uint32_t phase; 1730 uint32_t delay_multiplier; 1731 } eq_delay_record[8]; 1732#else 1733#error big endian version not defined 1734#endif 1735} sli4_req_common_modify_eq_delay_t; 1736 1737/** 1738 * @brief COMMON_CREATE_EQ 1739 * 1740 * Create an Event Queue. 1741 */ 1742typedef struct sli4_req_common_create_eq_s { 1743 sli4_req_hdr_t hdr; 1744#if BYTE_ORDER == LITTLE_ENDIAN 1745 uint32_t num_pages:16, 1746 :16; 1747 uint32_t :28, 1748 autovalid:1, 1749 valid:1, 1750 :1, 1751 eqesz:1; 1752 uint32_t :26, 1753 count:3, 1754 :2, 1755 arm:1; 1756 uint32_t :13, 1757 delay_multiplier:10, 1758 :9; 1759 uint32_t rsvd; 1760 struct { 1761 uint32_t low; 1762 uint32_t high; 1763 } page_address[8]; 1764#else 1765#error big endian version not defined 1766#endif 1767} sli4_req_common_create_eq_t; 1768 1769#define SLI4_EQ_CNT_256 0 1770#define SLI4_EQ_CNT_512 1 1771#define SLI4_EQ_CNT_1024 2 1772#define SLI4_EQ_CNT_2048 3 1773#define SLI4_EQ_CNT_4096 4 1774 1775#define SLI4_EQE_SIZE_4 0 1776#define SLI4_EQE_SIZE_16 1 1777 1778/** 1779 * @brief Common Destroy EQ 1780 */ 1781typedef struct sli4_req_common_destroy_eq_s { 1782 sli4_req_hdr_t hdr; 1783#if BYTE_ORDER == LITTLE_ENDIAN 1784 uint32_t eq_id:16, 1785 :16; 1786#else 1787#error big endian version not defined 1788#endif 1789} sli4_req_common_destroy_eq_t; 1790 1791/** 1792 * @brief COMMON_CREATE_MQ_EXT 1793 * 1794 * Create a Mailbox Queue; accommodate v0 and v1 forms. 1795 */ 1796typedef struct sli4_req_common_create_mq_ext_s { 1797 sli4_req_hdr_t hdr; 1798#if BYTE_ORDER == LITTLE_ENDIAN 1799 uint32_t num_pages:16, 1800 cq_id_v1:16; 1801 uint32_t async_event_bitmap; 1802 uint32_t async_cq_id_v1:16, 1803 ring_size:4, 1804 :2, 1805 cq_id_v0:10; 1806 uint32_t :31, 1807 val:1; 1808 uint32_t acqv:1, 1809 async_cq_id_v0:10, 1810 :21; 1811 uint32_t rsvd9; 1812 struct { 1813 uint32_t low; 1814 uint32_t high; 1815 } page_physical_address[8]; 1816#else 1817#error big endian version not defined 1818#endif 1819} sli4_req_common_create_mq_ext_t; 1820 1821#define SLI4_MQE_SIZE_16 0x05 1822#define SLI4_MQE_SIZE_32 0x06 1823#define SLI4_MQE_SIZE_64 0x07 1824#define SLI4_MQE_SIZE_128 0x08 1825 1826#define SLI4_ASYNC_EVT_LINK_STATE BIT(1) 1827#define SLI4_ASYNC_EVT_FCOE_FIP BIT(2) 1828#define SLI4_ASYNC_EVT_DCBX BIT(3) 1829#define SLI4_ASYNC_EVT_ISCSI BIT(4) 1830#define SLI4_ASYNC_EVT_GRP5 BIT(5) 1831#define SLI4_ASYNC_EVT_FC BIT(16) 1832#define SLI4_ASYNC_EVT_SLI_PORT BIT(17) 1833#define SLI4_ASYNC_EVT_VF BIT(18) 1834#define SLI4_ASYNC_EVT_MR BIT(19) 1835 1836#define SLI4_ASYNC_EVT_ALL \ 1837 SLI4_ASYNC_EVT_LINK_STATE | \ 1838 SLI4_ASYNC_EVT_FCOE_FIP | \ 1839 SLI4_ASYNC_EVT_DCBX | \ 1840 SLI4_ASYNC_EVT_ISCSI | \ 1841 SLI4_ASYNC_EVT_GRP5 | \ 1842 SLI4_ASYNC_EVT_FC | \ 1843 SLI4_ASYNC_EVT_SLI_PORT | \ 1844 SLI4_ASYNC_EVT_VF |\ 1845 SLI4_ASYNC_EVT_MR 1846 1847#define SLI4_ASYNC_EVT_FC_FCOE \ 1848 SLI4_ASYNC_EVT_LINK_STATE | \ 1849 SLI4_ASYNC_EVT_FCOE_FIP | \ 1850 SLI4_ASYNC_EVT_GRP5 | \ 1851 SLI4_ASYNC_EVT_FC | \ 1852 SLI4_ASYNC_EVT_SLI_PORT 1853 1854/** 1855 * @brief Common Destroy MQ 1856 */ 1857typedef struct sli4_req_common_destroy_mq_s { 1858 sli4_req_hdr_t hdr; 1859#if BYTE_ORDER == LITTLE_ENDIAN 1860 uint32_t mq_id:16, 1861 :16; 1862#else 1863#error big endian version not defined 1864#endif 1865} sli4_req_common_destroy_mq_t; 1866 1867/** 1868 * @brief COMMON_GET_CNTL_ATTRIBUTES 1869 * 1870 * Query for information about the SLI Port 1871 */ 1872typedef struct sli4_res_common_get_cntl_attributes_s { 1873 sli4_res_hdr_t hdr; 1874#if BYTE_ORDER == LITTLE_ENDIAN 1875 uint8_t version_string[32]; 1876 uint8_t manufacturer_name[32]; 1877 uint32_t supported_modes; 1878 uint32_t eprom_version_lo:8, 1879 eprom_version_hi:8, 1880 :16; 1881 uint32_t mbx_data_structure_version; 1882 uint32_t ep_firmware_data_structure_version; 1883 uint8_t ncsi_version_string[12]; 1884 uint32_t default_extended_timeout; 1885 uint8_t model_number[32]; 1886 uint8_t description[64]; 1887 uint8_t serial_number[32]; 1888 uint8_t ip_version_string[32]; 1889 uint8_t fw_version_string[32]; 1890 uint8_t bios_version_string[32]; 1891 uint8_t redboot_version_string[32]; 1892 uint8_t driver_version_string[32]; 1893 uint8_t fw_on_flash_version_string[32]; 1894 uint32_t functionalities_supported; 1895 uint32_t max_cdb_length:16, 1896 asic_revision:8, 1897 generational_guid0:8; 1898 uint32_t generational_guid1_12[3]; 1899 uint32_t generational_guid13:24, 1900 hba_port_count:8; 1901 uint32_t default_link_down_timeout:16, 1902 iscsi_version_min_max:8, 1903 multifunctional_device:8; 1904 uint32_t cache_valid:8, 1905 hba_status:8, 1906 max_domains_supported:8, 1907 port_number:6, 1908 port_type:2; 1909 uint32_t firmware_post_status; 1910 uint32_t hba_mtu; 1911 uint32_t iscsi_features:8, 1912 rsvd121:24; 1913 uint32_t pci_vendor_id:16, 1914 pci_device_id:16; 1915 uint32_t pci_sub_vendor_id:16, 1916 pci_sub_system_id:16; 1917 uint32_t pci_bus_number:8, 1918 pci_device_number:8, 1919 pci_function_number:8, 1920 interface_type:8; 1921 uint64_t unique_identifier; 1922 uint32_t number_of_netfilters:8, 1923 rsvd130:24; 1924#else 1925#error big endian version not defined 1926#endif 1927} sli4_res_common_get_cntl_attributes_t; 1928 1929/** 1930 * @brief COMMON_GET_CNTL_ATTRIBUTES 1931 * 1932 * This command queries the controller information from the Flash ROM. 1933 */ 1934typedef struct sli4_req_common_get_cntl_addl_attributes_s { 1935 sli4_req_hdr_t hdr; 1936} sli4_req_common_get_cntl_addl_attributes_t; 1937 1938typedef struct sli4_res_common_get_cntl_addl_attributes_s { 1939 sli4_res_hdr_t hdr; 1940 uint16_t ipl_file_number; 1941 uint8_t ipl_file_version; 1942 uint8_t rsvd0; 1943 uint8_t on_die_temperature; 1944 uint8_t rsvd1[3]; 1945 uint32_t driver_advanced_features_supported; 1946 uint32_t rsvd2[4]; 1947 char fcoe_universal_bios_version[32]; 1948 char fcoe_x86_bios_version[32]; 1949 char fcoe_efi_bios_version[32]; 1950 char fcoe_fcode_version[32]; 1951 char uefi_bios_version[32]; 1952 char uefi_nic_version[32]; 1953 char uefi_fcode_version[32]; 1954 char uefi_iscsi_version[32]; 1955 char iscsi_x86_bios_version[32]; 1956 char pxe_x86_bios_version[32]; 1957 uint8_t fcoe_default_wwpn[8]; 1958 uint8_t ext_phy_version[32]; 1959 uint8_t fc_universal_bios_version[32]; 1960 uint8_t fc_x86_bios_version[32]; 1961 uint8_t fc_efi_bios_version[32]; 1962 uint8_t fc_fcode_version[32]; 1963 uint8_t ext_phy_crc_label[8]; 1964 uint8_t ipl_file_name[16]; 1965 uint8_t rsvd3[72]; 1966} sli4_res_common_get_cntl_addl_attributes_t; 1967 1968/** 1969 * @brief COMMON_NOP 1970 * 1971 * This command does not do anything; it only returns the payload in the completion. 1972 */ 1973typedef struct sli4_req_common_nop_s { 1974 sli4_req_hdr_t hdr; 1975#if BYTE_ORDER == LITTLE_ENDIAN 1976 uint32_t context[2]; 1977#else 1978#error big endian version not defined 1979#endif 1980} sli4_req_common_nop_t; 1981 1982typedef struct sli4_res_common_nop_s { 1983 sli4_res_hdr_t hdr; 1984#if BYTE_ORDER == LITTLE_ENDIAN 1985 uint32_t context[2]; 1986#else 1987#error big endian version not defined 1988#endif 1989} sli4_res_common_nop_t; 1990 1991/** 1992 * @brief COMMON_GET_RESOURCE_EXTENT_INFO 1993 */ 1994typedef struct sli4_req_common_get_resource_extent_info_s { 1995 sli4_req_hdr_t hdr; 1996#if BYTE_ORDER == LITTLE_ENDIAN 1997 uint32_t resource_type:16, 1998 :16; 1999#else 2000#error big endian version not defined 2001#endif 2002} sli4_req_common_get_resource_extent_info_t; 2003 2004#define SLI4_RSC_TYPE_ISCSI_INI_XRI 0x0c 2005#define SLI4_RSC_TYPE_FCOE_VFI 0x20 2006#define SLI4_RSC_TYPE_FCOE_VPI 0x21 2007#define SLI4_RSC_TYPE_FCOE_RPI 0x22 2008#define SLI4_RSC_TYPE_FCOE_XRI 0x23 2009 2010typedef struct sli4_res_common_get_resource_extent_info_s { 2011 sli4_res_hdr_t hdr; 2012#if BYTE_ORDER == LITTLE_ENDIAN 2013 uint32_t resource_extent_count:16, 2014 resource_extent_size:16; 2015#else 2016#error big endian version not defined 2017#endif 2018} sli4_res_common_get_resource_extent_info_t; 2019 2020#define SLI4_128BYTE_WQE_SUPPORT 0x02 2021/** 2022 * @brief COMMON_GET_SLI4_PARAMETERS 2023 */ 2024typedef struct sli4_res_common_get_sli4_parameters_s { 2025 sli4_res_hdr_t hdr; 2026#if BYTE_ORDER == LITTLE_ENDIAN 2027 uint32_t protocol_type:8, 2028 :24; 2029 uint32_t ft:1, 2030 :3, 2031 sli_revision:4, 2032 sli_family:4, 2033 if_type:4, 2034 sli_hint_1:8, 2035 sli_hint_2:5, 2036 :3; 2037 uint32_t eq_page_cnt:4, 2038 :4, 2039 eqe_sizes:4, 2040 :4, 2041 eq_page_sizes:8, 2042 eqe_count_method:4, 2043 :4; 2044 uint32_t eqe_count_mask:16, 2045 :16; 2046 uint32_t cq_page_cnt:4, 2047 :4, 2048 cqe_sizes:4, 2049 :2, 2050 cqv:2, 2051 cq_page_sizes:8, 2052 cqe_count_method:4, 2053 :4; 2054 uint32_t cqe_count_mask:16, 2055 :16; 2056 uint32_t mq_page_cnt:4, 2057 :10, 2058 mqv:2, 2059 mq_page_sizes:8, 2060 mqe_count_method:4, 2061 :4; 2062 uint32_t mqe_count_mask:16, 2063 :16; 2064 uint32_t wq_page_cnt:4, 2065 :4, 2066 wqe_sizes:4, 2067 :2, 2068 wqv:2, 2069 wq_page_sizes:8, 2070 wqe_count_method:4, 2071 :4; 2072 uint32_t wqe_count_mask:16, 2073 :16; 2074 uint32_t rq_page_cnt:4, 2075 :4, 2076 rqe_sizes:4, 2077 :2, 2078 rqv:2, 2079 rq_page_sizes:8, 2080 rqe_count_method:4, 2081 :4; 2082 uint32_t rqe_count_mask:16, 2083 :12, 2084 rq_db_window:4; 2085 uint32_t fcoe:1, 2086 ext:1, 2087 hdrr:1, 2088 sglr:1, 2089 fbrr:1, 2090 areg:1, 2091 tgt:1, 2092 terp:1, 2093 assi:1, 2094 wchn:1, 2095 tcca:1, 2096 trty:1, 2097 trir:1, 2098 phoff:1, 2099 phon:1, 2100 phwq:1, /** Performance Hint WQ_ID Association */ 2101 boundary_4ga:1, 2102 rxc:1, 2103 hlm:1, 2104 ipr:1, 2105 rxri:1, 2106 sglc:1, 2107 timm:1, 2108 tsmm:1, 2109 :1, 2110 oas:1, 2111 lc:1, 2112 agxf:1, 2113 loopback_scope:4; 2114 uint32_t sge_supported_length; 2115 uint32_t sgl_page_cnt:4, 2116 :4, 2117 sgl_page_sizes:8, 2118 sgl_pp_align:8, 2119 :8; 2120 uint32_t min_rq_buffer_size:16, 2121 :16; 2122 uint32_t max_rq_buffer_size; 2123 uint32_t physical_xri_max:16, 2124 physical_rpi_max:16; 2125 uint32_t physical_vpi_max:16, 2126 physical_vfi_max:16; 2127 uint32_t rsvd19; 2128 uint32_t frag_num_field_offset:16, /* dword 20 */ 2129 frag_num_field_size:16; 2130 uint32_t sgl_index_field_offset:16, /* dword 21 */ 2131 sgl_index_field_size:16; 2132 uint32_t chain_sge_initial_value_lo; /* dword 22 */ 2133 uint32_t chain_sge_initial_value_hi; /* dword 23 */ 2134#else 2135#error big endian version not defined 2136#endif 2137} sli4_res_common_get_sli4_parameters_t; 2138 2139/** 2140 * @brief COMMON_QUERY_FW_CONFIG 2141 * 2142 * This command retrieves firmware configuration parameters and adapter 2143 * resources available to the driver. 2144 */ 2145typedef struct sli4_req_common_query_fw_config_s { 2146 sli4_req_hdr_t hdr; 2147} sli4_req_common_query_fw_config_t; 2148 2149#define SLI4_FUNCTION_MODE_FCOE_INI_MODE 0x40 2150#define SLI4_FUNCTION_MODE_FCOE_TGT_MODE 0x80 2151#define SLI4_FUNCTION_MODE_DUA_MODE 0x800 2152 2153#define SLI4_ULP_MODE_FCOE_INI 0x40 2154#define SLI4_ULP_MODE_FCOE_TGT 0x80 2155 2156typedef struct sli4_res_common_query_fw_config_s { 2157 sli4_res_hdr_t hdr; 2158 uint32_t config_number; 2159 uint32_t asic_rev; 2160 uint32_t physical_port; 2161 uint32_t function_mode; 2162 uint32_t ulp0_mode; 2163 uint32_t ulp0_nic_wqid_base; 2164 uint32_t ulp0_nic_wq_total; /* Dword 10 */ 2165 uint32_t ulp0_toe_wqid_base; 2166 uint32_t ulp0_toe_wq_total; 2167 uint32_t ulp0_toe_rqid_base; 2168 uint32_t ulp0_toe_rq_total; 2169 uint32_t ulp0_toe_defrqid_base; 2170 uint32_t ulp0_toe_defrq_total; 2171 uint32_t ulp0_lro_rqid_base; 2172 uint32_t ulp0_lro_rq_total; 2173 uint32_t ulp0_iscsi_icd_base; 2174 uint32_t ulp0_iscsi_icd_total; /* Dword 20 */ 2175 uint32_t ulp1_mode; 2176 uint32_t ulp1_nic_wqid_base; 2177 uint32_t ulp1_nic_wq_total; 2178 uint32_t ulp1_toe_wqid_base; 2179 uint32_t ulp1_toe_wq_total; 2180 uint32_t ulp1_toe_rqid_base; 2181 uint32_t ulp1_toe_rq_total; 2182 uint32_t ulp1_toe_defrqid_base; 2183 uint32_t ulp1_toe_defrq_total; 2184 uint32_t ulp1_lro_rqid_base; /* Dword 30 */ 2185 uint32_t ulp1_lro_rq_total; 2186 uint32_t ulp1_iscsi_icd_base; 2187 uint32_t ulp1_iscsi_icd_total; 2188 uint32_t function_capabilities; 2189 uint32_t ulp0_cq_base; 2190 uint32_t ulp0_cq_total; 2191 uint32_t ulp0_eq_base; 2192 uint32_t ulp0_eq_total; 2193 uint32_t ulp0_iscsi_chain_icd_base; 2194 uint32_t ulp0_iscsi_chain_icd_total; /* Dword 40 */ 2195 uint32_t ulp1_iscsi_chain_icd_base; 2196 uint32_t ulp1_iscsi_chain_icd_total; 2197} sli4_res_common_query_fw_config_t; 2198 2199/** 2200 * @brief COMMON_GET_PORT_NAME 2201 */ 2202typedef struct sli4_req_common_get_port_name_s { 2203 sli4_req_hdr_t hdr; 2204#if BYTE_ORDER == LITTLE_ENDIAN 2205 uint32_t pt:2, /* only COMMON_GET_PORT_NAME_V1 */ 2206 :30; 2207#else 2208#error big endian version not defined 2209#endif 2210} sli4_req_common_get_port_name_t; 2211 2212typedef struct sli4_res_common_get_port_name_s { 2213 sli4_res_hdr_t hdr; 2214 char port_name[4]; 2215} sli4_res_common_get_port_name_t; 2216 2217/** 2218 * @brief COMMON_WRITE_FLASHROM 2219 */ 2220typedef struct sli4_req_common_write_flashrom_s { 2221 sli4_req_hdr_t hdr; 2222#if BYTE_ORDER == LITTLE_ENDIAN 2223 uint32_t flash_rom_access_opcode; 2224 uint32_t flash_rom_access_operation_type; 2225 uint32_t data_buffer_size; 2226 uint32_t offset; 2227 uint8_t data_buffer[4]; 2228#else 2229#error big endian version not defined 2230#endif 2231} sli4_req_common_write_flashrom_t; 2232 2233#define SLI4_MGMT_FLASHROM_OPCODE_FLASH 0x01 2234#define SLI4_MGMT_FLASHROM_OPCODE_SAVE 0x02 2235#define SLI4_MGMT_FLASHROM_OPCODE_CLEAR 0x03 2236#define SLI4_MGMT_FLASHROM_OPCODE_REPORT 0x04 2237#define SLI4_MGMT_FLASHROM_OPCODE_IMAGE_INFO 0x05 2238#define SLI4_MGMT_FLASHROM_OPCODE_IMAGE_CRC 0x06 2239#define SLI4_MGMT_FLASHROM_OPCODE_OFFSET_BASED_FLASH 0x07 2240#define SLI4_MGMT_FLASHROM_OPCODE_OFFSET_BASED_SAVE 0x08 2241#define SLI4_MGMT_PHY_FLASHROM_OPCODE_FLASH 0x09 2242#define SLI4_MGMT_PHY_FLASHROM_OPCODE_SAVE 0x0a 2243 2244#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ISCSI 0x00 2245#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_REDBOOT 0x01 2246#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_BIOS 0x02 2247#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_PXE_BIOS 0x03 2248#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_CODE_CONTROL 0x04 2249#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_IPSEC_CFG 0x05 2250#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_INIT_DATA 0x06 2251#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ROM_OFFSET 0x07 2252#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_BIOS 0x08 2253#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ISCSI_BAK 0x09 2254#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_ACT 0x0a 2255#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_BAK 0x0b 2256#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_CODE_CTRL_P 0x0c 2257#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_NCSI 0x0d 2258#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_NIC 0x0e 2259#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_DCBX 0x0f 2260#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_PXE_BIOS_CFG 0x10 2261#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ALL_CFG_DATA 0x11 2262 2263/** 2264 * @brief COMMON_MANAGE_FAT 2265 */ 2266typedef struct sli4_req_common_manage_fat_s { 2267 sli4_req_hdr_t hdr; 2268#if BYTE_ORDER == LITTLE_ENDIAN 2269 uint32_t fat_operation; 2270 uint32_t read_log_offset; 2271 uint32_t read_log_length; 2272 uint32_t data_buffer_size; 2273 uint32_t data_buffer; /* response only */ 2274#else 2275#error big endian version not defined 2276#endif 2277} sli4_req_common_manage_fat_t; 2278 2279/** 2280 * @brief COMMON_GET_EXT_FAT_CAPABILITIES 2281 */ 2282typedef struct sli4_req_common_get_ext_fat_capabilities_s { 2283 sli4_req_hdr_t hdr; 2284#if BYTE_ORDER == LITTLE_ENDIAN 2285 uint32_t parameter_type; 2286#else 2287#error big endian version not defined 2288#endif 2289} sli4_req_common_get_ext_fat_capabilities_t; 2290 2291/** 2292 * @brief COMMON_SET_EXT_FAT_CAPABILITIES 2293 */ 2294typedef struct sli4_req_common_set_ext_fat_capabilities_s { 2295 sli4_req_hdr_t hdr; 2296#if BYTE_ORDER == LITTLE_ENDIAN 2297 uint32_t maximum_log_entries; 2298 uint32_t log_entry_size; 2299 uint32_t logging_type:8, 2300 maximum_logging_functions:8, 2301 maximum_logging_ports:8, 2302 :8; 2303 uint32_t supported_modes; 2304 uint32_t number_modules; 2305 uint32_t debug_module[14]; 2306#else 2307#error big endian version not defined 2308#endif 2309} sli4_req_common_set_ext_fat_capabilities_t; 2310 2311/** 2312 * @brief COMMON_EXT_FAT_CONFIGURE_SNAPSHOT 2313 */ 2314typedef struct sli4_req_common_ext_fat_configure_snapshot_s { 2315 sli4_req_hdr_t hdr; 2316#if BYTE_ORDER == LITTLE_ENDIAN 2317 uint32_t total_log_entries; 2318#else 2319#error big endian version not defined 2320#endif 2321} sli4_req_common_ext_fat_configure_snapshot_t; 2322 2323/** 2324 * @brief COMMON_EXT_FAT_RETRIEVE_SNAPSHOT 2325 */ 2326typedef struct sli4_req_common_ext_fat_retrieve_snapshot_s { 2327 sli4_req_hdr_t hdr; 2328#if BYTE_ORDER == LITTLE_ENDIAN 2329 uint32_t snapshot_mode; 2330 uint32_t start_index; 2331 uint32_t number_log_entries; 2332#else 2333#error big endian version not defined 2334#endif 2335} sli4_req_common_ext_fat_retrieve_snapshot_t; 2336 2337typedef struct sli4_res_common_ext_fat_retrieve_snapshot_s { 2338 sli4_res_hdr_t hdr; 2339#if BYTE_ORDER == LITTLE_ENDIAN 2340 uint32_t number_log_entries; 2341 uint32_t version:8, 2342 physical_port:8, 2343 function_id:16; 2344 uint32_t trace_level; 2345 uint32_t module_mask[2]; 2346 uint32_t trace_table_index; 2347 uint32_t timestamp; 2348 uint8_t string_data[16]; 2349 uint32_t data[6]; 2350#else 2351#error big endian version not defined 2352#endif 2353} sli4_res_common_ext_fat_retrieve_snapshot_t; 2354 2355/** 2356 * @brief COMMON_EXT_FAT_READ_STRING_TABLE 2357 */ 2358typedef struct sli4_req_common_ext_fat_read_string_table_s { 2359 sli4_req_hdr_t hdr; 2360#if BYTE_ORDER == LITTLE_ENDIAN 2361 uint32_t byte_offset; 2362 uint32_t number_bytes; 2363#else 2364#error big endian version not defined 2365#endif 2366} sli4_req_common_ext_fat_read_string_table_t; 2367 2368typedef struct sli4_res_common_ext_fat_read_string_table_s { 2369 sli4_res_hdr_t hdr; 2370#if BYTE_ORDER == LITTLE_ENDIAN 2371 uint32_t number_returned_bytes; 2372 uint32_t number_remaining_bytes; 2373 uint32_t table_data0:8, 2374 :24; 2375 uint8_t table_data[0]; 2376#else 2377#error big endian version not defined 2378#endif 2379} sli4_res_common_ext_fat_read_string_table_t; 2380 2381/** 2382 * @brief COMMON_READ_TRANSCEIVER_DATA 2383 * 2384 * This command reads SFF transceiver data(Format is defined 2385 * by the SFF-8472 specification). 2386 */ 2387typedef struct sli4_req_common_read_transceiver_data_s { 2388 sli4_req_hdr_t hdr; 2389#if BYTE_ORDER == LITTLE_ENDIAN 2390 uint32_t page_number; 2391 uint32_t port; 2392#else 2393#error big endian version not defined 2394#endif 2395} sli4_req_common_read_transceiver_data_t; 2396 2397typedef struct sli4_res_common_read_transceiver_data_s { 2398 sli4_res_hdr_t hdr; 2399#if BYTE_ORDER == LITTLE_ENDIAN 2400 uint32_t page_number; 2401 uint32_t port; 2402 uint32_t page_data[32]; 2403 uint32_t page_data_2[32]; 2404#else 2405#error big endian version not defined 2406#endif 2407} sli4_res_common_read_transceiver_data_t; 2408 2409/** 2410 * @brief COMMON_READ_OBJECT 2411 */ 2412typedef struct sli4_req_common_read_object_s { 2413 sli4_req_hdr_t hdr; 2414#if BYTE_ORDER == LITTLE_ENDIAN 2415 uint32_t desired_read_length:24, 2416 :8; 2417 uint32_t read_offset; 2418 uint8_t object_name[104]; 2419 uint32_t host_buffer_descriptor_count; 2420 sli4_bde_t host_buffer_descriptor[0]; 2421#else 2422#error big endian version not defined 2423#endif 2424} sli4_req_common_read_object_t; 2425 2426typedef struct sli4_res_common_read_object_s { 2427 sli4_res_hdr_t hdr; 2428#if BYTE_ORDER == LITTLE_ENDIAN 2429 uint32_t actual_read_length; 2430 uint32_t resv:31, 2431 eof:1; 2432#else 2433#error big endian version not defined 2434#endif 2435} sli4_res_common_read_object_t; 2436 2437/** 2438 * @brief COMMON_WRITE_OBJECT 2439 */ 2440typedef struct sli4_req_common_write_object_s { 2441 sli4_req_hdr_t hdr; 2442#if BYTE_ORDER == LITTLE_ENDIAN 2443 uint32_t desired_write_length:24, 2444 :6, 2445 noc:1, 2446 eof:1; 2447 uint32_t write_offset; 2448 uint8_t object_name[104]; 2449 uint32_t host_buffer_descriptor_count; 2450 sli4_bde_t host_buffer_descriptor[0]; 2451#else 2452#error big endian version not defined 2453#endif 2454} sli4_req_common_write_object_t; 2455 2456typedef struct sli4_res_common_write_object_s { 2457 sli4_res_hdr_t hdr; 2458#if BYTE_ORDER == LITTLE_ENDIAN 2459 uint32_t actual_write_length; 2460 uint32_t change_status:8, 2461 :24; 2462#else 2463#error big endian version not defined 2464#endif 2465} sli4_res_common_write_object_t; 2466 2467/** 2468 * @brief COMMON_DELETE_OBJECT 2469 */ 2470typedef struct sli4_req_common_delete_object_s { 2471 sli4_req_hdr_t hdr; 2472#if BYTE_ORDER == LITTLE_ENDIAN 2473 uint32_t rsvd4; 2474 uint32_t rsvd5; 2475 uint8_t object_name[104]; 2476#else 2477#error big endian version not defined 2478#endif 2479} sli4_req_common_delete_object_t; 2480 2481/** 2482 * @brief COMMON_READ_OBJECT_LIST 2483 */ 2484typedef struct sli4_req_common_read_object_list_s { 2485 sli4_req_hdr_t hdr; 2486#if BYTE_ORDER == LITTLE_ENDIAN 2487 uint32_t desired_read_length:24, 2488 :8; 2489 uint32_t read_offset; 2490 uint8_t object_name[104]; 2491 uint32_t host_buffer_descriptor_count; 2492 sli4_bde_t host_buffer_descriptor[0]; 2493#else 2494#error big endian version not defined 2495#endif 2496} sli4_req_common_read_object_list_t; 2497 2498/** 2499 * @brief COMMON_SET_DUMP_LOCATION 2500 */ 2501typedef struct sli4_req_common_set_dump_location_s { 2502 sli4_req_hdr_t hdr; 2503#if BYTE_ORDER == LITTLE_ENDIAN 2504 uint32_t buffer_length:24, 2505 :5, 2506 fdb:1, 2507 blp:1, 2508 qry:1; 2509 uint32_t buf_addr_low; 2510 uint32_t buf_addr_high; 2511#else 2512#error big endian version not defined 2513#endif 2514} sli4_req_common_set_dump_location_t; 2515 2516typedef struct sli4_res_common_set_dump_location_s { 2517 sli4_res_hdr_t hdr; 2518#if BYTE_ORDER == LITTLE_ENDIAN 2519 uint32_t buffer_length:24, 2520 :8; 2521#else 2522#error big endian version not defined 2523#endif 2524}sli4_res_common_set_dump_location_t; 2525 2526/** 2527 * @brief COMMON_SET_SET_FEATURES 2528 */ 2529#define SLI4_SET_FEATURES_DIF_SEED 0x01 2530#define SLI4_SET_FEATURES_XRI_TIMER 0x03 2531#define SLI4_SET_FEATURES_MAX_PCIE_SPEED 0x04 2532#define SLI4_SET_FEATURES_FCTL_CHECK 0x05 2533#define SLI4_SET_FEATURES_FEC 0x06 2534#define SLI4_SET_FEATURES_PCIE_RECV_DETECT 0x07 2535#define SLI4_SET_FEATURES_DIF_MEMORY_MODE 0x08 2536#define SLI4_SET_FEATURES_DISABLE_SLI_PORT_PAUSE_STATE 0x09 2537#define SLI4_SET_FEATURES_ENABLE_PCIE_OPTIONS 0x0A 2538#define SLI4_SET_FEATURES_SET_CONFIG_AUTO_XFER_RDY_T10PI 0x0C 2539#define SLI4_SET_FEATURES_ENABLE_MULTI_RECEIVE_QUEUE 0x0D 2540#define SLI4_SET_FEATURES_SET_FTD_XFER_HINT 0x0F 2541#define SLI4_SET_FEATURES_SLI_PORT_HEALTH_CHECK 0x11 2542#define SLI4_SET_FEATURES_PERSISTENT_TOPOLOGY 0x20 2543 2544typedef struct sli4_req_common_set_features_s { 2545 sli4_req_hdr_t hdr; 2546#if BYTE_ORDER == LITTLE_ENDIAN 2547 uint32_t feature; 2548 uint32_t param_len; 2549 uint32_t params[8]; 2550#else 2551#error big endian version not defined 2552#endif 2553} sli4_req_common_set_features_t; 2554 2555typedef struct sli4_req_common_set_features_dif_seed_s { 2556#if BYTE_ORDER == LITTLE_ENDIAN 2557 uint32_t seed:16, 2558 :16; 2559#else 2560#error big endian version not defined 2561#endif 2562} sli4_req_common_set_features_dif_seed_t; 2563 2564typedef struct sli4_req_common_set_features_t10_pi_mem_model_s { 2565#if BYTE_ORDER == LITTLE_ENDIAN 2566 uint32_t tmm:1, 2567 :31; 2568#else 2569#error big endian version not defined 2570#endif 2571} sli4_req_common_set_features_t10_pi_mem_model_t; 2572 2573typedef struct sli4_req_common_set_features_multirq_s { 2574#if BYTE_ORDER == LITTLE_ENDIAN 2575 uint32_t isr:1, /*<< Include Sequence Reporting */ 2576 agxfe:1, /*<< Auto Generate XFER-RDY Feature Enabled */ 2577 :30; 2578 uint32_t num_rqs:8, 2579 rq_select_policy:4, 2580 :20; 2581#else 2582#error big endian version not defined 2583#endif 2584} sli4_req_common_set_features_multirq_t; 2585 2586typedef struct sli4_req_common_set_features_xfer_rdy_t10pi_s { 2587#if BYTE_ORDER == LITTLE_ENDIAN 2588 uint32_t rtc:1, 2589 atv:1, 2590 tmm:1, 2591 :1, 2592 p_type:3, 2593 blk_size:3, 2594 :22; 2595 uint32_t app_tag:16, 2596 :16; 2597#else 2598#error big endian version not defined 2599#endif 2600} sli4_req_common_set_features_xfer_rdy_t10pi_t; 2601 2602typedef struct sli4_req_common_set_features_health_check_s { 2603#if BYTE_ORDER == LITTLE_ENDIAN 2604 uint32_t hck:1, 2605 qry:1, 2606 :30; 2607#else 2608#error big endian version not defined 2609#endif 2610} sli4_req_common_set_features_health_check_t; 2611 2612typedef struct sli4_req_common_set_features_set_fdt_xfer_hint_s { 2613#if BYTE_ORDER == LITTLE_ENDIAN 2614 uint32_t fdt_xfer_hint; 2615#else 2616#error big endian version not defined 2617#endif 2618} sli4_req_common_set_features_set_fdt_xfer_hint_t; 2619 2620typedef struct sli4_req_common_set_features_persistent_topo_param_s { 2621#if BYTE_ORDER == LITTLE_ENDIAN 2622 uint32_t persistent_topo:2, 2623 topo_failover:1, 2624 :29; 2625#else 2626#error big endian version not defined 2627#endif 2628} sli4_req_common_set_features_persistent_topo_param_t; 2629 2630/** 2631 * @brief DMTF_EXEC_CLP_CMD 2632 */ 2633typedef struct sli4_req_dmtf_exec_clp_cmd_s { 2634 sli4_req_hdr_t hdr; 2635#if BYTE_ORDER == LITTLE_ENDIAN 2636 uint32_t cmd_buf_length; 2637 uint32_t resp_buf_length; 2638 uint32_t cmd_buf_addr_low; 2639 uint32_t cmd_buf_addr_high; 2640 uint32_t resp_buf_addr_low; 2641 uint32_t resp_buf_addr_high; 2642#else 2643#error big endian version not defined 2644#endif 2645} sli4_req_dmtf_exec_clp_cmd_t; 2646 2647typedef struct sli4_res_dmtf_exec_clp_cmd_s { 2648 sli4_res_hdr_t hdr; 2649#if BYTE_ORDER == LITTLE_ENDIAN 2650 uint32_t :32; 2651 uint32_t resp_length; 2652 uint32_t :32; 2653 uint32_t :32; 2654 uint32_t :32; 2655 uint32_t :32; 2656 uint32_t clp_status; 2657 uint32_t clp_detailed_status; 2658#else 2659#error big endian version not defined 2660#endif 2661} sli4_res_dmtf_exec_clp_cmd_t; 2662 2663/** 2664 * @brief Resource descriptor 2665 */ 2666 2667#define SLI4_RESOURCE_DESCRIPTOR_TYPE_PCIE 0x50 2668#define SLI4_RESOURCE_DESCRIPTOR_TYPE_NIC 0x51 2669#define SLI4_RESOURCE_DESCRIPTOR_TYPE_ISCSI 0x52 2670#define SLI4_RESOURCE_DESCRIPTOR_TYPE_FCFCOE 0x53 2671#define SLI4_RESOURCE_DESCRIPTOR_TYPE_RDMA 0x54 2672#define SLI4_RESOURCE_DESCRIPTOR_TYPE_PORT 0x55 2673#define SLI4_RESOURCE_DESCRIPTOR_TYPE_ISAP 0x56 2674 2675#define SLI4_PROTOCOL_NIC_TOE 0x01 2676#define SLI4_PROTOCOL_ISCSI 0x02 2677#define SLI4_PROTOCOL_FCOE 0x04 2678#define SLI4_PROTOCOL_NIC_TOE_RDMA 0x08 2679#define SLI4_PROTOCOL_FC 0x10 2680#define SLI4_PROTOCOL_DEFAULT 0xff 2681 2682typedef struct sli4_resource_descriptor_v1_s { 2683 uint32_t descriptor_type:8, 2684 descriptor_length:8, 2685 :16; 2686 uint32_t type_specific[0]; 2687} sli4_resource_descriptor_v1_t; 2688 2689typedef struct sli4_pcie_resource_descriptor_v1_s { 2690 uint32_t descriptor_type:8, 2691 descriptor_length:8, 2692 :14, 2693 imm:1, 2694 nosv:1; 2695 uint32_t :16, 2696 pf_number:10, 2697 :6; 2698 uint32_t rsvd1; 2699 uint32_t sriov_state:8, 2700 pf_state:8, 2701 pf_type:8, 2702 :8; 2703 uint32_t number_of_vfs:16, 2704 :16; 2705 uint32_t mission_roles:8, 2706 :19, 2707 pchg:1, 2708 schg:1, 2709 xchg:1, 2710 xrom:2; 2711 uint32_t rsvd2[16]; 2712} sli4_pcie_resource_descriptor_v1_t; 2713 2714typedef struct sli4_isap_resource_descriptor_v1_s { 2715 uint32_t descriptor_type:8, 2716 descriptor_length:8, 2717 :16; 2718 uint32_t iscsi_tgt:1, 2719 iscsi_ini:1, 2720 iscsi_dif:1, 2721 :29; 2722 uint32_t rsvd1[3]; 2723 uint32_t fcoe_tgt:1, 2724 fcoe_ini:1, 2725 fcoe_dif:1, 2726 :29; 2727 uint32_t rsvd2[7]; 2728 uint32_t mc_type0:8, 2729 mc_type1:8, 2730 mc_type2:8, 2731 mc_type3:8; 2732 uint32_t rsvd3[3]; 2733} sli4_isap_resouce_descriptor_v1_t; 2734 2735/** 2736 * @brief COMMON_GET_FUNCTION_CONFIG 2737 */ 2738typedef struct sli4_req_common_get_function_config_s { 2739 sli4_req_hdr_t hdr; 2740} sli4_req_common_get_function_config_t; 2741 2742typedef struct sli4_res_common_get_function_config_s { 2743 sli4_res_hdr_t hdr; 2744#if BYTE_ORDER == LITTLE_ENDIAN 2745 uint32_t desc_count; 2746 uint32_t desc[54]; 2747#else 2748#error big endian version not defined 2749#endif 2750} sli4_res_common_get_function_config_t; 2751 2752/** 2753 * @brief COMMON_GET_PROFILE_CONFIG 2754 */ 2755typedef struct sli4_req_common_get_profile_config_s { 2756 sli4_req_hdr_t hdr; 2757 uint32_t profile_id:8, 2758 typ:2, 2759 :22; 2760} sli4_req_common_get_profile_config_t; 2761 2762typedef struct sli4_res_common_get_profile_config_s { 2763 sli4_res_hdr_t hdr; 2764#if BYTE_ORDER == LITTLE_ENDIAN 2765 uint32_t desc_count; 2766 uint32_t desc[0]; 2767#else 2768#error big endian version not defined 2769#endif 2770} sli4_res_common_get_profile_config_t; 2771 2772/** 2773 * @brief COMMON_SET_PROFILE_CONFIG 2774 */ 2775typedef struct sli4_req_common_set_profile_config_s { 2776 sli4_req_hdr_t hdr; 2777 uint32_t profile_id:8, 2778 :23, 2779 isap:1; 2780 uint32_t desc_count; 2781 uint32_t desc[0]; 2782} sli4_req_common_set_profile_config_t; 2783 2784typedef struct sli4_res_common_set_profile_config_s { 2785 sli4_res_hdr_t hdr; 2786#if BYTE_ORDER == LITTLE_ENDIAN 2787#else 2788#error big endian version not defined 2789#endif 2790} sli4_res_common_set_profile_config_t; 2791 2792/** 2793 * @brief Profile Descriptor for profile functions 2794 */ 2795typedef struct sli4_profile_descriptor_s { 2796#if BYTE_ORDER == LITTLE_ENDIAN 2797 uint32_t profile_id:8, 2798 :8, 2799 profile_index:8, 2800 :8; 2801 uint32_t profile_description[128]; 2802#else 2803#error big endian version not defined 2804#endif 2805} sli4_profile_descriptor_t; 2806 2807/* We don't know in advance how many descriptors there are. We have 2808 to pick a number that we think will be big enough and ask for that 2809 many. */ 2810 2811#define MAX_PRODUCT_DESCRIPTORS 40 2812 2813/** 2814 * @brief COMMON_GET_PROFILE_LIST 2815 */ 2816typedef struct sli4_req_common_get_profile_list_s { 2817 sli4_req_hdr_t hdr; 2818#if BYTE_ORDER == LITTLE_ENDIAN 2819 uint32_t start_profile_index:8, 2820 :24; 2821#else 2822#error big endian version not defined 2823#endif 2824} sli4_req_common_get_profile_list_t; 2825 2826typedef struct sli4_res_common_get_profile_list_s { 2827 sli4_res_hdr_t hdr; 2828#if BYTE_ORDER == LITTLE_ENDIAN 2829 uint32_t profile_descriptor_count; 2830 sli4_profile_descriptor_t profile_descriptor[MAX_PRODUCT_DESCRIPTORS]; 2831#else 2832#error big endian version not defined 2833#endif 2834} sli4_res_common_get_profile_list_t; 2835 2836/** 2837 * @brief COMMON_GET_ACTIVE_PROFILE 2838 */ 2839typedef struct sli4_req_common_get_active_profile_s { 2840 sli4_req_hdr_t hdr; 2841} sli4_req_common_get_active_profile_t; 2842 2843typedef struct sli4_res_common_get_active_profile_s { 2844 sli4_res_hdr_t hdr; 2845#if BYTE_ORDER == LITTLE_ENDIAN 2846 uint32_t active_profile_id:8, 2847 :8, 2848 next_profile_id:8, 2849 :8; 2850#else 2851#error big endian version not defined 2852#endif 2853} sli4_res_common_get_active_profile_t; 2854 2855/** 2856 * @brief COMMON_SET_ACTIVE_PROFILE 2857 */ 2858typedef struct sli4_req_common_set_active_profile_s { 2859 sli4_req_hdr_t hdr; 2860#if BYTE_ORDER == LITTLE_ENDIAN 2861 uint32_t active_profile_id:8, 2862 :23, 2863 fd:1; 2864#else 2865#error big endian version not defined 2866#endif 2867} sli4_req_common_set_active_profile_t; 2868 2869typedef struct sli4_res_common_set_active_profile_s { 2870 sli4_res_hdr_t hdr; 2871} sli4_res_common_set_active_profile_t; 2872 2873/** 2874 * @brief Link Config Descriptor for link config functions 2875 */ 2876typedef struct sli4_link_config_descriptor_s { 2877#if BYTE_ORDER == LITTLE_ENDIAN 2878 uint32_t link_config_id:8, 2879 :24; 2880 uint32_t config_description[8]; 2881#else 2882#error big endian version not defined 2883#endif 2884} sli4_link_config_descriptor_t; 2885 2886#define MAX_LINK_CONFIG_DESCRIPTORS 10 2887 2888/** 2889 * @brief COMMON_GET_RECONFIG_LINK_INFO 2890 */ 2891typedef struct sli4_req_common_get_reconfig_link_info_s { 2892 sli4_req_hdr_t hdr; 2893#if BYTE_ORDER == LITTLE_ENDIAN 2894#else 2895#error big endian version not defined 2896#endif 2897} sli4_req_common_get_reconfig_link_info_t; 2898 2899typedef struct sli4_res_common_get_reconfig_link_info_s { 2900 sli4_res_hdr_t hdr; 2901#if BYTE_ORDER == LITTLE_ENDIAN 2902 uint32_t active_link_config_id:8, 2903 :8, 2904 next_link_config_id:8, 2905 :8; 2906 uint32_t link_configuration_descriptor_count; 2907 sli4_link_config_descriptor_t desc[MAX_LINK_CONFIG_DESCRIPTORS]; 2908#else 2909#error big endian version not defined 2910#endif 2911} sli4_res_common_get_reconfig_link_info_t; 2912 2913/** 2914 * @brief COMMON_SET_RECONFIG_LINK_ID 2915 */ 2916typedef struct sli4_req_common_set_reconfig_link_id_s { 2917 sli4_req_hdr_t hdr; 2918#if BYTE_ORDER == LITTLE_ENDIAN 2919 uint32_t next_link_config_id:8, 2920 :23, 2921 fd:1; 2922#else 2923#error big endian version not defined 2924#endif 2925} sli4_req_common_set_reconfig_link_id_t; 2926 2927typedef struct sli4_res_common_set_reconfig_link_id_s { 2928 sli4_res_hdr_t hdr; 2929#if BYTE_ORDER == LITTLE_ENDIAN 2930#else 2931#error big endian version not defined 2932#endif 2933} sli4_res_common_set_reconfig_link_id_t; 2934 2935typedef struct sli4_req_lowlevel_set_watchdog_s { 2936 sli4_req_hdr_t hdr; 2937#if BYTE_ORDER == LITTLE_ENDIAN 2938 uint32_t watchdog_timeout:16, 2939 :16; 2940#else 2941#error big endian version not defined 2942#endif 2943 2944} sli4_req_lowlevel_set_watchdog_t; 2945 2946typedef struct sli4_res_lowlevel_set_watchdog_s { 2947 sli4_res_hdr_t hdr; 2948#if BYTE_ORDER == LITTLE_ENDIAN 2949 uint32_t rsvd; 2950#else 2951#error big endian version not defined 2952#endif 2953} sli4_res_lowlevel_set_watchdog_t; 2954 2955/** 2956 * @brief Event Queue Entry 2957 */ 2958typedef struct sli4_eqe_s { 2959#if BYTE_ORDER == LITTLE_ENDIAN 2960 uint32_t vld:1, /** valid */ 2961 major_code:3, 2962 minor_code:12, 2963 resource_id:16; 2964#else 2965#error big endian version not defined 2966#endif 2967} sli4_eqe_t; 2968 2969#define SLI4_MAJOR_CODE_STANDARD 0 2970#define SLI4_MAJOR_CODE_SENTINEL 1 2971 2972/** 2973 * @brief Mailbox Completion Queue Entry 2974 * 2975 * A CQE generated on the completion of a MQE from a MQ. 2976 */ 2977typedef struct sli4_mcqe_s { 2978#if BYTE_ORDER == LITTLE_ENDIAN 2979 uint32_t completion_status:16, /** values are protocol specific */ 2980 extended_status:16; 2981 uint32_t mqe_tag_low; 2982 uint32_t mqe_tag_high; 2983 uint32_t :27, 2984 con:1, /** consumed - command now being executed */ 2985 cmp:1, /** completed - command still executing if clear */ 2986 :1, 2987 ae:1, /** async event - this is an ACQE */ 2988 val:1; /** valid - contents of CQE are valid */ 2989#else 2990#error big endian version not defined 2991#endif 2992} sli4_mcqe_t; 2993 2994/** 2995 * @brief Asynchronous Completion Queue Entry 2996 * 2997 * A CQE generated asynchronously in response to the link or other internal events. 2998 */ 2999typedef struct sli4_acqe_s { 3000#if BYTE_ORDER == LITTLE_ENDIAN 3001 uint32_t event_data[3]; 3002 uint32_t :8, 3003 event_code:8, 3004 event_type:8, /** values are protocol specific */ 3005 :6, 3006 ae:1, /** async event - this is an ACQE */ 3007 val:1; /** valid - contents of CQE are valid */ 3008#else 3009#error big endian version not defined 3010#endif 3011} sli4_acqe_t; 3012 3013#define SLI4_ACQE_EVENT_CODE_LINK_STATE 0x01 3014#define SLI4_ACQE_EVENT_CODE_FCOE_FIP 0x02 3015#define SLI4_ACQE_EVENT_CODE_DCBX 0x03 3016#define SLI4_ACQE_EVENT_CODE_ISCSI 0x04 3017#define SLI4_ACQE_EVENT_CODE_GRP_5 0x05 3018#define SLI4_ACQE_EVENT_CODE_FC_LINK_EVENT 0x10 3019#define SLI4_ACQE_EVENT_CODE_SLI_PORT_EVENT 0x11 3020#define SLI4_ACQE_EVENT_CODE_VF_EVENT 0x12 3021#define SLI4_ACQE_EVENT_CODE_MR_EVENT 0x13 3022 3023/** 3024 * @brief Register name enums 3025 */ 3026typedef enum { 3027 SLI4_REG_BMBX, 3028 SLI4_REG_EQ_DOORBELL, 3029 SLI4_REG_CQ_DOORBELL, 3030 SLI4_REG_FCOE_RQ_DOORBELL, 3031 SLI4_REG_IO_WQ_DOORBELL, 3032 SLI4_REG_MQ_DOORBELL, 3033 SLI4_REG_PHYSDEV_CONTROL, 3034 SLI4_REG_SLIPORT_CONTROL, 3035 SLI4_REG_SLIPORT_ERROR1, 3036 SLI4_REG_SLIPORT_ERROR2, 3037 SLI4_REG_SLIPORT_SEMAPHORE, 3038 SLI4_REG_SLIPORT_STATUS, 3039 SLI4_REG_UERR_MASK_HI, 3040 SLI4_REG_UERR_MASK_LO, 3041 SLI4_REG_UERR_STATUS_HI, 3042 SLI4_REG_UERR_STATUS_LO, 3043 SLI4_REG_SW_UE_CSR1, 3044 SLI4_REG_SW_UE_CSR2, 3045 SLI4_REG_MAX /* must be last */ 3046} sli4_regname_e; 3047 3048typedef struct sli4_reg_s { 3049 uint32_t rset; 3050 uint32_t off; 3051} sli4_reg_t; 3052 3053typedef enum { 3054 SLI_QTYPE_EQ, 3055 SLI_QTYPE_CQ, 3056 SLI_QTYPE_MQ, 3057 SLI_QTYPE_WQ, 3058 SLI_QTYPE_RQ, 3059 SLI_QTYPE_MAX, /* must be last */ 3060} sli4_qtype_e; 3061 3062#define SLI_USER_MQ_COUNT 1 /** User specified max mail queues */ 3063#define SLI_MAX_CQ_SET_COUNT 16 3064#define SLI_MAX_RQ_SET_COUNT 16 3065 3066typedef enum { 3067 SLI_QENTRY_ASYNC, 3068 SLI_QENTRY_MQ, 3069 SLI_QENTRY_RQ, 3070 SLI_QENTRY_WQ, 3071 SLI_QENTRY_WQ_RELEASE, 3072 SLI_QENTRY_OPT_WRITE_CMD, 3073 SLI_QENTRY_OPT_WRITE_DATA, 3074 SLI_QENTRY_XABT, 3075 SLI_QENTRY_MAX /* must be last */ 3076} sli4_qentry_e; 3077 3078typedef struct sli4_queue_s { 3079 /* Common to all queue types */ 3080 ocs_dma_t dma; 3081 ocs_lock_t lock; 3082 uint32_t index; /** current host entry index */ 3083 uint16_t size; /** entry size */ 3084 uint16_t length; /** number of entries */ 3085 uint16_t n_posted; /** number entries posted */ 3086 uint16_t id; /** Port assigned xQ_ID */ 3087 uint16_t ulp; /** ULP assigned to this queue */ 3088 uint32_t doorbell_offset;/** The offset for the doorbell */ 3089 uint16_t doorbell_rset; /** register set for the doorbell */ 3090 uint8_t type; /** queue type ie EQ, CQ, ... */ 3091 uint32_t proc_limit; /** limit number of CQE processed per iteration */ 3092 uint32_t posted_limit; /** number of CQE/EQE to process before ringing doorbell */ 3093 uint32_t max_num_processed; 3094 time_t max_process_time; 3095 3096 uint16_t phase; /** For if_type = 6, this value toggle for each iteration 3097 of the queue, a queue entry is valid when a cqe valid 3098 bit matches this value */ 3099 /* Type specific gunk */ 3100 union { 3101 uint32_t r_idx; /** "read" index (MQ only) */ 3102 struct { 3103 uint32_t is_mq:1,/** CQ contains MQ/Async completions */ 3104 is_hdr:1,/** is a RQ for packet headers */ 3105 rq_batch:1;/** RQ index incremented by 8 */ 3106 } flag; 3107 } u; 3108} sli4_queue_t; 3109 3110static inline void 3111sli_queue_lock(sli4_queue_t *q) 3112{ 3113 ocs_lock(&q->lock); 3114} 3115 3116static inline void 3117sli_queue_unlock(sli4_queue_t *q) 3118{ 3119 ocs_unlock(&q->lock); 3120} 3121 3122#define SLI4_QUEUE_DEFAULT_CQ UINT16_MAX /** Use the default CQ */ 3123 3124#define SLI4_QUEUE_RQ_BATCH 8 3125 3126typedef enum { 3127 SLI4_CB_LINK, 3128 SLI4_CB_FIP, 3129 SLI4_CB_MAX /* must be last */ 3130} sli4_callback_e; 3131 3132typedef enum { 3133 SLI_LINK_STATUS_UP, 3134 SLI_LINK_STATUS_DOWN, 3135 SLI_LINK_STATUS_NO_ALPA, 3136 SLI_LINK_STATUS_MAX, 3137} sli4_link_status_e; 3138 3139typedef enum { 3140 SLI_LINK_TOPO_NPORT = 1, /** fabric or point-to-point */ 3141 SLI_LINK_TOPO_LOOP, 3142 SLI_LINK_TOPO_LOOPBACK_INTERNAL, 3143 SLI_LINK_TOPO_LOOPBACK_EXTERNAL, 3144 SLI_LINK_TOPO_NONE, 3145 SLI_LINK_TOPO_MAX, 3146} sli4_link_topology_e; 3147 3148/* TODO do we need both sli4_port_type_e & sli4_link_medium_e */ 3149typedef enum { 3150 SLI_LINK_MEDIUM_ETHERNET, 3151 SLI_LINK_MEDIUM_FC, 3152 SLI_LINK_MEDIUM_MAX, 3153} sli4_link_medium_e; 3154 3155typedef struct sli4_link_event_s { 3156 sli4_link_status_e status; /* link up/down */ 3157 sli4_link_topology_e topology; 3158 sli4_link_medium_e medium; /* Ethernet / FC */ 3159 uint32_t speed; /* Mbps */ 3160 uint8_t *loop_map; 3161 uint32_t fc_id; 3162} sli4_link_event_t; 3163 3164/** 3165 * @brief Fields retrieved from skyhawk that used used to build chained SGL 3166 */ 3167typedef struct sli4_sgl_chaining_params_s { 3168 uint8_t chaining_capable; 3169 uint16_t frag_num_field_offset; 3170 uint16_t sgl_index_field_offset; 3171 uint64_t frag_num_field_mask; 3172 uint64_t sgl_index_field_mask; 3173 uint32_t chain_sge_initial_value_lo; 3174 uint32_t chain_sge_initial_value_hi; 3175} sli4_sgl_chaining_params_t; 3176 3177typedef struct sli4_fip_event_s { 3178 uint32_t type; 3179 uint32_t index; /* FCF index or UINT32_MAX if invalid */ 3180} sli4_fip_event_t; 3181 3182typedef enum { 3183 SLI_RSRC_FCOE_VFI, 3184 SLI_RSRC_FCOE_VPI, 3185 SLI_RSRC_FCOE_RPI, 3186 SLI_RSRC_FCOE_XRI, 3187 SLI_RSRC_FCOE_FCFI, 3188 SLI_RSRC_MAX /* must be last */ 3189} sli4_resource_e; 3190 3191typedef enum { 3192 SLI4_PORT_TYPE_FC, 3193 SLI4_PORT_TYPE_NIC, 3194 SLI4_PORT_TYPE_MAX /* must be last */ 3195} sli4_port_type_e; 3196 3197typedef enum { 3198 SLI4_ASIC_TYPE_BE3 = 1, 3199 SLI4_ASIC_TYPE_SKYHAWK, 3200 SLI4_ASIC_TYPE_LANCER, 3201 SLI4_ASIC_TYPE_CORSAIR, 3202 SLI4_ASIC_TYPE_LANCERG6, 3203 SLI4_ASIC_TYPE_LANCERG7 3204} sli4_asic_type_e; 3205 3206typedef enum { 3207 SLI4_ASIC_REV_FPGA = 1, 3208 SLI4_ASIC_REV_A0, 3209 SLI4_ASIC_REV_A1, 3210 SLI4_ASIC_REV_A2, 3211 SLI4_ASIC_REV_A3, 3212 SLI4_ASIC_REV_B0, 3213 SLI4_ASIC_REV_B1, 3214 SLI4_ASIC_REV_C0, 3215 SLI4_ASIC_REV_D0, 3216} sli4_asic_rev_e; 3217 3218typedef struct sli4_s { 3219 ocs_os_handle_t os; 3220 sli4_port_type_e port_type; 3221 3222 uint32_t sli_rev; /* SLI revision number */ 3223 uint32_t sli_family; 3224 uint32_t if_type; /* SLI Interface type */ 3225 3226 sli4_asic_type_e asic_type; /*<< ASIC type */ 3227 sli4_asic_rev_e asic_rev; /*<< ASIC revision */ 3228 uint32_t physical_port; 3229 3230 struct { 3231 uint16_t e_d_tov; 3232 uint16_t r_a_tov; 3233 uint16_t max_qcount[SLI_QTYPE_MAX]; 3234 uint32_t max_qentries[SLI_QTYPE_MAX]; 3235 uint16_t count_mask[SLI_QTYPE_MAX]; 3236 uint16_t count_method[SLI_QTYPE_MAX]; 3237 uint32_t qpage_count[SLI_QTYPE_MAX]; 3238 uint16_t link_module_type; 3239 uint8_t rq_batch; 3240 uint16_t rq_min_buf_size; 3241 uint32_t rq_max_buf_size; 3242 uint8_t topology; 3243 uint8_t pt:4, 3244 tf:1, 3245 ptv:1, 3246 :2; 3247 uint8_t wwpn[8]; 3248 uint8_t wwnn[8]; 3249 uint32_t fw_rev[2]; 3250 uint8_t fw_name[2][16]; 3251 char ipl_name[16]; 3252 uint32_t hw_rev[3]; 3253 uint8_t port_number; 3254 char port_name[2]; 3255 char bios_version_string[32]; 3256 uint8_t dual_ulp_capable; 3257 uint8_t is_ulp_fc[2]; 3258 /* 3259 * Tracks the port resources using extents metaphor. For 3260 * devices that don't implement extents (i.e. 3261 * has_extents == FALSE), the code models each resource as 3262 * a single large extent. 3263 */ 3264 struct { 3265 uint32_t number; /* number of extents */ 3266 uint32_t size; /* number of elements in each extent */ 3267 uint32_t n_alloc;/* number of elements allocated */ 3268 uint32_t *base; 3269 ocs_bitmap_t *use_map;/* bitmap showing resources in use */ 3270 uint32_t map_size;/* number of bits in bitmap */ 3271 } extent[SLI_RSRC_MAX]; 3272 sli4_features_t features; 3273 uint32_t has_extents:1, 3274 auto_reg:1, 3275 auto_xfer_rdy:1, 3276 hdr_template_req:1, 3277 perf_hint:1, 3278 perf_wq_id_association:1, 3279 cq_create_version:2, 3280 mq_create_version:2, 3281 high_login_mode:1, 3282 sgl_pre_registered:1, 3283 sgl_pre_registration_required:1, 3284 t10_dif_inline_capable:1, 3285 t10_dif_separate_capable:1; 3286 uint32_t sge_supported_length; 3287 uint32_t sgl_page_sizes; 3288 uint32_t max_sgl_pages; 3289 sli4_sgl_chaining_params_t sgl_chaining_params; 3290 size_t wqe_size; 3291 } config; 3292 3293 /* 3294 * Callback functions 3295 */ 3296 int32_t (*link)(void *, void *); 3297 void *link_arg; 3298 int32_t (*fip)(void *, void *); 3299 void *fip_arg; 3300 3301 ocs_dma_t bmbx; 3302#if defined(OCS_INCLUDE_DEBUG) 3303 /* Save pointer to physical memory descriptor for non-embedded SLI_CONFIG 3304 * commands for BMBX dumping purposes */ 3305 ocs_dma_t *bmbx_non_emb_pmd; 3306#endif 3307 3308 struct { 3309 ocs_dma_t data; 3310 uint32_t length; 3311 } vpd; 3312} sli4_t; 3313 3314/** 3315 * Get / set parameter functions 3316 */ 3317static inline uint32_t 3318sli_get_max_rsrc(sli4_t *sli4, sli4_resource_e rsrc) 3319{ 3320 if (rsrc >= SLI_RSRC_MAX) { 3321 return 0; 3322 } 3323 3324 return sli4->config.extent[rsrc].size; 3325} 3326 3327static inline uint32_t 3328sli_get_max_queue(sli4_t *sli4, sli4_qtype_e qtype) 3329{ 3330 if (qtype >= SLI_QTYPE_MAX) { 3331 return 0; 3332 } 3333 return sli4->config.max_qcount[qtype]; 3334} 3335 3336static inline uint32_t 3337sli_get_max_qentries(sli4_t *sli4, sli4_qtype_e qtype) 3338{ 3339 3340 return sli4->config.max_qentries[qtype]; 3341} 3342 3343static inline uint32_t 3344sli_get_max_sge(sli4_t *sli4) 3345{ 3346 return sli4->config.sge_supported_length; 3347} 3348 3349static inline uint32_t 3350sli_get_max_sgl(sli4_t *sli4) 3351{ 3352 3353 if (sli4->config.sgl_page_sizes != 1) { 3354 ocs_log_test(sli4->os, "unsupported SGL page sizes %#x\n", 3355 sli4->config.sgl_page_sizes); 3356 return 0; 3357 } 3358 3359 return ((sli4->config.max_sgl_pages * SLI_PAGE_SIZE) / sizeof(sli4_sge_t)); 3360} 3361 3362static inline sli4_link_medium_e 3363sli_get_medium(sli4_t *sli4) 3364{ 3365 switch (sli4->config.topology) { 3366 case SLI4_READ_CFG_TOPO_FCOE: 3367 return SLI_LINK_MEDIUM_ETHERNET; 3368 case SLI4_READ_CFG_TOPO_FC: 3369 case SLI4_READ_CFG_TOPO_FC_DA: 3370 case SLI4_READ_CFG_TOPO_FC_AL: 3371 return SLI_LINK_MEDIUM_FC; 3372 default: 3373 return SLI_LINK_MEDIUM_MAX; 3374 } 3375} 3376 3377static inline void 3378sli_skh_chain_sge_build(sli4_t *sli4, sli4_sge_t *sge, uint32_t xri_index, uint32_t frag_num, uint32_t offset) 3379{ 3380 sli4_sgl_chaining_params_t *cparms = &sli4->config.sgl_chaining_params; 3381 3382 ocs_memset(sge, 0, sizeof(*sge)); 3383 sge->sge_type = SLI4_SGE_TYPE_CHAIN; 3384 sge->buffer_address_high = (uint32_t)cparms->chain_sge_initial_value_hi; 3385 sge->buffer_address_low = 3386 (uint32_t)((cparms->chain_sge_initial_value_lo | 3387 (((uintptr_t)(xri_index & cparms->sgl_index_field_mask)) << 3388 cparms->sgl_index_field_offset) | 3389 (((uintptr_t)(frag_num & cparms->frag_num_field_mask)) << 3390 cparms->frag_num_field_offset) | 3391 offset) >> 3); 3392} 3393 3394static inline uint32_t 3395sli_get_sli_rev(sli4_t *sli4) 3396{ 3397 return sli4->sli_rev; 3398} 3399 3400static inline uint32_t 3401sli_get_sli_family(sli4_t *sli4) 3402{ 3403 return sli4->sli_family; 3404} 3405 3406static inline uint32_t 3407sli_get_if_type(sli4_t *sli4) 3408{ 3409 return sli4->if_type; 3410} 3411 3412static inline void * 3413sli_get_wwn_port(sli4_t *sli4) 3414{ 3415 return sli4->config.wwpn; 3416} 3417 3418static inline void * 3419sli_get_wwn_node(sli4_t *sli4) 3420{ 3421 return sli4->config.wwnn; 3422} 3423 3424static inline void * 3425sli_get_vpd(sli4_t *sli4) 3426{ 3427 return sli4->vpd.data.virt; 3428} 3429 3430static inline uint32_t 3431sli_get_vpd_len(sli4_t *sli4) 3432{ 3433 return sli4->vpd.length; 3434} 3435 3436static inline uint32_t 3437sli_get_fw_revision(sli4_t *sli4, uint32_t which) 3438{ 3439 return sli4->config.fw_rev[which]; 3440} 3441 3442static inline void * 3443sli_get_fw_name(sli4_t *sli4, uint32_t which) 3444{ 3445 return sli4->config.fw_name[which]; 3446} 3447 3448static inline char * 3449sli_get_ipl_name(sli4_t *sli4) 3450{ 3451 return sli4->config.ipl_name; 3452} 3453 3454static inline uint32_t 3455sli_get_hw_revision(sli4_t *sli4, uint32_t which) 3456{ 3457 return sli4->config.hw_rev[which]; 3458} 3459 3460static inline uint32_t 3461sli_get_auto_xfer_rdy_capable(sli4_t *sli4) 3462{ 3463 return sli4->config.auto_xfer_rdy; 3464} 3465 3466static inline uint32_t 3467sli_get_dif_capable(sli4_t *sli4) 3468{ 3469 return sli4->config.features.flag.dif; 3470} 3471 3472static inline uint32_t 3473sli_is_dif_inline_capable(sli4_t *sli4) 3474{ 3475 return sli_get_dif_capable(sli4) && sli4->config.t10_dif_inline_capable; 3476} 3477 3478static inline uint32_t 3479sli_is_dif_separate_capable(sli4_t *sli4) 3480{ 3481 return sli_get_dif_capable(sli4) && sli4->config.t10_dif_separate_capable; 3482} 3483 3484static inline uint32_t 3485sli_get_is_dual_ulp_capable(sli4_t *sli4) 3486{ 3487 return sli4->config.dual_ulp_capable; 3488} 3489 3490static inline uint32_t 3491sli_get_is_sgl_chaining_capable(sli4_t *sli4) 3492{ 3493 return sli4->config.sgl_chaining_params.chaining_capable; 3494} 3495 3496static inline uint32_t 3497sli_get_is_ulp_enabled(sli4_t *sli4, uint16_t ulp) 3498{ 3499 return sli4->config.is_ulp_fc[ulp]; 3500} 3501 3502static inline uint32_t 3503sli_get_hlm_capable(sli4_t *sli4) 3504{ 3505 return sli4->config.features.flag.hlm; 3506} 3507 3508static inline int32_t 3509sli_set_hlm(sli4_t *sli4, uint32_t value) 3510{ 3511 if (value && !sli4->config.features.flag.hlm) { 3512 ocs_log_test(sli4->os, "HLM not supported\n"); 3513 return -1; 3514 } 3515 3516 sli4->config.high_login_mode = value != 0 ? TRUE : FALSE; 3517 3518 return 0; 3519} 3520 3521static inline uint32_t 3522sli_get_hlm(sli4_t *sli4) 3523{ 3524 return sli4->config.high_login_mode; 3525} 3526 3527static inline uint32_t 3528sli_get_sgl_preregister_required(sli4_t *sli4) 3529{ 3530 return sli4->config.sgl_pre_registration_required; 3531} 3532 3533static inline uint32_t 3534sli_get_sgl_preregister(sli4_t *sli4) 3535{ 3536 return sli4->config.sgl_pre_registered; 3537} 3538 3539static inline int32_t 3540sli_set_sgl_preregister(sli4_t *sli4, uint32_t value) 3541{ 3542 if ((value == 0) && sli4->config.sgl_pre_registration_required) { 3543 ocs_log_test(sli4->os, "SGL pre-registration required\n"); 3544 return -1; 3545 } 3546 3547 sli4->config.sgl_pre_registered = value != 0 ? TRUE : FALSE; 3548 3549 return 0; 3550} 3551 3552static inline sli4_asic_type_e 3553sli_get_asic_type(sli4_t *sli4) 3554{ 3555 return sli4->asic_type; 3556} 3557 3558static inline sli4_asic_rev_e 3559sli_get_asic_rev(sli4_t *sli4) 3560{ 3561 return sli4->asic_rev; 3562} 3563 3564static inline int32_t 3565sli_set_topology(sli4_t *sli4, uint32_t value) 3566{ 3567 int32_t rc = 0; 3568 3569 switch (value) { 3570 case SLI4_READ_CFG_TOPO_FCOE: 3571 case SLI4_READ_CFG_TOPO_FC: 3572 case SLI4_READ_CFG_TOPO_FC_DA: 3573 case SLI4_READ_CFG_TOPO_FC_AL: 3574 sli4->config.topology = value; 3575 break; 3576 default: 3577 ocs_log_test(sli4->os, "unsupported topology %#x\n", value); 3578 rc = -1; 3579 } 3580 3581 return rc; 3582} 3583 3584static inline void 3585sli_config_persistent_topology(sli4_t *sli4, sli4_req_common_set_features_persistent_topo_param_t *req) 3586{ 3587 sli4->config.pt = req->persistent_topo; 3588 sli4->config.tf = req->topo_failover; 3589} 3590 3591static inline uint16_t 3592sli_get_link_module_type(sli4_t *sli4) 3593{ 3594 return sli4->config.link_module_type; 3595} 3596 3597static inline char * 3598sli_get_portnum(sli4_t *sli4) 3599{ 3600 return sli4->config.port_name; 3601} 3602 3603static inline char * 3604sli_get_bios_version_string(sli4_t *sli4) 3605{ 3606 return sli4->config.bios_version_string; 3607} 3608 3609static inline uint32_t 3610sli_convert_mask_to_count(uint32_t method, uint32_t mask) 3611{ 3612 uint32_t count = 0; 3613 3614 if (method) { 3615 count = 1 << ocs_lg2(mask); 3616 count *= 16; 3617 } else { 3618 count = mask; 3619 } 3620 3621 return count; 3622} 3623 3624static inline bool 3625sli_fcal_is_speed_supported(uint32_t link_speed) 3626{ 3627 if ((link_speed == FC_LINK_SPEED_16G) || 3628 (link_speed == FC_LINK_SPEED_32G) || 3629 (link_speed >= FC_LINK_SPEED_AUTO_32_16)) { 3630 ocs_log_err(NULL, "unsupported FC-AL speed (speed_code: %d)\n", link_speed); 3631 return FALSE; 3632 } 3633 3634 return TRUE; 3635} 3636 3637/** 3638 * @brief Common Create Queue function prototype 3639 */ 3640typedef int32_t (*sli4_create_q_fn_t)(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t); 3641 3642/** 3643 * @brief Common Destroy Queue function prototype 3644 */ 3645typedef int32_t (*sli4_destroy_q_fn_t)(sli4_t *, void *, size_t, uint16_t); 3646 3647/**************************************************************************** 3648 * Function prototypes 3649 */ 3650extern int32_t sli_cmd_config_auto_xfer_rdy(sli4_t *, void *, size_t, uint32_t); 3651extern int32_t sli_cmd_config_auto_xfer_rdy_hp(sli4_t *, void *, size_t, uint32_t, uint32_t, uint32_t); 3652extern int32_t sli_cmd_config_link(sli4_t *, void *, size_t); 3653extern int32_t sli_cmd_down_link(sli4_t *, void *, size_t); 3654extern int32_t sli_cmd_dump_type4(sli4_t *, void *, size_t, uint16_t); 3655extern int32_t sli_cmd_common_read_transceiver_data(sli4_t *, void *, size_t, uint32_t, ocs_dma_t *); 3656extern int32_t sli_cmd_read_link_stats(sli4_t *, void *, size_t,uint8_t, uint8_t, uint8_t); 3657extern int32_t sli_cmd_read_status(sli4_t *sli4, void *buf, size_t size, uint8_t clear_counters); 3658extern int32_t sli_cmd_init_link(sli4_t *, void *, size_t, uint32_t, uint8_t); 3659extern int32_t sli_cmd_init_vfi(sli4_t *, void *, size_t, uint16_t, uint16_t, uint16_t); 3660extern int32_t sli_cmd_init_vpi(sli4_t *, void *, size_t, uint16_t, uint16_t); 3661extern int32_t sli_cmd_post_xri(sli4_t *, void *, size_t, uint16_t, uint16_t); 3662extern int32_t sli_cmd_release_xri(sli4_t *, void *, size_t, uint8_t); 3663extern int32_t sli_cmd_read_sparm64(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t); 3664extern int32_t sli_cmd_read_topology(sli4_t *, void *, size_t, ocs_dma_t *); 3665extern int32_t sli_cmd_read_nvparms(sli4_t *, void *, size_t); 3666extern int32_t sli_cmd_write_nvparms(sli4_t *, void *, size_t, uint8_t *, uint8_t *, uint8_t, uint32_t); 3667typedef struct { 3668 uint16_t rq_id; 3669 uint8_t r_ctl_mask; 3670 uint8_t r_ctl_match; 3671 uint8_t type_mask; 3672 uint8_t type_match; 3673} sli4_cmd_rq_cfg_t; 3674extern int32_t sli_cmd_reg_fcfi(sli4_t *, void *, size_t, uint16_t, 3675 sli4_cmd_rq_cfg_t rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG], uint16_t); 3676extern int32_t sli_cmd_reg_fcfi_mrq(sli4_t *, void *, size_t, uint8_t, uint16_t, uint16_t, uint8_t, uint8_t , uint16_t, sli4_cmd_rq_cfg_t rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG]); 3677 3678extern int32_t sli_cmd_reg_rpi(sli4_t *, void *, size_t, uint32_t, uint16_t, uint16_t, ocs_dma_t *, uint8_t, uint8_t); 3679extern int32_t sli_cmd_reg_vfi(sli4_t *, void *, size_t, ocs_domain_t *); 3680extern int32_t sli_cmd_reg_vpi(sli4_t *, void *, size_t, ocs_sli_port_t *, uint8_t); 3681extern int32_t sli_cmd_sli_config(sli4_t *, void *, size_t, uint32_t, ocs_dma_t *); 3682extern int32_t sli_cmd_unreg_fcfi(sli4_t *, void *, size_t, uint16_t); 3683extern int32_t sli_cmd_unreg_rpi(sli4_t *, void *, size_t, uint16_t, sli4_resource_e, uint32_t); 3684extern int32_t sli_cmd_unreg_vfi(sli4_t *, void *, size_t, ocs_domain_t *, uint32_t); 3685extern int32_t sli_cmd_unreg_vpi(sli4_t *, void *, size_t, uint16_t, uint32_t); 3686extern int32_t sli_cmd_common_nop(sli4_t *, void *, size_t, uint64_t); 3687extern int32_t sli_cmd_common_get_resource_extent_info(sli4_t *, void *, size_t, uint16_t); 3688extern int32_t sli_cmd_common_get_sli4_parameters(sli4_t *, void *, size_t); 3689extern int32_t sli_cmd_common_write_object(sli4_t *, void *, size_t, 3690 uint16_t, uint16_t, uint32_t, uint32_t, char *, ocs_dma_t *); 3691extern int32_t sli_cmd_common_delete_object(sli4_t *, void *, size_t, char *); 3692extern int32_t sli_cmd_common_read_object(sli4_t *, void *, size_t, uint32_t, 3693 uint32_t, char *, ocs_dma_t *); 3694extern int32_t sli_cmd_dmtf_exec_clp_cmd(sli4_t *sli4, void *buf, size_t size, 3695 ocs_dma_t *cmd, 3696 ocs_dma_t *resp); 3697extern int32_t sli_cmd_common_set_dump_location(sli4_t *sli4, void *buf, size_t size, 3698 uint8_t query, uint8_t is_buffer_list, 3699 ocs_dma_t *buffer, uint8_t fdb); 3700extern int32_t sli_cmd_common_set_features(sli4_t *, void *, size_t, uint32_t, uint32_t, void*); 3701extern int32_t sli_cmd_common_get_profile_list(sli4_t *sli4, void *buf, 3702 size_t size, uint32_t start_profile_index, ocs_dma_t *dma); 3703extern int32_t sli_cmd_common_get_active_profile(sli4_t *sli4, void *buf, 3704 size_t size); 3705extern int32_t sli_cmd_common_set_active_profile(sli4_t *sli4, void *buf, 3706 size_t size, 3707 uint32_t fd, 3708 uint32_t active_profile_id); 3709extern int32_t sli_cmd_common_get_reconfig_link_info(sli4_t *sli4, void *buf, 3710 size_t size, ocs_dma_t *dma); 3711extern int32_t sli_cmd_common_set_reconfig_link_id(sli4_t *sli4, void *buf, 3712 size_t size, ocs_dma_t *dma, 3713 uint32_t fd, uint32_t active_link_config_id); 3714extern int32_t sli_cmd_common_get_function_config(sli4_t *sli4, void *buf, 3715 size_t size); 3716extern int32_t sli_cmd_common_get_profile_config(sli4_t *sli4, void *buf, 3717 size_t size, ocs_dma_t *dma); 3718extern int32_t sli_cmd_common_set_profile_config(sli4_t *sli4, void *buf, 3719 size_t size, ocs_dma_t *dma, 3720 uint8_t profile_id, uint32_t descriptor_count, 3721 uint8_t isap); 3722 3723extern int32_t sli_cqe_mq(void *); 3724extern int32_t sli_cqe_async(sli4_t *, void *); 3725 3726extern int32_t sli_setup(sli4_t *, ocs_os_handle_t, sli4_port_type_e); 3727extern void sli_calc_max_qentries(sli4_t *sli4); 3728extern int32_t sli_init(sli4_t *); 3729extern int32_t sli_reset(sli4_t *); 3730extern int32_t sli_fw_reset(sli4_t *); 3731extern int32_t sli_teardown(sli4_t *); 3732extern int32_t sli_callback(sli4_t *, sli4_callback_e, void *, void *); 3733extern int32_t sli_bmbx_command(sli4_t *); 3734extern int32_t __sli_queue_init(sli4_t *, sli4_queue_t *, uint32_t, size_t, uint32_t, uint32_t); 3735extern int32_t __sli_create_queue(sli4_t *, sli4_queue_t *); 3736extern int32_t sli_eq_modify_delay(sli4_t *sli4, sli4_queue_t *eq, uint32_t num_eq, uint32_t shift, uint32_t delay_mult); 3737extern int32_t sli_queue_alloc(sli4_t *, uint32_t, sli4_queue_t *, uint32_t, sli4_queue_t *, uint16_t); 3738extern int32_t sli_cq_alloc_set(sli4_t *, sli4_queue_t *qs[], uint32_t, uint32_t, sli4_queue_t *eqs[]); 3739extern int32_t sli_get_queue_entry_size(sli4_t *, uint32_t); 3740extern int32_t sli_queue_free(sli4_t *, sli4_queue_t *, uint32_t, uint32_t); 3741extern int32_t sli_queue_reset(sli4_t *, sli4_queue_t *); 3742extern int32_t sli_queue_is_empty(sli4_t *, sli4_queue_t *); 3743extern int32_t sli_queue_eq_arm(sli4_t *, sli4_queue_t *, uint8_t); 3744extern int32_t sli_queue_arm(sli4_t *, sli4_queue_t *, uint8_t); 3745extern int32_t _sli_queue_write(sli4_t *, sli4_queue_t *, uint8_t *); 3746extern int32_t sli_queue_write(sli4_t *, sli4_queue_t *, uint8_t *); 3747extern int32_t sli_queue_read(sli4_t *, sli4_queue_t *, uint8_t *); 3748extern int32_t sli_queue_index(sli4_t *, sli4_queue_t *); 3749extern int32_t _sli_queue_poke(sli4_t *, sli4_queue_t *, uint32_t, uint8_t *); 3750extern int32_t sli_queue_poke(sli4_t *, sli4_queue_t *, uint32_t, uint8_t *); 3751extern int32_t sli_resource_alloc(sli4_t *, sli4_resource_e, uint32_t *, uint32_t *); 3752extern int32_t sli_resource_free(sli4_t *, sli4_resource_e, uint32_t); 3753extern int32_t sli_resource_reset(sli4_t *, sli4_resource_e); 3754extern int32_t sli_eq_parse(sli4_t *, uint8_t *, uint16_t *); 3755extern int32_t sli_cq_parse(sli4_t *, sli4_queue_t *, uint8_t *, sli4_qentry_e *, uint16_t *); 3756 3757extern int32_t sli_raise_ue(sli4_t *, uint8_t); 3758extern int32_t sli_dump_is_ready(sli4_t *); 3759extern int32_t sli_dump_is_present(sli4_t *); 3760extern int32_t sli_reset_required(sli4_t *); 3761extern int32_t sli_fw_error_status(sli4_t *); 3762extern int32_t sli_fw_ready(sli4_t *); 3763extern uint32_t sli_reg_read(sli4_t *, sli4_regname_e); 3764extern void sli_reg_write(sli4_t *, sli4_regname_e, uint32_t); 3765extern int32_t sli_link_is_configurable(sli4_t *); 3766 3767#include "ocs_fcp.h" 3768 3769/** 3770 * @brief Maximum value for a FCFI 3771 * 3772 * Note that although most commands provide a 16 bit field for the FCFI, 3773 * the FC/FCoE Asynchronous Recived CQE format only provides 6 bits for 3774 * the returned FCFI. Then effectively, the FCFI cannot be larger than 3775 * 1 << 6 or 64. 3776 */ 3777#define SLI4_MAX_FCFI 64 3778 3779/** 3780 * @brief Maximum value for FCF index 3781 * 3782 * The SLI-4 specification uses a 16 bit field in most places for the FCF 3783 * index, but practically, this value will be much smaller. Arbitrarily 3784 * limit the max FCF index to match the max FCFI value. 3785 */ 3786#define SLI4_MAX_FCF_INDEX SLI4_MAX_FCFI 3787 3788/************************************************************************* 3789 * SLI-4 FC/FCoE mailbox command formats and definitions. 3790 */ 3791 3792/** 3793 * FC/FCoE opcode (OPC) values. 3794 */ 3795#define SLI4_OPC_FCOE_WQ_CREATE 0x1 3796#define SLI4_OPC_FCOE_WQ_DESTROY 0x2 3797#define SLI4_OPC_FCOE_POST_SGL_PAGES 0x3 3798#define SLI4_OPC_FCOE_RQ_CREATE 0x5 3799#define SLI4_OPC_FCOE_RQ_DESTROY 0x6 3800#define SLI4_OPC_FCOE_READ_FCF_TABLE 0x8 3801#define SLI4_OPC_FCOE_POST_HDR_TEMPLATES 0xb 3802#define SLI4_OPC_FCOE_REDISCOVER_FCF 0x10 3803 3804/* Use the default CQ associated with the WQ */ 3805#define SLI4_CQ_DEFAULT 0xffff 3806 3807typedef struct sli4_physical_page_descriptor_s { 3808 uint32_t low; 3809 uint32_t high; 3810} sli4_physical_page_descriptor_t; 3811 3812/** 3813 * @brief FCOE_WQ_CREATE 3814 * 3815 * Create a Work Queue for FC/FCoE use. 3816 */ 3817#define SLI4_FCOE_WQ_CREATE_V0_MAX_PAGES 4 3818 3819typedef struct sli4_req_fcoe_wq_create_s { 3820 sli4_req_hdr_t hdr; 3821#if BYTE_ORDER == LITTLE_ENDIAN 3822 uint32_t num_pages:8, 3823 dua:1, 3824 :7, 3825 cq_id:16; 3826 sli4_physical_page_descriptor_t page_physical_address[SLI4_FCOE_WQ_CREATE_V0_MAX_PAGES]; 3827 uint32_t bqu:1, 3828 :7, 3829 ulp:8, 3830 :16; 3831#else 3832#error big endian version not defined 3833#endif 3834} sli4_req_fcoe_wq_create_t; 3835 3836/** 3837 * @brief FCOE_WQ_CREATE_V1 3838 * 3839 * Create a version 1 Work Queue for FC/FCoE use. 3840 */ 3841typedef struct sli4_req_fcoe_wq_create_v1_s { 3842 sli4_req_hdr_t hdr; 3843#if BYTE_ORDER == LITTLE_ENDIAN 3844 uint32_t num_pages:16, 3845 cq_id:16; 3846 uint32_t page_size:8, 3847 wqe_size:4, 3848 :4, 3849 wqe_count:16; 3850 uint32_t rsvd6; 3851 sli4_physical_page_descriptor_t page_physical_address[8]; 3852#else 3853#error big endian version not defined 3854#endif 3855} sli4_req_fcoe_wq_create_v1_t; 3856 3857#define SLI4_FCOE_WQ_CREATE_V1_MAX_PAGES 8 3858 3859/** 3860 * @brief FCOE_WQ_DESTROY 3861 * 3862 * Destroy an FC/FCoE Work Queue. 3863 */ 3864typedef struct sli4_req_fcoe_wq_destroy_s { 3865 sli4_req_hdr_t hdr; 3866#if BYTE_ORDER == LITTLE_ENDIAN 3867 uint32_t wq_id:16, 3868 :16; 3869#else 3870#error big endian version not defined 3871#endif 3872} sli4_req_fcoe_wq_destroy_t; 3873 3874/** 3875 * @brief FCOE_POST_SGL_PAGES 3876 * 3877 * Register the scatter gather list (SGL) memory and associate it with an XRI. 3878 */ 3879typedef struct sli4_req_fcoe_post_sgl_pages_s { 3880 sli4_req_hdr_t hdr; 3881#if BYTE_ORDER == LITTLE_ENDIAN 3882 uint32_t xri_start:16, 3883 xri_count:16; 3884 struct { 3885 uint32_t page0_low; 3886 uint32_t page0_high; 3887 uint32_t page1_low; 3888 uint32_t page1_high; 3889 } page_set[10]; 3890#else 3891#error big endian version not defined 3892#endif 3893} sli4_req_fcoe_post_sgl_pages_t; 3894 3895/** 3896 * @brief FCOE_RQ_CREATE 3897 * 3898 * Create a Receive Queue for FC/FCoE use. 3899 */ 3900typedef struct sli4_req_fcoe_rq_create_s { 3901 sli4_req_hdr_t hdr; 3902#if BYTE_ORDER == LITTLE_ENDIAN 3903 uint32_t num_pages:16, 3904 dua:1, 3905 bqu:1, 3906 :6, 3907 ulp:8; 3908 uint32_t :16, 3909 rqe_count:4, 3910 :12; 3911 uint32_t rsvd6; 3912 uint32_t buffer_size:16, 3913 cq_id:16; 3914 uint32_t rsvd8; 3915 sli4_physical_page_descriptor_t page_physical_address[8]; 3916#else 3917#error big endian version not defined 3918#endif 3919} sli4_req_fcoe_rq_create_t; 3920 3921#define SLI4_FCOE_RQ_CREATE_V0_MAX_PAGES 8 3922#define SLI4_FCOE_RQ_CREATE_V0_MIN_BUF_SIZE 128 3923#define SLI4_FCOE_RQ_CREATE_V0_MAX_BUF_SIZE 2048 3924 3925/** 3926 * @brief FCOE_RQ_CREATE_V1 3927 * 3928 * Create a version 1 Receive Queue for FC/FCoE use. 3929 */ 3930typedef struct sli4_req_fcoe_rq_create_v1_s { 3931 sli4_req_hdr_t hdr; 3932#if BYTE_ORDER == LITTLE_ENDIAN 3933 uint32_t num_pages:16, 3934 :13, 3935 dim:1, 3936 dfd:1, 3937 dnb:1; 3938 uint32_t page_size:8, 3939 rqe_size:4, 3940 :4, 3941 rqe_count:16; 3942 uint32_t rsvd6; 3943 uint32_t :16, 3944 cq_id:16; 3945 uint32_t buffer_size; 3946 sli4_physical_page_descriptor_t page_physical_address[8]; 3947#else 3948#error big endian version not defined 3949#endif 3950} sli4_req_fcoe_rq_create_v1_t; 3951 3952/** 3953 * @brief FCOE_RQ_CREATE_V2 3954 * 3955 * Create a version 2 Receive Queue for FC/FCoE use. 3956 */ 3957typedef struct sli4_req_fcoe_rq_create_v2_s { 3958 sli4_req_hdr_t hdr; 3959#if BYTE_ORDER == LITTLE_ENDIAN 3960 uint32_t num_pages:16, 3961 rq_count:8, 3962 :5, 3963 dim:1, 3964 dfd:1, 3965 dnb:1; 3966 uint32_t page_size:8, 3967 rqe_size:4, 3968 :4, 3969 rqe_count:16; 3970 uint32_t hdr_buffer_size:16, 3971 payload_buffer_size:16; 3972 uint32_t base_cq_id:16, 3973 :16; 3974 uint32_t rsvd; 3975 sli4_physical_page_descriptor_t page_physical_address[0]; 3976#else 3977#error big endian version not defined 3978#endif 3979} sli4_req_fcoe_rq_create_v2_t; 3980 3981#define SLI4_FCOE_RQ_CREATE_V1_MAX_PAGES 8 3982#define SLI4_FCOE_RQ_CREATE_V1_MIN_BUF_SIZE 64 3983#define SLI4_FCOE_RQ_CREATE_V1_MAX_BUF_SIZE 2048 3984 3985#define SLI4_FCOE_RQE_SIZE_8 0x2 3986#define SLI4_FCOE_RQE_SIZE_16 0x3 3987#define SLI4_FCOE_RQE_SIZE_32 0x4 3988#define SLI4_FCOE_RQE_SIZE_64 0x5 3989#define SLI4_FCOE_RQE_SIZE_128 0x6 3990 3991#define SLI4_FCOE_RQ_PAGE_SIZE_4096 0x1 3992#define SLI4_FCOE_RQ_PAGE_SIZE_8192 0x2 3993#define SLI4_FCOE_RQ_PAGE_SIZE_16384 0x4 3994#define SLI4_FCOE_RQ_PAGE_SIZE_32768 0x8 3995#define SLI4_FCOE_RQ_PAGE_SIZE_64536 0x10 3996 3997#define SLI4_FCOE_RQE_SIZE 8 3998 3999/** 4000 * @brief FCOE_RQ_DESTROY 4001 * 4002 * Destroy an FC/FCoE Receive Queue. 4003 */ 4004typedef struct sli4_req_fcoe_rq_destroy_s { 4005 sli4_req_hdr_t hdr; 4006#if BYTE_ORDER == LITTLE_ENDIAN 4007 uint32_t rq_id:16, 4008 :16; 4009#else 4010#error big endian version not defined 4011#endif 4012} sli4_req_fcoe_rq_destroy_t; 4013 4014/** 4015 * @brief FCOE_READ_FCF_TABLE 4016 * 4017 * Retrieve a FCF database (also known as a table) entry created by the SLI Port 4018 * during FIP discovery. 4019 */ 4020typedef struct sli4_req_fcoe_read_fcf_table_s { 4021 sli4_req_hdr_t hdr; 4022#if BYTE_ORDER == LITTLE_ENDIAN 4023 uint32_t fcf_index:16, 4024 :16; 4025#else 4026#error big endian version not defined 4027#endif 4028} sli4_req_fcoe_read_fcf_table_t; 4029 4030/* A FCF index of -1 on the request means return the first valid entry */ 4031#define SLI4_FCOE_FCF_TABLE_FIRST (UINT16_MAX) 4032 4033/** 4034 * @brief FCF table entry 4035 * 4036 * This is the information returned by the FCOE_READ_FCF_TABLE command. 4037 */ 4038typedef struct sli4_fcf_entry_s { 4039#if BYTE_ORDER == LITTLE_ENDIAN 4040 uint32_t max_receive_size; 4041 uint32_t fip_keep_alive; 4042 uint32_t fip_priority; 4043 uint8_t fcf_mac_address[6]; 4044 uint8_t fcf_available; 4045 uint8_t mac_address_provider; 4046 uint8_t fabric_name_id[8]; 4047 uint8_t fc_map[3]; 4048 uint8_t val:1, 4049 fc:1, 4050 :5, 4051 sol:1; 4052 uint32_t fcf_index:16, 4053 fcf_state:16; 4054 uint8_t vlan_bitmap[512]; 4055 uint8_t switch_name[8]; 4056#else 4057#error big endian version not defined 4058#endif 4059} sli4_fcf_entry_t; 4060 4061/** 4062 * @brief FCOE_READ_FCF_TABLE response. 4063 */ 4064typedef struct sli4_res_fcoe_read_fcf_table_s { 4065 sli4_res_hdr_t hdr; 4066#if BYTE_ORDER == LITTLE_ENDIAN 4067 uint32_t event_tag; 4068 uint32_t next_index:16, 4069 :16; 4070 sli4_fcf_entry_t fcf_entry; 4071#else 4072#error big endian version not defined 4073#endif 4074} sli4_res_fcoe_read_fcf_table_t; 4075 4076/* A next FCF index of -1 in the response means this is the last valid entry */ 4077#define SLI4_FCOE_FCF_TABLE_LAST (UINT16_MAX) 4078 4079/** 4080 * @brief FCOE_POST_HDR_TEMPLATES 4081 */ 4082typedef struct sli4_req_fcoe_post_hdr_templates_s { 4083 sli4_req_hdr_t hdr; 4084#if BYTE_ORDER == LITTLE_ENDIAN 4085 uint32_t rpi_offset:16, 4086 page_count:16; 4087 sli4_physical_page_descriptor_t page_descriptor[0]; 4088#else 4089#error big endian version not defined 4090#endif 4091} sli4_req_fcoe_post_hdr_templates_t; 4092 4093#define SLI4_FCOE_HDR_TEMPLATE_SIZE 64 4094 4095/** 4096 * @brief FCOE_REDISCOVER_FCF 4097 */ 4098typedef struct sli4_req_fcoe_rediscover_fcf_s { 4099 sli4_req_hdr_t hdr; 4100#if BYTE_ORDER == LITTLE_ENDIAN 4101 uint32_t fcf_count:16, 4102 :16; 4103 uint32_t rsvd5; 4104 uint16_t fcf_index[16]; 4105#else 4106#error big endian version not defined 4107#endif 4108} sli4_req_fcoe_rediscover_fcf_t; 4109 4110/** 4111 * Work Queue Entry (WQE) types. 4112 */ 4113#define SLI4_WQE_ABORT 0x0f 4114#define SLI4_WQE_ELS_REQUEST64 0x8a 4115#define SLI4_WQE_FCP_IBIDIR64 0xac 4116#define SLI4_WQE_FCP_IREAD64 0x9a 4117#define SLI4_WQE_FCP_IWRITE64 0x98 4118#define SLI4_WQE_FCP_ICMND64 0x9c 4119#define SLI4_WQE_FCP_TRECEIVE64 0xa1 4120#define SLI4_WQE_FCP_CONT_TRECEIVE64 0xe5 4121#define SLI4_WQE_FCP_TRSP64 0xa3 4122#define SLI4_WQE_FCP_TSEND64 0x9f 4123#define SLI4_WQE_GEN_REQUEST64 0xc2 4124#define SLI4_WQE_SEND_FRAME 0xe1 4125#define SLI4_WQE_XMIT_BCAST64 0X84 4126#define SLI4_WQE_XMIT_BLS_RSP 0x97 4127#define SLI4_WQE_ELS_RSP64 0x95 4128#define SLI4_WQE_XMIT_SEQUENCE64 0x82 4129#define SLI4_WQE_REQUEUE_XRI 0x93 4130 4131/** 4132 * WQE command types. 4133 */ 4134#define SLI4_CMD_FCP_IREAD64_WQE 0x00 4135#define SLI4_CMD_FCP_ICMND64_WQE 0x00 4136#define SLI4_CMD_FCP_IWRITE64_WQE 0x01 4137#define SLI4_CMD_FCP_TRECEIVE64_WQE 0x02 4138#define SLI4_CMD_FCP_TRSP64_WQE 0x03 4139#define SLI4_CMD_FCP_TSEND64_WQE 0x07 4140#define SLI4_CMD_GEN_REQUEST64_WQE 0x08 4141#define SLI4_CMD_XMIT_BCAST64_WQE 0x08 4142#define SLI4_CMD_XMIT_BLS_RSP64_WQE 0x08 4143#define SLI4_CMD_ABORT_WQE 0x08 4144#define SLI4_CMD_XMIT_SEQUENCE64_WQE 0x08 4145#define SLI4_CMD_REQUEUE_XRI_WQE 0x0A 4146#define SLI4_CMD_SEND_FRAME_WQE 0x0a 4147 4148#define SLI4_WQE_SIZE 0x05 4149#define SLI4_WQE_EXT_SIZE 0x06 4150 4151#define SLI4_WQE_BYTES (16 * sizeof(uint32_t)) 4152#define SLI4_WQE_EXT_BYTES (32 * sizeof(uint32_t)) 4153 4154/* Mask for ccp (CS_CTL) */ 4155#define SLI4_MASK_CCP 0xfe /* Upper 7 bits of CS_CTL is priority */ 4156 4157/** 4158 * @brief Generic WQE 4159 */ 4160typedef struct sli4_generic_wqe_s { 4161#if BYTE_ORDER == LITTLE_ENDIAN 4162 uint32_t cmd_spec0_5[6]; 4163 uint32_t xri_tag:16, 4164 context_tag:16; 4165 uint32_t :2, 4166 ct:2, 4167 :4, 4168 command:8, 4169 class:3, 4170 :1, 4171 pu:2, 4172 :2, 4173 timer:8; 4174 uint32_t abort_tag; 4175 uint32_t request_tag:16, 4176 :16; 4177 uint32_t ebde_cnt:4, 4178 :3, 4179 len_loc:2, 4180 qosd:1, 4181 :1, 4182 xbl:1, 4183 hlm:1, 4184 iod:1, 4185 dbde:1, 4186 wqes:1, 4187 pri:3, 4188 pv:1, 4189 eat:1, 4190 xc:1, 4191 :1, 4192 ccpe:1, 4193 ccp:8; 4194 uint32_t cmd_type:4, 4195 :3, 4196 wqec:1, 4197 :8, 4198 cq_id:16; 4199#else 4200#error big endian version not defined 4201#endif 4202} sli4_generic_wqe_t; 4203 4204/** 4205 * @brief WQE used to abort exchanges. 4206 */ 4207typedef struct sli4_abort_wqe_s { 4208#if BYTE_ORDER == LITTLE_ENDIAN 4209 uint32_t rsvd0; 4210 uint32_t rsvd1; 4211 uint32_t ext_t_tag; 4212 uint32_t ia:1, 4213 ir:1, 4214 :6, 4215 criteria:8, 4216 :16; 4217 uint32_t ext_t_mask; 4218 uint32_t t_mask; 4219 uint32_t xri_tag:16, 4220 context_tag:16; 4221 uint32_t :2, 4222 ct:2, 4223 :4, 4224 command:8, 4225 class:3, 4226 :1, 4227 pu:2, 4228 :2, 4229 timer:8; 4230 uint32_t t_tag; 4231 uint32_t request_tag:16, 4232 :16; 4233 uint32_t ebde_cnt:4, 4234 :3, 4235 len_loc:2, 4236 qosd:1, 4237 :1, 4238 xbl:1, 4239 :1, 4240 iod:1, 4241 dbde:1, 4242 wqes:1, 4243 pri:3, 4244 pv:1, 4245 eat:1, 4246 xc:1, 4247 :1, 4248 ccpe:1, 4249 ccp:8; 4250 uint32_t cmd_type:4, 4251 :3, 4252 wqec:1, 4253 :8, 4254 cq_id:16; 4255#else 4256#error big endian version not defined 4257#endif 4258} sli4_abort_wqe_t; 4259 4260#define SLI4_ABORT_CRITERIA_XRI_TAG 0x01 4261#define SLI4_ABORT_CRITERIA_ABORT_TAG 0x02 4262#define SLI4_ABORT_CRITERIA_REQUEST_TAG 0x03 4263#define SLI4_ABORT_CRITERIA_EXT_ABORT_TAG 0x04 4264 4265typedef enum { 4266 SLI_ABORT_XRI, 4267 SLI_ABORT_ABORT_ID, 4268 SLI_ABORT_REQUEST_ID, 4269 SLI_ABORT_MAX, /* must be last */ 4270} sli4_abort_type_e; 4271 4272/** 4273 * @brief WQE used to create an ELS request. 4274 */ 4275typedef struct sli4_els_request64_wqe_s { 4276 sli4_bde_t els_request_payload; 4277#if BYTE_ORDER == LITTLE_ENDIAN 4278 uint32_t els_request_payload_length; 4279 uint32_t sid:24, 4280 sp:1, 4281 :7; 4282 uint32_t remote_id:24, 4283 :8; 4284 uint32_t xri_tag:16, 4285 context_tag:16; 4286 uint32_t :2, 4287 ct:2, 4288 :4, 4289 command:8, 4290 class:3, 4291 ar:1, 4292 pu:2, 4293 :2, 4294 timer:8; 4295 uint32_t abort_tag; 4296 uint32_t request_tag:16, 4297 temporary_rpi:16; 4298 uint32_t ebde_cnt:4, 4299 :3, 4300 len_loc:2, 4301 qosd:1, 4302 :1, 4303 xbl:1, 4304 hlm:1, 4305 iod:1, 4306 dbde:1, 4307 wqes:1, 4308 pri:3, 4309 pv:1, 4310 eat:1, 4311 xc:1, 4312 :1, 4313 ccpe:1, 4314 ccp:8; 4315 uint32_t cmd_type:4, 4316 els_id:3, 4317 wqec:1, 4318 :8, 4319 cq_id:16; 4320 sli4_bde_t els_response_payload_bde; 4321 uint32_t max_response_payload_length; 4322#else 4323#error big endian version not defined 4324#endif 4325} sli4_els_request64_wqe_t; 4326 4327#define SLI4_ELS_REQUEST64_CONTEXT_RPI 0x0 4328#define SLI4_ELS_REQUEST64_CONTEXT_VPI 0x1 4329#define SLI4_ELS_REQUEST64_CONTEXT_VFI 0x2 4330#define SLI4_ELS_REQUEST64_CONTEXT_FCFI 0x3 4331 4332#define SLI4_ELS_REQUEST64_CLASS_2 0x1 4333#define SLI4_ELS_REQUEST64_CLASS_3 0x2 4334 4335#define SLI4_ELS_REQUEST64_DIR_WRITE 0x0 4336#define SLI4_ELS_REQUEST64_DIR_READ 0x1 4337 4338#define SLI4_ELS_REQUEST64_OTHER 0x0 4339#define SLI4_ELS_REQUEST64_LOGO 0x1 4340#define SLI4_ELS_REQUEST64_FDISC 0x2 4341#define SLI4_ELS_REQUEST64_FLOGIN 0x3 4342#define SLI4_ELS_REQUEST64_PLOGI 0x4 4343 4344#define SLI4_ELS_REQUEST64_CMD_GEN 0x08 4345#define SLI4_ELS_REQUEST64_CMD_NON_FABRIC 0x0c 4346#define SLI4_ELS_REQUEST64_CMD_FABRIC 0x0d 4347 4348/** 4349 * @brief WQE used to create an FCP initiator no data command. 4350 */ 4351typedef struct sli4_fcp_icmnd64_wqe_s { 4352 sli4_bde_t bde; 4353#if BYTE_ORDER == LITTLE_ENDIAN 4354 uint32_t payload_offset_length:16, 4355 fcp_cmd_buffer_length:16; 4356 uint32_t rsvd4; 4357 uint32_t remote_n_port_id:24, 4358 :8; 4359 uint32_t xri_tag:16, 4360 context_tag:16; 4361 uint32_t dif:2, 4362 ct:2, 4363 bs:3, 4364 :1, 4365 command:8, 4366 class:3, 4367 :1, 4368 pu:2, 4369 erp:1, 4370 lnk:1, 4371 timer:8; 4372 uint32_t abort_tag; 4373 uint32_t request_tag:16, 4374 :16; 4375 uint32_t ebde_cnt:4, 4376 :3, 4377 len_loc:2, 4378 qosd:1, 4379 :1, 4380 xbl:1, 4381 hlm:1, 4382 iod:1, 4383 dbde:1, 4384 wqes:1, 4385 pri:3, 4386 pv:1, 4387 eat:1, 4388 xc:1, 4389 :1, 4390 ccpe:1, 4391 ccp:8; 4392 uint32_t cmd_type:4, 4393 :3, 4394 wqec:1, 4395 :8, 4396 cq_id:16; 4397 uint32_t rsvd12; 4398 uint32_t rsvd13; 4399 uint32_t rsvd14; 4400 uint32_t rsvd15; 4401#else 4402#error big endian version not defined 4403#endif 4404} sli4_fcp_icmnd64_wqe_t; 4405 4406/** 4407 * @brief WQE used to create an FCP initiator read. 4408 */ 4409typedef struct sli4_fcp_iread64_wqe_s { 4410 sli4_bde_t bde; 4411#if BYTE_ORDER == LITTLE_ENDIAN 4412 uint32_t payload_offset_length:16, 4413 fcp_cmd_buffer_length:16; 4414 uint32_t total_transfer_length; 4415 uint32_t remote_n_port_id:24, 4416 :8; 4417 uint32_t xri_tag:16, 4418 context_tag:16; 4419 uint32_t dif:2, 4420 ct:2, 4421 bs:3, 4422 :1, 4423 command:8, 4424 class:3, 4425 :1, 4426 pu:2, 4427 erp:1, 4428 lnk:1, 4429 timer:8; 4430 uint32_t abort_tag; 4431 uint32_t request_tag:16, 4432 :16; 4433 uint32_t ebde_cnt:4, 4434 :3, 4435 len_loc:2, 4436 qosd:1, 4437 :1, 4438 xbl:1, 4439 hlm:1, 4440 iod:1, 4441 dbde:1, 4442 wqes:1, 4443 pri:3, 4444 pv:1, 4445 eat:1, 4446 xc:1, 4447 :1, 4448 ccpe:1, 4449 ccp:8; 4450 uint32_t cmd_type:4, 4451 :3, 4452 wqec:1, 4453 :8, 4454 cq_id:16; 4455 uint32_t rsvd12; 4456#else 4457#error big endian version not defined 4458#endif 4459 sli4_bde_t first_data_bde; /* reserved if performance hints disabled */ 4460} sli4_fcp_iread64_wqe_t; 4461 4462/** 4463 * @brief WQE used to create an FCP initiator write. 4464 */ 4465typedef struct sli4_fcp_iwrite64_wqe_s { 4466 sli4_bde_t bde; 4467#if BYTE_ORDER == LITTLE_ENDIAN 4468 uint32_t payload_offset_length:16, 4469 fcp_cmd_buffer_length:16; 4470 uint32_t total_transfer_length; 4471 uint32_t initial_transfer_length; 4472 uint32_t xri_tag:16, 4473 context_tag:16; 4474 uint32_t dif:2, 4475 ct:2, 4476 bs:3, 4477 :1, 4478 command:8, 4479 class:3, 4480 :1, 4481 pu:2, 4482 erp:1, 4483 lnk:1, 4484 timer:8; 4485 uint32_t abort_tag; 4486 uint32_t request_tag:16, 4487 :16; 4488 uint32_t ebde_cnt:4, 4489 :3, 4490 len_loc:2, 4491 qosd:1, 4492 :1, 4493 xbl:1, 4494 hlm:1, 4495 iod:1, 4496 dbde:1, 4497 wqes:1, 4498 pri:3, 4499 pv:1, 4500 eat:1, 4501 xc:1, 4502 :1, 4503 ccpe:1, 4504 ccp:8; 4505 uint32_t cmd_type:4, 4506 :3, 4507 wqec:1, 4508 :8, 4509 cq_id:16; 4510 uint32_t remote_n_port_id:24, 4511 :8; 4512#else 4513#error big endian version not defined 4514#endif 4515 sli4_bde_t first_data_bde; 4516} sli4_fcp_iwrite64_wqe_t; 4517 4518typedef struct sli4_fcp_128byte_wqe_s { 4519 uint32_t dw[32]; 4520} sli4_fcp_128byte_wqe_t; 4521 4522/** 4523 * @brief WQE used to create an FCP target receive, and FCP target 4524 * receive continue. 4525 */ 4526typedef struct sli4_fcp_treceive64_wqe_s { 4527 sli4_bde_t bde; 4528#if BYTE_ORDER == LITTLE_ENDIAN 4529 uint32_t payload_offset_length; 4530 uint32_t relative_offset; 4531 /** 4532 * DWord 5 can either be the task retry identifier (HLM=0) or 4533 * the remote N_Port ID (HLM=1), or if implementing the Skyhawk 4534 * T10-PI workaround, the secondary xri tag 4535 */ 4536 union { 4537 uint32_t sec_xri_tag:16, 4538 :16; 4539 uint32_t dword; 4540 } dword5; 4541 uint32_t xri_tag:16, 4542 context_tag:16; 4543 uint32_t dif:2, 4544 ct:2, 4545 bs:3, 4546 :1, 4547 command:8, 4548 class:3, 4549 ar:1, 4550 pu:2, 4551 conf:1, 4552 lnk:1, 4553 timer:8; 4554 uint32_t abort_tag; 4555 uint32_t request_tag:16, 4556 remote_xid:16; 4557 uint32_t ebde_cnt:4, 4558 :1, 4559 app_id_valid:1, 4560 :1, 4561 len_loc:2, 4562 qosd:1, 4563 wchn:1, 4564 xbl:1, 4565 hlm:1, 4566 iod:1, 4567 dbde:1, 4568 wqes:1, 4569 pri:3, 4570 pv:1, 4571 eat:1, 4572 xc:1, 4573 sr:1, 4574 ccpe:1, 4575 ccp:8; 4576 uint32_t cmd_type:4, 4577 :3, 4578 wqec:1, 4579 :8, 4580 cq_id:16; 4581 uint32_t fcp_data_receive_length; 4582 4583#else 4584#error big endian version not defined 4585#endif 4586 sli4_bde_t first_data_bde; /* For performance hints */ 4587 4588} sli4_fcp_treceive64_wqe_t; 4589 4590/** 4591 * @brief WQE used to create an FCP target response. 4592 */ 4593typedef struct sli4_fcp_trsp64_wqe_s { 4594 sli4_bde_t bde; 4595#if BYTE_ORDER == LITTLE_ENDIAN 4596 uint32_t fcp_response_length; 4597 uint32_t rsvd4; 4598 /** 4599 * DWord 5 can either be the task retry identifier (HLM=0) or 4600 * the remote N_Port ID (HLM=1) 4601 */ 4602 uint32_t dword5; 4603 uint32_t xri_tag:16, 4604 rpi:16; 4605 uint32_t :2, 4606 ct:2, 4607 dnrx:1, 4608 :3, 4609 command:8, 4610 class:3, 4611 ag:1, 4612 pu:2, 4613 conf:1, 4614 lnk:1, 4615 timer:8; 4616 uint32_t abort_tag; 4617 uint32_t request_tag:16, 4618 remote_xid:16; 4619 uint32_t ebde_cnt:4, 4620 :1, 4621 app_id_valid:1, 4622 :1, 4623 len_loc:2, 4624 qosd:1, 4625 wchn:1, 4626 xbl:1, 4627 hlm:1, 4628 iod:1, 4629 dbde:1, 4630 wqes:1, 4631 pri:3, 4632 pv:1, 4633 eat:1, 4634 xc:1, 4635 sr:1, 4636 ccpe:1, 4637 ccp:8; 4638 uint32_t cmd_type:4, 4639 :3, 4640 wqec:1, 4641 :8, 4642 cq_id:16; 4643 uint32_t rsvd12; 4644 uint32_t rsvd13; 4645 uint32_t rsvd14; 4646 uint32_t rsvd15; 4647#else 4648#error big endian version not defined 4649#endif 4650} sli4_fcp_trsp64_wqe_t; 4651 4652/** 4653 * @brief WQE used to create an FCP target send (DATA IN). 4654 */ 4655typedef struct sli4_fcp_tsend64_wqe_s { 4656 sli4_bde_t bde; 4657#if BYTE_ORDER == LITTLE_ENDIAN 4658 uint32_t payload_offset_length; 4659 uint32_t relative_offset; 4660 /** 4661 * DWord 5 can either be the task retry identifier (HLM=0) or 4662 * the remote N_Port ID (HLM=1) 4663 */ 4664 uint32_t dword5; 4665 uint32_t xri_tag:16, 4666 rpi:16; 4667 uint32_t dif:2, 4668 ct:2, 4669 bs:3, 4670 :1, 4671 command:8, 4672 class:3, 4673 ar:1, 4674 pu:2, 4675 conf:1, 4676 lnk:1, 4677 timer:8; 4678 uint32_t abort_tag; 4679 uint32_t request_tag:16, 4680 remote_xid:16; 4681 uint32_t ebde_cnt:4, 4682 :1, 4683 app_id_valid:1, 4684 :1, 4685 len_loc:2, 4686 qosd:1, 4687 wchn:1, 4688 xbl:1, 4689 hlm:1, 4690 iod:1, 4691 dbde:1, 4692 wqes:1, 4693 pri:3, 4694 pv:1, 4695 eat:1, 4696 xc:1, 4697 sr:1, 4698 ccpe:1, 4699 ccp:8; 4700 uint32_t cmd_type:4, 4701 :3, 4702 wqec:1, 4703 :8, 4704 cq_id:16; 4705 uint32_t fcp_data_transmit_length; 4706 4707#else 4708#error big endian version not defined 4709#endif 4710 sli4_bde_t first_data_bde; /* For performance hints */ 4711} sli4_fcp_tsend64_wqe_t; 4712 4713#define SLI4_IO_CONTINUATION BIT(0) /** The XRI associated with this IO is already active */ 4714#define SLI4_IO_AUTO_GOOD_RESPONSE BIT(1) /** Automatically generate a good RSP frame */ 4715#define SLI4_IO_NO_ABORT BIT(2) 4716#define SLI4_IO_DNRX BIT(3) /** Set the DNRX bit because no auto xref rdy buffer is posted */ 4717 4718/* WQE DIF field contents */ 4719#define SLI4_DIF_DISABLED 0 4720#define SLI4_DIF_PASS_THROUGH 1 4721#define SLI4_DIF_STRIP 2 4722#define SLI4_DIF_INSERT 3 4723 4724/** 4725 * @brief WQE used to create a general request. 4726 */ 4727typedef struct sli4_gen_request64_wqe_s { 4728 sli4_bde_t bde; 4729#if BYTE_ORDER == LITTLE_ENDIAN 4730 uint32_t request_payload_length; 4731 uint32_t relative_offset; 4732 uint32_t :8, 4733 df_ctl:8, 4734 type:8, 4735 r_ctl:8; 4736 uint32_t xri_tag:16, 4737 context_tag:16; 4738 uint32_t :2, 4739 ct:2, 4740 :4, 4741 command:8, 4742 class:3, 4743 :1, 4744 pu:2, 4745 :2, 4746 timer:8; 4747 uint32_t abort_tag; 4748 uint32_t request_tag:16, 4749 :16; 4750 uint32_t ebde_cnt:4, 4751 :3, 4752 len_loc:2, 4753 qosd:1, 4754 :1, 4755 xbl:1, 4756 hlm:1, 4757 iod:1, 4758 dbde:1, 4759 wqes:1, 4760 pri:3, 4761 pv:1, 4762 eat:1, 4763 xc:1, 4764 :1, 4765 ccpe:1, 4766 ccp:8; 4767 uint32_t cmd_type:4, 4768 :3, 4769 wqec:1, 4770 :8, 4771 cq_id:16; 4772 uint32_t remote_n_port_id:24, 4773 :8; 4774 uint32_t rsvd13; 4775 uint32_t rsvd14; 4776 uint32_t max_response_payload_length; 4777#else 4778#error big endian version not defined 4779#endif 4780} sli4_gen_request64_wqe_t; 4781 4782/** 4783 * @brief WQE used to create a send frame request. 4784 */ 4785typedef struct sli4_send_frame_wqe_s { 4786 sli4_bde_t bde; 4787#if BYTE_ORDER == LITTLE_ENDIAN 4788 uint32_t frame_length; 4789 uint32_t fc_header_0_1[2]; 4790 uint32_t xri_tag:16, 4791 context_tag:16; 4792 uint32_t :2, 4793 ct:2, 4794 :4, 4795 command:8, 4796 class:3, 4797 :1, 4798 pu:2, 4799 :2, 4800 timer:8; 4801 uint32_t abort_tag; 4802 uint32_t request_tag:16, 4803 eof:8, 4804 sof:8; 4805 uint32_t ebde_cnt:4, 4806 :3, 4807 lenloc:2, 4808 qosd:1, 4809 wchn:1, 4810 xbl:1, 4811 hlm:1, 4812 iod:1, 4813 dbde:1, 4814 wqes:1, 4815 pri:3, 4816 pv:1, 4817 eat:1, 4818 xc:1, 4819 :1, 4820 ccpe:1, 4821 ccp:8; 4822 uint32_t cmd_type:4, 4823 :3, 4824 wqec:1, 4825 :8, 4826 cq_id:16; 4827 uint32_t fc_header_2_5[4]; 4828#else 4829#error big endian version not defined 4830#endif 4831} sli4_send_frame_wqe_t; 4832 4833/** 4834 * @brief WQE used to create a transmit sequence. 4835 */ 4836typedef struct sli4_xmit_sequence64_wqe_s { 4837 sli4_bde_t bde; 4838#if BYTE_ORDER == LITTLE_ENDIAN 4839 uint32_t remote_n_port_id:24, 4840 :8; 4841 uint32_t relative_offset; 4842 uint32_t :2, 4843 si:1, 4844 ft:1, 4845 :2, 4846 xo:1, 4847 ls:1, 4848 df_ctl:8, 4849 type:8, 4850 r_ctl:8; 4851 uint32_t xri_tag:16, 4852 context_tag:16; 4853 uint32_t dif:2, 4854 ct:2, 4855 bs:3, 4856 :1, 4857 command:8, 4858 class:3, 4859 :1, 4860 pu:2, 4861 :2, 4862 timer:8; 4863 uint32_t abort_tag; 4864 uint32_t request_tag:16, 4865 remote_xid:16; 4866 uint32_t ebde_cnt:4, 4867 :3, 4868 len_loc:2, 4869 qosd:1, 4870 :1, 4871 xbl:1, 4872 hlm:1, 4873 iod:1, 4874 dbde:1, 4875 wqes:1, 4876 pri:3, 4877 pv:1, 4878 eat:1, 4879 xc:1, 4880 sr:1, 4881 ccpe:1, 4882 ccp:8; 4883 uint32_t cmd_type:4, 4884 :3, 4885 wqec:1, 4886 :8, 4887 cq_id:16; 4888 uint32_t sequence_payload_len; 4889 uint32_t rsvd13; 4890 uint32_t rsvd14; 4891 uint32_t rsvd15; 4892#else 4893#error big endian version not defined 4894#endif 4895} sli4_xmit_sequence64_wqe_t; 4896 4897/** 4898 * @brief WQE used unblock the specified XRI and to release it to the SLI Port's free pool. 4899 */ 4900typedef struct sli4_requeue_xri_wqe_s { 4901 uint32_t rsvd0; 4902 uint32_t rsvd1; 4903 uint32_t rsvd2; 4904 uint32_t rsvd3; 4905 uint32_t rsvd4; 4906 uint32_t rsvd5; 4907#if BYTE_ORDER == LITTLE_ENDIAN 4908 uint32_t xri_tag:16, 4909 context_tag:16; 4910 uint32_t :2, 4911 ct:2, 4912 :4, 4913 command:8, 4914 class:3, 4915 :1, 4916 pu:2, 4917 :2, 4918 timer:8; 4919 uint32_t rsvd8; 4920 uint32_t request_tag:16, 4921 :16; 4922 uint32_t ebde_cnt:4, 4923 :3, 4924 len_loc:2, 4925 qosd:1, 4926 wchn:1, 4927 xbl:1, 4928 hlm:1, 4929 iod:1, 4930 dbde:1, 4931 wqes:1, 4932 pri:3, 4933 pv:1, 4934 eat:1, 4935 xc:1, 4936 :1, 4937 ccpe:1, 4938 ccp:8; 4939 uint32_t cmd_type:4, 4940 :3, 4941 wqec:1, 4942 :8, 4943 cq_id:16; 4944 uint32_t rsvd12; 4945 uint32_t rsvd13; 4946 uint32_t rsvd14; 4947 uint32_t rsvd15; 4948#else 4949#error big endian version not defined 4950#endif 4951} sli4_requeue_xri_wqe_t; 4952 4953/** 4954 * @brief WQE used to send a single frame sequence to broadcast address 4955 */ 4956typedef struct sli4_xmit_bcast64_wqe_s { 4957 sli4_bde_t sequence_payload; 4958#if BYTE_ORDER == LITTLE_ENDIAN 4959 uint32_t sequence_payload_length; 4960 uint32_t rsvd4; 4961 uint32_t :8, 4962 df_ctl:8, 4963 type:8, 4964 r_ctl:8; 4965 uint32_t xri_tag:16, 4966 context_tag:16; 4967 uint32_t :2, 4968 ct:2, 4969 :4, 4970 command:8, 4971 class:3, 4972 :1, 4973 pu:2, 4974 :2, 4975 timer:8; 4976 uint32_t abort_tag; 4977 uint32_t request_tag:16, 4978 temporary_rpi:16; 4979 uint32_t ebde_cnt:4, 4980 :3, 4981 len_loc:2, 4982 qosd:1, 4983 :1, 4984 xbl:1, 4985 hlm:1, 4986 iod:1, 4987 dbde:1, 4988 wqes:1, 4989 pri:3, 4990 pv:1, 4991 eat:1, 4992 xc:1, 4993 :1, 4994 ccpe:1, 4995 ccp:8; 4996 uint32_t cmd_type:4, 4997 :3, 4998 wqec:1, 4999 :8, 5000 cq_id:16; 5001 uint32_t rsvd12; 5002 uint32_t rsvd13; 5003 uint32_t rsvd14; 5004 uint32_t rsvd15; 5005#else 5006#error big endian version not defined 5007#endif 5008} sli4_xmit_bcast64_wqe_t; 5009 5010/** 5011 * @brief WQE used to create a BLS response. 5012 */ 5013typedef struct sli4_xmit_bls_rsp_wqe_s { 5014#if BYTE_ORDER == LITTLE_ENDIAN 5015 uint32_t payload_word0; 5016 uint32_t rx_id:16, 5017 ox_id:16; 5018 uint32_t high_seq_cnt:16, 5019 low_seq_cnt:16; 5020 uint32_t rsvd3; 5021 uint32_t local_n_port_id:24, 5022 :8; 5023 uint32_t remote_id:24, 5024 :6, 5025 ar:1, 5026 xo:1; 5027 uint32_t xri_tag:16, 5028 context_tag:16; 5029 uint32_t :2, 5030 ct:2, 5031 :4, 5032 command:8, 5033 class:3, 5034 :1, 5035 pu:2, 5036 :2, 5037 timer:8; 5038 uint32_t abort_tag; 5039 uint32_t request_tag:16, 5040 :16; 5041 uint32_t ebde_cnt:4, 5042 :3, 5043 len_loc:2, 5044 qosd:1, 5045 :1, 5046 xbl:1, 5047 hlm:1, 5048 iod:1, 5049 dbde:1, 5050 wqes:1, 5051 pri:3, 5052 pv:1, 5053 eat:1, 5054 xc:1, 5055 :1, 5056 ccpe:1, 5057 ccp:8; 5058 uint32_t cmd_type:4, 5059 :3, 5060 wqec:1, 5061 :8, 5062 cq_id:16; 5063 uint32_t temporary_rpi:16, 5064 :16; 5065 uint32_t rsvd13; 5066 uint32_t rsvd14; 5067 uint32_t rsvd15; 5068#else 5069#error big endian version not defined 5070#endif 5071} sli4_xmit_bls_rsp_wqe_t; 5072 5073typedef enum { 5074 SLI_BLS_ACC, 5075 SLI_BLS_RJT, 5076 SLI_BLS_MAX 5077} sli_bls_type_e; 5078 5079typedef struct sli_bls_payload_s { 5080 sli_bls_type_e type; 5081 uint16_t ox_id; 5082 uint16_t rx_id; 5083 union { 5084 struct { 5085 uint32_t seq_id_validity:8, 5086 seq_id_last:8, 5087 :16; 5088 uint16_t ox_id; 5089 uint16_t rx_id; 5090 uint16_t low_seq_cnt; 5091 uint16_t high_seq_cnt; 5092 } acc; 5093 struct { 5094 uint32_t vendor_unique:8, 5095 reason_explanation:8, 5096 reason_code:8, 5097 :8; 5098 } rjt; 5099 } u; 5100} sli_bls_payload_t; 5101 5102/** 5103 * @brief WQE used to create an ELS response. 5104 */ 5105typedef struct sli4_xmit_els_rsp64_wqe_s { 5106 sli4_bde_t els_response_payload; 5107#if BYTE_ORDER == LITTLE_ENDIAN 5108 uint32_t els_response_payload_length; 5109 uint32_t s_id:24, 5110 sp:1, 5111 :7; 5112 uint32_t remote_id:24, 5113 :8; 5114 uint32_t xri_tag:16, 5115 context_tag:16; 5116 uint32_t :2, 5117 ct:2, 5118 :4, 5119 command:8, 5120 class:3, 5121 :1, 5122 pu:2, 5123 :2, 5124 timer:8; 5125 uint32_t abort_tag; 5126 uint32_t request_tag:16, 5127 ox_id:16; 5128 uint32_t ebde_cnt:4, 5129 :3, 5130 len_loc:2, 5131 qosd:1, 5132 :1, 5133 xbl:1, 5134 hlm:1, 5135 iod:1, 5136 dbde:1, 5137 wqes:1, 5138 pri:3, 5139 pv:1, 5140 eat:1, 5141 xc:1, 5142 :1, 5143 ccpe:1, 5144 ccp:8; 5145 uint32_t cmd_type:4, 5146 :3, 5147 wqec:1, 5148 :8, 5149 cq_id:16; 5150 uint32_t temporary_rpi:16, 5151 :16; 5152 uint32_t rsvd13; 5153 uint32_t rsvd14; 5154 uint32_t rsvd15; 5155#else 5156#error big endian version not defined 5157#endif 5158} sli4_xmit_els_rsp64_wqe_t; 5159 5160/** 5161 * @brief Asynchronouse Event: Link State ACQE. 5162 */ 5163typedef struct sli4_link_state_s { 5164#if BYTE_ORDER == LITTLE_ENDIAN 5165 uint32_t link_number:6, 5166 link_type:2, 5167 port_link_status:8, 5168 port_duplex:8, 5169 port_speed:8; 5170 uint32_t port_fault:8, 5171 :8, 5172 logical_link_speed:16; 5173 uint32_t event_tag; 5174 uint32_t :8, 5175 event_code:8, 5176 event_type:8, /** values are protocol specific */ 5177 :6, 5178 ae:1, /** async event - this is an ACQE */ 5179 val:1; /** valid - contents of CQE are valid */ 5180#else 5181#error big endian version not defined 5182#endif 5183} sli4_link_state_t; 5184 5185#define SLI4_LINK_ATTN_TYPE_LINK_UP 0x01 5186#define SLI4_LINK_ATTN_TYPE_LINK_DOWN 0x02 5187#define SLI4_LINK_ATTN_TYPE_NO_HARD_ALPA 0x03 5188 5189#define SLI4_LINK_ATTN_P2P 0x01 5190#define SLI4_LINK_ATTN_FC_AL 0x02 5191#define SLI4_LINK_ATTN_INTERNAL_LOOPBACK 0x03 5192#define SLI4_LINK_ATTN_SERDES_LOOPBACK 0x04 5193 5194#define SLI4_LINK_ATTN_1G 0x01 5195#define SLI4_LINK_ATTN_2G 0x02 5196#define SLI4_LINK_ATTN_4G 0x04 5197#define SLI4_LINK_ATTN_8G 0x08 5198#define SLI4_LINK_ATTN_10G 0x0a 5199#define SLI4_LINK_ATTN_16G 0x10 5200 5201#define SLI4_LINK_TYPE_ETHERNET 0x0 5202#define SLI4_LINK_TYPE_FC 0x1 5203 5204/** 5205 * @brief Asynchronouse Event: FC Link Attention Event. 5206 */ 5207typedef struct sli4_link_attention_s { 5208#if BYTE_ORDER == LITTLE_ENDIAN 5209 uint32_t link_number:8, 5210 attn_type:8, 5211 topology:8, 5212 port_speed:8; 5213 uint32_t port_fault:8, 5214 shared_link_status:8, 5215 logical_link_speed:16; 5216 uint32_t event_tag; 5217 uint32_t :8, 5218 event_code:8, 5219 event_type:8, /** values are protocol specific */ 5220 :6, 5221 ae:1, /** async event - this is an ACQE */ 5222 val:1; /** valid - contents of CQE are valid */ 5223#else 5224#error big endian version not defined 5225#endif 5226} sli4_link_attention_t; 5227 5228/** 5229 * @brief FC/FCoE event types. 5230 */ 5231#define SLI4_LINK_STATE_PHYSICAL 0x00 5232#define SLI4_LINK_STATE_LOGICAL 0x01 5233 5234#define SLI4_FCOE_FIP_FCF_DISCOVERED 0x01 5235#define SLI4_FCOE_FIP_FCF_TABLE_FULL 0x02 5236#define SLI4_FCOE_FIP_FCF_DEAD 0x03 5237#define SLI4_FCOE_FIP_FCF_CLEAR_VLINK 0x04 5238#define SLI4_FCOE_FIP_FCF_MODIFIED 0x05 5239 5240#define SLI4_GRP5_QOS_SPEED 0x01 5241 5242#define SLI4_FC_EVENT_LINK_ATTENTION 0x01 5243#define SLI4_FC_EVENT_SHARED_LINK_ATTENTION 0x02 5244 5245#define SLI4_PORT_SPEED_NO_LINK 0x0 5246#define SLI4_PORT_SPEED_10_MBPS 0x1 5247#define SLI4_PORT_SPEED_100_MBPS 0x2 5248#define SLI4_PORT_SPEED_1_GBPS 0x3 5249#define SLI4_PORT_SPEED_10_GBPS 0x4 5250 5251#define SLI4_PORT_DUPLEX_NONE 0x0 5252#define SLI4_PORT_DUPLEX_HWF 0x1 5253#define SLI4_PORT_DUPLEX_FULL 0x2 5254 5255#define SLI4_PORT_LINK_STATUS_PHYSICAL_DOWN 0x0 5256#define SLI4_PORT_LINK_STATUS_PHYSICAL_UP 0x1 5257#define SLI4_PORT_LINK_STATUS_LOGICAL_DOWN 0x2 5258#define SLI4_PORT_LINK_STATUS_LOGICAL_UP 0x3 5259 5260/** 5261 * @brief Asynchronouse Event: FCoE/FIP ACQE. 5262 */ 5263typedef struct sli4_fcoe_fip_s { 5264#if BYTE_ORDER == LITTLE_ENDIAN 5265 uint32_t event_information; 5266 uint32_t fcf_count:16, 5267 fcoe_event_type:16; 5268 uint32_t event_tag; 5269 uint32_t :8, 5270 event_code:8, 5271 event_type:8, /** values are protocol specific */ 5272 :6, 5273 ae:1, /** async event - this is an ACQE */ 5274 val:1; /** valid - contents of CQE are valid */ 5275#else 5276#error big endian version not defined 5277#endif 5278} sli4_fcoe_fip_t; 5279 5280/** 5281 * @brief FC/FCoE WQ completion queue entry. 5282 */ 5283typedef struct sli4_fc_wcqe_s { 5284#if BYTE_ORDER == LITTLE_ENDIAN 5285 uint32_t hw_status:8, 5286 status:8, 5287 request_tag:16; 5288 uint32_t wqe_specific_1; 5289 uint32_t wqe_specific_2; 5290 uint32_t :15, 5291 qx:1, 5292 code:8, 5293 pri:3, 5294 pv:1, 5295 xb:1, 5296 :2, 5297 vld:1; 5298#else 5299#error big endian version not defined 5300#endif 5301} sli4_fc_wcqe_t; 5302 5303/** 5304 * @brief FC/FCoE WQ consumed CQ queue entry. 5305 */ 5306typedef struct sli4_fc_wqec_s { 5307#if BYTE_ORDER == LITTLE_ENDIAN 5308 uint32_t :32; 5309 uint32_t :32; 5310 uint32_t wqe_index:16, 5311 wq_id:16; 5312 uint32_t :16, 5313 code:8, 5314 :7, 5315 vld:1; 5316#else 5317#error big endian version not defined 5318#endif 5319} sli4_fc_wqec_t; 5320 5321/** 5322 * @brief FC/FCoE Completion Status Codes. 5323 */ 5324#define SLI4_FC_WCQE_STATUS_SUCCESS 0x00 5325#define SLI4_FC_WCQE_STATUS_FCP_RSP_FAILURE 0x01 5326#define SLI4_FC_WCQE_STATUS_REMOTE_STOP 0x02 5327#define SLI4_FC_WCQE_STATUS_LOCAL_REJECT 0x03 5328#define SLI4_FC_WCQE_STATUS_NPORT_RJT 0x04 5329#define SLI4_FC_WCQE_STATUS_FABRIC_RJT 0x05 5330#define SLI4_FC_WCQE_STATUS_NPORT_BSY 0x06 5331#define SLI4_FC_WCQE_STATUS_FABRIC_BSY 0x07 5332#define SLI4_FC_WCQE_STATUS_LS_RJT 0x09 5333#define SLI4_FC_WCQE_STATUS_CMD_REJECT 0x0b 5334#define SLI4_FC_WCQE_STATUS_FCP_TGT_LENCHECK 0x0c 5335#define SLI4_FC_WCQE_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 5336#define SLI4_FC_WCQE_STATUS_RQ_INSUFF_BUF_NEEDED 0x12 5337#define SLI4_FC_WCQE_STATUS_RQ_INSUFF_FRM_DISC 0x13 5338#define SLI4_FC_WCQE_STATUS_RQ_DMA_FAILURE 0x14 5339#define SLI4_FC_WCQE_STATUS_FCP_RSP_TRUNCATE 0x15 5340#define SLI4_FC_WCQE_STATUS_DI_ERROR 0x16 5341#define SLI4_FC_WCQE_STATUS_BA_RJT 0x17 5342#define SLI4_FC_WCQE_STATUS_RQ_INSUFF_XRI_NEEDED 0x18 5343#define SLI4_FC_WCQE_STATUS_RQ_INSUFF_XRI_DISC 0x19 5344#define SLI4_FC_WCQE_STATUS_RX_ERROR_DETECT 0x1a 5345#define SLI4_FC_WCQE_STATUS_RX_ABORT_REQUEST 0x1b 5346 5347/* driver generated status codes; better not overlap with chip's status codes! */ 5348#define SLI4_FC_WCQE_STATUS_WQE_TIMEOUT 0xff 5349#define SLI4_FC_WCQE_STATUS_SHUTDOWN 0xfe 5350#define SLI4_FC_WCQE_STATUS_DISPATCH_ERROR 0xfd 5351 5352/** 5353 * @brief DI_ERROR Extended Status 5354 */ 5355#define SLI4_FC_DI_ERROR_GE (1 << 0) /* Guard Error */ 5356#define SLI4_FC_DI_ERROR_AE (1 << 1) /* Application Tag Error */ 5357#define SLI4_FC_DI_ERROR_RE (1 << 2) /* Reference Tag Error */ 5358#define SLI4_FC_DI_ERROR_TDPV (1 << 3) /* Total Data Placed Valid */ 5359#define SLI4_FC_DI_ERROR_UDB (1 << 4) /* Uninitialized DIF Block */ 5360#define SLI4_FC_DI_ERROR_EDIR (1 << 5) /* Error direction */ 5361 5362/** 5363 * @brief Local Reject Reason Codes. 5364 */ 5365#define SLI4_FC_LOCAL_REJECT_MISSING_CONTINUE 0x01 5366#define SLI4_FC_LOCAL_REJECT_SEQUENCE_TIMEOUT 0x02 5367#define SLI4_FC_LOCAL_REJECT_INTERNAL_ERROR 0x03 5368#define SLI4_FC_LOCAL_REJECT_INVALID_RPI 0x04 5369#define SLI4_FC_LOCAL_REJECT_NO_XRI 0x05 5370#define SLI4_FC_LOCAL_REJECT_ILLEGAL_COMMAND 0x06 5371#define SLI4_FC_LOCAL_REJECT_XCHG_DROPPED 0x07 5372#define SLI4_FC_LOCAL_REJECT_ILLEGAL_FIELD 0x08 5373#define SLI4_FC_LOCAL_REJECT_NO_ABORT_MATCH 0x0c 5374#define SLI4_FC_LOCAL_REJECT_TX_DMA_FAILED 0x0d 5375#define SLI4_FC_LOCAL_REJECT_RX_DMA_FAILED 0x0e 5376#define SLI4_FC_LOCAL_REJECT_ILLEGAL_FRAME 0x0f 5377#define SLI4_FC_LOCAL_REJECT_NO_RESOURCES 0x11 5378#define SLI4_FC_LOCAL_REJECT_FCP_CONF_FAILURE 0x12 5379#define SLI4_FC_LOCAL_REJECT_ILLEGAL_LENGTH 0x13 5380#define SLI4_FC_LOCAL_REJECT_UNSUPPORTED_FEATURE 0x14 5381#define SLI4_FC_LOCAL_REJECT_ABORT_IN_PROGRESS 0x15 5382#define SLI4_FC_LOCAL_REJECT_ABORT_REQUESTED 0x16 5383#define SLI4_FC_LOCAL_REJECT_RCV_BUFFER_TIMEOUT 0x17 5384#define SLI4_FC_LOCAL_REJECT_LOOP_OPEN_FAILURE 0x18 5385#define SLI4_FC_LOCAL_REJECT_LINK_DOWN 0x1a 5386#define SLI4_FC_LOCAL_REJECT_CORRUPTED_DATA 0x1b 5387#define SLI4_FC_LOCAL_REJECT_CORRUPTED_RPI 0x1c 5388#define SLI4_FC_LOCAL_REJECT_OUT_OF_ORDER_DATA 0x1d 5389#define SLI4_FC_LOCAL_REJECT_OUT_OF_ORDER_ACK 0x1e 5390#define SLI4_FC_LOCAL_REJECT_DUP_FRAME 0x1f 5391#define SLI4_FC_LOCAL_REJECT_LINK_CONTROL_FRAME 0x20 5392#define SLI4_FC_LOCAL_REJECT_BAD_HOST_ADDRESS 0x21 5393#define SLI4_FC_LOCAL_REJECT_MISSING_HDR_BUFFER 0x23 5394#define SLI4_FC_LOCAL_REJECT_MSEQ_CHAIN_CORRUPTED 0x24 5395#define SLI4_FC_LOCAL_REJECT_ABORTMULT_REQUESTED 0x25 5396#define SLI4_FC_LOCAL_REJECT_BUFFER_SHORTAGE 0x28 5397#define SLI4_FC_LOCAL_REJECT_RCV_XRIBUF_WAITING 0x29 5398#define SLI4_FC_LOCAL_REJECT_INVALID_VPI 0x2e 5399#define SLI4_FC_LOCAL_REJECT_MISSING_XRIBUF 0x30 5400#define SLI4_FC_LOCAL_REJECT_INVALID_RELOFFSET 0x40 5401#define SLI4_FC_LOCAL_REJECT_MISSING_RELOFFSET 0x41 5402#define SLI4_FC_LOCAL_REJECT_INSUFF_BUFFERSPACE 0x42 5403#define SLI4_FC_LOCAL_REJECT_MISSING_SI 0x43 5404#define SLI4_FC_LOCAL_REJECT_MISSING_ES 0x44 5405#define SLI4_FC_LOCAL_REJECT_INCOMPLETE_XFER 0x45 5406#define SLI4_FC_LOCAL_REJECT_SLER_FAILURE 0x46 5407#define SLI4_FC_LOCAL_REJECT_SLER_CMD_RCV_FAILURE 0x47 5408#define SLI4_FC_LOCAL_REJECT_SLER_REC_RJT_ERR 0x48 5409#define SLI4_FC_LOCAL_REJECT_SLER_REC_SRR_RETRY_ERR 0x49 5410#define SLI4_FC_LOCAL_REJECT_SLER_SRR_RJT_ERR 0x4a 5411#define SLI4_FC_LOCAL_REJECT_SLER_RRQ_RJT_ERR 0x4c 5412#define SLI4_FC_LOCAL_REJECT_SLER_RRQ_RETRY_ERR 0x4d 5413#define SLI4_FC_LOCAL_REJECT_SLER_ABTS_ERR 0x4e 5414 5415typedef struct sli4_fc_async_rcqe_s { 5416#if BYTE_ORDER == LITTLE_ENDIAN 5417 uint32_t :8, 5418 status:8, 5419 rq_element_index:12, 5420 :4; 5421 uint32_t rsvd1; 5422 uint32_t fcfi:6, 5423 rq_id:10, 5424 payload_data_placement_length:16; 5425 uint32_t sof_byte:8, 5426 eof_byte:8, 5427 code:8, 5428 header_data_placement_length:6, 5429 :1, 5430 vld:1; 5431#else 5432#error big endian version not defined 5433#endif 5434} sli4_fc_async_rcqe_t; 5435 5436typedef struct sli4_fc_async_rcqe_v1_s { 5437#if BYTE_ORDER == LITTLE_ENDIAN 5438 uint32_t :8, 5439 status:8, 5440 rq_element_index:12, 5441 :4; 5442 uint32_t fcfi:6, 5443 :26; 5444 uint32_t rq_id:16, 5445 payload_data_placement_length:16; 5446 uint32_t sof_byte:8, 5447 eof_byte:8, 5448 code:8, 5449 header_data_placement_length:6, 5450 :1, 5451 vld:1; 5452#else 5453#error big endian version not defined 5454#endif 5455} sli4_fc_async_rcqe_v1_t; 5456 5457#define SLI4_FC_ASYNC_RQ_SUCCESS 0x10 5458#define SLI4_FC_ASYNC_RQ_BUF_LEN_EXCEEDED 0x11 5459#define SLI4_FC_ASYNC_RQ_INSUFF_BUF_NEEDED 0x12 5460#define SLI4_FC_ASYNC_RQ_INSUFF_BUF_FRM_DISC 0x13 5461#define SLI4_FC_ASYNC_RQ_DMA_FAILURE 0x14 5462 5463typedef struct sli4_fc_coalescing_rcqe_s { 5464#if BYTE_ORDER == LITTLE_ENDIAN 5465 uint32_t :8, 5466 status:8, 5467 rq_element_index:12, 5468 :4; 5469 uint32_t rsvd1; 5470 uint32_t rq_id:16, 5471 sequence_reporting_placement_length:16; 5472 uint32_t :16, 5473 code:8, 5474 :7, 5475 vld:1; 5476#else 5477#error big endian version not defined 5478#endif 5479} sli4_fc_coalescing_rcqe_t; 5480 5481#define SLI4_FC_COALESCE_RQ_SUCCESS 0x10 5482#define SLI4_FC_COALESCE_RQ_INSUFF_XRI_NEEDED 0x18 5483 5484typedef struct sli4_fc_optimized_write_cmd_cqe_s { 5485#if BYTE_ORDER == LITTLE_ENDIAN 5486 uint32_t :8, 5487 status:8, 5488 rq_element_index:15, 5489 iv:1; 5490 uint32_t fcfi:6, 5491 :8, 5492 oox:1, 5493 agxr:1, 5494 xri:16; 5495 uint32_t rq_id:16, 5496 payload_data_placement_length:16; 5497 uint32_t rpi:16, 5498 code:8, 5499 header_data_placement_length:6, 5500 :1, 5501 vld:1; 5502#else 5503#error big endian version not defined 5504#endif 5505} sli4_fc_optimized_write_cmd_cqe_t; 5506 5507typedef struct sli4_fc_optimized_write_data_cqe_s { 5508#if BYTE_ORDER == LITTLE_ENDIAN 5509 uint32_t hw_status:8, 5510 status:8, 5511 xri:16; 5512 uint32_t total_data_placed; 5513 uint32_t extended_status; 5514 uint32_t :16, 5515 code:8, 5516 pri:3, 5517 pv:1, 5518 xb:1, 5519 rha:1, 5520 :1, 5521 vld:1; 5522#else 5523#error big endian version not defined 5524#endif 5525} sli4_fc_optimized_write_data_cqe_t; 5526 5527typedef struct sli4_fc_xri_aborted_cqe_s { 5528#if BYTE_ORDER == LITTLE_ENDIAN 5529 uint32_t :8, 5530 status:8, 5531 :16; 5532 uint32_t extended_status; 5533 uint32_t xri:16, 5534 remote_xid:16; 5535 uint32_t :16, 5536 code:8, 5537 xr:1, 5538 :3, 5539 eo:1, 5540 br:1, 5541 ia:1, 5542 vld:1; 5543#else 5544#error big endian version not defined 5545#endif 5546} sli4_fc_xri_aborted_cqe_t; 5547 5548/** 5549 * Code definitions applicable to all FC/FCoE CQE types. 5550 */ 5551#define SLI4_CQE_CODE_OFFSET 14 5552 5553#define SLI4_CQE_CODE_WORK_REQUEST_COMPLETION 0x01 5554#define SLI4_CQE_CODE_RELEASE_WQE 0x02 5555#define SLI4_CQE_CODE_RQ_ASYNC 0x04 5556#define SLI4_CQE_CODE_XRI_ABORTED 0x05 5557#define SLI4_CQE_CODE_RQ_COALESCING 0x06 5558#define SLI4_CQE_CODE_RQ_CONSUMPTION 0x07 5559#define SLI4_CQE_CODE_MEASUREMENT_REPORTING 0x08 5560#define SLI4_CQE_CODE_RQ_ASYNC_V1 0x09 5561#define SLI4_CQE_CODE_OPTIMIZED_WRITE_CMD 0x0B 5562#define SLI4_CQE_CODE_OPTIMIZED_WRITE_DATA 0x0C 5563 5564extern int32_t sli_fc_process_link_state(sli4_t *, void *); 5565extern int32_t sli_fc_process_link_attention(sli4_t *, void *); 5566extern int32_t sli_fc_cqe_parse(sli4_t *, sli4_queue_t *, uint8_t *, sli4_qentry_e *, uint16_t *); 5567extern uint32_t sli_fc_response_length(sli4_t *, uint8_t *); 5568extern uint32_t sli_fc_io_length(sli4_t *, uint8_t *); 5569extern int32_t sli_fc_els_did(sli4_t *, uint8_t *, uint32_t *); 5570extern uint32_t sli_fc_ext_status(sli4_t *, uint8_t *); 5571extern int32_t sli_fc_rqe_rqid_and_index(sli4_t *, uint8_t *, uint16_t *, uint32_t *); 5572extern int32_t sli_fc_process_fcoe(sli4_t *, void *); 5573extern int32_t sli_cmd_fcoe_wq_create(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t); 5574extern int32_t sli_cmd_fcoe_wq_create_v1(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t); 5575extern int32_t sli_cmd_fcoe_wq_destroy(sli4_t *, void *, size_t, uint16_t); 5576extern int32_t sli_cmd_fcoe_post_sgl_pages(sli4_t *, void *, size_t, uint16_t, uint32_t, ocs_dma_t **, ocs_dma_t **, 5577ocs_dma_t *); 5578extern int32_t sli_cmd_fcoe_rq_create(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t); 5579extern int32_t sli_cmd_fcoe_rq_create_v1(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t); 5580extern int32_t sli_cmd_fcoe_rq_destroy(sli4_t *, void *, size_t, uint16_t); 5581extern int32_t sli_cmd_fcoe_read_fcf_table(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t); 5582extern int32_t sli_cmd_fcoe_post_hdr_templates(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, ocs_dma_t *); 5583extern int32_t sli_cmd_fcoe_rediscover_fcf(sli4_t *, void *, size_t, uint16_t); 5584extern int32_t sli_fc_rq_alloc(sli4_t *, sli4_queue_t *, uint32_t, uint32_t, sli4_queue_t *, uint16_t, uint8_t); 5585extern int32_t sli_fc_rq_set_alloc(sli4_t *, uint32_t, sli4_queue_t *[], uint32_t, uint32_t, uint32_t, uint32_t, uint16_t); 5586extern uint32_t sli_fc_get_rpi_requirements(sli4_t *, uint32_t); 5587extern int32_t sli_abort_wqe(sli4_t *, void *, size_t, sli4_abort_type_e, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t); 5588 5589extern int32_t sli_els_request64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint8_t, uint32_t, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *); 5590extern int32_t sli_fcp_iread64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t); 5591extern int32_t sli_fcp_iwrite64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t); 5592extern int32_t sli_fcp_icmnd64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t); 5593 5594extern int32_t sli_fcp_treceive64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t); 5595extern int32_t sli_fcp_trsp64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint32_t); 5596extern int32_t sli_fcp_tsend64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t); 5597extern int32_t sli_fcp_cont_treceive64_wqe(sli4_t *, void*, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t); 5598extern int32_t sli_gen_request64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t,uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t); 5599extern int32_t sli_send_frame_wqe(sli4_t *sli4, void *buf, size_t size, uint8_t sof, uint8_t eof, uint32_t *hdr, 5600 ocs_dma_t *payload, uint32_t req_len, uint8_t timeout, 5601 uint16_t xri, uint16_t req_tag); 5602extern int32_t sli_xmit_sequence64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t); 5603extern int32_t sli_xmit_bcast64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t); 5604extern int32_t sli_xmit_bls_rsp64_wqe(sli4_t *, void *, size_t, sli_bls_payload_t *, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint32_t); 5605extern int32_t sli_xmit_els_rsp64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint32_t, uint32_t); 5606extern int32_t sli_requeue_xri_wqe(sli4_t *, void *, size_t, uint16_t, uint16_t, uint16_t); 5607extern void sli4_cmd_lowlevel_set_watchdog(sli4_t *sli4, void *buf, size_t size, uint16_t timeout); 5608extern bool sli_persist_topology_enabled(sli4_t *sli4); 5609 5610 5611/** 5612 * @ingroup sli_fc 5613 * @brief Retrieve the received header and payload length. 5614 * 5615 * @param sli4 SLI context. 5616 * @param cqe Pointer to the CQ entry. 5617 * @param len_hdr Pointer where the header length is written. 5618 * @param len_data Pointer where the payload length is written. 5619 * 5620 * @return Returns 0 on success, or a non-zero value on failure. 5621 */ 5622static inline int32_t 5623sli_fc_rqe_length(sli4_t *sli4, void *cqe, uint32_t *len_hdr, uint32_t *len_data) 5624{ 5625 sli4_fc_async_rcqe_t *rcqe = cqe; 5626 5627 *len_hdr = *len_data = 0; 5628 5629 if (SLI4_FC_ASYNC_RQ_SUCCESS == rcqe->status) { 5630 *len_hdr = rcqe->header_data_placement_length; 5631 *len_data = rcqe->payload_data_placement_length; 5632 return 0; 5633 } else { 5634 return -1; 5635 } 5636} 5637 5638/** 5639 * @ingroup sli_fc 5640 * @brief Retrieve the received FCFI. 5641 * 5642 * @param sli4 SLI context. 5643 * @param cqe Pointer to the CQ entry. 5644 * 5645 * @return Returns the FCFI in the CQE. or UINT8_MAX if invalid CQE code. 5646 */ 5647static inline uint8_t 5648sli_fc_rqe_fcfi(sli4_t *sli4, void *cqe) 5649{ 5650 uint8_t code = ((uint8_t*)cqe)[SLI4_CQE_CODE_OFFSET]; 5651 uint8_t fcfi = UINT8_MAX; 5652 5653 switch(code) { 5654 case SLI4_CQE_CODE_RQ_ASYNC: { 5655 sli4_fc_async_rcqe_t *rcqe = cqe; 5656 fcfi = rcqe->fcfi; 5657 break; 5658 } 5659 case SLI4_CQE_CODE_RQ_ASYNC_V1: { 5660 sli4_fc_async_rcqe_v1_t *rcqev1 = cqe; 5661 fcfi = rcqev1->fcfi; 5662 break; 5663 } 5664 case SLI4_CQE_CODE_OPTIMIZED_WRITE_CMD: { 5665 sli4_fc_optimized_write_cmd_cqe_t *opt_wr = cqe; 5666 fcfi = opt_wr->fcfi; 5667 break; 5668 } 5669 } 5670 5671 return fcfi; 5672} 5673 5674extern const char *sli_fc_get_status_string(uint32_t status); 5675 5676#endif /* !_SLI4_H */ 5677