1/*- 2 * Copyright (C) 2012-2016 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/param.h> 28#include <sys/systm.h> 29#include <sys/buf.h> 30#include <sys/bus.h> 31#include <sys/conf.h> 32#include <sys/proc.h> 33#include <sys/smp.h> 34#include <vm/vm.h> 35 36#include <dev/pci/pcireg.h> 37#include <dev/pci/pcivar.h> 38 39#include "nvme_private.h" 40 41static int nvme_pci_probe(device_t); 42static int nvme_pci_attach(device_t); 43static int nvme_pci_detach(device_t); 44static int nvme_pci_suspend(device_t); 45static int nvme_pci_resume(device_t); 46 47static int nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr); 48 49static device_method_t nvme_pci_methods[] = { 50 /* Device interface */ 51 DEVMETHOD(device_probe, nvme_pci_probe), 52 DEVMETHOD(device_attach, nvme_pci_attach), 53 DEVMETHOD(device_detach, nvme_pci_detach), 54 DEVMETHOD(device_suspend, nvme_pci_suspend), 55 DEVMETHOD(device_resume, nvme_pci_resume), 56 DEVMETHOD(device_shutdown, nvme_shutdown), 57 { 0, 0 } 58}; 59 60static driver_t nvme_pci_driver = { 61 "nvme", 62 nvme_pci_methods, 63 sizeof(struct nvme_controller), 64}; 65 66DRIVER_MODULE(nvme, pci, nvme_pci_driver, NULL, NULL); 67 68static struct _pcsid 69{ 70 uint32_t devid; 71 int match_subdevice; 72 uint16_t subdevice; 73 const char *desc; 74 uint32_t quirks; 75} pci_ids[] = { 76 { 0x01118086, 0, 0, "NVMe Controller" }, 77 { IDT32_PCI_ID, 0, 0, "IDT NVMe Controller (32 channel)" }, 78 { IDT8_PCI_ID, 0, 0, "IDT NVMe Controller (8 channel)" }, 79 { 0x09538086, 1, 0x3702, "DC P3700 SSD" }, 80 { 0x09538086, 1, 0x3703, "DC P3700 SSD [2.5\" SFF]" }, 81 { 0x09538086, 1, 0x3704, "DC P3500 SSD [Add-in Card]" }, 82 { 0x09538086, 1, 0x3705, "DC P3500 SSD [2.5\" SFF]" }, 83 { 0x09538086, 1, 0x3709, "DC P3600 SSD [Add-in Card]" }, 84 { 0x09538086, 1, 0x370a, "DC P3600 SSD [2.5\" SFF]" }, 85 { 0x09538086, 0, 0, "Intel DC PC3500", QUIRK_INTEL_ALIGNMENT }, 86 { 0x0a538086, 0, 0, "Intel DC PC3520", QUIRK_INTEL_ALIGNMENT }, 87 { 0x0a548086, 0, 0, "Intel DC PC4500", QUIRK_INTEL_ALIGNMENT }, 88 { 0x0a558086, 0, 0, "Dell Intel P4600", QUIRK_INTEL_ALIGNMENT }, 89 { 0x00031c58, 0, 0, "HGST SN100", QUIRK_DELAY_B4_CHK_RDY }, 90 { 0x00231c58, 0, 0, "WDC SN200", QUIRK_DELAY_B4_CHK_RDY }, 91 { 0x05401c5f, 0, 0, "Memblaze Pblaze4", QUIRK_DELAY_B4_CHK_RDY }, 92 { 0xa821144d, 0, 0, "Samsung PM1725", QUIRK_DELAY_B4_CHK_RDY }, 93 { 0xa822144d, 0, 0, "Samsung PM1725a", QUIRK_DELAY_B4_CHK_RDY }, 94 { 0x07f015ad, 0, 0, "VMware NVMe Controller" }, 95 { 0x2003106b, 0, 0, "Apple S3X NVMe Controller" }, 96 { 0x00000000, 0, 0, NULL } 97}; 98 99static int 100nvme_match(uint32_t devid, uint16_t subdevice, struct _pcsid *ep) 101{ 102 if (devid != ep->devid) 103 return 0; 104 105 if (!ep->match_subdevice) 106 return 1; 107 108 if (subdevice == ep->subdevice) 109 return 1; 110 else 111 return 0; 112} 113 114static int 115nvme_pci_probe (device_t device) 116{ 117 struct nvme_controller *ctrlr = DEVICE2SOFTC(device); 118 struct _pcsid *ep; 119 uint32_t devid; 120 uint16_t subdevice; 121 122 devid = pci_get_devid(device); 123 subdevice = pci_get_subdevice(device); 124 ep = pci_ids; 125 126 while (ep->devid) { 127 if (nvme_match(devid, subdevice, ep)) 128 break; 129 ++ep; 130 } 131 if (ep->devid) 132 ctrlr->quirks = ep->quirks; 133 134 if (ep->desc) { 135 device_set_desc(device, ep->desc); 136 return (BUS_PROBE_DEFAULT); 137 } 138 139#if defined(PCIS_STORAGE_NVM) 140 if (pci_get_class(device) == PCIC_STORAGE && 141 pci_get_subclass(device) == PCIS_STORAGE_NVM && 142 pci_get_progif(device) == PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0) { 143 device_set_desc(device, "Generic NVMe Device"); 144 return (BUS_PROBE_GENERIC); 145 } 146#endif 147 148 return (ENXIO); 149} 150 151static int 152nvme_ctrlr_allocate_bar(struct nvme_controller *ctrlr) 153{ 154 155 ctrlr->resource_id = PCIR_BAR(0); 156 157 ctrlr->resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY, 158 &ctrlr->resource_id, RF_ACTIVE); 159 160 if(ctrlr->resource == NULL) { 161 nvme_printf(ctrlr, "unable to allocate pci resource\n"); 162 return (ENOMEM); 163 } 164 165 ctrlr->bus_tag = rman_get_bustag(ctrlr->resource); 166 ctrlr->bus_handle = rman_get_bushandle(ctrlr->resource); 167 ctrlr->regs = (struct nvme_registers *)ctrlr->bus_handle; 168 169 /* 170 * The NVMe spec allows for the MSI-X table to be placed behind 171 * BAR 4/5, separate from the control/doorbell registers. Always 172 * try to map this bar, because it must be mapped prior to calling 173 * pci_alloc_msix(). If the table isn't behind BAR 4/5, 174 * bus_alloc_resource() will just return NULL which is OK. 175 */ 176 ctrlr->bar4_resource_id = PCIR_BAR(4); 177 ctrlr->bar4_resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY, 178 &ctrlr->bar4_resource_id, RF_ACTIVE); 179 180 return (0); 181} 182 183static int 184nvme_pci_attach(device_t dev) 185{ 186 struct nvme_controller*ctrlr = DEVICE2SOFTC(dev); 187 int status; 188 189 ctrlr->dev = dev; 190 status = nvme_ctrlr_allocate_bar(ctrlr); 191 if (status != 0) 192 goto bad; 193 pci_enable_busmaster(dev); 194 status = nvme_ctrlr_setup_interrupts(ctrlr); 195 if (status != 0) 196 goto bad; 197 return nvme_attach(dev); 198bad: 199 if (ctrlr->resource != NULL) { 200 bus_release_resource(dev, SYS_RES_MEMORY, 201 ctrlr->resource_id, ctrlr->resource); 202 } 203 204 if (ctrlr->bar4_resource != NULL) { 205 bus_release_resource(dev, SYS_RES_MEMORY, 206 ctrlr->bar4_resource_id, ctrlr->bar4_resource); 207 } 208 209 if (ctrlr->tag) 210 bus_teardown_intr(dev, ctrlr->res, ctrlr->tag); 211 212 if (ctrlr->res) 213 bus_release_resource(dev, SYS_RES_IRQ, 214 rman_get_rid(ctrlr->res), ctrlr->res); 215 216 if (ctrlr->msi_count > 0) 217 pci_release_msi(dev); 218 219 return status; 220} 221 222static int 223nvme_pci_detach(device_t dev) 224{ 225 struct nvme_controller*ctrlr = DEVICE2SOFTC(dev); 226 int rv; 227 228 rv = nvme_detach(dev); 229 if (ctrlr->msi_count > 0) 230 pci_release_msi(dev); 231 pci_disable_busmaster(dev); 232 return (rv); 233} 234 235static int 236nvme_ctrlr_setup_shared(struct nvme_controller *ctrlr, int rid) 237{ 238 int error; 239 240 ctrlr->num_io_queues = 1; 241 ctrlr->rid = rid; 242 ctrlr->res = bus_alloc_resource_any(ctrlr->dev, SYS_RES_IRQ, 243 &ctrlr->rid, RF_SHAREABLE | RF_ACTIVE); 244 if (ctrlr->res == NULL) { 245 nvme_printf(ctrlr, "unable to allocate shared interrupt\n"); 246 return (ENOMEM); 247 } 248 249 error = bus_setup_intr(ctrlr->dev, ctrlr->res, 250 INTR_TYPE_MISC | INTR_MPSAFE, NULL, nvme_ctrlr_shared_handler, 251 ctrlr, &ctrlr->tag); 252 if (error) { 253 nvme_printf(ctrlr, "unable to setup shared interrupt\n"); 254 return (error); 255 } 256 257 return (0); 258} 259 260static int 261nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr) 262{ 263 device_t dev; 264 int force_intx, num_io_queues, per_cpu_io_queues; 265 int min_cpus_per_ioq; 266 int num_vectors_requested; 267 268 dev = ctrlr->dev; 269 270 force_intx = 0; 271 TUNABLE_INT_FETCH("hw.nvme.force_intx", &force_intx); 272 if (force_intx) 273 return (nvme_ctrlr_setup_shared(ctrlr, 0)); 274 275 if (pci_msix_count(dev) == 0) 276 goto msi; 277 278 /* 279 * Try to allocate one MSI-X per core for I/O queues, plus one 280 * for admin queue, but accept single shared MSI-X if have to. 281 * Fall back to MSI if can't get any MSI-X. 282 */ 283 num_io_queues = mp_ncpus; 284 TUNABLE_INT_FETCH("hw.nvme.num_io_queues", &num_io_queues); 285 if (num_io_queues < 1 || num_io_queues > mp_ncpus) 286 num_io_queues = mp_ncpus; 287 288 per_cpu_io_queues = 1; 289 TUNABLE_INT_FETCH("hw.nvme.per_cpu_io_queues", &per_cpu_io_queues); 290 if (per_cpu_io_queues == 0) 291 num_io_queues = 1; 292 293 min_cpus_per_ioq = smp_threads_per_core; 294 TUNABLE_INT_FETCH("hw.nvme.min_cpus_per_ioq", &min_cpus_per_ioq); 295 if (min_cpus_per_ioq > 1) { 296 num_io_queues = min(num_io_queues, 297 max(1, mp_ncpus / min_cpus_per_ioq)); 298 } 299 300 num_io_queues = min(num_io_queues, max(1, pci_msix_count(dev) - 1)); 301 302again: 303 if (num_io_queues > vm_ndomains) 304 num_io_queues -= num_io_queues % vm_ndomains; 305 num_vectors_requested = min(num_io_queues + 1, pci_msix_count(dev)); 306 ctrlr->msi_count = num_vectors_requested; 307 if (pci_alloc_msix(dev, &ctrlr->msi_count) != 0) { 308 nvme_printf(ctrlr, "unable to allocate MSI-X\n"); 309 ctrlr->msi_count = 0; 310 goto msi; 311 } 312 if (ctrlr->msi_count == 1) 313 return (nvme_ctrlr_setup_shared(ctrlr, 1)); 314 if (ctrlr->msi_count != num_vectors_requested) { 315 pci_release_msi(dev); 316 num_io_queues = ctrlr->msi_count - 1; 317 goto again; 318 } 319 320 ctrlr->num_io_queues = num_io_queues; 321 return (0); 322 323msi: 324 /* 325 * Try to allocate 2 MSIs (admin and I/O queues), but accept single 326 * shared if have to. Fall back to INTx if can't get any MSI. 327 */ 328 ctrlr->msi_count = min(pci_msi_count(dev), 2); 329 if (ctrlr->msi_count > 0) { 330 if (pci_alloc_msi(dev, &ctrlr->msi_count) != 0) { 331 nvme_printf(ctrlr, "unable to allocate MSI\n"); 332 ctrlr->msi_count = 0; 333 } else if (ctrlr->msi_count == 2) { 334 ctrlr->num_io_queues = 1; 335 return (0); 336 } 337 } 338 return (nvme_ctrlr_setup_shared(ctrlr, ctrlr->msi_count > 0 ? 1 : 0)); 339} 340 341static int 342nvme_pci_suspend(device_t dev) 343{ 344 struct nvme_controller *ctrlr; 345 346 ctrlr = DEVICE2SOFTC(dev); 347 return (nvme_ctrlr_suspend(ctrlr)); 348} 349 350static int 351nvme_pci_resume(device_t dev) 352{ 353 struct nvme_controller *ctrlr; 354 355 ctrlr = DEVICE2SOFTC(dev); 356 return (nvme_ctrlr_resume(ctrlr)); 357} 358