1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (C) 2012-2013 Intel Corporation
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#ifndef __NVME_H__
30#define __NVME_H__
31
32#ifdef _KERNEL
33#include <sys/types.h>
34#endif
35
36#include <sys/param.h>
37#include <sys/endian.h>
38
39#define	NVME_PASSTHROUGH_CMD		_IOWR('n', 0, struct nvme_pt_command)
40#define	NVME_RESET_CONTROLLER		_IO('n', 1)
41#define	NVME_GET_NSID			_IOR('n', 2, struct nvme_get_nsid)
42#define	NVME_GET_MAX_XFER_SIZE		_IOR('n', 3, uint64_t)
43
44#define	NVME_IO_TEST			_IOWR('n', 100, struct nvme_io_test)
45#define	NVME_BIO_TEST			_IOWR('n', 101, struct nvme_io_test)
46
47/* NB: Fabrics-specific ioctls defined in nvmf.h start at 200. */
48
49/*
50 * Macros to deal with NVME revisions, as defined VS register
51 */
52#define NVME_REV(x, y)			(((x) << 16) | ((y) << 8))
53#define NVME_MAJOR(r)			(((r) >> 16) & 0xffff)
54#define NVME_MINOR(r)			(((r) >> 8) & 0xff)
55
56/*
57 * Use to mark a command to apply to all namespaces, or to retrieve global
58 *  log pages.
59 */
60#define NVME_GLOBAL_NAMESPACE_TAG	((uint32_t)0xFFFFFFFF)
61
62/* Host memory buffer sizes are always in 4096 byte chunks */
63#define	NVME_HMB_UNITS			4096
64
65/* Many items are expressed in terms of power of two times MPS */
66#define NVME_MPS_SHIFT			12
67
68/* Limits on queue sizes: See 4.1.3 Queue Size in NVMe 1.4b. */
69#define NVME_MIN_ADMIN_ENTRIES		2
70#define NVME_MAX_ADMIN_ENTRIES		4096
71
72#define NVME_MIN_IO_ENTRIES		2
73#define NVME_MAX_IO_ENTRIES		65536
74
75/* Register field definitions */
76#define NVME_CAP_LO_REG_MQES_SHIFT			(0)
77#define NVME_CAP_LO_REG_MQES_MASK			(0xFFFF)
78#define NVME_CAP_LO_REG_CQR_SHIFT			(16)
79#define NVME_CAP_LO_REG_CQR_MASK			(0x1)
80#define NVME_CAP_LO_REG_AMS_SHIFT			(17)
81#define NVME_CAP_LO_REG_AMS_MASK			(0x3)
82#define NVME_CAP_LO_REG_TO_SHIFT			(24)
83#define NVME_CAP_LO_REG_TO_MASK				(0xFF)
84#define NVME_CAP_LO_MQES(x) \
85	NVMEV(NVME_CAP_LO_REG_MQES, x)
86#define NVME_CAP_LO_CQR(x) \
87	NVMEV(NVME_CAP_LO_REG_CQR, x)
88#define NVME_CAP_LO_AMS(x) \
89	NVMEV(NVME_CAP_LO_REG_AMS, x)
90#define NVME_CAP_LO_TO(x) \
91	NVMEV(NVME_CAP_LO_REG_TO, x)
92
93#define NVME_CAP_HI_REG_DSTRD_SHIFT			(0)
94#define NVME_CAP_HI_REG_DSTRD_MASK			(0xF)
95#define NVME_CAP_HI_REG_NSSRS_SHIFT			(4)
96#define NVME_CAP_HI_REG_NSSRS_MASK			(0x1)
97#define NVME_CAP_HI_REG_CSS_SHIFT			(5)
98#define NVME_CAP_HI_REG_CSS_MASK			(0xff)
99#define NVME_CAP_HI_REG_CSS_NVM_SHIFT			(5)
100#define NVME_CAP_HI_REG_CSS_NVM_MASK			(0x1)
101#define NVME_CAP_HI_REG_BPS_SHIFT			(13)
102#define NVME_CAP_HI_REG_BPS_MASK			(0x1)
103#define NVME_CAP_HI_REG_CPS_SHIFT			(14)
104#define NVME_CAP_HI_REG_CPS_MASK			(0x3)
105#define NVME_CAP_HI_REG_MPSMIN_SHIFT			(16)
106#define NVME_CAP_HI_REG_MPSMIN_MASK			(0xF)
107#define NVME_CAP_HI_REG_MPSMAX_SHIFT			(20)
108#define NVME_CAP_HI_REG_MPSMAX_MASK			(0xF)
109#define NVME_CAP_HI_REG_PMRS_SHIFT			(24)
110#define NVME_CAP_HI_REG_PMRS_MASK			(0x1)
111#define NVME_CAP_HI_REG_CMBS_SHIFT			(25)
112#define NVME_CAP_HI_REG_CMBS_MASK			(0x1)
113#define NVME_CAP_HI_REG_NSSS_SHIFT			(26)
114#define NVME_CAP_HI_REG_NSSS_MASK			(0x1)
115#define NVME_CAP_HI_REG_CRWMS_SHIFT			(27)
116#define NVME_CAP_HI_REG_CRWMS_MASK			(0x1)
117#define NVME_CAP_HI_REG_CRIMS_SHIFT			(28)
118#define NVME_CAP_HI_REG_CRIMS_MASK			(0x1)
119#define NVME_CAP_HI_DSTRD(x) \
120	NVMEV(NVME_CAP_HI_REG_DSTRD, x)
121#define NVME_CAP_HI_NSSRS(x) \
122	NVMEV(NVME_CAP_HI_REG_NSSRS, x)
123#define NVME_CAP_HI_CSS(x) \
124	NVMEV(NVME_CAP_HI_REG_CSS, x)
125#define NVME_CAP_HI_CSS_NVM(x) \
126	NVMEV(NVME_CAP_HI_REG_CSS_NVM, x)
127#define NVME_CAP_HI_BPS(x) \
128	NVMEV(NVME_CAP_HI_REG_BPS, x)
129#define NVME_CAP_HI_CPS(x) \
130	NVMEV(NVME_CAP_HI_REG_CPS, x)
131#define NVME_CAP_HI_MPSMIN(x) \
132	NVMEV(NVME_CAP_HI_REG_MPSMIN, x)
133#define NVME_CAP_HI_MPSMAX(x) \
134	NVMEV(NVME_CAP_HI_REG_MPSMAX, x)
135#define NVME_CAP_HI_PMRS(x) \
136	NVMEV(NVME_CAP_HI_REG_PMRS, x)
137#define NVME_CAP_HI_CMBS(x) \
138	NVMEV(NVME_CAP_HI_REG_CMBS, x)
139#define NVME_CAP_HI_NSSS(x) \
140	NVMEV(NVME_CAP_HI_REG_NSSS, x)
141#define NVME_CAP_HI_CRWMS(x) \
142	NVMEV(NVME_CAP_HI_REG_CRWMS, x)
143#define NVME_CAP_HI_CRIMS(x) \
144	NVMEV(NVME_CAP_HI_REG_CRIMS, x)
145
146#define NVME_CC_REG_EN_SHIFT				(0)
147#define NVME_CC_REG_EN_MASK				(0x1)
148#define NVME_CC_REG_CSS_SHIFT				(4)
149#define NVME_CC_REG_CSS_MASK				(0x7)
150#define NVME_CC_REG_MPS_SHIFT				(7)
151#define NVME_CC_REG_MPS_MASK				(0xF)
152#define NVME_CC_REG_AMS_SHIFT				(11)
153#define NVME_CC_REG_AMS_MASK				(0x7)
154#define NVME_CC_REG_SHN_SHIFT				(14)
155#define NVME_CC_REG_SHN_MASK				(0x3)
156#define NVME_CC_REG_IOSQES_SHIFT			(16)
157#define NVME_CC_REG_IOSQES_MASK				(0xF)
158#define NVME_CC_REG_IOCQES_SHIFT			(20)
159#define NVME_CC_REG_IOCQES_MASK				(0xF)
160#define NVME_CC_REG_CRIME_SHIFT				(24)
161#define NVME_CC_REG_CRIME_MASK				(0x1)
162
163#define NVME_CSTS_REG_RDY_SHIFT				(0)
164#define NVME_CSTS_REG_RDY_MASK				(0x1)
165#define NVME_CSTS_REG_CFS_SHIFT				(1)
166#define NVME_CSTS_REG_CFS_MASK				(0x1)
167#define NVME_CSTS_REG_SHST_SHIFT			(2)
168#define NVME_CSTS_REG_SHST_MASK				(0x3)
169#define NVME_CSTS_REG_NVSRO_SHIFT			(4)
170#define NVME_CSTS_REG_NVSRO_MASK			(0x1)
171#define NVME_CSTS_REG_PP_SHIFT				(5)
172#define NVME_CSTS_REG_PP_MASK				(0x1)
173#define NVME_CSTS_REG_ST_SHIFT				(6)
174#define NVME_CSTS_REG_ST_MASK				(0x1)
175
176#define NVME_CSTS_GET_SHST(csts) \
177	NVMEV(NVME_CSTS_REG_SHST, csts)
178
179#define NVME_AQA_REG_ASQS_SHIFT				(0)
180#define NVME_AQA_REG_ASQS_MASK				(0xFFF)
181#define NVME_AQA_REG_ACQS_SHIFT				(16)
182#define NVME_AQA_REG_ACQS_MASK				(0xFFF)
183
184#define NVME_PMRCAP_REG_RDS_SHIFT			(3)
185#define NVME_PMRCAP_REG_RDS_MASK			(0x1)
186#define NVME_PMRCAP_REG_WDS_SHIFT			(4)
187#define NVME_PMRCAP_REG_WDS_MASK			(0x1)
188#define NVME_PMRCAP_REG_BIR_SHIFT			(5)
189#define NVME_PMRCAP_REG_BIR_MASK			(0x7)
190#define NVME_PMRCAP_REG_PMRTU_SHIFT			(8)
191#define NVME_PMRCAP_REG_PMRTU_MASK			(0x3)
192#define NVME_PMRCAP_REG_PMRWBM_SHIFT			(10)
193#define NVME_PMRCAP_REG_PMRWBM_MASK			(0xf)
194#define NVME_PMRCAP_REG_PMRTO_SHIFT			(16)
195#define NVME_PMRCAP_REG_PMRTO_MASK			(0xff)
196#define NVME_PMRCAP_REG_CMSS_SHIFT			(24)
197#define NVME_PMRCAP_REG_CMSS_MASK			(0x1)
198
199#define NVME_PMRCAP_RDS(x) \
200	NVMEV(NVME_PMRCAP_REG_RDS, x)
201#define NVME_PMRCAP_WDS(x) \
202	NVMEV(NVME_PMRCAP_REG_WDS, x)
203#define NVME_PMRCAP_BIR(x) \
204	NVMEV(NVME_PMRCAP_REG_BIR, x)
205#define NVME_PMRCAP_PMRTU(x) \
206	NVMEV(NVME_PMRCAP_REG_PMRTU, x)
207#define NVME_PMRCAP_PMRWBM(x) \
208	NVMEV(NVME_PMRCAP_REG_PMRWBM, x)
209#define NVME_PMRCAP_PMRTO(x) \
210	NVMEV(NVME_PMRCAP_REG_PMRTO, x)
211#define NVME_PMRCAP_CMSS(x) \
212	NVMEV(NVME_PMRCAP_REG_CMSS, x)
213
214/* Command field definitions */
215
216enum nvme_fuse {
217	NVME_FUSE_NORMAL				= 0x0,
218	NVME_FUSE_FIRST					= 0x1,
219	NVME_FUSE_SECOND				= 0x2
220};
221#define NVME_CMD_FUSE_SHIFT				(0)
222#define NVME_CMD_FUSE_MASK				(0x3)
223
224enum nvme_psdt {
225	NVME_PSDT_PRP					= 0x0,
226	NVME_PSDT_SGL					= 0x1,
227	NVME_PSDT_SGL_MPTR				= 0x2
228};
229#define	NVME_CMD_PSDT_SHIFT				(6)
230#define	NVME_CMD_PSDT_MASK				(0x3)
231
232
233#define NVME_STATUS_P_SHIFT				(0)
234#define NVME_STATUS_P_MASK				(0x1)
235#define NVME_STATUS_SC_SHIFT				(1)
236#define NVME_STATUS_SC_MASK				(0xFF)
237#define NVME_STATUS_SCT_SHIFT				(9)
238#define NVME_STATUS_SCT_MASK				(0x7)
239#define NVME_STATUS_CRD_SHIFT				(12)
240#define NVME_STATUS_CRD_MASK				(0x3)
241#define NVME_STATUS_M_SHIFT				(14)
242#define NVME_STATUS_M_MASK				(0x1)
243#define NVME_STATUS_DNR_SHIFT				(15)
244#define NVME_STATUS_DNR_MASK				(0x1)
245
246#define NVME_STATUS_GET_P(st) \
247	NVMEV(NVME_STATUS_P, st)
248#define NVME_STATUS_GET_SC(st) \
249	NVMEV(NVME_STATUS_SC, st)
250#define NVME_STATUS_GET_SCT(st) \
251	NVMEV(NVME_STATUS_SCT, st)
252#define NVME_STATUS_GET_CRD(st) \
253	NVMEV(NVME_STATUS_CRD, st)
254#define NVME_STATUS_GET_M(st) \
255	NVMEV(NVME_STATUS_M, st)
256#define NVME_STATUS_GET_DNR(st) \
257	NVMEV(NVME_STATUS_DNR, st)
258
259#define NVME_PWR_ST_MPS_SHIFT				(0)
260#define NVME_PWR_ST_MPS_MASK				(0x1)
261#define NVME_PWR_ST_NOPS_SHIFT				(1)
262#define NVME_PWR_ST_NOPS_MASK				(0x1)
263#define NVME_PWR_ST_RRT_SHIFT				(0)
264#define NVME_PWR_ST_RRT_MASK				(0x1F)
265#define NVME_PWR_ST_RRL_SHIFT				(0)
266#define NVME_PWR_ST_RRL_MASK				(0x1F)
267#define NVME_PWR_ST_RWT_SHIFT				(0)
268#define NVME_PWR_ST_RWT_MASK				(0x1F)
269#define NVME_PWR_ST_RWL_SHIFT				(0)
270#define NVME_PWR_ST_RWL_MASK				(0x1F)
271#define NVME_PWR_ST_IPS_SHIFT				(6)
272#define NVME_PWR_ST_IPS_MASK				(0x3)
273#define NVME_PWR_ST_APW_SHIFT				(0)
274#define NVME_PWR_ST_APW_MASK				(0x7)
275#define NVME_PWR_ST_APS_SHIFT				(6)
276#define NVME_PWR_ST_APS_MASK				(0x3)
277
278/** Controller Multi-path I/O and Namespace Sharing Capabilities */
279/* More then one port */
280#define NVME_CTRLR_DATA_MIC_MPORTS_SHIFT		(0)
281#define NVME_CTRLR_DATA_MIC_MPORTS_MASK			(0x1)
282/* More then one controller */
283#define NVME_CTRLR_DATA_MIC_MCTRLRS_SHIFT		(1)
284#define NVME_CTRLR_DATA_MIC_MCTRLRS_MASK		(0x1)
285/* SR-IOV Virtual Function */
286#define NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT		(2)
287#define NVME_CTRLR_DATA_MIC_SRIOVVF_MASK		(0x1)
288/* Asymmetric Namespace Access Reporting */
289#define NVME_CTRLR_DATA_MIC_ANAR_SHIFT			(3)
290#define NVME_CTRLR_DATA_MIC_ANAR_MASK			(0x1)
291
292/** OAES - Optional Asynchronous Events Supported */
293/* supports Namespace Attribute Notices event */
294#define NVME_CTRLR_DATA_OAES_NS_ATTR_SHIFT		(8)
295#define NVME_CTRLR_DATA_OAES_NS_ATTR_MASK		(0x1)
296/* supports Firmware Activation Notices event */
297#define NVME_CTRLR_DATA_OAES_FW_ACTIVATE_SHIFT		(9)
298#define NVME_CTRLR_DATA_OAES_FW_ACTIVATE_MASK		(0x1)
299/* supports Asymmetric Namespace Access Change Notices event */
300#define NVME_CTRLR_DATA_OAES_ASYM_NS_CHANGE_SHIFT	(11)
301#define NVME_CTRLR_DATA_OAES_ASYM_NS_CHANGE_MASK	(0x1)
302/* supports Predictable Latency Event Aggregate Log Change Notices event */
303#define NVME_CTRLR_DATA_OAES_PREDICT_LATENCY_SHIFT	(12)
304#define NVME_CTRLR_DATA_OAES_PREDICT_LATENCY_MASK	(0x1)
305/* supports LBA Status Information Notices event */
306#define NVME_CTRLR_DATA_OAES_LBA_STATUS_SHIFT		(13)
307#define NVME_CTRLR_DATA_OAES_LBA_STATUS_MASK		(0x1)
308/* supports Endurance Group Event Aggregate Log Page Changes Notices event */
309#define NVME_CTRLR_DATA_OAES_ENDURANCE_GROUP_SHIFT	(14)
310#define NVME_CTRLR_DATA_OAES_ENDURANCE_GROUP_MASK	(0x1)
311/* supports Normal NVM Subsystem Shutdown event */
312#define NVME_CTRLR_DATA_OAES_NORMAL_SHUTDOWN_SHIFT	(15)
313#define NVME_CTRLR_DATA_OAES_NORMAL_SHUTDOWN_MASK	(0x1)
314/* supports Zone Descriptor Changed Notices event */
315#define NVME_CTRLR_DATA_OAES_ZONE_DESC_CHANGE_SHIFT	(27)
316#define NVME_CTRLR_DATA_OAES_ZONE_DESC_CHANGE_MASK	(0x1)
317/* supports Discovery Log Page Change Notification event */
318#define NVME_CTRLR_DATA_OAES_LOG_PAGE_CHANGE_SHIFT	(31)
319#define NVME_CTRLR_DATA_OAES_LOG_PAGE_CHANGE_MASK	(0x1)
320
321/** CTRATT - Controller Attributes */
322/* supports 128-bit Host Identifier */
323#define NVME_CTRLR_DATA_CTRATT_128BIT_HOSTID_SHIFT	(0)
324#define NVME_CTRLR_DATA_CTRATT_128BIT_HOSTID_MASK	(0x1)
325/* supports Non-Operational Power State Permissive Mode */
326#define NVME_CTRLR_DATA_CTRATT_NONOP_POWER_STATE_SHIFT	(1)
327#define NVME_CTRLR_DATA_CTRATT_NONOP_POWER_STATE_MASK	(0x1)
328/* supports NVM Sets */
329#define NVME_CTRLR_DATA_CTRATT_NVM_SETS_SHIFT		(2)
330#define NVME_CTRLR_DATA_CTRATT_NVM_SETS_MASK		(0x1)
331/* supports Read Recovery Levels */
332#define NVME_CTRLR_DATA_CTRATT_READ_RECOVERY_LVLS_SHIFT	(3)
333#define NVME_CTRLR_DATA_CTRATT_READ_RECOVERY_LVLS_MASK	(0x1)
334/* supports Endurance Groups */
335#define NVME_CTRLR_DATA_CTRATT_ENDURANCE_GROUPS_SHIFT	(4)
336#define NVME_CTRLR_DATA_CTRATT_ENDURANCE_GROUPS_MASK	(0x1)
337/* supports Predictable Latency Mode */
338#define NVME_CTRLR_DATA_CTRATT_PREDICTABLE_LATENCY_SHIFT (5)
339#define NVME_CTRLR_DATA_CTRATT_PREDICTABLE_LATENCY_MASK	(0x1)
340/* supports Traffic Based Keep Alive Support */
341#define NVME_CTRLR_DATA_CTRATT_TBKAS_SHIFT		(6)
342#define NVME_CTRLR_DATA_CTRATT_TBKAS_MASK		(0x1)
343/* supports Namespace Granularity */
344#define NVME_CTRLR_DATA_CTRATT_NAMESPACE_GRANULARITY_SHIFT (7)
345#define NVME_CTRLR_DATA_CTRATT_NAMESPACE_GRANULARITY_MASK (0x1)
346/* supports SQ Associations */
347#define NVME_CTRLR_DATA_CTRATT_SQ_ASSOCIATIONS_SHIFT	(8)
348#define NVME_CTRLR_DATA_CTRATT_SQ_ASSOCIATIONS_MASK	(0x1)
349/* supports UUID List */
350#define NVME_CTRLR_DATA_CTRATT_UUID_LIST_SHIFT		(9)
351#define NVME_CTRLR_DATA_CTRATT_UUID_LIST_MASK		(0x1)
352
353/** OACS - optional admin command support */
354/* supports security send/receive commands */
355#define NVME_CTRLR_DATA_OACS_SECURITY_SHIFT		(0)
356#define NVME_CTRLR_DATA_OACS_SECURITY_MASK		(0x1)
357/* supports format nvm command */
358#define NVME_CTRLR_DATA_OACS_FORMAT_SHIFT		(1)
359#define NVME_CTRLR_DATA_OACS_FORMAT_MASK		(0x1)
360/* supports firmware activate/download commands */
361#define NVME_CTRLR_DATA_OACS_FIRMWARE_SHIFT		(2)
362#define NVME_CTRLR_DATA_OACS_FIRMWARE_MASK		(0x1)
363/* supports namespace management commands */
364#define NVME_CTRLR_DATA_OACS_NSMGMT_SHIFT		(3)
365#define NVME_CTRLR_DATA_OACS_NSMGMT_MASK		(0x1)
366/* supports Device Self-test command */
367#define NVME_CTRLR_DATA_OACS_SELFTEST_SHIFT		(4)
368#define NVME_CTRLR_DATA_OACS_SELFTEST_MASK		(0x1)
369/* supports Directives */
370#define NVME_CTRLR_DATA_OACS_DIRECTIVES_SHIFT		(5)
371#define NVME_CTRLR_DATA_OACS_DIRECTIVES_MASK		(0x1)
372/* supports NVMe-MI Send/Receive */
373#define NVME_CTRLR_DATA_OACS_NVMEMI_SHIFT		(6)
374#define NVME_CTRLR_DATA_OACS_NVMEMI_MASK		(0x1)
375/* supports Virtualization Management */
376#define NVME_CTRLR_DATA_OACS_VM_SHIFT			(7)
377#define NVME_CTRLR_DATA_OACS_VM_MASK			(0x1)
378/* supports Doorbell Buffer Config */
379#define NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT		(8)
380#define NVME_CTRLR_DATA_OACS_DBBUFFER_MASK		(0x1)
381/* supports Get LBA Status */
382#define NVME_CTRLR_DATA_OACS_GETLBA_SHIFT		(9)
383#define NVME_CTRLR_DATA_OACS_GETLBA_MASK		(0x1)
384
385/** firmware updates */
386/* first slot is read-only */
387#define NVME_CTRLR_DATA_FRMW_SLOT1_RO_SHIFT		(0)
388#define NVME_CTRLR_DATA_FRMW_SLOT1_RO_MASK		(0x1)
389/* number of firmware slots */
390#define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_SHIFT		(1)
391#define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_MASK		(0x7)
392/* firmware activation without reset */
393#define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_SHIFT		(4)
394#define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_MASK		(0x1)
395
396/** log page attributes */
397/* per namespace smart/health log page */
398#define NVME_CTRLR_DATA_LPA_NS_SMART_SHIFT		(0)
399#define NVME_CTRLR_DATA_LPA_NS_SMART_MASK		(0x1)
400/* Commands Supported and Effects log page */
401#define NVME_CTRLR_DATA_LPA_CMD_EFFECTS_SHIFT		(1)
402#define NVME_CTRLR_DATA_LPA_CMD_EFFECTS_MASK		(0x1)
403/* extended data for Get Log Page command */
404#define NVME_CTRLR_DATA_LPA_EXT_DATA_SHIFT		(2)
405#define NVME_CTRLR_DATA_LPA_EXT_DATA_MASK		(0x1)
406/* telemetry */
407#define NVME_CTRLR_DATA_LPA_TELEMETRY_SHIFT		(3)
408#define NVME_CTRLR_DATA_LPA_TELEMETRY_MASK		(0x1)
409/* persistent event */
410#define NVME_CTRLR_DATA_LPA_PERSISTENT_EVENT_SHIFT	(4)
411#define NVME_CTRLR_DATA_LPA_PERSISTENT_EVENT_MASK	(0x1)
412/* Supported log pages, etc */
413#define NVME_CTRLR_DATA_LPA_LOG_PAGES_PAGE_SHIFT	(5)
414#define NVME_CTRLR_DATA_LPA_LOG_PAGES_PAGE_MASK		(0x1)
415/* Data Area 4 for Telemetry */
416#define NVME_CTRLR_DATA_LPA_DA4_TELEMETRY_SHIFT		(6)
417#define NVME_CTRLR_DATA_LPA_DA4_TELEMETRY_MASK		(0x1)
418
419/** AVSCC - admin vendor specific command configuration */
420/* admin vendor specific commands use spec format */
421#define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_SHIFT		(0)
422#define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_MASK		(0x1)
423
424/** Autonomous Power State Transition Attributes */
425/* Autonomous Power State Transitions supported */
426#define NVME_CTRLR_DATA_APSTA_APST_SUPP_SHIFT		(0)
427#define NVME_CTRLR_DATA_APSTA_APST_SUPP_MASK		(0x1)
428
429/** Sanitize Capabilities */
430/* Crypto Erase Support  */
431#define NVME_CTRLR_DATA_SANICAP_CES_SHIFT		(0)
432#define NVME_CTRLR_DATA_SANICAP_CES_MASK		(0x1)
433/* Block Erase Support */
434#define NVME_CTRLR_DATA_SANICAP_BES_SHIFT		(1)
435#define NVME_CTRLR_DATA_SANICAP_BES_MASK		(0x1)
436/* Overwrite Support */
437#define NVME_CTRLR_DATA_SANICAP_OWS_SHIFT		(2)
438#define NVME_CTRLR_DATA_SANICAP_OWS_MASK		(0x1)
439/* No-Deallocate Inhibited  */
440#define NVME_CTRLR_DATA_SANICAP_NDI_SHIFT		(29)
441#define NVME_CTRLR_DATA_SANICAP_NDI_MASK		(0x1)
442/* No-Deallocate Modifies Media After Sanitize */
443#define NVME_CTRLR_DATA_SANICAP_NODMMAS_SHIFT		(30)
444#define NVME_CTRLR_DATA_SANICAP_NODMMAS_MASK		(0x3)
445#define NVME_CTRLR_DATA_SANICAP_NODMMAS_UNDEF		(0)
446#define NVME_CTRLR_DATA_SANICAP_NODMMAS_NO		(1)
447#define NVME_CTRLR_DATA_SANICAP_NODMMAS_YES		(2)
448
449/** submission queue entry size */
450#define NVME_CTRLR_DATA_SQES_MIN_SHIFT			(0)
451#define NVME_CTRLR_DATA_SQES_MIN_MASK			(0xF)
452#define NVME_CTRLR_DATA_SQES_MAX_SHIFT			(4)
453#define NVME_CTRLR_DATA_SQES_MAX_MASK			(0xF)
454
455/** completion queue entry size */
456#define NVME_CTRLR_DATA_CQES_MIN_SHIFT			(0)
457#define NVME_CTRLR_DATA_CQES_MIN_MASK			(0xF)
458#define NVME_CTRLR_DATA_CQES_MAX_SHIFT			(4)
459#define NVME_CTRLR_DATA_CQES_MAX_MASK			(0xF)
460
461/** optional nvm command support */
462#define NVME_CTRLR_DATA_ONCS_COMPARE_SHIFT		(0)
463#define NVME_CTRLR_DATA_ONCS_COMPARE_MASK		(0x1)
464#define NVME_CTRLR_DATA_ONCS_WRITE_UNC_SHIFT		(1)
465#define NVME_CTRLR_DATA_ONCS_WRITE_UNC_MASK		(0x1)
466#define NVME_CTRLR_DATA_ONCS_DSM_SHIFT			(2)
467#define NVME_CTRLR_DATA_ONCS_DSM_MASK			(0x1)
468#define NVME_CTRLR_DATA_ONCS_WRZERO_SHIFT		(3)
469#define NVME_CTRLR_DATA_ONCS_WRZERO_MASK		(0x1)
470#define NVME_CTRLR_DATA_ONCS_SAVEFEAT_SHIFT		(4)
471#define NVME_CTRLR_DATA_ONCS_SAVEFEAT_MASK		(0x1)
472#define NVME_CTRLR_DATA_ONCS_RESERV_SHIFT		(5)
473#define NVME_CTRLR_DATA_ONCS_RESERV_MASK		(0x1)
474#define NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT		(6)
475#define NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK		(0x1)
476#define NVME_CTRLR_DATA_ONCS_VERIFY_SHIFT		(7)
477#define NVME_CTRLR_DATA_ONCS_VERIFY_MASK		(0x1)
478
479/** Fused Operation Support */
480#define NVME_CTRLR_DATA_FUSES_CNW_SHIFT		(0)
481#define NVME_CTRLR_DATA_FUSES_CNW_MASK		(0x1)
482
483/** Format NVM Attributes */
484#define NVME_CTRLR_DATA_FNA_FORMAT_ALL_SHIFT		(0)
485#define NVME_CTRLR_DATA_FNA_FORMAT_ALL_MASK		(0x1)
486#define NVME_CTRLR_DATA_FNA_ERASE_ALL_SHIFT		(1)
487#define NVME_CTRLR_DATA_FNA_ERASE_ALL_MASK		(0x1)
488#define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_SHIFT		(2)
489#define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_MASK		(0x1)
490
491/** volatile write cache */
492/* volatile write cache present */
493#define NVME_CTRLR_DATA_VWC_PRESENT_SHIFT		(0)
494#define NVME_CTRLR_DATA_VWC_PRESENT_MASK		(0x1)
495/* flush all namespaces supported */
496#define NVME_CTRLR_DATA_VWC_ALL_SHIFT			(1)
497#define NVME_CTRLR_DATA_VWC_ALL_MASK			(0x3)
498#define NVME_CTRLR_DATA_VWC_ALL_UNKNOWN			(0)
499#define NVME_CTRLR_DATA_VWC_ALL_NO			(2)
500#define NVME_CTRLR_DATA_VWC_ALL_YES			(3)
501
502/** SGL Support */
503/* NVM command set SGL support */
504#define	NVME_CTRLR_DATA_SGLS_NVM_COMMAND_SET_SHIFT	(0)
505#define	NVME_CTRLR_DATA_SGLS_NVM_COMMAND_SET_MASK	(0x3)
506#define	NVME_CTRLR_DATA_SGLS_KEYED_DATA_BLOCK_SHIFT	(2)
507#define	NVME_CTRLR_DATA_SGLS_KEYED_DATA_BLOCK_MASK	(0x1)
508#define	NVME_CTRLR_DATA_SGLS_BIT_BUCKET_SHIFT		(16)
509#define	NVME_CTRLR_DATA_SGLS_BIT_BUCKET_MASK		(0x1)
510#define	NVME_CTRLR_DATA_SGLS_CONTIG_MPTR_SHIFT		(17)
511#define	NVME_CTRLR_DATA_SGLS_CONTIG_MPTR_MASK		(0x1)
512#define	NVME_CTRLR_DATA_SGLS_OVERSIZED_SHIFT		(18)
513#define	NVME_CTRLR_DATA_SGLS_OVERSIZED_MASK		(0x1)
514#define	NVME_CTRLR_DATA_SGLS_MPTR_SGL_SHIFT		(19)
515#define	NVME_CTRLR_DATA_SGLS_MPTR_SGL_MASK		(0x1)
516#define	NVME_CTRLR_DATA_SGLS_ADDRESS_AS_OFFSET_SHIFT	(20)
517#define	NVME_CTRLR_DATA_SGLS_ADDRESS_AS_OFFSET_MASK	(0x1)
518#define	NVME_CTRLR_DATA_SGLS_TRANSPORT_DATA_BLOCK_SHIFT	(21)
519#define	NVME_CTRLR_DATA_SGLS_TRANSPORT_DATA_BLOCK_MASK	(0x1)
520
521/** namespace features */
522/* thin provisioning */
523#define NVME_NS_DATA_NSFEAT_THIN_PROV_SHIFT		(0)
524#define NVME_NS_DATA_NSFEAT_THIN_PROV_MASK		(0x1)
525/* NAWUN, NAWUPF, and NACWU fields are valid */
526#define NVME_NS_DATA_NSFEAT_NA_FIELDS_SHIFT		(1)
527#define NVME_NS_DATA_NSFEAT_NA_FIELDS_MASK		(0x1)
528/* Deallocated or Unwritten Logical Block errors supported */
529#define NVME_NS_DATA_NSFEAT_DEALLOC_SHIFT		(2)
530#define NVME_NS_DATA_NSFEAT_DEALLOC_MASK		(0x1)
531/* NGUID and EUI64 fields are not reusable */
532#define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_SHIFT		(3)
533#define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_MASK		(0x1)
534/* NPWG, NPWA, NPDG, NPDA, and NOWS are valid */
535#define NVME_NS_DATA_NSFEAT_NPVALID_SHIFT		(4)
536#define NVME_NS_DATA_NSFEAT_NPVALID_MASK		(0x1)
537
538/** formatted lba size */
539#define NVME_NS_DATA_FLBAS_FORMAT_SHIFT			(0)
540#define NVME_NS_DATA_FLBAS_FORMAT_MASK			(0xF)
541#define NVME_NS_DATA_FLBAS_EXTENDED_SHIFT		(4)
542#define NVME_NS_DATA_FLBAS_EXTENDED_MASK		(0x1)
543
544/** metadata capabilities */
545/* metadata can be transferred as part of data prp list */
546#define NVME_NS_DATA_MC_EXTENDED_SHIFT			(0)
547#define NVME_NS_DATA_MC_EXTENDED_MASK			(0x1)
548/* metadata can be transferred with separate metadata pointer */
549#define NVME_NS_DATA_MC_POINTER_SHIFT			(1)
550#define NVME_NS_DATA_MC_POINTER_MASK			(0x1)
551
552/** end-to-end data protection capabilities */
553/* protection information type 1 */
554#define NVME_NS_DATA_DPC_PIT1_SHIFT			(0)
555#define NVME_NS_DATA_DPC_PIT1_MASK			(0x1)
556/* protection information type 2 */
557#define NVME_NS_DATA_DPC_PIT2_SHIFT			(1)
558#define NVME_NS_DATA_DPC_PIT2_MASK			(0x1)
559/* protection information type 3 */
560#define NVME_NS_DATA_DPC_PIT3_SHIFT			(2)
561#define NVME_NS_DATA_DPC_PIT3_MASK			(0x1)
562/* first eight bytes of metadata */
563#define NVME_NS_DATA_DPC_MD_START_SHIFT			(3)
564#define NVME_NS_DATA_DPC_MD_START_MASK			(0x1)
565/* last eight bytes of metadata */
566#define NVME_NS_DATA_DPC_MD_END_SHIFT			(4)
567#define NVME_NS_DATA_DPC_MD_END_MASK			(0x1)
568
569/** end-to-end data protection type settings */
570/* protection information type */
571#define NVME_NS_DATA_DPS_PIT_SHIFT			(0)
572#define NVME_NS_DATA_DPS_PIT_MASK			(0x7)
573/* 1 == protection info transferred at start of metadata */
574/* 0 == protection info transferred at end of metadata */
575#define NVME_NS_DATA_DPS_MD_START_SHIFT			(3)
576#define NVME_NS_DATA_DPS_MD_START_MASK			(0x1)
577
578/** Namespace Multi-path I/O and Namespace Sharing Capabilities */
579/* the namespace may be attached to two or more controllers */
580#define NVME_NS_DATA_NMIC_MAY_BE_SHARED_SHIFT		(0)
581#define NVME_NS_DATA_NMIC_MAY_BE_SHARED_MASK		(0x1)
582
583/** Reservation Capabilities */
584/* Persist Through Power Loss */
585#define NVME_NS_DATA_RESCAP_PTPL_SHIFT		(0)
586#define NVME_NS_DATA_RESCAP_PTPL_MASK		(0x1)
587/* supports the Write Exclusive */
588#define NVME_NS_DATA_RESCAP_WR_EX_SHIFT		(1)
589#define NVME_NS_DATA_RESCAP_WR_EX_MASK		(0x1)
590/* supports the Exclusive Access */
591#define NVME_NS_DATA_RESCAP_EX_AC_SHIFT		(2)
592#define NVME_NS_DATA_RESCAP_EX_AC_MASK		(0x1)
593/* supports the Write Exclusive ��� Registrants Only */
594#define NVME_NS_DATA_RESCAP_WR_EX_RO_SHIFT	(3)
595#define NVME_NS_DATA_RESCAP_WR_EX_RO_MASK	(0x1)
596/* supports the Exclusive Access - Registrants Only */
597#define NVME_NS_DATA_RESCAP_EX_AC_RO_SHIFT	(4)
598#define NVME_NS_DATA_RESCAP_EX_AC_RO_MASK	(0x1)
599/* supports the Write Exclusive ��� All Registrants */
600#define NVME_NS_DATA_RESCAP_WR_EX_AR_SHIFT	(5)
601#define NVME_NS_DATA_RESCAP_WR_EX_AR_MASK	(0x1)
602/* supports the Exclusive Access - All Registrants */
603#define NVME_NS_DATA_RESCAP_EX_AC_AR_SHIFT	(6)
604#define NVME_NS_DATA_RESCAP_EX_AC_AR_MASK	(0x1)
605/* Ignore Existing Key is used as defined in revision 1.3 or later */
606#define NVME_NS_DATA_RESCAP_IEKEY13_SHIFT	(7)
607#define NVME_NS_DATA_RESCAP_IEKEY13_MASK	(0x1)
608
609/** Format Progress Indicator */
610/* percentage of the Format NVM command that remains to be completed */
611#define NVME_NS_DATA_FPI_PERC_SHIFT		(0)
612#define NVME_NS_DATA_FPI_PERC_MASK		(0x7f)
613/* namespace supports the Format Progress Indicator */
614#define NVME_NS_DATA_FPI_SUPP_SHIFT		(7)
615#define NVME_NS_DATA_FPI_SUPP_MASK		(0x1)
616
617/** Deallocate Logical Block Features */
618/* deallocated logical block read behavior */
619#define NVME_NS_DATA_DLFEAT_READ_SHIFT		(0)
620#define NVME_NS_DATA_DLFEAT_READ_MASK		(0x07)
621#define NVME_NS_DATA_DLFEAT_READ_NR		(0x00)
622#define NVME_NS_DATA_DLFEAT_READ_00		(0x01)
623#define NVME_NS_DATA_DLFEAT_READ_FF		(0x02)
624/* supports the Deallocate bit in the Write Zeroes */
625#define NVME_NS_DATA_DLFEAT_DWZ_SHIFT		(3)
626#define NVME_NS_DATA_DLFEAT_DWZ_MASK		(0x01)
627/* Guard field for deallocated logical blocks is set to the CRC  */
628#define NVME_NS_DATA_DLFEAT_GCRC_SHIFT		(4)
629#define NVME_NS_DATA_DLFEAT_GCRC_MASK		(0x01)
630
631/** lba format support */
632/* metadata size */
633#define NVME_NS_DATA_LBAF_MS_SHIFT			(0)
634#define NVME_NS_DATA_LBAF_MS_MASK			(0xFFFF)
635/* lba data size */
636#define NVME_NS_DATA_LBAF_LBADS_SHIFT			(16)
637#define NVME_NS_DATA_LBAF_LBADS_MASK			(0xFF)
638/* relative performance */
639#define NVME_NS_DATA_LBAF_RP_SHIFT			(24)
640#define NVME_NS_DATA_LBAF_RP_MASK			(0x3)
641
642enum nvme_critical_warning_state {
643	NVME_CRIT_WARN_ST_AVAILABLE_SPARE		= 0x1,
644	NVME_CRIT_WARN_ST_TEMPERATURE			= 0x2,
645	NVME_CRIT_WARN_ST_DEVICE_RELIABILITY		= 0x4,
646	NVME_CRIT_WARN_ST_READ_ONLY			= 0x8,
647	NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP	= 0x10,
648	NVME_CRIT_WARN_ST_PERSISTENT_MEMORY_REGION	= 0x20,
649};
650#define NVME_CRIT_WARN_ST_RESERVED_MASK			(0xC0)
651#define	NVME_ASYNC_EVENT_NS_ATTRIBUTE			(0x100)
652#define	NVME_ASYNC_EVENT_FW_ACTIVATE			(0x200)
653
654/* slot for current FW */
655#define NVME_FIRMWARE_PAGE_AFI_SLOT_SHIFT		(0)
656#define NVME_FIRMWARE_PAGE_AFI_SLOT_MASK		(0x7)
657
658/* Commands Supported and Effects */
659#define	NVME_CE_PAGE_CSUP_SHIFT				(0)
660#define	NVME_CE_PAGE_CSUP_MASK				(0x1)
661#define	NVME_CE_PAGE_LBCC_SHIFT				(1)
662#define	NVME_CE_PAGE_LBCC_MASK				(0x1)
663#define	NVME_CE_PAGE_NCC_SHIFT				(2)
664#define	NVME_CE_PAGE_NCC_MASK				(0x1)
665#define	NVME_CE_PAGE_NIC_SHIFT				(3)
666#define	NVME_CE_PAGE_NIC_MASK				(0x1)
667#define	NVME_CE_PAGE_CCC_SHIFT				(4)
668#define	NVME_CE_PAGE_CCC_MASK				(0x1)
669#define	NVME_CE_PAGE_CSE_SHIFT				(16)
670#define	NVME_CE_PAGE_CSE_MASK				(0x7)
671#define	NVME_CE_PAGE_UUID_SHIFT				(19)
672#define	NVME_CE_PAGE_UUID_MASK				(0x1)
673
674/* Sanitize Status */
675#define	NVME_SS_PAGE_SSTAT_STATUS_SHIFT			(0)
676#define	NVME_SS_PAGE_SSTAT_STATUS_MASK			(0x7)
677#define	NVME_SS_PAGE_SSTAT_STATUS_NEVER			(0)
678#define	NVME_SS_PAGE_SSTAT_STATUS_COMPLETED		(1)
679#define	NVME_SS_PAGE_SSTAT_STATUS_INPROG		(2)
680#define	NVME_SS_PAGE_SSTAT_STATUS_FAILED		(3)
681#define	NVME_SS_PAGE_SSTAT_STATUS_COMPLETEDWD		(4)
682#define	NVME_SS_PAGE_SSTAT_PASSES_SHIFT			(3)
683#define	NVME_SS_PAGE_SSTAT_PASSES_MASK			(0x1f)
684#define	NVME_SS_PAGE_SSTAT_GDE_SHIFT			(8)
685#define	NVME_SS_PAGE_SSTAT_GDE_MASK			(0x1)
686
687/* Features */
688/* Get Features */
689#define NVME_FEAT_GET_SEL_SHIFT				(8)
690#define NVME_FEAT_GET_SEL_MASK				(0x7)
691#define NVME_FEAT_GET_FID_SHIFT				(0)
692#define NVME_FEAT_GET_FID_MASK				(0xff)
693
694/* Set Features */
695#define NVME_FEAT_SET_SV_SHIFT				(31)
696#define NVME_FEAT_SET_SV_MASK				(0x1)
697#define NVME_FEAT_SET_FID_SHIFT				(0)
698#define NVME_FEAT_SET_FID_MASK				(0xff)
699
700/* Async Events */
701#define	NVME_ASYNC_EVENT_TYPE_SHIFT			(0)
702#define	NVME_ASYNC_EVENT_TYPE_MASK			(0x7)
703#define	NVME_ASYNC_EVENT_INFO_SHIFT			(8)
704#define	NVME_ASYNC_EVENT_INFO_MASK			(0xff)
705#define	NVME_ASYNC_EVENT_LOG_PAGE_ID_SHIFT		(16)
706#define	NVME_ASYNC_EVENT_LOG_PAGE_ID_MASK		(0xff)
707
708/* Helper macro to combine *_MASK and *_SHIFT defines */
709#define NVMEM(name)	(name##_MASK << name##_SHIFT)
710
711/* Helper macro to extract value from x */
712#define NVMEV(name, x)  (((x) >> name##_SHIFT) & name##_MASK)
713
714/* Helper macro to construct a field value */
715#define	NVMEF(name, x)	(((x) & name##_MASK) << name##_SHIFT)
716
717/* CC register SHN field values */
718enum shn_value {
719	NVME_SHN_NORMAL		= 0x1,
720	NVME_SHN_ABRUPT		= 0x2,
721};
722
723/* CSTS register SHST field values */
724enum shst_value {
725	NVME_SHST_NORMAL	= 0x0,
726	NVME_SHST_OCCURRING	= 0x1,
727	NVME_SHST_COMPLETE	= 0x2,
728};
729
730struct nvme_registers {
731	uint32_t	cap_lo; /* controller capabilities */
732	uint32_t	cap_hi;
733	uint32_t	vs;	/* version */
734	uint32_t	intms;	/* interrupt mask set */
735	uint32_t	intmc;	/* interrupt mask clear */
736	uint32_t	cc;	/* controller configuration */
737	uint32_t	reserved1;
738	uint32_t	csts;	/* controller status */
739	uint32_t	nssr;	/* NVM Subsystem Reset */
740	uint32_t	aqa;	/* admin queue attributes */
741	uint64_t	asq;	/* admin submission queue base addr */
742	uint64_t	acq;	/* admin completion queue base addr */
743	uint32_t	cmbloc;	/* Controller Memory Buffer Location */
744	uint32_t	cmbsz;	/* Controller Memory Buffer Size */
745	uint32_t	bpinfo;	/* Boot Partition Information */
746	uint32_t	bprsel;	/* Boot Partition Read Select */
747	uint64_t	bpmbl;	/* Boot Partition Memory Buffer Location */
748	uint64_t	cmbmsc;	/* Controller Memory Buffer Memory Space Control */
749	uint32_t	cmbsts;	/* Controller Memory Buffer Status */
750	uint32_t	cmbebs;	/* Controller Memory Buffer Elasticity Buffer Size */
751	uint32_t	cmbswtp;/* Controller Memory Buffer Sustained Write Throughput */
752	uint32_t	nssd;	/* NVM Subsystem Shutdown */
753	uint32_t	crto;	/* Controller Ready Timeouts */
754	uint8_t		reserved3[3476]; /* 6Ch - DFFh */
755	uint32_t	pmrcap;	/* Persistent Memory Capabilities */
756	uint32_t	pmrctl;	/* Persistent Memory Region Control */
757	uint32_t	pmrsts;	/* Persistent Memory Region Status */
758	uint32_t	pmrebs;	/* Persistent Memory Region Elasticity Buffer Size */
759	uint32_t	pmrswtp; /* Persistent Memory Region Sustained Write Throughput */
760	uint32_t	pmrmsc_lo; /* Persistent Memory Region Controller Memory Space Control */
761	uint32_t	pmrmsc_hi;
762	uint8_t		reserved4[484]; /* E1Ch - FFFh */
763	struct {
764	    uint32_t	sq_tdbl; /* submission queue tail doorbell */
765	    uint32_t	cq_hdbl; /* completion queue head doorbell */
766	} doorbell[1];
767};
768
769_Static_assert(sizeof(struct nvme_registers) == 0x1008, "bad size for nvme_registers");
770
771#define NVME_SGL_SUBTYPE_SHIFT				(0)
772#define NVME_SGL_SUBTYPE_MASK				(0xF)
773#define NVME_SGL_TYPE_SHIFT				(4)
774#define NVME_SGL_TYPE_MASK				(0xF)
775
776#define	NVME_SGL_TYPE(type, subtype)		\
777	((subtype) << NVME_SGL_SUBTYPE_SHIFT | (type) << NVME_SGL_TYPE_SHIFT)
778
779enum nvme_sgl_type {
780	NVME_SGL_TYPE_DATA_BLOCK		= 0x0,
781	NVME_SGL_TYPE_BIT_BUCKET		= 0x1,
782	NVME_SGL_TYPE_SEGMENT			= 0x2,
783	NVME_SGL_TYPE_LAST_SEGMENT		= 0x3,
784	NVME_SGL_TYPE_KEYED_DATA_BLOCK		= 0x4,
785	NVME_SGL_TYPE_TRANSPORT_DATA_BLOCK	= 0x5,
786};
787
788enum nvme_sgl_subtype {
789	NVME_SGL_SUBTYPE_ADDRESS		= 0x0,
790	NVME_SGL_SUBTYPE_OFFSET			= 0x1,
791	NVME_SGL_SUBTYPE_TRANSPORT		= 0xa,
792};
793
794struct nvme_sgl_descriptor {
795	uint64_t address;
796	uint32_t length;
797	uint8_t reserved[3];
798	uint8_t type;
799};
800
801_Static_assert(sizeof(struct nvme_sgl_descriptor) == 16, "bad size for nvme_sgl_descriptor");
802
803struct nvme_command {
804	/* dword 0 */
805	uint8_t opc;		/* opcode */
806	uint8_t fuse;		/* fused operation */
807	uint16_t cid;		/* command identifier */
808
809	/* dword 1 */
810	uint32_t nsid;		/* namespace identifier */
811
812	/* dword 2-3 */
813	uint32_t rsvd2;
814	uint32_t rsvd3;
815
816	/* dword 4-5 */
817	uint64_t mptr;		/* metadata pointer */
818
819	/* dword 6-9 */
820	union {
821		struct {
822			uint64_t prp1;	/* prp entry 1 */
823			uint64_t prp2;	/* prp entry 2 */
824		};
825		struct nvme_sgl_descriptor sgl;
826	};
827
828	/* dword 10-15 */
829	uint32_t cdw10;		/* command-specific */
830	uint32_t cdw11;		/* command-specific */
831	uint32_t cdw12;		/* command-specific */
832	uint32_t cdw13;		/* command-specific */
833	uint32_t cdw14;		/* command-specific */
834	uint32_t cdw15;		/* command-specific */
835} __aligned(8);
836
837_Static_assert(sizeof(struct nvme_command) == 16 * 4, "bad size for nvme_command");
838
839struct nvme_completion {
840	/* dword 0 */
841	uint32_t		cdw0;	/* command-specific */
842
843	/* dword 1 */
844	uint32_t		rsvd1;
845
846	/* dword 2 */
847	uint16_t		sqhd;	/* submission queue head pointer */
848	uint16_t		sqid;	/* submission queue identifier */
849
850	/* dword 3 */
851	uint16_t		cid;	/* command identifier */
852	uint16_t		status;
853} __aligned(8);	/* riscv: nvme_qpair_process_completions has better code gen */
854
855_Static_assert(sizeof(struct nvme_completion) == 4 * 4, "bad size for nvme_completion");
856
857struct nvme_dsm_range {
858	uint32_t attributes;
859	uint32_t length;
860	uint64_t starting_lba;
861};
862
863/* Largest DSM Trim that can be done */
864#define NVME_MAX_DSM_TRIM		4096
865
866_Static_assert(sizeof(struct nvme_dsm_range) == 16, "bad size for nvme_dsm_ranage");
867
868/* status code types */
869enum nvme_status_code_type {
870	NVME_SCT_GENERIC		= 0x0,
871	NVME_SCT_COMMAND_SPECIFIC	= 0x1,
872	NVME_SCT_MEDIA_ERROR		= 0x2,
873	NVME_SCT_PATH_RELATED		= 0x3,
874	/* 0x3-0x6 - reserved */
875	NVME_SCT_VENDOR_SPECIFIC	= 0x7,
876};
877
878/* generic command status codes */
879enum nvme_generic_command_status_code {
880	NVME_SC_SUCCESS				= 0x00,
881	NVME_SC_INVALID_OPCODE			= 0x01,
882	NVME_SC_INVALID_FIELD			= 0x02,
883	NVME_SC_COMMAND_ID_CONFLICT		= 0x03,
884	NVME_SC_DATA_TRANSFER_ERROR		= 0x04,
885	NVME_SC_ABORTED_POWER_LOSS		= 0x05,
886	NVME_SC_INTERNAL_DEVICE_ERROR		= 0x06,
887	NVME_SC_ABORTED_BY_REQUEST		= 0x07,
888	NVME_SC_ABORTED_SQ_DELETION		= 0x08,
889	NVME_SC_ABORTED_FAILED_FUSED		= 0x09,
890	NVME_SC_ABORTED_MISSING_FUSED		= 0x0a,
891	NVME_SC_INVALID_NAMESPACE_OR_FORMAT	= 0x0b,
892	NVME_SC_COMMAND_SEQUENCE_ERROR		= 0x0c,
893	NVME_SC_INVALID_SGL_SEGMENT_DESCR	= 0x0d,
894	NVME_SC_INVALID_NUMBER_OF_SGL_DESCR	= 0x0e,
895	NVME_SC_DATA_SGL_LENGTH_INVALID		= 0x0f,
896	NVME_SC_METADATA_SGL_LENGTH_INVALID	= 0x10,
897	NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID	= 0x11,
898	NVME_SC_INVALID_USE_OF_CMB		= 0x12,
899	NVME_SC_PRP_OFFET_INVALID		= 0x13,
900	NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED	= 0x14,
901	NVME_SC_OPERATION_DENIED		= 0x15,
902	NVME_SC_SGL_OFFSET_INVALID		= 0x16,
903	/* 0x17 - reserved */
904	NVME_SC_HOST_ID_INCONSISTENT_FORMAT	= 0x18,
905	NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED	= 0x19,
906	NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID	= 0x1a,
907	NVME_SC_ABORTED_DUE_TO_PREEMPT		= 0x1b,
908	NVME_SC_SANITIZE_FAILED			= 0x1c,
909	NVME_SC_SANITIZE_IN_PROGRESS		= 0x1d,
910	NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID	= 0x1e,
911	NVME_SC_NOT_SUPPORTED_IN_CMB		= 0x1f,
912	NVME_SC_NAMESPACE_IS_WRITE_PROTECTED	= 0x20,
913	NVME_SC_COMMAND_INTERRUPTED		= 0x21,
914	NVME_SC_TRANSIENT_TRANSPORT_ERROR	= 0x22,
915
916	NVME_SC_LBA_OUT_OF_RANGE		= 0x80,
917	NVME_SC_CAPACITY_EXCEEDED		= 0x81,
918	NVME_SC_NAMESPACE_NOT_READY		= 0x82,
919	NVME_SC_RESERVATION_CONFLICT		= 0x83,
920	NVME_SC_FORMAT_IN_PROGRESS		= 0x84,
921};
922
923/* command specific status codes */
924enum nvme_command_specific_status_code {
925	NVME_SC_COMPLETION_QUEUE_INVALID	= 0x00,
926	NVME_SC_INVALID_QUEUE_IDENTIFIER	= 0x01,
927	NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED	= 0x02,
928	NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED	= 0x03,
929	/* 0x04 - reserved */
930	NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05,
931	NVME_SC_INVALID_FIRMWARE_SLOT		= 0x06,
932	NVME_SC_INVALID_FIRMWARE_IMAGE		= 0x07,
933	NVME_SC_INVALID_INTERRUPT_VECTOR	= 0x08,
934	NVME_SC_INVALID_LOG_PAGE		= 0x09,
935	NVME_SC_INVALID_FORMAT			= 0x0a,
936	NVME_SC_FIRMWARE_REQUIRES_RESET		= 0x0b,
937	NVME_SC_INVALID_QUEUE_DELETION		= 0x0c,
938	NVME_SC_FEATURE_NOT_SAVEABLE		= 0x0d,
939	NVME_SC_FEATURE_NOT_CHANGEABLE		= 0x0e,
940	NVME_SC_FEATURE_NOT_NS_SPECIFIC		= 0x0f,
941	NVME_SC_FW_ACT_REQUIRES_NVMS_RESET	= 0x10,
942	NVME_SC_FW_ACT_REQUIRES_RESET		= 0x11,
943	NVME_SC_FW_ACT_REQUIRES_TIME		= 0x12,
944	NVME_SC_FW_ACT_PROHIBITED		= 0x13,
945	NVME_SC_OVERLAPPING_RANGE		= 0x14,
946	NVME_SC_NS_INSUFFICIENT_CAPACITY	= 0x15,
947	NVME_SC_NS_ID_UNAVAILABLE		= 0x16,
948	/* 0x17 - reserved */
949	NVME_SC_NS_ALREADY_ATTACHED		= 0x18,
950	NVME_SC_NS_IS_PRIVATE			= 0x19,
951	NVME_SC_NS_NOT_ATTACHED			= 0x1a,
952	NVME_SC_THIN_PROV_NOT_SUPPORTED		= 0x1b,
953	NVME_SC_CTRLR_LIST_INVALID		= 0x1c,
954	NVME_SC_SELF_TEST_IN_PROGRESS		= 0x1d,
955	NVME_SC_BOOT_PART_WRITE_PROHIB		= 0x1e,
956	NVME_SC_INVALID_CTRLR_ID		= 0x1f,
957	NVME_SC_INVALID_SEC_CTRLR_STATE		= 0x20,
958	NVME_SC_INVALID_NUM_OF_CTRLR_RESRC	= 0x21,
959	NVME_SC_INVALID_RESOURCE_ID		= 0x22,
960	NVME_SC_SANITIZE_PROHIBITED_WPMRE	= 0x23,
961	NVME_SC_ANA_GROUP_ID_INVALID		= 0x24,
962	NVME_SC_ANA_ATTACH_FAILED		= 0x25,
963
964	NVME_SC_CONFLICTING_ATTRIBUTES		= 0x80,
965	NVME_SC_INVALID_PROTECTION_INFO		= 0x81,
966	NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE	= 0x82,
967};
968
969/* media error status codes */
970enum nvme_media_error_status_code {
971	NVME_SC_WRITE_FAULTS			= 0x80,
972	NVME_SC_UNRECOVERED_READ_ERROR		= 0x81,
973	NVME_SC_GUARD_CHECK_ERROR		= 0x82,
974	NVME_SC_APPLICATION_TAG_CHECK_ERROR	= 0x83,
975	NVME_SC_REFERENCE_TAG_CHECK_ERROR	= 0x84,
976	NVME_SC_COMPARE_FAILURE			= 0x85,
977	NVME_SC_ACCESS_DENIED			= 0x86,
978	NVME_SC_DEALLOCATED_OR_UNWRITTEN	= 0x87,
979};
980
981/* path related status codes */
982enum nvme_path_related_status_code {
983	NVME_SC_INTERNAL_PATH_ERROR		= 0x00,
984	NVME_SC_ASYMMETRIC_ACCESS_PERSISTENT_LOSS = 0x01,
985	NVME_SC_ASYMMETRIC_ACCESS_INACCESSIBLE	= 0x02,
986	NVME_SC_ASYMMETRIC_ACCESS_TRANSITION	= 0x03,
987	NVME_SC_CONTROLLER_PATHING_ERROR	= 0x60,
988	NVME_SC_HOST_PATHING_ERROR		= 0x70,
989	NVME_SC_COMMAND_ABORTED_BY_HOST		= 0x71,
990};
991
992/* admin opcodes */
993enum nvme_admin_opcode {
994	NVME_OPC_DELETE_IO_SQ			= 0x00,
995	NVME_OPC_CREATE_IO_SQ			= 0x01,
996	NVME_OPC_GET_LOG_PAGE			= 0x02,
997	/* 0x03 - reserved */
998	NVME_OPC_DELETE_IO_CQ			= 0x04,
999	NVME_OPC_CREATE_IO_CQ			= 0x05,
1000	NVME_OPC_IDENTIFY			= 0x06,
1001	/* 0x07 - reserved */
1002	NVME_OPC_ABORT				= 0x08,
1003	NVME_OPC_SET_FEATURES			= 0x09,
1004	NVME_OPC_GET_FEATURES			= 0x0a,
1005	/* 0x0b - reserved */
1006	NVME_OPC_ASYNC_EVENT_REQUEST		= 0x0c,
1007	NVME_OPC_NAMESPACE_MANAGEMENT		= 0x0d,
1008	/* 0x0e-0x0f - reserved */
1009	NVME_OPC_FIRMWARE_ACTIVATE		= 0x10,
1010	NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD	= 0x11,
1011	/* 0x12-0x13 - reserved */
1012	NVME_OPC_DEVICE_SELF_TEST		= 0x14,
1013	NVME_OPC_NAMESPACE_ATTACHMENT		= 0x15,
1014	/* 0x16-0x17 - reserved */
1015	NVME_OPC_KEEP_ALIVE			= 0x18,
1016	NVME_OPC_DIRECTIVE_SEND			= 0x19,
1017	NVME_OPC_DIRECTIVE_RECEIVE		= 0x1a,
1018	/* 0x1b - reserved */
1019	NVME_OPC_VIRTUALIZATION_MANAGEMENT	= 0x1c,
1020	NVME_OPC_NVME_MI_SEND			= 0x1d,
1021	NVME_OPC_NVME_MI_RECEIVE		= 0x1e,
1022	/* 0x1f - reserved */
1023	NVME_OPC_CAPACITY_MANAGEMENT		= 0x20,
1024	/* 0x21-0x23 - reserved */
1025	NVME_OPC_LOCKDOWN			= 0x24,
1026	/* 0x25-0x7b - reserved */
1027	NVME_OPC_DOORBELL_BUFFER_CONFIG		= 0x7c,
1028	/* 0x7d-0x7e - reserved */
1029	NVME_OPC_FABRICS_COMMANDS		= 0x7f,
1030
1031	NVME_OPC_FORMAT_NVM			= 0x80,
1032	NVME_OPC_SECURITY_SEND			= 0x81,
1033	NVME_OPC_SECURITY_RECEIVE		= 0x82,
1034	/* 0x83 - reserved */
1035	NVME_OPC_SANITIZE			= 0x84,
1036	/* 0x85 - reserved */
1037	NVME_OPC_GET_LBA_STATUS			= 0x86,
1038};
1039
1040/* nvme nvm opcodes */
1041enum nvme_nvm_opcode {
1042	NVME_OPC_FLUSH				= 0x00,
1043	NVME_OPC_WRITE				= 0x01,
1044	NVME_OPC_READ				= 0x02,
1045	/* 0x03 - reserved */
1046	NVME_OPC_WRITE_UNCORRECTABLE		= 0x04,
1047	NVME_OPC_COMPARE			= 0x05,
1048	/* 0x06-0x07 - reserved */
1049	NVME_OPC_WRITE_ZEROES			= 0x08,
1050	NVME_OPC_DATASET_MANAGEMENT		= 0x09,
1051	/* 0x0a-0x0b - reserved */
1052	NVME_OPC_VERIFY				= 0x0c,
1053	NVME_OPC_RESERVATION_REGISTER		= 0x0d,
1054	NVME_OPC_RESERVATION_REPORT		= 0x0e,
1055	/* 0x0f-0x10 - reserved */
1056	NVME_OPC_RESERVATION_ACQUIRE		= 0x11,
1057	/* 0x12-0x14 - reserved */
1058	NVME_OPC_RESERVATION_RELEASE		= 0x15,
1059	/* 0x16-0x18 - reserved */
1060	NVME_OPC_COPY				= 0x19,
1061};
1062
1063enum nvme_feature {
1064	/* 0x00 - reserved */
1065	NVME_FEAT_ARBITRATION			= 0x01,
1066	NVME_FEAT_POWER_MANAGEMENT		= 0x02,
1067	NVME_FEAT_LBA_RANGE_TYPE		= 0x03,
1068	NVME_FEAT_TEMPERATURE_THRESHOLD		= 0x04,
1069	NVME_FEAT_ERROR_RECOVERY		= 0x05,
1070	NVME_FEAT_VOLATILE_WRITE_CACHE		= 0x06,
1071	NVME_FEAT_NUMBER_OF_QUEUES		= 0x07,
1072	NVME_FEAT_INTERRUPT_COALESCING		= 0x08,
1073	NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09,
1074	NVME_FEAT_WRITE_ATOMICITY		= 0x0A,
1075	NVME_FEAT_ASYNC_EVENT_CONFIGURATION	= 0x0B,
1076	NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION = 0x0C,
1077	NVME_FEAT_HOST_MEMORY_BUFFER		= 0x0D,
1078	NVME_FEAT_TIMESTAMP			= 0x0E,
1079	NVME_FEAT_KEEP_ALIVE_TIMER		= 0x0F,
1080	NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT	= 0x10,
1081	NVME_FEAT_NON_OP_POWER_STATE_CONFIG	= 0x11,
1082	NVME_FEAT_READ_RECOVERY_LEVEL_CONFIG	= 0x12,
1083	NVME_FEAT_PREDICTABLE_LATENCY_MODE_CONFIG = 0x13,
1084	NVME_FEAT_PREDICTABLE_LATENCY_MODE_WINDOW = 0x14,
1085	NVME_FEAT_LBA_STATUS_INFORMATION_ATTRIBUTES = 0x15,
1086	NVME_FEAT_HOST_BEHAVIOR_SUPPORT		= 0x16,
1087	NVME_FEAT_SANITIZE_CONFIG		= 0x17,
1088	NVME_FEAT_ENDURANCE_GROUP_EVENT_CONFIGURATION = 0x18,
1089	/* 0x19-0x77 - reserved */
1090	/* 0x78-0x7f - NVMe Management Interface */
1091	NVME_FEAT_SOFTWARE_PROGRESS_MARKER	= 0x80,
1092	NVME_FEAT_HOST_IDENTIFIER		= 0x81,
1093	NVME_FEAT_RESERVATION_NOTIFICATION_MASK	= 0x82,
1094	NVME_FEAT_RESERVATION_PERSISTENCE	= 0x83,
1095	NVME_FEAT_NAMESPACE_WRITE_PROTECTION_CONFIG = 0x84,
1096	/* 0x85-0xBF - command set specific (reserved) */
1097	/* 0xC0-0xFF - vendor specific */
1098};
1099
1100enum nvme_dsm_attribute {
1101	NVME_DSM_ATTR_INTEGRAL_READ		= 0x1,
1102	NVME_DSM_ATTR_INTEGRAL_WRITE		= 0x2,
1103	NVME_DSM_ATTR_DEALLOCATE		= 0x4,
1104};
1105
1106enum nvme_activate_action {
1107	NVME_AA_REPLACE_NO_ACTIVATE		= 0x0,
1108	NVME_AA_REPLACE_ACTIVATE		= 0x1,
1109	NVME_AA_ACTIVATE			= 0x2,
1110};
1111
1112struct nvme_power_state {
1113	/** Maximum Power */
1114	uint16_t	mp;			/* Maximum Power */
1115	uint8_t		ps_rsvd1;
1116	uint8_t		mps_nops;		/* Max Power Scale, Non-Operational State */
1117
1118	uint32_t	enlat;			/* Entry Latency */
1119	uint32_t	exlat;			/* Exit Latency */
1120
1121	uint8_t		rrt;			/* Relative Read Throughput */
1122	uint8_t		rrl;			/* Relative Read Latency */
1123	uint8_t		rwt;			/* Relative Write Throughput */
1124	uint8_t		rwl;			/* Relative Write Latency */
1125
1126	uint16_t	idlp;			/* Idle Power */
1127	uint8_t		ips;			/* Idle Power Scale */
1128	uint8_t		ps_rsvd8;
1129
1130	uint16_t	actp;			/* Active Power */
1131	uint8_t		apw_aps;		/* Active Power Workload, Active Power Scale */
1132	uint8_t		ps_rsvd10[9];
1133} __packed;
1134
1135_Static_assert(sizeof(struct nvme_power_state) == 32, "bad size for nvme_power_state");
1136
1137#define NVME_SERIAL_NUMBER_LENGTH	20
1138#define NVME_MODEL_NUMBER_LENGTH	40
1139#define NVME_FIRMWARE_REVISION_LENGTH	8
1140
1141struct nvme_controller_data {
1142	/* bytes 0-255: controller capabilities and features */
1143
1144	/** pci vendor id */
1145	uint16_t		vid;
1146
1147	/** pci subsystem vendor id */
1148	uint16_t		ssvid;
1149
1150	/** serial number */
1151	uint8_t			sn[NVME_SERIAL_NUMBER_LENGTH];
1152
1153	/** model number */
1154	uint8_t			mn[NVME_MODEL_NUMBER_LENGTH];
1155
1156	/** firmware revision */
1157	uint8_t			fr[NVME_FIRMWARE_REVISION_LENGTH];
1158
1159	/** recommended arbitration burst */
1160	uint8_t			rab;
1161
1162	/** ieee oui identifier */
1163	uint8_t			ieee[3];
1164
1165	/** multi-interface capabilities */
1166	uint8_t			mic;
1167
1168	/** maximum data transfer size */
1169	uint8_t			mdts;
1170
1171	/** Controller ID */
1172	uint16_t		ctrlr_id;
1173
1174	/** Version */
1175	uint32_t		ver;
1176
1177	/** RTD3 Resume Latency */
1178	uint32_t		rtd3r;
1179
1180	/** RTD3 Enter Latency */
1181	uint32_t		rtd3e;
1182
1183	/** Optional Asynchronous Events Supported */
1184	uint32_t		oaes;	/* bitfield really */
1185
1186	/** Controller Attributes */
1187	uint32_t		ctratt;	/* bitfield really */
1188
1189	/** Read Recovery Levels Supported */
1190	uint16_t		rrls;
1191
1192	uint8_t			reserved1[9];
1193
1194	/** Controller Type */
1195	uint8_t			cntrltype;
1196
1197	/** FRU Globally Unique Identifier */
1198	uint8_t			fguid[16];
1199
1200	/** Command Retry Delay Time 1 */
1201	uint16_t		crdt1;
1202
1203	/** Command Retry Delay Time 2 */
1204	uint16_t		crdt2;
1205
1206	/** Command Retry Delay Time 3 */
1207	uint16_t		crdt3;
1208
1209	uint8_t			reserved2[122];
1210
1211	/* bytes 256-511: admin command set attributes */
1212
1213	/** optional admin command support */
1214	uint16_t		oacs;
1215
1216	/** abort command limit */
1217	uint8_t			acl;
1218
1219	/** asynchronous event request limit */
1220	uint8_t			aerl;
1221
1222	/** firmware updates */
1223	uint8_t			frmw;
1224
1225	/** log page attributes */
1226	uint8_t			lpa;
1227
1228	/** error log page entries */
1229	uint8_t			elpe;
1230
1231	/** number of power states supported */
1232	uint8_t			npss;
1233
1234	/** admin vendor specific command configuration */
1235	uint8_t			avscc;
1236
1237	/** Autonomous Power State Transition Attributes */
1238	uint8_t			apsta;
1239
1240	/** Warning Composite Temperature Threshold */
1241	uint16_t		wctemp;
1242
1243	/** Critical Composite Temperature Threshold */
1244	uint16_t		cctemp;
1245
1246	/** Maximum Time for Firmware Activation */
1247	uint16_t		mtfa;
1248
1249	/** Host Memory Buffer Preferred Size */
1250	uint32_t		hmpre;
1251
1252	/** Host Memory Buffer Minimum Size */
1253	uint32_t		hmmin;
1254
1255	/** Name space capabilities  */
1256	struct {
1257		/* if nsmgmt, report tnvmcap and unvmcap */
1258		uint8_t    tnvmcap[16];
1259		uint8_t    unvmcap[16];
1260	} __packed untncap;
1261
1262	/** Replay Protected Memory Block Support */
1263	uint32_t		rpmbs; /* Really a bitfield */
1264
1265	/** Extended Device Self-test Time */
1266	uint16_t		edstt;
1267
1268	/** Device Self-test Options */
1269	uint8_t			dsto; /* Really a bitfield */
1270
1271	/** Firmware Update Granularity */
1272	uint8_t			fwug;
1273
1274	/** Keep Alive Support */
1275	uint16_t		kas;
1276
1277	/** Host Controlled Thermal Management Attributes */
1278	uint16_t		hctma; /* Really a bitfield */
1279
1280	/** Minimum Thermal Management Temperature */
1281	uint16_t		mntmt;
1282
1283	/** Maximum Thermal Management Temperature */
1284	uint16_t		mxtmt;
1285
1286	/** Sanitize Capabilities */
1287	uint32_t		sanicap; /* Really a bitfield */
1288
1289	/** Host Memory Buffer Minimum Descriptor Entry Size */
1290	uint32_t		hmminds;
1291
1292	/** Host Memory Maximum Descriptors Entries */
1293	uint16_t		hmmaxd;
1294
1295	/** NVM Set Identifier Maximum */
1296	uint16_t		nsetidmax;
1297
1298	/** Endurance Group Identifier Maximum */
1299	uint16_t		endgidmax;
1300
1301	/** ANA Transition Time */
1302	uint8_t			anatt;
1303
1304	/** Asymmetric Namespace Access Capabilities */
1305	uint8_t			anacap;
1306
1307	/** ANA Group Identifier Maximum */
1308	uint32_t		anagrpmax;
1309
1310	/** Number of ANA Group Identifiers */
1311	uint32_t		nanagrpid;
1312
1313	/** Persistent Event Log Size */
1314	uint32_t		pels;
1315
1316	uint8_t			reserved3[156];
1317	/* bytes 512-703: nvm command set attributes */
1318
1319	/** submission queue entry size */
1320	uint8_t			sqes;
1321
1322	/** completion queue entry size */
1323	uint8_t			cqes;
1324
1325	/** Maximum Outstanding Commands */
1326	uint16_t		maxcmd;
1327
1328	/** number of namespaces */
1329	uint32_t		nn;
1330
1331	/** optional nvm command support */
1332	uint16_t		oncs;
1333
1334	/** fused operation support */
1335	uint16_t		fuses;
1336
1337	/** format nvm attributes */
1338	uint8_t			fna;
1339
1340	/** volatile write cache */
1341	uint8_t			vwc;
1342
1343	/** Atomic Write Unit Normal */
1344	uint16_t		awun;
1345
1346	/** Atomic Write Unit Power Fail */
1347	uint16_t		awupf;
1348
1349	/** NVM Vendor Specific Command Configuration */
1350	uint8_t			nvscc;
1351
1352	/** Namespace Write Protection Capabilities */
1353	uint8_t			nwpc;
1354
1355	/** Atomic Compare & Write Unit */
1356	uint16_t		acwu;
1357	uint16_t		reserved6;
1358
1359	/** SGL Support */
1360	uint32_t		sgls;
1361
1362	/** Maximum Number of Allowed Namespaces */
1363	uint32_t		mnan;
1364
1365	/* bytes 540-767: Reserved */
1366	uint8_t			reserved7[224];
1367
1368	/** NVM Subsystem NVMe Qualified Name */
1369	uint8_t			subnqn[256];
1370
1371	/* bytes 1024-1791: Reserved */
1372	uint8_t			reserved8[768];
1373
1374	/* bytes 1792-2047: NVMe over Fabrics specification */
1375	uint32_t		ioccsz;
1376	uint32_t		iorcsz;
1377	uint16_t		icdoff;
1378	uint8_t			fcatt;
1379	uint8_t			msdbd;
1380	uint16_t		ofcs;
1381	uint8_t			reserved9[242];
1382
1383	/* bytes 2048-3071: power state descriptors */
1384	struct nvme_power_state power_state[32];
1385
1386	/* bytes 3072-4095: vendor specific */
1387	uint8_t			vs[1024];
1388} __packed __aligned(4);
1389
1390_Static_assert(sizeof(struct nvme_controller_data) == 4096, "bad size for nvme_controller_data");
1391
1392struct nvme_namespace_data {
1393	/** namespace size */
1394	uint64_t		nsze;
1395
1396	/** namespace capacity */
1397	uint64_t		ncap;
1398
1399	/** namespace utilization */
1400	uint64_t		nuse;
1401
1402	/** namespace features */
1403	uint8_t			nsfeat;
1404
1405	/** number of lba formats */
1406	uint8_t			nlbaf;
1407
1408	/** formatted lba size */
1409	uint8_t			flbas;
1410
1411	/** metadata capabilities */
1412	uint8_t			mc;
1413
1414	/** end-to-end data protection capabilities */
1415	uint8_t			dpc;
1416
1417	/** end-to-end data protection type settings */
1418	uint8_t			dps;
1419
1420	/** Namespace Multi-path I/O and Namespace Sharing Capabilities */
1421	uint8_t			nmic;
1422
1423	/** Reservation Capabilities */
1424	uint8_t			rescap;
1425
1426	/** Format Progress Indicator */
1427	uint8_t			fpi;
1428
1429	/** Deallocate Logical Block Features */
1430	uint8_t			dlfeat;
1431
1432	/** Namespace Atomic Write Unit Normal  */
1433	uint16_t		nawun;
1434
1435	/** Namespace Atomic Write Unit Power Fail */
1436	uint16_t		nawupf;
1437
1438	/** Namespace Atomic Compare & Write Unit */
1439	uint16_t		nacwu;
1440
1441	/** Namespace Atomic Boundary Size Normal */
1442	uint16_t		nabsn;
1443
1444	/** Namespace Atomic Boundary Offset */
1445	uint16_t		nabo;
1446
1447	/** Namespace Atomic Boundary Size Power Fail */
1448	uint16_t		nabspf;
1449
1450	/** Namespace Optimal IO Boundary */
1451	uint16_t		noiob;
1452
1453	/** NVM Capacity */
1454	uint8_t			nvmcap[16];
1455
1456	/** Namespace Preferred Write Granularity  */
1457	uint16_t		npwg;
1458
1459	/** Namespace Preferred Write Alignment */
1460	uint16_t		npwa;
1461
1462	/** Namespace Preferred Deallocate Granularity */
1463	uint16_t		npdg;
1464
1465	/** Namespace Preferred Deallocate Alignment */
1466	uint16_t		npda;
1467
1468	/** Namespace Optimal Write Size */
1469	uint16_t		nows;
1470
1471	/* bytes 74-91: Reserved */
1472	uint8_t			reserved5[18];
1473
1474	/** ANA Group Identifier */
1475	uint32_t		anagrpid;
1476
1477	/* bytes 96-98: Reserved */
1478	uint8_t			reserved6[3];
1479
1480	/** Namespace Attributes */
1481	uint8_t			nsattr;
1482
1483	/** NVM Set Identifier */
1484	uint16_t		nvmsetid;
1485
1486	/** Endurance Group Identifier */
1487	uint16_t		endgid;
1488
1489	/** Namespace Globally Unique Identifier */
1490	uint8_t			nguid[16];
1491
1492	/** IEEE Extended Unique Identifier */
1493	uint8_t			eui64[8];
1494
1495	/** lba format support */
1496	uint32_t		lbaf[16];
1497
1498	uint8_t			reserved7[192];
1499
1500	uint8_t			vendor_specific[3712];
1501} __packed __aligned(4);
1502
1503_Static_assert(sizeof(struct nvme_namespace_data) == 4096, "bad size for nvme_namepsace_data");
1504
1505enum nvme_log_page {
1506	/* 0x00 - reserved */
1507	NVME_LOG_ERROR			= 0x01,
1508	NVME_LOG_HEALTH_INFORMATION	= 0x02,
1509	NVME_LOG_FIRMWARE_SLOT		= 0x03,
1510	NVME_LOG_CHANGED_NAMESPACE	= 0x04,
1511	NVME_LOG_COMMAND_EFFECT		= 0x05,
1512	NVME_LOG_DEVICE_SELF_TEST	= 0x06,
1513	NVME_LOG_TELEMETRY_HOST_INITIATED = 0x07,
1514	NVME_LOG_TELEMETRY_CONTROLLER_INITIATED = 0x08,
1515	NVME_LOG_ENDURANCE_GROUP_INFORMATION = 0x09,
1516	NVME_LOG_PREDICTABLE_LATENCY_PER_NVM_SET = 0x0a,
1517	NVME_LOG_PREDICTABLE_LATENCY_EVENT_AGGREGATE = 0x0b,
1518	NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS = 0x0c,
1519	NVME_LOG_PERSISTENT_EVENT_LOG	= 0x0d,
1520	NVME_LOG_LBA_STATUS_INFORMATION	= 0x0e,
1521	NVME_LOG_ENDURANCE_GROUP_EVENT_AGGREGATE = 0x0f,
1522	NVME_LOG_DISCOVERY		= 0x70,
1523	/* 0x06-0x7F - reserved */
1524	/* 0x80-0xBF - I/O command set specific */
1525	NVME_LOG_RES_NOTIFICATION	= 0x80,
1526	NVME_LOG_SANITIZE_STATUS	= 0x81,
1527	/* 0x82-0xBF - reserved */
1528	/* 0xC0-0xFF - vendor specific */
1529
1530	/*
1531	 * The following are Intel Specific log pages, but they seem
1532	 * to be widely implemented.
1533	 */
1534	INTEL_LOG_READ_LAT_LOG		= 0xc1,
1535	INTEL_LOG_WRITE_LAT_LOG		= 0xc2,
1536	INTEL_LOG_TEMP_STATS		= 0xc5,
1537	INTEL_LOG_ADD_SMART		= 0xca,
1538	INTEL_LOG_DRIVE_MKT_NAME	= 0xdd,
1539
1540	/*
1541	 * HGST log page, with lots ofs sub pages.
1542	 */
1543	HGST_INFO_LOG			= 0xc1,
1544};
1545
1546struct nvme_error_information_entry {
1547	uint64_t		error_count;
1548	uint16_t		sqid;
1549	uint16_t		cid;
1550	uint16_t		status;
1551	uint16_t		error_location;
1552	uint64_t		lba;
1553	uint32_t		nsid;
1554	uint8_t			vendor_specific;
1555	uint8_t			trtype;
1556	uint16_t		reserved30;
1557	uint64_t		csi;
1558	uint16_t		ttsi;
1559	uint8_t			reserved[22];
1560} __packed __aligned(4);
1561
1562_Static_assert(sizeof(struct nvme_error_information_entry) == 64, "bad size for nvme_error_information_entry");
1563
1564struct nvme_health_information_page {
1565	uint8_t			critical_warning;
1566	uint16_t		temperature;
1567	uint8_t			available_spare;
1568	uint8_t			available_spare_threshold;
1569	uint8_t			percentage_used;
1570
1571	uint8_t			reserved[26];
1572
1573	/*
1574	 * Note that the following are 128-bit values, but are
1575	 *  defined as an array of 2 64-bit values.
1576	 */
1577	/* Data Units Read is always in 512-byte units. */
1578	uint64_t		data_units_read[2];
1579	/* Data Units Written is always in 512-byte units. */
1580	uint64_t		data_units_written[2];
1581	/* For NVM command set, this includes Compare commands. */
1582	uint64_t		host_read_commands[2];
1583	uint64_t		host_write_commands[2];
1584	/* Controller Busy Time is reported in minutes. */
1585	uint64_t		controller_busy_time[2];
1586	uint64_t		power_cycles[2];
1587	uint64_t		power_on_hours[2];
1588	uint64_t		unsafe_shutdowns[2];
1589	uint64_t		media_errors[2];
1590	uint64_t		num_error_info_log_entries[2];
1591	uint32_t		warning_temp_time;
1592	uint32_t		error_temp_time;
1593	uint16_t		temp_sensor[8];
1594	/* Thermal Management Temperature 1 Transition Count */
1595	uint32_t		tmt1tc;
1596	/* Thermal Management Temperature 2 Transition Count */
1597	uint32_t		tmt2tc;
1598	/* Total Time For Thermal Management Temperature 1 */
1599	uint32_t		ttftmt1;
1600	/* Total Time For Thermal Management Temperature 2 */
1601	uint32_t		ttftmt2;
1602
1603	uint8_t			reserved2[280];
1604} __packed __aligned(8);
1605
1606_Static_assert(sizeof(struct nvme_health_information_page) == 512, "bad size for nvme_health_information_page");
1607
1608struct nvme_firmware_page {
1609	uint8_t			afi;
1610	uint8_t			reserved[7];
1611	/* revisions for 7 slots */
1612	uint8_t			revision[7][NVME_FIRMWARE_REVISION_LENGTH];
1613	uint8_t			reserved2[448];
1614} __packed __aligned(4);
1615
1616_Static_assert(sizeof(struct nvme_firmware_page) == 512, "bad size for nvme_firmware_page");
1617
1618struct nvme_ns_list {
1619	uint32_t		ns[1024];
1620} __packed __aligned(4);
1621
1622_Static_assert(sizeof(struct nvme_ns_list) == 4096, "bad size for nvme_ns_list");
1623
1624struct nvme_command_effects_page {
1625	uint32_t		acs[256];
1626	uint32_t		iocs[256];
1627	uint8_t			reserved[2048];
1628} __packed __aligned(4);
1629
1630_Static_assert(sizeof(struct nvme_command_effects_page) == 4096,
1631    "bad size for nvme_command_effects_page");
1632
1633struct nvme_device_self_test_page {
1634	uint8_t			curr_operation;
1635	uint8_t			curr_compl;
1636	uint8_t			rsvd2[2];
1637	struct {
1638		uint8_t		status;
1639		uint8_t		segment_num;
1640		uint8_t		valid_diag_info;
1641		uint8_t		rsvd3;
1642		uint64_t	poh;
1643		uint32_t	nsid;
1644		/* Define as an array to simplify alignment issues */
1645		uint8_t		failing_lba[8];
1646		uint8_t		status_code_type;
1647		uint8_t		status_code;
1648		uint8_t		vendor_specific[2];
1649	} __packed result[20];
1650} __packed __aligned(4);
1651
1652_Static_assert(sizeof(struct nvme_device_self_test_page) == 564,
1653    "bad size for nvme_device_self_test_page");
1654
1655/*
1656 * Header structure for both host initiated telemetry (page 7) and controller
1657 * initiated telemetry (page 8).
1658 */
1659struct nvme_telemetry_log_page {
1660	uint8_t			identifier;
1661	uint8_t			rsvd[4];
1662	uint8_t			oui[3];
1663	uint16_t		da1_last;
1664	uint16_t		da2_last;
1665	uint16_t		da3_last;
1666	uint8_t			rsvd2[2];
1667	uint32_t		da4_last;
1668	uint8_t			rsvd3[361];
1669	uint8_t			hi_gen;
1670	uint8_t			ci_avail;
1671	uint8_t			ci_gen;
1672	uint8_t			reason[128];
1673	/* Blocks of telemetry data follow */
1674} __packed __aligned(4);
1675
1676_Static_assert(sizeof(struct nvme_telemetry_log_page) == 512,
1677    "bad size for nvme_telemetry_log");
1678
1679struct nvme_discovery_log_entry {
1680	uint8_t			trtype;
1681	uint8_t			adrfam;
1682	uint8_t			subtype;
1683	uint8_t			treq;
1684	uint16_t		portid;
1685	uint16_t		cntlid;
1686	uint16_t		aqsz;
1687	uint8_t			reserved1[22];
1688	uint8_t			trsvcid[32];
1689	uint8_t			reserved2[192];
1690	uint8_t			subnqn[256];
1691	uint8_t			traddr[256];
1692	union {
1693		struct {
1694			uint8_t	rdma_qptype;
1695			uint8_t	rdma_prtype;
1696			uint8_t	rdma_cms;
1697			uint8_t	reserved[5];
1698			uint16_t rdma_pkey;
1699		} rdma;
1700		struct {
1701			uint8_t	sectype;
1702		} tcp;
1703		uint8_t		reserved[256];
1704	} tsas;
1705} __packed __aligned(4);
1706
1707_Static_assert(sizeof(struct nvme_discovery_log_entry) == 1024,
1708    "bad size for nvme_discovery_log_entry");
1709
1710struct nvme_discovery_log {
1711	uint64_t		genctr;
1712	uint64_t		numrec;
1713	uint16_t		recfmt;
1714	uint8_t			reserved[1006];
1715	struct nvme_discovery_log_entry entries[];
1716} __packed __aligned(4);
1717
1718_Static_assert(sizeof(struct nvme_discovery_log) == 1024,
1719    "bad size for nvme_discovery_log");
1720
1721struct nvme_res_notification_page {
1722	uint64_t		log_page_count;
1723	uint8_t			log_page_type;
1724	uint8_t			available_log_pages;
1725	uint8_t			reserved2;
1726	uint32_t		nsid;
1727	uint8_t			reserved[48];
1728} __packed __aligned(4);
1729
1730_Static_assert(sizeof(struct nvme_res_notification_page) == 64,
1731    "bad size for nvme_res_notification_page");
1732
1733struct nvme_sanitize_status_page {
1734	uint16_t		sprog;
1735	uint16_t		sstat;
1736	uint32_t		scdw10;
1737	uint32_t		etfo;
1738	uint32_t		etfbe;
1739	uint32_t		etfce;
1740	uint32_t		etfownd;
1741	uint32_t		etfbewnd;
1742	uint32_t		etfcewnd;
1743	uint8_t			reserved[480];
1744} __packed __aligned(4);
1745
1746_Static_assert(sizeof(struct nvme_sanitize_status_page) == 512,
1747    "bad size for nvme_sanitize_status_page");
1748
1749struct intel_log_temp_stats {
1750	uint64_t	current;
1751	uint64_t	overtemp_flag_last;
1752	uint64_t	overtemp_flag_life;
1753	uint64_t	max_temp;
1754	uint64_t	min_temp;
1755	uint64_t	_rsvd[5];
1756	uint64_t	max_oper_temp;
1757	uint64_t	min_oper_temp;
1758	uint64_t	est_offset;
1759} __packed __aligned(4);
1760
1761_Static_assert(sizeof(struct intel_log_temp_stats) == 13 * 8, "bad size for intel_log_temp_stats");
1762
1763struct nvme_resv_reg_ctrlr {
1764	uint16_t		ctrlr_id;	/* Controller ID */
1765	uint8_t			rcsts;		/* Reservation Status */
1766	uint8_t			reserved3[5];
1767	uint64_t		hostid;		/* Host Identifier */
1768	uint64_t		rkey;		/* Reservation Key */
1769} __packed __aligned(4);
1770
1771_Static_assert(sizeof(struct nvme_resv_reg_ctrlr) == 24, "bad size for nvme_resv_reg_ctrlr");
1772
1773struct nvme_resv_reg_ctrlr_ext {
1774	uint16_t		ctrlr_id;	/* Controller ID */
1775	uint8_t			rcsts;		/* Reservation Status */
1776	uint8_t			reserved3[5];
1777	uint64_t		rkey;		/* Reservation Key */
1778	uint64_t		hostid[2];	/* Host Identifier */
1779	uint8_t			reserved32[32];
1780} __packed __aligned(4);
1781
1782_Static_assert(sizeof(struct nvme_resv_reg_ctrlr_ext) == 64, "bad size for nvme_resv_reg_ctrlr_ext");
1783
1784struct nvme_resv_status {
1785	uint32_t		gen;		/* Generation */
1786	uint8_t			rtype;		/* Reservation Type */
1787	uint8_t			regctl[2];	/* Number of Registered Controllers */
1788	uint8_t			reserved7[2];
1789	uint8_t			ptpls;		/* Persist Through Power Loss State */
1790	uint8_t			reserved10[14];
1791	struct nvme_resv_reg_ctrlr	ctrlr[0];
1792} __packed __aligned(4);
1793
1794_Static_assert(sizeof(struct nvme_resv_status) == 24, "bad size for nvme_resv_status");
1795
1796struct nvme_resv_status_ext {
1797	uint32_t		gen;		/* Generation */
1798	uint8_t			rtype;		/* Reservation Type */
1799	uint8_t			regctl[2];	/* Number of Registered Controllers */
1800	uint8_t			reserved7[2];
1801	uint8_t			ptpls;		/* Persist Through Power Loss State */
1802	uint8_t			reserved10[14];
1803	uint8_t			reserved24[40];
1804	struct nvme_resv_reg_ctrlr_ext	ctrlr[0];
1805} __packed __aligned(4);
1806
1807_Static_assert(sizeof(struct nvme_resv_status_ext) == 64, "bad size for nvme_resv_status_ext");
1808
1809#define NVME_TEST_MAX_THREADS	128
1810
1811struct nvme_io_test {
1812	enum nvme_nvm_opcode	opc;
1813	uint32_t		size;
1814	uint32_t		time;	/* in seconds */
1815	uint32_t		num_threads;
1816	uint32_t		flags;
1817	uint64_t		io_completed[NVME_TEST_MAX_THREADS];
1818};
1819
1820enum nvme_io_test_flags {
1821	/*
1822	 * Specifies whether dev_refthread/dev_relthread should be
1823	 *  called during NVME_BIO_TEST.  Ignored for other test
1824	 *  types.
1825	 */
1826	NVME_TEST_FLAG_REFTHREAD =	0x1,
1827};
1828
1829struct nvme_pt_command {
1830	/*
1831	 * cmd is used to specify a passthrough command to a controller or
1832	 *  namespace.
1833	 *
1834	 * The following fields from cmd may be specified by the caller:
1835	 *	* opc  (opcode)
1836	 *	* nsid (namespace id) - for admin commands only
1837	 *	* cdw10-cdw15
1838	 *
1839	 * Remaining fields must be set to 0 by the caller.
1840	 */
1841	struct nvme_command	cmd;
1842
1843	/*
1844	 * cpl returns completion status for the passthrough command
1845	 *  specified by cmd.
1846	 *
1847	 * The following fields will be filled out by the driver, for
1848	 *  consumption by the caller:
1849	 *	* cdw0
1850	 *	* status (except for phase)
1851	 *
1852	 * Remaining fields will be set to 0 by the driver.
1853	 */
1854	struct nvme_completion	cpl;
1855
1856	/* buf is the data buffer associated with this passthrough command. */
1857	void *			buf;
1858
1859	/*
1860	 * len is the length of the data buffer associated with this
1861	 *  passthrough command.
1862	 */
1863	uint32_t		len;
1864
1865	/*
1866	 * is_read = 1 if the passthrough command will read data into the
1867	 *  supplied buffer from the controller.
1868	 *
1869	 * is_read = 0 if the passthrough command will write data from the
1870	 *  supplied buffer to the controller.
1871	 */
1872	uint32_t		is_read;
1873
1874	/*
1875	 * driver_lock is used by the driver only.  It must be set to 0
1876	 *  by the caller.
1877	 */
1878	struct mtx *		driver_lock;
1879};
1880
1881struct nvme_get_nsid {
1882	char		cdev[SPECNAMELEN + 1];
1883	uint32_t	nsid;
1884};
1885
1886struct nvme_hmb_desc {
1887	uint64_t	addr;
1888	uint32_t	size;
1889	uint32_t	reserved;
1890};
1891
1892#define nvme_completion_is_error(cpl)					\
1893	(NVME_STATUS_GET_SC((cpl)->status) != 0 || NVME_STATUS_GET_SCT((cpl)->status) != 0)
1894
1895void	nvme_strvis(uint8_t *dst, const uint8_t *src, int dstlen, int srclen);
1896
1897#ifdef _KERNEL
1898
1899struct bio;
1900struct thread;
1901
1902struct nvme_namespace;
1903struct nvme_controller;
1904struct nvme_consumer;
1905
1906typedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *);
1907
1908typedef void *(*nvme_cons_ns_fn_t)(struct nvme_namespace *, void *);
1909typedef void *(*nvme_cons_ctrlr_fn_t)(struct nvme_controller *);
1910typedef void (*nvme_cons_async_fn_t)(void *, const struct nvme_completion *,
1911				     uint32_t, void *, uint32_t);
1912typedef void (*nvme_cons_fail_fn_t)(void *);
1913
1914enum nvme_namespace_flags {
1915	NVME_NS_DEALLOCATE_SUPPORTED	= 0x1,
1916	NVME_NS_FLUSH_SUPPORTED		= 0x2,
1917};
1918
1919int	nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr,
1920				   struct nvme_pt_command *pt,
1921				   uint32_t nsid, int is_user_buffer,
1922				   int is_admin_cmd);
1923
1924/* Admin functions */
1925void	nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr,
1926				   uint8_t feature, uint32_t cdw11,
1927				   uint32_t cdw12, uint32_t cdw13,
1928				   uint32_t cdw14, uint32_t cdw15,
1929				   void *payload, uint32_t payload_size,
1930				   nvme_cb_fn_t cb_fn, void *cb_arg);
1931void	nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr,
1932				   uint8_t feature, uint32_t cdw11,
1933				   void *payload, uint32_t payload_size,
1934				   nvme_cb_fn_t cb_fn, void *cb_arg);
1935void	nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr,
1936				    uint8_t log_page, uint32_t nsid,
1937				    void *payload, uint32_t payload_size,
1938				    nvme_cb_fn_t cb_fn, void *cb_arg);
1939
1940/* NVM I/O functions */
1941int	nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload,
1942			  uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
1943			  void *cb_arg);
1944int	nvme_ns_cmd_write_bio(struct nvme_namespace *ns, struct bio *bp,
1945			      nvme_cb_fn_t cb_fn, void *cb_arg);
1946int	nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload,
1947			 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
1948			 void *cb_arg);
1949int	nvme_ns_cmd_read_bio(struct nvme_namespace *ns, struct bio *bp,
1950			      nvme_cb_fn_t cb_fn, void *cb_arg);
1951int	nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload,
1952			       uint8_t num_ranges, nvme_cb_fn_t cb_fn,
1953			       void *cb_arg);
1954int	nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn,
1955			  void *cb_arg);
1956int	nvme_ns_dump(struct nvme_namespace *ns, void *virt, off_t offset,
1957		     size_t len);
1958
1959/* Registration functions */
1960struct nvme_consumer *	nvme_register_consumer(nvme_cons_ns_fn_t    ns_fn,
1961					       nvme_cons_ctrlr_fn_t ctrlr_fn,
1962					       nvme_cons_async_fn_t async_fn,
1963					       nvme_cons_fail_fn_t  fail_fn);
1964void		nvme_unregister_consumer(struct nvme_consumer *consumer);
1965
1966/* Controller helper functions */
1967device_t	nvme_ctrlr_get_device(struct nvme_controller *ctrlr);
1968const struct nvme_controller_data *
1969		nvme_ctrlr_get_data(struct nvme_controller *ctrlr);
1970static inline bool
1971nvme_ctrlr_has_dataset_mgmt(const struct nvme_controller_data *cd)
1972{
1973	/* Assumes cd was byte swapped by nvme_controller_data_swapbytes() */
1974	return (NVMEV(NVME_CTRLR_DATA_ONCS_DSM, cd->oncs) != 0);
1975}
1976
1977/* Namespace helper functions */
1978uint32_t	nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns);
1979uint32_t	nvme_ns_get_sector_size(struct nvme_namespace *ns);
1980uint64_t	nvme_ns_get_num_sectors(struct nvme_namespace *ns);
1981uint64_t	nvme_ns_get_size(struct nvme_namespace *ns);
1982uint32_t	nvme_ns_get_flags(struct nvme_namespace *ns);
1983const char *	nvme_ns_get_serial_number(struct nvme_namespace *ns);
1984const char *	nvme_ns_get_model_number(struct nvme_namespace *ns);
1985const struct nvme_namespace_data *
1986		nvme_ns_get_data(struct nvme_namespace *ns);
1987uint32_t	nvme_ns_get_stripesize(struct nvme_namespace *ns);
1988
1989int	nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp,
1990			    nvme_cb_fn_t cb_fn);
1991int	nvme_ns_ioctl_process(struct nvme_namespace *ns, u_long cmd,
1992    caddr_t arg, int flag, struct thread *td);
1993
1994/*
1995 * Command building helper functions -- shared with CAM
1996 * These functions assume allocator zeros out cmd structure
1997 * CAM's xpt_get_ccb and the request allocator for nvme both
1998 * do zero'd allocations.
1999 */
2000static inline
2001void	nvme_ns_flush_cmd(struct nvme_command *cmd, uint32_t nsid)
2002{
2003
2004	cmd->opc = NVME_OPC_FLUSH;
2005	cmd->nsid = htole32(nsid);
2006}
2007
2008static inline
2009void	nvme_ns_rw_cmd(struct nvme_command *cmd, uint32_t rwcmd, uint32_t nsid,
2010    uint64_t lba, uint32_t count)
2011{
2012	cmd->opc = rwcmd;
2013	cmd->nsid = htole32(nsid);
2014	cmd->cdw10 = htole32(lba & 0xffffffffu);
2015	cmd->cdw11 = htole32(lba >> 32);
2016	cmd->cdw12 = htole32(count-1);
2017}
2018
2019static inline
2020void	nvme_ns_write_cmd(struct nvme_command *cmd, uint32_t nsid,
2021    uint64_t lba, uint32_t count)
2022{
2023	nvme_ns_rw_cmd(cmd, NVME_OPC_WRITE, nsid, lba, count);
2024}
2025
2026static inline
2027void	nvme_ns_read_cmd(struct nvme_command *cmd, uint32_t nsid,
2028    uint64_t lba, uint32_t count)
2029{
2030	nvme_ns_rw_cmd(cmd, NVME_OPC_READ, nsid, lba, count);
2031}
2032
2033static inline
2034void	nvme_ns_trim_cmd(struct nvme_command *cmd, uint32_t nsid,
2035    uint32_t num_ranges)
2036{
2037	cmd->opc = NVME_OPC_DATASET_MANAGEMENT;
2038	cmd->nsid = htole32(nsid);
2039	cmd->cdw10 = htole32(num_ranges - 1);
2040	cmd->cdw11 = htole32(NVME_DSM_ATTR_DEALLOCATE);
2041}
2042
2043extern int nvme_use_nvd;
2044
2045#endif /* _KERNEL */
2046
2047/* Endianess conversion functions for NVMe structs */
2048static inline
2049void	nvme_completion_swapbytes(struct nvme_completion *s __unused)
2050{
2051#if _BYTE_ORDER != _LITTLE_ENDIAN
2052
2053	s->cdw0 = le32toh(s->cdw0);
2054	/* omit rsvd1 */
2055	s->sqhd = le16toh(s->sqhd);
2056	s->sqid = le16toh(s->sqid);
2057	/* omit cid */
2058	s->status = le16toh(s->status);
2059#endif
2060}
2061
2062static inline
2063void	nvme_power_state_swapbytes(struct nvme_power_state *s __unused)
2064{
2065#if _BYTE_ORDER != _LITTLE_ENDIAN
2066
2067	s->mp = le16toh(s->mp);
2068	s->enlat = le32toh(s->enlat);
2069	s->exlat = le32toh(s->exlat);
2070	s->idlp = le16toh(s->idlp);
2071	s->actp = le16toh(s->actp);
2072#endif
2073}
2074
2075static inline
2076void	nvme_controller_data_swapbytes(struct nvme_controller_data *s __unused)
2077{
2078#if _BYTE_ORDER != _LITTLE_ENDIAN
2079	int i;
2080
2081	s->vid = le16toh(s->vid);
2082	s->ssvid = le16toh(s->ssvid);
2083	s->ctrlr_id = le16toh(s->ctrlr_id);
2084	s->ver = le32toh(s->ver);
2085	s->rtd3r = le32toh(s->rtd3r);
2086	s->rtd3e = le32toh(s->rtd3e);
2087	s->oaes = le32toh(s->oaes);
2088	s->ctratt = le32toh(s->ctratt);
2089	s->rrls = le16toh(s->rrls);
2090	s->crdt1 = le16toh(s->crdt1);
2091	s->crdt2 = le16toh(s->crdt2);
2092	s->crdt3 = le16toh(s->crdt3);
2093	s->oacs = le16toh(s->oacs);
2094	s->wctemp = le16toh(s->wctemp);
2095	s->cctemp = le16toh(s->cctemp);
2096	s->mtfa = le16toh(s->mtfa);
2097	s->hmpre = le32toh(s->hmpre);
2098	s->hmmin = le32toh(s->hmmin);
2099	s->rpmbs = le32toh(s->rpmbs);
2100	s->edstt = le16toh(s->edstt);
2101	s->kas = le16toh(s->kas);
2102	s->hctma = le16toh(s->hctma);
2103	s->mntmt = le16toh(s->mntmt);
2104	s->mxtmt = le16toh(s->mxtmt);
2105	s->sanicap = le32toh(s->sanicap);
2106	s->hmminds = le32toh(s->hmminds);
2107	s->hmmaxd = le16toh(s->hmmaxd);
2108	s->nsetidmax = le16toh(s->nsetidmax);
2109	s->endgidmax = le16toh(s->endgidmax);
2110	s->anagrpmax = le32toh(s->anagrpmax);
2111	s->nanagrpid = le32toh(s->nanagrpid);
2112	s->pels = le32toh(s->pels);
2113	s->maxcmd = le16toh(s->maxcmd);
2114	s->nn = le32toh(s->nn);
2115	s->oncs = le16toh(s->oncs);
2116	s->fuses = le16toh(s->fuses);
2117	s->awun = le16toh(s->awun);
2118	s->awupf = le16toh(s->awupf);
2119	s->acwu = le16toh(s->acwu);
2120	s->sgls = le32toh(s->sgls);
2121	s->mnan = le32toh(s->mnan);
2122	s->ioccsz = le32toh(s->ioccsz);
2123	s->iorcsz = le32toh(s->iorcsz);
2124	s->icdoff = le16toh(s->icdoff);
2125	s->ofcs = le16toh(s->ofcs);
2126	for (i = 0; i < 32; i++)
2127		nvme_power_state_swapbytes(&s->power_state[i]);
2128#endif
2129}
2130
2131static inline
2132void	nvme_namespace_data_swapbytes(struct nvme_namespace_data *s __unused)
2133{
2134#if _BYTE_ORDER != _LITTLE_ENDIAN
2135	int i;
2136
2137	s->nsze = le64toh(s->nsze);
2138	s->ncap = le64toh(s->ncap);
2139	s->nuse = le64toh(s->nuse);
2140	s->nawun = le16toh(s->nawun);
2141	s->nawupf = le16toh(s->nawupf);
2142	s->nacwu = le16toh(s->nacwu);
2143	s->nabsn = le16toh(s->nabsn);
2144	s->nabo = le16toh(s->nabo);
2145	s->nabspf = le16toh(s->nabspf);
2146	s->noiob = le16toh(s->noiob);
2147	s->npwg = le16toh(s->npwg);
2148	s->npwa = le16toh(s->npwa);
2149	s->npdg = le16toh(s->npdg);
2150	s->npda = le16toh(s->npda);
2151	s->nows = le16toh(s->nows);
2152	s->anagrpid = le32toh(s->anagrpid);
2153	s->nvmsetid = le16toh(s->nvmsetid);
2154	s->endgid = le16toh(s->endgid);
2155	for (i = 0; i < 16; i++)
2156		s->lbaf[i] = le32toh(s->lbaf[i]);
2157#endif
2158}
2159
2160static inline
2161void	nvme_error_information_entry_swapbytes(
2162    struct nvme_error_information_entry *s __unused)
2163{
2164#if _BYTE_ORDER != _LITTLE_ENDIAN
2165
2166	s->error_count = le64toh(s->error_count);
2167	s->sqid = le16toh(s->sqid);
2168	s->cid = le16toh(s->cid);
2169	s->status = le16toh(s->status);
2170	s->error_location = le16toh(s->error_location);
2171	s->lba = le64toh(s->lba);
2172	s->nsid = le32toh(s->nsid);
2173	s->csi = le64toh(s->csi);
2174	s->ttsi = le16toh(s->ttsi);
2175#endif
2176}
2177
2178static inline
2179void	nvme_le128toh(void *p __unused)
2180{
2181#if _BYTE_ORDER != _LITTLE_ENDIAN
2182	/* Swap 16 bytes in place */
2183	char *tmp = (char*)p;
2184	char b;
2185	int i;
2186	for (i = 0; i < 8; i++) {
2187		b = tmp[i];
2188		tmp[i] = tmp[15-i];
2189		tmp[15-i] = b;
2190	}
2191#endif
2192}
2193
2194static inline
2195void	nvme_health_information_page_swapbytes(
2196    struct nvme_health_information_page *s __unused)
2197{
2198#if _BYTE_ORDER != _LITTLE_ENDIAN
2199	int i;
2200
2201	s->temperature = le16toh(s->temperature);
2202	nvme_le128toh((void *)s->data_units_read);
2203	nvme_le128toh((void *)s->data_units_written);
2204	nvme_le128toh((void *)s->host_read_commands);
2205	nvme_le128toh((void *)s->host_write_commands);
2206	nvme_le128toh((void *)s->controller_busy_time);
2207	nvme_le128toh((void *)s->power_cycles);
2208	nvme_le128toh((void *)s->power_on_hours);
2209	nvme_le128toh((void *)s->unsafe_shutdowns);
2210	nvme_le128toh((void *)s->media_errors);
2211	nvme_le128toh((void *)s->num_error_info_log_entries);
2212	s->warning_temp_time = le32toh(s->warning_temp_time);
2213	s->error_temp_time = le32toh(s->error_temp_time);
2214	for (i = 0; i < 8; i++)
2215		s->temp_sensor[i] = le16toh(s->temp_sensor[i]);
2216	s->tmt1tc = le32toh(s->tmt1tc);
2217	s->tmt2tc = le32toh(s->tmt2tc);
2218	s->ttftmt1 = le32toh(s->ttftmt1);
2219	s->ttftmt2 = le32toh(s->ttftmt2);
2220#endif
2221}
2222
2223static inline
2224void	nvme_ns_list_swapbytes(struct nvme_ns_list *s __unused)
2225{
2226#if _BYTE_ORDER != _LITTLE_ENDIAN
2227	int i;
2228
2229	for (i = 0; i < 1024; i++)
2230		s->ns[i] = le32toh(s->ns[i]);
2231#endif
2232}
2233
2234static inline
2235void	nvme_command_effects_page_swapbytes(
2236    struct nvme_command_effects_page *s __unused)
2237{
2238#if _BYTE_ORDER != _LITTLE_ENDIAN
2239	int i;
2240
2241	for (i = 0; i < 256; i++)
2242		s->acs[i] = le32toh(s->acs[i]);
2243	for (i = 0; i < 256; i++)
2244		s->iocs[i] = le32toh(s->iocs[i]);
2245#endif
2246}
2247
2248static inline
2249void	nvme_res_notification_page_swapbytes(
2250    struct nvme_res_notification_page *s __unused)
2251{
2252#if _BYTE_ORDER != _LITTLE_ENDIAN
2253	s->log_page_count = le64toh(s->log_page_count);
2254	s->nsid = le32toh(s->nsid);
2255#endif
2256}
2257
2258static inline
2259void	nvme_sanitize_status_page_swapbytes(
2260    struct nvme_sanitize_status_page *s __unused)
2261{
2262#if _BYTE_ORDER != _LITTLE_ENDIAN
2263	s->sprog = le16toh(s->sprog);
2264	s->sstat = le16toh(s->sstat);
2265	s->scdw10 = le32toh(s->scdw10);
2266	s->etfo = le32toh(s->etfo);
2267	s->etfbe = le32toh(s->etfbe);
2268	s->etfce = le32toh(s->etfce);
2269	s->etfownd = le32toh(s->etfownd);
2270	s->etfbewnd = le32toh(s->etfbewnd);
2271	s->etfcewnd = le32toh(s->etfcewnd);
2272#endif
2273}
2274
2275static inline
2276void	nvme_resv_status_swapbytes(struct nvme_resv_status *s __unused,
2277    size_t size __unused)
2278{
2279#if _BYTE_ORDER != _LITTLE_ENDIAN
2280	size_t i, n;
2281
2282	s->gen = le32toh(s->gen);
2283	n = (s->regctl[1] << 8) | s->regctl[0];
2284	n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0]));
2285	for (i = 0; i < n; i++) {
2286		s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id);
2287		s->ctrlr[i].hostid = le64toh(s->ctrlr[i].hostid);
2288		s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey);
2289	}
2290#endif
2291}
2292
2293static inline
2294void	nvme_resv_status_ext_swapbytes(struct nvme_resv_status_ext *s __unused,
2295    size_t size __unused)
2296{
2297#if _BYTE_ORDER != _LITTLE_ENDIAN
2298	size_t i, n;
2299
2300	s->gen = le32toh(s->gen);
2301	n = (s->regctl[1] << 8) | s->regctl[0];
2302	n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0]));
2303	for (i = 0; i < n; i++) {
2304		s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id);
2305		s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey);
2306		nvme_le128toh((void *)s->ctrlr[i].hostid);
2307	}
2308#endif
2309}
2310
2311static inline void
2312nvme_device_self_test_swapbytes(struct nvme_device_self_test_page *s __unused)
2313{
2314#if _BYTE_ORDER != _LITTLE_ENDIAN
2315	uint8_t *tmp;
2316	uint32_t r, i;
2317	uint8_t b;
2318
2319	for (r = 0; r < 20; r++) {
2320		s->result[r].poh = le64toh(s->result[r].poh);
2321		s->result[r].nsid = le32toh(s->result[r].nsid);
2322		/* Unaligned 64-bit loads fail on some architectures */
2323		tmp = s->result[r].failing_lba;
2324		for (i = 0; i < 4; i++) {
2325			b = tmp[i];
2326			tmp[i] = tmp[7-i];
2327			tmp[7-i] = b;
2328		}
2329	}
2330#endif
2331}
2332
2333static inline void
2334nvme_discovery_log_entry_swapbytes(struct nvme_discovery_log_entry *s __unused)
2335{
2336#if _BYTE_ORDER != _LITTLE_ENDIAN
2337	s->portid = le16toh(s->portid);
2338	s->cntlid = le16toh(s->cntlid);
2339	s->aqsz = le16toh(s->aqsz);
2340	if (s->trtype == 0x01 /* RDMA */) {
2341		s->tsas.rdma.rdma_pkey = le16toh(s->tsas.rdma.rdma_pkey);
2342	}
2343#endif
2344}
2345
2346static inline void
2347nvme_discovery_log_swapbytes(struct nvme_discovery_log *s __unused)
2348{
2349#if _BYTE_ORDER != _LITTLE_ENDIAN
2350	s->genctr = le64toh(s->genctr);
2351	s->numrec = le64toh(s->numrec);
2352	s->recfmt = le16toh(s->recfmt);
2353#endif
2354}
2355#endif /* __NVME_H__ */
2356