1/******************************************************************************* 2SPDX-License-Identifier: BSD-2-Clause 3 4Copyright (c) 2006-2009, Myricom Inc. 5All rights reserved. 6 7Redistribution and use in source and binary forms, with or without 8modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Neither the name of the Myricom Inc, nor the names of its 14 contributors may be used to endorse or promote products derived from 15 this software without specific prior written permission. 16 17THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27POSSIBILITY OF SUCH DAMAGE. 28***************************************************************************/ 29 30#ifndef _myri10ge_mcp_h 31#define _myri10ge_mcp_h 32 33#define MXGEFW_VERSION_MAJOR 1 34#define MXGEFW_VERSION_MINOR 4 35 36#if defined MXGEFW && !defined _stdint_h_ 37typedef signed char int8_t; 38typedef signed short int16_t; 39typedef signed int int32_t; 40typedef signed long long int64_t; 41typedef unsigned char uint8_t; 42typedef unsigned short uint16_t; 43typedef unsigned int uint32_t; 44typedef unsigned long long uint64_t; 45#endif 46 47/* 8 Bytes */ 48struct mcp_dma_addr { 49 uint32_t high; 50 uint32_t low; 51}; 52typedef struct mcp_dma_addr mcp_dma_addr_t; 53 54/* 4 Bytes */ 55struct mcp_slot { 56 uint16_t checksum; 57 uint16_t length; 58}; 59typedef struct mcp_slot mcp_slot_t; 60 61#ifdef MXGEFW_NDIS 62/* 8-byte descriptor, exclusively used by NDIS drivers. */ 63struct mcp_slot_8 { 64 /* Place hash value at the top so it gets written before length. 65 * The driver polls length. 66 */ 67 uint32_t hash; 68 uint16_t checksum; 69 uint16_t length; 70}; 71typedef struct mcp_slot_8 mcp_slot_8_t; 72 73/* Two bits of length in mcp_slot are used to indicate hash type. */ 74#define MXGEFW_RSS_HASH_NULL (0 << 14) /* bit 15:14 = 00 */ 75#define MXGEFW_RSS_HASH_IPV4 (1 << 14) /* bit 15:14 = 01 */ 76#define MXGEFW_RSS_HASH_TCP_IPV4 (2 << 14) /* bit 15:14 = 10 */ 77#define MXGEFW_RSS_HASH_MASK (3 << 14) /* bit 15:14 = 11 */ 78#endif 79 80/* 64 Bytes */ 81struct mcp_cmd { 82 uint32_t cmd; 83 uint32_t data0; /* will be low portion if data > 32 bits */ 84 /* 8 */ 85 uint32_t data1; /* will be high portion if data > 32 bits */ 86 uint32_t data2; /* currently unused.. */ 87 /* 16 */ 88 struct mcp_dma_addr response_addr; 89 /* 24 */ 90 uint8_t pad[40]; 91}; 92typedef struct mcp_cmd mcp_cmd_t; 93 94/* 8 Bytes */ 95struct mcp_cmd_response { 96 uint32_t data; 97 uint32_t result; 98}; 99typedef struct mcp_cmd_response mcp_cmd_response_t; 100 101/* 102 flags used in mcp_kreq_ether_send_t: 103 104 The SMALL flag is only needed in the first segment. It is raised 105 for packets that are total less or equal 512 bytes. 106 107 The CKSUM flag must be set in all segments. 108 109 The PADDED flags is set if the packet needs to be padded, and it 110 must be set for all segments. 111 112 The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative 113 length of all previous segments was odd. 114*/ 115 116#define MXGEFW_FLAGS_SMALL 0x1 117#define MXGEFW_FLAGS_TSO_HDR 0x1 118#define MXGEFW_FLAGS_FIRST 0x2 119#define MXGEFW_FLAGS_ALIGN_ODD 0x4 120#define MXGEFW_FLAGS_CKSUM 0x8 121#define MXGEFW_FLAGS_TSO_LAST 0x8 122#define MXGEFW_FLAGS_NO_TSO 0x10 123#define MXGEFW_FLAGS_TSO_CHOP 0x10 124#define MXGEFW_FLAGS_TSO_PLD 0x20 125 126#define MXGEFW_SEND_SMALL_SIZE 1520 127#define MXGEFW_MAX_MTU 9400 128 129union mcp_pso_or_cumlen { 130 uint16_t pseudo_hdr_offset; 131 uint16_t cum_len; 132}; 133typedef union mcp_pso_or_cumlen mcp_pso_or_cumlen_t; 134 135#define MXGEFW_MAX_SEND_DESC 12 136#define MXGEFW_PAD 2 137 138/* 16 Bytes */ 139struct mcp_kreq_ether_send { 140 uint32_t addr_high; 141 uint32_t addr_low; 142 uint16_t pseudo_hdr_offset; 143 uint16_t length; 144 uint8_t pad; 145 uint8_t rdma_count; 146 uint8_t cksum_offset; /* where to start computing cksum */ 147 uint8_t flags; /* as defined above */ 148}; 149typedef struct mcp_kreq_ether_send mcp_kreq_ether_send_t; 150 151/* 8 Bytes */ 152struct mcp_kreq_ether_recv { 153 uint32_t addr_high; 154 uint32_t addr_low; 155}; 156typedef struct mcp_kreq_ether_recv mcp_kreq_ether_recv_t; 157 158/* Commands */ 159 160#define MXGEFW_BOOT_HANDOFF 0xfc0000 161#define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0 162 163#define MXGEFW_ETH_CMD 0xf80000 164#define MXGEFW_ETH_SEND_4 0x200000 165#define MXGEFW_ETH_SEND_1 0x240000 166#define MXGEFW_ETH_SEND_2 0x280000 167#define MXGEFW_ETH_SEND_3 0x2c0000 168#define MXGEFW_ETH_RECV_SMALL 0x300000 169#define MXGEFW_ETH_RECV_BIG 0x340000 170#define MXGEFW_ETH_SEND_GO 0x380000 171#define MXGEFW_ETH_SEND_STOP 0x3C0000 172 173#define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000)) 174#define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4) 175 176enum myri10ge_mcp_cmd_type { 177 MXGEFW_CMD_NONE = 0, 178 /* Reset the mcp, it is left in a safe state, waiting 179 for the driver to set all its parameters */ 180 MXGEFW_CMD_RESET = 1, 181 182 /* get the version number of the current firmware.. 183 (may be available in the eeprom strings..? */ 184 MXGEFW_GET_MCP_VERSION = 2, 185 186 /* Parameters which must be set by the driver before it can 187 issue MXGEFW_CMD_ETHERNET_UP. They persist until the next 188 MXGEFW_CMD_RESET is issued */ 189 190 MXGEFW_CMD_SET_INTRQ_DMA = 3, 191 /* data0 = LSW of the host address 192 * data1 = MSW of the host address 193 * data2 = slice number if multiple slices are used 194 */ 195 196 MXGEFW_CMD_SET_BIG_BUFFER_SIZE = 4, /* in bytes, power of 2 */ 197 MXGEFW_CMD_SET_SMALL_BUFFER_SIZE = 5, /* in bytes */ 198 199 200 /* Parameters which refer to lanai SRAM addresses where the 201 driver must issue PIO writes for various things */ 202 203 MXGEFW_CMD_GET_SEND_OFFSET = 6, 204 MXGEFW_CMD_GET_SMALL_RX_OFFSET = 7, 205 MXGEFW_CMD_GET_BIG_RX_OFFSET = 8, 206 /* data0 = slice number if multiple slices are used */ 207 208 MXGEFW_CMD_GET_IRQ_ACK_OFFSET = 9, 209 MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET = 10, 210 211 /* Parameters which refer to rings stored on the MCP, 212 and whose size is controlled by the mcp */ 213 214 MXGEFW_CMD_GET_SEND_RING_SIZE = 11, /* in bytes */ 215 MXGEFW_CMD_GET_RX_RING_SIZE = 12, /* in bytes */ 216 217 /* Parameters which refer to rings stored in the host, 218 and whose size is controlled by the host. Note that 219 all must be physically contiguous and must contain 220 a power of 2 number of entries. */ 221 222 MXGEFW_CMD_SET_INTRQ_SIZE = 13, /* in bytes */ 223#define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK (1U << 31) 224 225 /* command to bring ethernet interface up. Above parameters 226 (plus mtu & mac address) must have been exchanged prior 227 to issuing this command */ 228 MXGEFW_CMD_ETHERNET_UP = 14, 229 230 /* command to bring ethernet interface down. No further sends 231 or receives may be processed until an MXGEFW_CMD_ETHERNET_UP 232 is issued, and all interrupt queues must be flushed prior 233 to ack'ing this command */ 234 235 MXGEFW_CMD_ETHERNET_DOWN = 15, 236 237 /* commands the driver may issue live, without resetting 238 the nic. Note that increasing the mtu "live" should 239 only be done if the driver has already supplied buffers 240 sufficiently large to handle the new mtu. Decreasing 241 the mtu live is safe */ 242 243 MXGEFW_CMD_SET_MTU = 16, 244 MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET = 17, /* in microseconds */ 245 MXGEFW_CMD_SET_STATS_INTERVAL = 18, /* in microseconds */ 246 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE = 19, /* replaced by SET_STATS_DMA_V2 */ 247 248 MXGEFW_ENABLE_PROMISC = 20, 249 MXGEFW_DISABLE_PROMISC = 21, 250 MXGEFW_SET_MAC_ADDRESS = 22, 251 252 MXGEFW_ENABLE_FLOW_CONTROL = 23, 253 MXGEFW_DISABLE_FLOW_CONTROL = 24, 254 255 /* do a DMA test 256 data0,data1 = DMA address 257 data2 = RDMA length (MSH), WDMA length (LSH) 258 command return data = repetitions (MSH), 0.5-ms ticks (LSH) 259 */ 260 MXGEFW_DMA_TEST = 25, 261 262 MXGEFW_ENABLE_ALLMULTI = 26, 263 MXGEFW_DISABLE_ALLMULTI = 27, 264 265 /* returns MXGEFW_CMD_ERROR_MULTICAST 266 if there is no room in the cache 267 data0,MSH(data1) = multicast group address */ 268 MXGEFW_JOIN_MULTICAST_GROUP = 28, 269 /* returns MXGEFW_CMD_ERROR_MULTICAST 270 if the address is not in the cache, 271 or is equal to FF-FF-FF-FF-FF-FF 272 data0,MSH(data1) = multicast group address */ 273 MXGEFW_LEAVE_MULTICAST_GROUP = 29, 274 MXGEFW_LEAVE_ALL_MULTICAST_GROUPS = 30, 275 276 MXGEFW_CMD_SET_STATS_DMA_V2 = 31, 277 /* data0, data1 = bus addr, 278 * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows 279 * adding new stuff to mcp_irq_data without changing the ABI 280 * 281 * If multiple slices are used, data2 contains both the size of the 282 * structure (in the lower 16 bits) and the slice number 283 * (in the upper 16 bits). 284 */ 285 286 MXGEFW_CMD_UNALIGNED_TEST = 32, 287 /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned 288 chipset */ 289 290 MXGEFW_CMD_UNALIGNED_STATUS = 33, 291 /* return data = boolean, true if the chipset is known to be unaligned */ 292 293 MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS = 34, 294 /* data0 = number of big buffers to use. It must be 0 or a power of 2. 295 * 0 indicates that the NIC consumes as many buffers as they are required 296 * for packet. This is the default behavior. 297 * A power of 2 number indicates that the NIC always uses the specified 298 * number of buffers for each big receive packet. 299 * It is up to the driver to ensure that this value is big enough for 300 * the NIC to be able to receive maximum-sized packets. 301 */ 302 303 MXGEFW_CMD_GET_MAX_RSS_QUEUES = 35, 304 MXGEFW_CMD_ENABLE_RSS_QUEUES = 36, 305 /* data0 = number of slices n (0, 1, ..., n-1) to enable 306 * data1 = interrupt mode | use of multiple transmit queues. 307 * 0=share one INTx/MSI. 308 * 1=use one MSI-X per queue. 309 * If all queues share one interrupt, the driver must have set 310 * RSS_SHARED_INTERRUPT_DMA before enabling queues. 311 * 2=enable both receive and send queues. 312 * Without this bit set, only one send queue (slice 0's send queue) 313 * is enabled. The receive queues are always enabled. 314 */ 315#define MXGEFW_SLICE_INTR_MODE_SHARED 0x0 316#define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 0x1 317#define MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES 0x2 318 319 MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET = 37, 320 MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA = 38, 321 /* data0, data1 = bus address lsw, msw */ 322 MXGEFW_CMD_GET_RSS_TABLE_OFFSET = 39, 323 /* get the offset of the indirection table */ 324 MXGEFW_CMD_SET_RSS_TABLE_SIZE = 40, 325 /* set the size of the indirection table */ 326 MXGEFW_CMD_GET_RSS_KEY_OFFSET = 41, 327 /* get the offset of the secret key */ 328 MXGEFW_CMD_RSS_KEY_UPDATED = 42, 329 /* tell nic that the secret key's been updated */ 330 MXGEFW_CMD_SET_RSS_ENABLE = 43, 331 /* data0 = enable/disable rss 332 * 0: disable rss. nic does not distribute receive packets. 333 * 1: enable rss. nic distributes receive packets among queues. 334 * data1 = hash type 335 * 1: IPV4 (required by RSS) 336 * 2: TCP_IPV4 (required by RSS) 337 * 3: IPV4 | TCP_IPV4 (required by RSS) 338 * 4: source port 339 * 5: source port + destination port 340 */ 341#define MXGEFW_RSS_HASH_TYPE_IPV4 0x1 342#define MXGEFW_RSS_HASH_TYPE_TCP_IPV4 0x2 343#define MXGEFW_RSS_HASH_TYPE_SRC_PORT 0x4 344#define MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT 0x5 345#define MXGEFW_RSS_HASH_TYPE_MAX 0x5 346 347 MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE = 44, 348 /* Return data = the max. size of the entire headers of a IPv6 TSO packet. 349 * If the header size of a IPv6 TSO packet is larger than the specified 350 * value, then the driver must not use TSO. 351 * This size restriction only applies to IPv6 TSO. 352 * For IPv4 TSO, the maximum size of the headers is fixed, and the NIC 353 * always has enough header buffer to store maximum-sized headers. 354 */ 355 356 MXGEFW_CMD_SET_TSO_MODE = 45, 357 /* data0 = TSO mode. 358 * 0: Linux/FreeBSD style (NIC default) 359 * 1: NDIS/NetBSD style 360 */ 361#define MXGEFW_TSO_MODE_LINUX 0 362#define MXGEFW_TSO_MODE_NDIS 1 363 364 MXGEFW_CMD_MDIO_READ = 46, 365 /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */ 366 MXGEFW_CMD_MDIO_WRITE = 47, 367 /* data0 = dev_addr, data1 = register/addr, data2 = value */ 368 369 MXGEFW_CMD_I2C_READ = 48, 370 /* Starts to get a fresh copy of one byte or of the module i2c table, the 371 * obtained data is cached inside the xaui-xfi chip : 372 * data0 : 0 => get one byte, 1=> get 256 bytes 373 * data1 : If data0 == 0: location to refresh 374 * bit 7:0 register location 375 * bit 8:15 is the i2c slave addr (0 is interpreted as 0xA1) 376 * bit 23:16 is the i2c bus number (for multi-port NICs) 377 * If data0 == 1: unused 378 * The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes 379 * During the i2c operation, MXGEFW_CMD_I2C_READ or MXGEFW_CMD_I2C_BYTE attempts 380 * will return MXGEFW_CMD_ERROR_BUSY 381 */ 382 MXGEFW_CMD_I2C_BYTE = 49, 383 /* Return the last obtained copy of a given byte in the xfp i2c table 384 * (copy cached during the last relevant MXGEFW_CMD_I2C_READ) 385 * data0 : index of the desired table entry 386 * Return data = the byte stored at the requested index in the table 387 */ 388 389 MXGEFW_CMD_GET_VPUMP_OFFSET = 50, 390 /* Return data = NIC memory offset of mcp_vpump_public_global */ 391 MXGEFW_CMD_RESET_VPUMP = 51, 392 /* Resets the VPUMP state */ 393 394 MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE = 52, 395 /* data0 = mcp_slot type to use. 396 * 0 = the default 4B mcp_slot 397 * 1 = 8B mcp_slot_8 398 */ 399#define MXGEFW_RSS_MCP_SLOT_TYPE_MIN 0 400#define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH 1 401 402 MXGEFW_CMD_SET_THROTTLE_FACTOR = 53, 403 /* set the throttle factor for ethp_z8e 404 data0 = throttle_factor 405 throttle_factor = 256 * pcie-raw-speed / tx_speed 406 tx_speed = 256 * pcie-raw-speed / throttle_factor 407 408 For PCI-E x8: pcie-raw-speed == 16Gb/s 409 For PCI-E x4: pcie-raw-speed == 8Gb/s 410 411 ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s 412 ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s 413 414 with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s 415 with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s 416 */ 417 418 MXGEFW_CMD_VPUMP_UP = 54, 419 /* Allocates VPump Connection, Send Request and Zero copy buffer address tables */ 420 MXGEFW_CMD_GET_VPUMP_CLK = 55, 421 /* Get the lanai clock */ 422 423 MXGEFW_CMD_GET_DCA_OFFSET = 56, 424 /* offset of dca control for WDMAs */ 425 426 /* VMWare NetQueue commands */ 427 MXGEFW_CMD_NETQ_GET_FILTERS_PER_QUEUE = 57, 428 MXGEFW_CMD_NETQ_ADD_FILTER = 58, 429 /* data0 = filter_id << 16 | queue << 8 | type */ 430 /* data1 = MS4 of MAC Addr */ 431 /* data2 = LS2_MAC << 16 | VLAN_tag */ 432 MXGEFW_CMD_NETQ_DEL_FILTER = 59, 433 /* data0 = filter_id */ 434 MXGEFW_CMD_NETQ_QUERY1 = 60, 435 MXGEFW_CMD_NETQ_QUERY2 = 61, 436 MXGEFW_CMD_NETQ_QUERY3 = 62, 437 MXGEFW_CMD_NETQ_QUERY4 = 63, 438 439 MXGEFW_CMD_RELAX_RXBUFFER_ALIGNMENT = 64, 440 /* When set, small receive buffers can cross page boundaries. 441 * Both small and big receive buffers may start at any address. 442 * This option has performance implications, so use with caution. 443 */ 444}; 445typedef enum myri10ge_mcp_cmd_type myri10ge_mcp_cmd_type_t; 446 447enum myri10ge_mcp_cmd_status { 448 MXGEFW_CMD_OK = 0, 449 MXGEFW_CMD_UNKNOWN = 1, 450 MXGEFW_CMD_ERROR_RANGE = 2, 451 MXGEFW_CMD_ERROR_BUSY = 3, 452 MXGEFW_CMD_ERROR_EMPTY = 4, 453 MXGEFW_CMD_ERROR_CLOSED = 5, 454 MXGEFW_CMD_ERROR_HASH_ERROR = 6, 455 MXGEFW_CMD_ERROR_BAD_PORT = 7, 456 MXGEFW_CMD_ERROR_RESOURCES = 8, 457 MXGEFW_CMD_ERROR_MULTICAST = 9, 458 MXGEFW_CMD_ERROR_UNALIGNED = 10, 459 MXGEFW_CMD_ERROR_NO_MDIO = 11, 460 MXGEFW_CMD_ERROR_I2C_FAILURE = 12, 461 MXGEFW_CMD_ERROR_I2C_ABSENT = 13, 462 MXGEFW_CMD_ERROR_BAD_PCIE_LINK = 14 463}; 464typedef enum myri10ge_mcp_cmd_status myri10ge_mcp_cmd_status_t; 465 466#define MXGEFW_OLD_IRQ_DATA_LEN 40 467 468struct mcp_irq_data { 469 /* add new counters at the beginning */ 470 uint32_t future_use[1]; 471 uint32_t dropped_pause; 472 uint32_t dropped_unicast_filtered; 473 uint32_t dropped_bad_crc32; 474 uint32_t dropped_bad_phy; 475 uint32_t dropped_multicast_filtered; 476/* 40 Bytes */ 477 uint32_t send_done_count; 478 479#define MXGEFW_LINK_DOWN 0 480#define MXGEFW_LINK_UP 1 481#define MXGEFW_LINK_MYRINET 2 482#define MXGEFW_LINK_UNKNOWN 3 483 uint32_t link_up; 484 uint32_t dropped_link_overflow; 485 uint32_t dropped_link_error_or_filtered; 486 uint32_t dropped_runt; 487 uint32_t dropped_overrun; 488 uint32_t dropped_no_small_buffer; 489 uint32_t dropped_no_big_buffer; 490 uint32_t rdma_tags_available; 491 492 uint8_t tx_stopped; 493 uint8_t link_down; 494 uint8_t stats_updated; 495 uint8_t valid; 496}; 497typedef struct mcp_irq_data mcp_irq_data_t; 498 499#ifdef MXGEFW_NDIS 500/* Exclusively used by NDIS drivers */ 501struct mcp_rss_shared_interrupt { 502 uint8_t pad[2]; 503 uint8_t queue; 504 uint8_t valid; 505}; 506#endif 507 508/* definitions for NETQ filter type */ 509#define MXGEFW_NETQ_FILTERTYPE_NONE 0 510#define MXGEFW_NETQ_FILTERTYPE_MACADDR 1 511#define MXGEFW_NETQ_FILTERTYPE_VLAN 2 512#define MXGEFW_NETQ_FILTERTYPE_VLANMACADDR 3 513 514#endif /* _myri10ge_mcp_h */ 515