1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sys/param.h> 30#include <sys/module.h> 31#include <sys/systm.h> 32#include <sys/kernel.h> 33#include <sys/bus.h> 34#include <sys/endian.h> 35#include <sys/malloc.h> 36#include <sys/lock.h> 37#include <sys/mutex.h> 38#include <vm/uma.h> 39#include <machine/stdarg.h> 40#include <machine/resource.h> 41#include <machine/bus.h> 42#include <sys/rman.h> 43#include <sys/sbuf.h> 44#include <arm/mv/mvreg.h> 45#include <arm/mv/mvvar.h> 46#include <dev/ofw/ofw_bus.h> 47#include <dev/ofw/ofw_bus_subr.h> 48#include "mvs.h" 49 50/* local prototypes */ 51static int mvs_setup_interrupt(device_t dev); 52static void mvs_intr(void *data); 53static int mvs_suspend(device_t dev); 54static int mvs_resume(device_t dev); 55static int mvs_ctlr_setup(device_t dev); 56 57static struct { 58 uint32_t id; 59 uint8_t rev; 60 const char *name; 61 int ports; 62 int quirks; 63} mvs_ids[] = { 64 {MV_DEV_88F5182, 0x00, "Marvell 88F5182", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 65 {MV_DEV_88F6281, 0x00, "Marvell 88F6281", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 66 {MV_DEV_88F6282, 0x00, "Marvell 88F6282", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 67 {MV_DEV_MV78100, 0x00, "Marvell MV78100", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 68 {MV_DEV_MV78100_Z0, 0x00,"Marvell MV78100", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 69 {MV_DEV_MV78260, 0x00, "Marvell MV78260", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 70 {MV_DEV_MV78460, 0x00, "Marvell MV78460", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 71 {0, 0x00, NULL, 0, 0} 72}; 73 74static int 75mvs_probe(device_t dev) 76{ 77 char buf[64]; 78 int i; 79 uint32_t devid, revid; 80 81 if (!ofw_bus_status_okay(dev)) 82 return (ENXIO); 83 84 if (!ofw_bus_is_compatible(dev, "mrvl,sata")) 85 return (ENXIO); 86 87 soc_id(&devid, &revid); 88 for (i = 0; mvs_ids[i].id != 0; i++) { 89 if (mvs_ids[i].id == devid && 90 mvs_ids[i].rev <= revid) { 91 snprintf(buf, sizeof(buf), "%s SATA controller", 92 mvs_ids[i].name); 93 device_set_desc_copy(dev, buf); 94 return (BUS_PROBE_DEFAULT); 95 } 96 } 97 return (ENXIO); 98} 99 100static int 101mvs_attach(device_t dev) 102{ 103 struct mvs_controller *ctlr = device_get_softc(dev); 104 device_t child; 105 int error, unit, i; 106 uint32_t devid, revid; 107 108 soc_id(&devid, &revid); 109 ctlr->dev = dev; 110 i = 0; 111 while (mvs_ids[i].id != 0 && 112 (mvs_ids[i].id != devid || 113 mvs_ids[i].rev > revid)) 114 i++; 115 ctlr->channels = mvs_ids[i].ports; 116 ctlr->quirks = mvs_ids[i].quirks; 117 ctlr->ccc = 0; 118 resource_int_value(device_get_name(dev), 119 device_get_unit(dev), "ccc", &ctlr->ccc); 120 ctlr->cccc = 8; 121 resource_int_value(device_get_name(dev), 122 device_get_unit(dev), "cccc", &ctlr->cccc); 123 if (ctlr->ccc == 0 || ctlr->cccc == 0) { 124 ctlr->ccc = 0; 125 ctlr->cccc = 0; 126 } 127 if (ctlr->ccc > 100000) 128 ctlr->ccc = 100000; 129 device_printf(dev, 130 "Gen-%s, %d %sGbps ports, Port Multiplier %s%s\n", 131 ((ctlr->quirks & MVS_Q_GENI) ? "I" : 132 ((ctlr->quirks & MVS_Q_GENII) ? "II" : "IIe")), 133 ctlr->channels, 134 ((ctlr->quirks & MVS_Q_GENI) ? "1.5" : "3"), 135 ((ctlr->quirks & MVS_Q_GENI) ? 136 "not supported" : "supported"), 137 ((ctlr->quirks & MVS_Q_GENIIE) ? 138 " with FBS" : "")); 139 mtx_init(&ctlr->mtx, "MVS controller lock", NULL, MTX_DEF); 140 /* We should have a memory BAR(0). */ 141 ctlr->r_rid = 0; 142 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 143 &ctlr->r_rid, RF_ACTIVE))) 144 return ENXIO; 145 if (ATA_INL(ctlr->r_mem, PORT_BASE(0) + SATA_PHYCFG_OFS) != 0) 146 ctlr->quirks |= MVS_Q_SOC65; 147 /* Setup our own memory management for channels. */ 148 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 149 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 150 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 151 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 152 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 153 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 154 return (error); 155 } 156 if ((error = rman_manage_region(&ctlr->sc_iomem, 157 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 158 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 159 rman_fini(&ctlr->sc_iomem); 160 return (error); 161 } 162 mvs_ctlr_setup(dev); 163 /* Setup interrupts. */ 164 if (mvs_setup_interrupt(dev)) { 165 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 166 rman_fini(&ctlr->sc_iomem); 167 return ENXIO; 168 } 169 /* Attach all channels on this controller */ 170 for (unit = 0; unit < ctlr->channels; unit++) { 171 child = device_add_child(dev, "mvsch", -1); 172 if (child == NULL) 173 device_printf(dev, "failed to add channel device\n"); 174 else 175 device_set_ivars(child, (void *)(intptr_t)unit); 176 } 177 bus_generic_attach(dev); 178 return 0; 179} 180 181static int 182mvs_detach(device_t dev) 183{ 184 struct mvs_controller *ctlr = device_get_softc(dev); 185 186 /* Detach & delete all children */ 187 device_delete_children(dev); 188 189 /* Free interrupt. */ 190 if (ctlr->irq.r_irq) { 191 bus_teardown_intr(dev, ctlr->irq.r_irq, 192 ctlr->irq.handle); 193 bus_release_resource(dev, SYS_RES_IRQ, 194 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 195 } 196 /* Free memory. */ 197 rman_fini(&ctlr->sc_iomem); 198 if (ctlr->r_mem) 199 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 200 mtx_destroy(&ctlr->mtx); 201 return (0); 202} 203 204static int 205mvs_ctlr_setup(device_t dev) 206{ 207 struct mvs_controller *ctlr = device_get_softc(dev); 208 int ccc = ctlr->ccc, cccc = ctlr->cccc; 209 210 /* Mask chip interrupts */ 211 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000); 212 /* Clear HC interrupts */ 213 ATA_OUTL(ctlr->r_mem, HC_IC, 0x00000000); 214 /* Clear chip interrupts */ 215 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIC, 0); 216 /* Configure per-HC CCC */ 217 if (ccc && bootverbose) { 218 device_printf(dev, 219 "CCC with %dus/%dcmd enabled\n", 220 ctlr->ccc, ctlr->cccc); 221 } 222 ccc *= 150; 223 ATA_OUTL(ctlr->r_mem, HC_ICT, cccc); 224 ATA_OUTL(ctlr->r_mem, HC_ITT, ccc); 225 /* Enable chip interrupts */ 226 ctlr->gmim = ((ccc ? IC_HC0_COAL_DONE : 227 (IC_DONE_HC0 & CHIP_SOC_HC0_MASK(ctlr->channels))) | 228 (IC_ERR_HC0 & CHIP_SOC_HC0_MASK(ctlr->channels))); 229 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim); 230 return (0); 231} 232 233static void 234mvs_edma(device_t dev, device_t child, int mode) 235{ 236 struct mvs_controller *ctlr = device_get_softc(dev); 237 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 238 int bit = IC_DONE_IRQ << (unit * 2); 239 240 if (ctlr->ccc == 0) 241 return; 242 /* CCC is not working for non-EDMA mode. Unmask device interrupts. */ 243 mtx_lock(&ctlr->mtx); 244 if (mode == MVS_EDMA_OFF) 245 ctlr->pmim |= bit; 246 else 247 ctlr->pmim &= ~bit; 248 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim); 249 mtx_unlock(&ctlr->mtx); 250} 251 252static int 253mvs_suspend(device_t dev) 254{ 255 struct mvs_controller *ctlr = device_get_softc(dev); 256 257 bus_generic_suspend(dev); 258 /* Mask chip interrupts */ 259 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000); 260 return 0; 261} 262 263static int 264mvs_resume(device_t dev) 265{ 266 267 mvs_ctlr_setup(dev); 268 return (bus_generic_resume(dev)); 269} 270 271static int 272mvs_setup_interrupt(device_t dev) 273{ 274 struct mvs_controller *ctlr = device_get_softc(dev); 275 276 /* Allocate all IRQs. */ 277 ctlr->irq.r_irq_rid = 0; 278 if (!(ctlr->irq.r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 279 &ctlr->irq.r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 280 device_printf(dev, "unable to map interrupt\n"); 281 return (ENXIO); 282 } 283 if ((bus_setup_intr(dev, ctlr->irq.r_irq, ATA_INTR_FLAGS, NULL, 284 mvs_intr, ctlr, &ctlr->irq.handle))) { 285 device_printf(dev, "unable to setup interrupt\n"); 286 bus_release_resource(dev, SYS_RES_IRQ, 287 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 288 ctlr->irq.r_irq = NULL; 289 return (ENXIO); 290 } 291 return (0); 292} 293 294/* 295 * Common case interrupt handler. 296 */ 297static void 298mvs_intr(void *data) 299{ 300 struct mvs_controller *ctlr = data; 301 struct mvs_intr_arg arg; 302 void (*function)(void *); 303 int p, chan_num; 304 u_int32_t ic, aic; 305 306 ic = ATA_INL(ctlr->r_mem, CHIP_SOC_MIC); 307 if ((ic & IC_HC0) == 0) 308 return; 309 310 /* Acknowledge interrupts of this HC. */ 311 aic = 0; 312 313 /* Processing interrupts from each initialized channel */ 314 for (chan_num = 0; chan_num < ctlr->channels; chan_num++) { 315 if (ic & (IC_DONE_IRQ << (chan_num * 2))) 316 aic |= HC_IC_DONE(chan_num) | HC_IC_DEV(chan_num); 317 } 318 319 if (ic & IC_HC0_COAL_DONE) 320 aic |= HC_IC_COAL; 321 ATA_OUTL(ctlr->r_mem, HC_IC, ~aic); 322 323 /* Call per-port interrupt handler. */ 324 for (p = 0; p < ctlr->channels; p++) { 325 arg.cause = ic & (IC_ERR_IRQ|IC_DONE_IRQ); 326 if ((arg.cause != 0) && 327 (function = ctlr->interrupt[p].function)) { 328 arg.arg = ctlr->interrupt[p].argument; 329 function(&arg); 330 } 331 ic >>= 2; 332 } 333} 334 335static struct resource * 336mvs_alloc_resource(device_t dev, device_t child, int type, int *rid, 337 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 338{ 339 struct mvs_controller *ctlr = device_get_softc(dev); 340 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 341 struct resource *res = NULL; 342 int offset = PORT_BASE(unit & 0x03); 343 rman_res_t st; 344 345 switch (type) { 346 case SYS_RES_MEMORY: 347 st = rman_get_start(ctlr->r_mem); 348 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 349 st + offset + PORT_SIZE - 1, PORT_SIZE, RF_ACTIVE, child); 350 if (res) { 351 bus_space_handle_t bsh; 352 bus_space_tag_t bst; 353 bsh = rman_get_bushandle(ctlr->r_mem); 354 bst = rman_get_bustag(ctlr->r_mem); 355 bus_space_subregion(bst, bsh, offset, PORT_SIZE, &bsh); 356 rman_set_bushandle(res, bsh); 357 rman_set_bustag(res, bst); 358 } 359 break; 360 case SYS_RES_IRQ: 361 if (*rid == ATA_IRQ_RID) 362 res = ctlr->irq.r_irq; 363 break; 364 } 365 return (res); 366} 367 368static int 369mvs_release_resource(device_t dev, device_t child, struct resource *r) 370{ 371 372 switch (rman_get_type(r)) { 373 case SYS_RES_MEMORY: 374 rman_release_resource(r); 375 return (0); 376 case SYS_RES_IRQ: 377 if (rid != ATA_IRQ_RID) 378 return ENOENT; 379 return (0); 380 } 381 return (EINVAL); 382} 383 384static int 385mvs_setup_intr(device_t dev, device_t child, struct resource *irq, 386 int flags, driver_filter_t *filter, driver_intr_t *function, 387 void *argument, void **cookiep) 388{ 389 struct mvs_controller *ctlr = device_get_softc(dev); 390 int unit = (intptr_t)device_get_ivars(child); 391 392 if (filter != NULL) { 393 printf("mvs.c: we cannot use a filter here\n"); 394 return (EINVAL); 395 } 396 ctlr->interrupt[unit].function = function; 397 ctlr->interrupt[unit].argument = argument; 398 return (0); 399} 400 401static int 402mvs_teardown_intr(device_t dev, device_t child, struct resource *irq, 403 void *cookie) 404{ 405 struct mvs_controller *ctlr = device_get_softc(dev); 406 int unit = (intptr_t)device_get_ivars(child); 407 408 ctlr->interrupt[unit].function = NULL; 409 ctlr->interrupt[unit].argument = NULL; 410 return (0); 411} 412 413static int 414mvs_print_child(device_t dev, device_t child) 415{ 416 int retval; 417 418 retval = bus_print_child_header(dev, child); 419 retval += printf(" at channel %d", 420 (int)(intptr_t)device_get_ivars(child)); 421 retval += bus_print_child_footer(dev, child); 422 423 return (retval); 424} 425 426static int 427mvs_child_location(device_t dev, device_t child, struct sbuf *sb) 428{ 429 430 sbuf_printf(sb, "channel=%d", (int)(intptr_t)device_get_ivars(child)); 431 return (0); 432} 433 434static bus_dma_tag_t 435mvs_get_dma_tag(device_t bus, device_t child) 436{ 437 438 return (bus_get_dma_tag(bus)); 439} 440 441static device_method_t mvs_methods[] = { 442 DEVMETHOD(device_probe, mvs_probe), 443 DEVMETHOD(device_attach, mvs_attach), 444 DEVMETHOD(device_detach, mvs_detach), 445 DEVMETHOD(device_suspend, mvs_suspend), 446 DEVMETHOD(device_resume, mvs_resume), 447 DEVMETHOD(bus_print_child, mvs_print_child), 448 DEVMETHOD(bus_alloc_resource, mvs_alloc_resource), 449 DEVMETHOD(bus_release_resource, mvs_release_resource), 450 DEVMETHOD(bus_setup_intr, mvs_setup_intr), 451 DEVMETHOD(bus_teardown_intr,mvs_teardown_intr), 452 DEVMETHOD(bus_child_location, mvs_child_location), 453 DEVMETHOD(bus_get_dma_tag, mvs_get_dma_tag), 454 DEVMETHOD(mvs_edma, mvs_edma), 455 { 0, 0 } 456}; 457static driver_t mvs_driver = { 458 "mvs", 459 mvs_methods, 460 sizeof(struct mvs_controller) 461}; 462DRIVER_MODULE(mvs, simplebus, mvs_driver, 0, 0); 463MODULE_VERSION(mvs, 1); 464MODULE_DEPEND(mvs, cam, 1, 1, 1); 465