1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2006 Bernd Walter. All rights reserved. 5 * Copyright (c) 2006 M. Warner Losh <imp@FreeBSD.org> 6 * Copyright (c) 2017 Marius Strobl <marius@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Portions of this software may have been developed with reference to 29 * the SD Simplified Specification. The following disclaimer may apply: 30 * 31 * The following conditions apply to the release of the simplified 32 * specification ("Simplified Specification") by the SD Card Association and 33 * the SD Group. The Simplified Specification is a subset of the complete SD 34 * Specification which is owned by the SD Card Association and the SD 35 * Group. This Simplified Specification is provided on a non-confidential 36 * basis subject to the disclaimers below. Any implementation of the 37 * Simplified Specification may require a license from the SD Card 38 * Association, SD Group, SD-3C LLC or other third parties. 39 * 40 * Disclaimers: 41 * 42 * The information contained in the Simplified Specification is presented only 43 * as a standard specification for SD Cards and SD Host/Ancillary products and 44 * is provided "AS-IS" without any representations or warranties of any 45 * kind. No responsibility is assumed by the SD Group, SD-3C LLC or the SD 46 * Card Association for any damages, any infringements of patents or other 47 * right of the SD Group, SD-3C LLC, the SD Card Association or any third 48 * parties, which may result from its use. No license is granted by 49 * implication, estoppel or otherwise under any patent or other rights of the 50 * SD Group, SD-3C LLC, the SD Card Association or any third party. Nothing 51 * herein shall be construed as an obligation by the SD Group, the SD-3C LLC 52 * or the SD Card Association to disclose or distribute any technical 53 * information, know-how or other confidential information to any third party. 54 */ 55 56#include <sys/param.h> 57#include <sys/systm.h> 58#include <sys/kernel.h> 59#include <sys/malloc.h> 60#include <sys/lock.h> 61#include <sys/module.h> 62#include <sys/mutex.h> 63#include <sys/bus.h> 64#include <sys/endian.h> 65#include <sys/sbuf.h> 66#include <sys/sysctl.h> 67#include <sys/time.h> 68 69#include <dev/mmc/bridge.h> 70#include <dev/mmc/mmc_private.h> 71#include <dev/mmc/mmc_subr.h> 72#include <dev/mmc/mmcreg.h> 73#include <dev/mmc/mmcbrvar.h> 74#include <dev/mmc/mmcvar.h> 75 76#include "mmcbr_if.h" 77#include "mmcbus_if.h" 78 79CTASSERT(bus_timing_max <= sizeof(uint32_t) * NBBY); 80 81/* 82 * Per-card data 83 */ 84struct mmc_ivars { 85 uint32_t raw_cid[4]; /* Raw bits of the CID */ 86 uint32_t raw_csd[4]; /* Raw bits of the CSD */ 87 uint32_t raw_scr[2]; /* Raw bits of the SCR */ 88 uint8_t raw_ext_csd[MMC_EXTCSD_SIZE]; /* Raw bits of the EXT_CSD */ 89 uint32_t raw_sd_status[16]; /* Raw bits of the SD_STATUS */ 90 uint16_t rca; 91 u_char read_only; /* True when the device is read-only */ 92 u_char high_cap; /* High Capacity device (block addressed) */ 93 enum mmc_card_mode mode; 94 enum mmc_bus_width bus_width; /* Bus width to use */ 95 struct mmc_cid cid; /* cid decoded */ 96 struct mmc_csd csd; /* csd decoded */ 97 struct mmc_scr scr; /* scr decoded */ 98 struct mmc_sd_status sd_status; /* SD_STATUS decoded */ 99 uint32_t sec_count; /* Card capacity in 512byte blocks */ 100 uint32_t timings; /* Mask of bus timings supported */ 101 uint32_t vccq_120; /* Mask of bus timings at VCCQ of 1.2 V */ 102 uint32_t vccq_180; /* Mask of bus timings at VCCQ of 1.8 V */ 103 uint32_t tran_speed; /* Max speed in normal mode */ 104 uint32_t hs_tran_speed; /* Max speed in high speed mode */ 105 uint32_t erase_sector; /* Card native erase sector size */ 106 uint32_t cmd6_time; /* Generic switch timeout [us] */ 107 uint32_t quirks; /* Quirks as per mmc_quirk->quirks */ 108 char card_id_string[64];/* Formatted CID info (serial, MFG, etc) */ 109 char card_sn_string[16];/* Formatted serial # for disk->d_ident */ 110}; 111 112#define CMD_RETRIES 3 113 114static const struct mmc_quirk mmc_quirks[] = { 115 /* 116 * For some SanDisk iNAND devices, the CMD38 argument needs to be 117 * provided in EXT_CSD[113]. 118 */ 119 { 0x2, 0x100, "SEM02G", MMC_QUIRK_INAND_CMD38 }, 120 { 0x2, 0x100, "SEM04G", MMC_QUIRK_INAND_CMD38 }, 121 { 0x2, 0x100, "SEM08G", MMC_QUIRK_INAND_CMD38 }, 122 { 0x2, 0x100, "SEM16G", MMC_QUIRK_INAND_CMD38 }, 123 { 0x2, 0x100, "SEM32G", MMC_QUIRK_INAND_CMD38 }, 124 125 /* 126 * Disable TRIM for Kingston eMMCs where a firmware bug can lead to 127 * unrecoverable data corruption. 128 */ 129 { 0x70, MMC_QUIRK_OID_ANY, "V10008", MMC_QUIRK_BROKEN_TRIM }, 130 { 0x70, MMC_QUIRK_OID_ANY, "V10016", MMC_QUIRK_BROKEN_TRIM }, 131 { 0x0, 0x0, NULL, 0x0 } 132}; 133 134static SYSCTL_NODE(_hw, OID_AUTO, mmc, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 135 "mmc driver"); 136 137static int mmc_debug; 138SYSCTL_INT(_hw_mmc, OID_AUTO, debug, CTLFLAG_RWTUN, &mmc_debug, 0, 139 "Debug level"); 140 141/* bus entry points */ 142static int mmc_acquire_bus(device_t busdev, device_t dev); 143static int mmc_attach(device_t dev); 144static int mmc_child_location(device_t dev, device_t child, struct sbuf *sb); 145static int mmc_detach(device_t dev); 146static int mmc_probe(device_t dev); 147static int mmc_read_ivar(device_t bus, device_t child, int which, 148 uintptr_t *result); 149static int mmc_release_bus(device_t busdev, device_t dev); 150static int mmc_resume(device_t dev); 151static void mmc_retune_pause(device_t busdev, device_t dev, bool retune); 152static void mmc_retune_unpause(device_t busdev, device_t dev); 153static int mmc_suspend(device_t dev); 154static int mmc_wait_for_request(device_t busdev, device_t dev, 155 struct mmc_request *req); 156static int mmc_write_ivar(device_t bus, device_t child, int which, 157 uintptr_t value); 158 159#define MMC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 160#define MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 161#define MMC_LOCK_INIT(_sc) \ 162 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->dev), \ 163 "mmc", MTX_DEF) 164#define MMC_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx); 165#define MMC_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED); 166#define MMC_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED); 167 168static int mmc_all_send_cid(struct mmc_softc *sc, uint32_t *rawcid); 169static void mmc_app_decode_scr(uint32_t *raw_scr, struct mmc_scr *scr); 170static void mmc_app_decode_sd_status(uint32_t *raw_sd_status, 171 struct mmc_sd_status *sd_status); 172static int mmc_app_sd_status(struct mmc_softc *sc, uint16_t rca, 173 uint32_t *rawsdstatus); 174static int mmc_app_send_scr(struct mmc_softc *sc, uint16_t rca, 175 uint32_t *rawscr); 176static int mmc_calculate_clock(struct mmc_softc *sc); 177static void mmc_decode_cid_mmc(uint32_t *raw_cid, struct mmc_cid *cid, 178 bool is_4_41p); 179static void mmc_decode_cid_sd(uint32_t *raw_cid, struct mmc_cid *cid); 180static void mmc_decode_csd_mmc(uint32_t *raw_csd, struct mmc_csd *csd); 181static int mmc_decode_csd_sd(uint32_t *raw_csd, struct mmc_csd *csd); 182static void mmc_delayed_attach(void *xsc); 183static int mmc_delete_cards(struct mmc_softc *sc, bool final); 184static void mmc_discover_cards(struct mmc_softc *sc); 185static void mmc_format_card_id_string(struct mmc_ivars *ivar); 186static void mmc_go_discovery(struct mmc_softc *sc); 187static uint32_t mmc_get_bits(uint32_t *bits, int bit_len, int start, 188 int size); 189static int mmc_highest_voltage(uint32_t ocr); 190static bool mmc_host_timing(device_t dev, enum mmc_bus_timing timing); 191static void mmc_idle_cards(struct mmc_softc *sc); 192static void mmc_ms_delay(int ms); 193static void mmc_log_card(device_t dev, struct mmc_ivars *ivar, int newcard); 194static void mmc_power_down(struct mmc_softc *sc); 195static void mmc_power_up(struct mmc_softc *sc); 196static void mmc_rescan_cards(struct mmc_softc *sc); 197static int mmc_retune(device_t busdev, device_t dev, bool reset); 198static void mmc_scan(struct mmc_softc *sc); 199static int mmc_sd_switch(struct mmc_softc *sc, uint8_t mode, uint8_t grp, 200 uint8_t value, uint8_t *res); 201static int mmc_select_card(struct mmc_softc *sc, uint16_t rca); 202static uint32_t mmc_select_vdd(struct mmc_softc *sc, uint32_t ocr); 203static int mmc_send_app_op_cond(struct mmc_softc *sc, uint32_t ocr, 204 uint32_t *rocr); 205static int mmc_send_csd(struct mmc_softc *sc, uint16_t rca, uint32_t *rawcsd); 206static int mmc_send_if_cond(struct mmc_softc *sc, uint8_t vhs); 207static int mmc_send_op_cond(struct mmc_softc *sc, uint32_t ocr, 208 uint32_t *rocr); 209static int mmc_send_relative_addr(struct mmc_softc *sc, uint32_t *resp); 210static int mmc_set_blocklen(struct mmc_softc *sc, uint32_t len); 211static int mmc_set_card_bus_width(struct mmc_softc *sc, struct mmc_ivars *ivar, 212 enum mmc_bus_timing timing); 213static int mmc_set_power_class(struct mmc_softc *sc, struct mmc_ivars *ivar); 214static int mmc_set_relative_addr(struct mmc_softc *sc, uint16_t resp); 215static int mmc_set_timing(struct mmc_softc *sc, struct mmc_ivars *ivar, 216 enum mmc_bus_timing timing); 217static int mmc_set_vccq(struct mmc_softc *sc, struct mmc_ivars *ivar, 218 enum mmc_bus_timing timing); 219static int mmc_switch_to_hs200(struct mmc_softc *sc, struct mmc_ivars *ivar, 220 uint32_t clock); 221static int mmc_switch_to_hs400(struct mmc_softc *sc, struct mmc_ivars *ivar, 222 uint32_t max_dtr, enum mmc_bus_timing max_timing); 223static int mmc_test_bus_width(struct mmc_softc *sc); 224static uint32_t mmc_timing_to_dtr(struct mmc_ivars *ivar, 225 enum mmc_bus_timing timing); 226static const char *mmc_timing_to_string(enum mmc_bus_timing timing); 227static void mmc_update_child_list(struct mmc_softc *sc); 228static int mmc_wait_for_command(struct mmc_softc *sc, uint32_t opcode, 229 uint32_t arg, uint32_t flags, uint32_t *resp, int retries); 230static int mmc_wait_for_req(struct mmc_softc *sc, struct mmc_request *req); 231static void mmc_wakeup(struct mmc_request *req); 232 233static void 234mmc_ms_delay(int ms) 235{ 236 237 DELAY(1000 * ms); /* XXX BAD */ 238} 239 240static int 241mmc_probe(device_t dev) 242{ 243 244 device_set_desc(dev, "MMC/SD bus"); 245 return (0); 246} 247 248static int 249mmc_attach(device_t dev) 250{ 251 struct mmc_softc *sc; 252 253 sc = device_get_softc(dev); 254 sc->dev = dev; 255 MMC_LOCK_INIT(sc); 256 257 /* We'll probe and attach our children later, but before / mount */ 258 sc->config_intrhook.ich_func = mmc_delayed_attach; 259 sc->config_intrhook.ich_arg = sc; 260 if (config_intrhook_establish(&sc->config_intrhook) != 0) 261 device_printf(dev, "config_intrhook_establish failed\n"); 262 return (0); 263} 264 265static int 266mmc_detach(device_t dev) 267{ 268 struct mmc_softc *sc = device_get_softc(dev); 269 int err; 270 271 config_intrhook_drain(&sc->config_intrhook); 272 err = mmc_delete_cards(sc, true); 273 if (err != 0) 274 return (err); 275 mmc_power_down(sc); 276 MMC_LOCK_DESTROY(sc); 277 278 return (0); 279} 280 281static int 282mmc_suspend(device_t dev) 283{ 284 struct mmc_softc *sc = device_get_softc(dev); 285 int err; 286 287 err = bus_generic_suspend(dev); 288 if (err != 0) 289 return (err); 290 /* 291 * We power down with the bus acquired here, mainly so that no device 292 * is selected any longer and sc->last_rca gets set to 0. Otherwise, 293 * the deselect as part of the bus acquisition in mmc_scan() may fail 294 * during resume, as the bus isn't powered up again before later in 295 * mmc_go_discovery(). 296 */ 297 err = mmc_acquire_bus(dev, dev); 298 if (err != 0) 299 return (err); 300 mmc_power_down(sc); 301 err = mmc_release_bus(dev, dev); 302 return (err); 303} 304 305static int 306mmc_resume(device_t dev) 307{ 308 struct mmc_softc *sc = device_get_softc(dev); 309 310 mmc_scan(sc); 311 return (bus_generic_resume(dev)); 312} 313 314static int 315mmc_acquire_bus(device_t busdev, device_t dev) 316{ 317 struct mmc_softc *sc; 318 struct mmc_ivars *ivar; 319 int err; 320 uint16_t rca; 321 enum mmc_bus_timing timing; 322 323 err = MMCBR_ACQUIRE_HOST(device_get_parent(busdev), busdev); 324 if (err) 325 return (err); 326 sc = device_get_softc(busdev); 327 MMC_LOCK(sc); 328 if (sc->owner) 329 panic("mmc: host bridge didn't serialize us."); 330 sc->owner = dev; 331 MMC_UNLOCK(sc); 332 333 if (busdev != dev) { 334 /* 335 * Keep track of the last rca that we've selected. If 336 * we're asked to do it again, don't. We never 337 * unselect unless the bus code itself wants the mmc 338 * bus, and constantly reselecting causes problems. 339 */ 340 ivar = device_get_ivars(dev); 341 rca = ivar->rca; 342 if (sc->last_rca != rca) { 343 if (mmc_select_card(sc, rca) != MMC_ERR_NONE) { 344 device_printf(busdev, "Card at relative " 345 "address %d failed to select\n", rca); 346 return (ENXIO); 347 } 348 sc->last_rca = rca; 349 timing = mmcbr_get_timing(busdev); 350 /* 351 * For eMMC modes, setting/updating bus width and VCCQ 352 * only really is necessary if there actually is more 353 * than one device on the bus as generally that already 354 * had to be done by mmc_calculate_clock() or one of 355 * its calees. Moreover, setting the bus width anew 356 * can trigger re-tuning (via a CRC error on the next 357 * CMD), even if not switching between devices an the 358 * previously selected one is still tuned. Obviously, 359 * we need to re-tune the host controller if devices 360 * are actually switched, though. 361 */ 362 if (timing >= bus_timing_mmc_ddr52 && 363 sc->child_count == 1) 364 return (0); 365 /* Prepare bus width for the new card. */ 366 if (bootverbose || mmc_debug) { 367 device_printf(busdev, 368 "setting bus width to %d bits %s timing\n", 369 (ivar->bus_width == bus_width_4) ? 4 : 370 (ivar->bus_width == bus_width_8) ? 8 : 1, 371 mmc_timing_to_string(timing)); 372 } 373 if (mmc_set_card_bus_width(sc, ivar, timing) != 374 MMC_ERR_NONE) { 375 device_printf(busdev, "Card at relative " 376 "address %d failed to set bus width\n", 377 rca); 378 return (ENXIO); 379 } 380 mmcbr_set_bus_width(busdev, ivar->bus_width); 381 mmcbr_update_ios(busdev); 382 if (mmc_set_vccq(sc, ivar, timing) != MMC_ERR_NONE) { 383 device_printf(busdev, "Failed to set VCCQ " 384 "for card at relative address %d\n", rca); 385 return (ENXIO); 386 } 387 if (timing >= bus_timing_mmc_hs200 && 388 mmc_retune(busdev, dev, true) != 0) { 389 device_printf(busdev, "Card at relative " 390 "address %d failed to re-tune\n", rca); 391 return (ENXIO); 392 } 393 } 394 } else { 395 /* 396 * If there's a card selected, stand down. 397 */ 398 if (sc->last_rca != 0) { 399 if (mmc_select_card(sc, 0) != MMC_ERR_NONE) 400 return (ENXIO); 401 sc->last_rca = 0; 402 } 403 } 404 405 return (0); 406} 407 408static int 409mmc_release_bus(device_t busdev, device_t dev) 410{ 411 struct mmc_softc *sc; 412 413 sc = device_get_softc(busdev); 414 415 MMC_LOCK(sc); 416 if (!sc->owner) 417 panic("mmc: releasing unowned bus."); 418 if (sc->owner != dev) 419 panic("mmc: you don't own the bus. game over."); 420 sc->owner = NULL; 421 MMC_UNLOCK(sc); 422 return (MMCBR_RELEASE_HOST(device_get_parent(busdev), busdev)); 423} 424 425static uint32_t 426mmc_select_vdd(struct mmc_softc *sc, uint32_t ocr) 427{ 428 429 return (ocr & MMC_OCR_VOLTAGE); 430} 431 432static int 433mmc_highest_voltage(uint32_t ocr) 434{ 435 int i; 436 437 for (i = MMC_OCR_MAX_VOLTAGE_SHIFT; 438 i >= MMC_OCR_MIN_VOLTAGE_SHIFT; i--) 439 if (ocr & (1 << i)) 440 return (i); 441 return (-1); 442} 443 444static void 445mmc_wakeup(struct mmc_request *req) 446{ 447 struct mmc_softc *sc; 448 449 sc = (struct mmc_softc *)req->done_data; 450 MMC_LOCK(sc); 451 req->flags |= MMC_REQ_DONE; 452 MMC_UNLOCK(sc); 453 wakeup(req); 454} 455 456static int 457mmc_wait_for_req(struct mmc_softc *sc, struct mmc_request *req) 458{ 459 460 req->done = mmc_wakeup; 461 req->done_data = sc; 462 if (__predict_false(mmc_debug > 1)) { 463 device_printf(sc->dev, "REQUEST: CMD%d arg %#x flags %#x", 464 req->cmd->opcode, req->cmd->arg, req->cmd->flags); 465 if (req->cmd->data) { 466 printf(" data %d\n", (int)req->cmd->data->len); 467 } else 468 printf("\n"); 469 } 470 MMCBR_REQUEST(device_get_parent(sc->dev), sc->dev, req); 471 MMC_LOCK(sc); 472 while ((req->flags & MMC_REQ_DONE) == 0) 473 msleep(req, &sc->sc_mtx, 0, "mmcreq", 0); 474 MMC_UNLOCK(sc); 475 if (__predict_false(mmc_debug > 2 || (mmc_debug > 0 && 476 req->cmd->error != MMC_ERR_NONE))) 477 device_printf(sc->dev, "CMD%d RESULT: %d\n", 478 req->cmd->opcode, req->cmd->error); 479 return (0); 480} 481 482static int 483mmc_wait_for_request(device_t busdev, device_t dev, struct mmc_request *req) 484{ 485 struct mmc_softc *sc; 486 struct mmc_ivars *ivar; 487 int err, i; 488 enum mmc_retune_req retune_req; 489 490 sc = device_get_softc(busdev); 491 KASSERT(sc->owner != NULL, 492 ("%s: Request from %s without bus being acquired.", __func__, 493 device_get_nameunit(dev))); 494 495 /* 496 * Unless no device is selected or re-tuning is already ongoing, 497 * execute re-tuning if a) the bridge is requesting to do so and 498 * re-tuning hasn't been otherwise paused, or b) if a child asked 499 * to be re-tuned prior to pausing (see also mmc_retune_pause()). 500 */ 501 if (__predict_false(sc->last_rca != 0 && sc->retune_ongoing == 0 && 502 (((retune_req = mmcbr_get_retune_req(busdev)) != retune_req_none && 503 sc->retune_paused == 0) || sc->retune_needed == 1))) { 504 if (__predict_false(mmc_debug > 1)) { 505 device_printf(busdev, 506 "Re-tuning with%s circuit reset required\n", 507 retune_req == retune_req_reset ? "" : "out"); 508 } 509 if (device_get_parent(dev) == busdev) 510 ivar = device_get_ivars(dev); 511 else { 512 for (i = 0; i < sc->child_count; i++) { 513 ivar = device_get_ivars(sc->child_list[i]); 514 if (ivar->rca == sc->last_rca) 515 break; 516 } 517 if (ivar->rca != sc->last_rca) 518 return (EINVAL); 519 } 520 sc->retune_ongoing = 1; 521 err = mmc_retune(busdev, dev, retune_req == retune_req_reset); 522 sc->retune_ongoing = 0; 523 switch (err) { 524 case MMC_ERR_NONE: 525 case MMC_ERR_FAILED: /* Re-tune error but still might work */ 526 break; 527 case MMC_ERR_BADCRC: /* Switch failure on HS400 recovery */ 528 return (ENXIO); 529 case MMC_ERR_INVALID: /* Driver implementation b0rken */ 530 default: /* Unknown error, should not happen */ 531 return (EINVAL); 532 } 533 sc->retune_needed = 0; 534 } 535 return (mmc_wait_for_req(sc, req)); 536} 537 538static int 539mmc_wait_for_command(struct mmc_softc *sc, uint32_t opcode, 540 uint32_t arg, uint32_t flags, uint32_t *resp, int retries) 541{ 542 struct mmc_command cmd; 543 int err; 544 545 memset(&cmd, 0, sizeof(cmd)); 546 cmd.opcode = opcode; 547 cmd.arg = arg; 548 cmd.flags = flags; 549 cmd.data = NULL; 550 err = mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, retries); 551 if (err) 552 return (err); 553 if (resp) { 554 if (flags & MMC_RSP_136) 555 memcpy(resp, cmd.resp, 4 * sizeof(uint32_t)); 556 else 557 *resp = cmd.resp[0]; 558 } 559 return (0); 560} 561 562static void 563mmc_idle_cards(struct mmc_softc *sc) 564{ 565 device_t dev; 566 struct mmc_command cmd; 567 568 dev = sc->dev; 569 mmcbr_set_chip_select(dev, cs_high); 570 mmcbr_update_ios(dev); 571 mmc_ms_delay(1); 572 573 memset(&cmd, 0, sizeof(cmd)); 574 cmd.opcode = MMC_GO_IDLE_STATE; 575 cmd.arg = 0; 576 cmd.flags = MMC_RSP_NONE | MMC_CMD_BC; 577 cmd.data = NULL; 578 mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, CMD_RETRIES); 579 mmc_ms_delay(1); 580 581 mmcbr_set_chip_select(dev, cs_dontcare); 582 mmcbr_update_ios(dev); 583 mmc_ms_delay(1); 584} 585 586static int 587mmc_send_app_op_cond(struct mmc_softc *sc, uint32_t ocr, uint32_t *rocr) 588{ 589 struct mmc_command cmd; 590 int err = MMC_ERR_NONE, i; 591 592 memset(&cmd, 0, sizeof(cmd)); 593 cmd.opcode = ACMD_SD_SEND_OP_COND; 594 cmd.arg = ocr; 595 cmd.flags = MMC_RSP_R3 | MMC_CMD_BCR; 596 cmd.data = NULL; 597 598 for (i = 0; i < 1000; i++) { 599 err = mmc_wait_for_app_cmd(sc->dev, sc->dev, 0, &cmd, 600 CMD_RETRIES); 601 if (err != MMC_ERR_NONE) 602 break; 603 if ((cmd.resp[0] & MMC_OCR_CARD_BUSY) || 604 (ocr & MMC_OCR_VOLTAGE) == 0) 605 break; 606 err = MMC_ERR_TIMEOUT; 607 mmc_ms_delay(10); 608 } 609 if (rocr && err == MMC_ERR_NONE) 610 *rocr = cmd.resp[0]; 611 return (err); 612} 613 614static int 615mmc_send_op_cond(struct mmc_softc *sc, uint32_t ocr, uint32_t *rocr) 616{ 617 struct mmc_command cmd; 618 int err = MMC_ERR_NONE, i; 619 620 memset(&cmd, 0, sizeof(cmd)); 621 cmd.opcode = MMC_SEND_OP_COND; 622 cmd.arg = ocr; 623 cmd.flags = MMC_RSP_R3 | MMC_CMD_BCR; 624 cmd.data = NULL; 625 626 for (i = 0; i < 1000; i++) { 627 err = mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, CMD_RETRIES); 628 if (err != MMC_ERR_NONE) 629 break; 630 if ((cmd.resp[0] & MMC_OCR_CARD_BUSY) || 631 (ocr & MMC_OCR_VOLTAGE) == 0) 632 break; 633 err = MMC_ERR_TIMEOUT; 634 mmc_ms_delay(10); 635 } 636 if (rocr && err == MMC_ERR_NONE) 637 *rocr = cmd.resp[0]; 638 return (err); 639} 640 641static int 642mmc_send_if_cond(struct mmc_softc *sc, uint8_t vhs) 643{ 644 struct mmc_command cmd; 645 int err; 646 647 memset(&cmd, 0, sizeof(cmd)); 648 cmd.opcode = SD_SEND_IF_COND; 649 cmd.arg = (vhs << 8) + 0xAA; 650 cmd.flags = MMC_RSP_R7 | MMC_CMD_BCR; 651 cmd.data = NULL; 652 653 err = mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, CMD_RETRIES); 654 return (err); 655} 656 657static void 658mmc_power_up(struct mmc_softc *sc) 659{ 660 device_t dev; 661 enum mmc_vccq vccq; 662 663 dev = sc->dev; 664 mmcbr_set_vdd(dev, mmc_highest_voltage(mmcbr_get_host_ocr(dev))); 665 mmcbr_set_bus_mode(dev, opendrain); 666 mmcbr_set_chip_select(dev, cs_dontcare); 667 mmcbr_set_bus_width(dev, bus_width_1); 668 mmcbr_set_power_mode(dev, power_up); 669 mmcbr_set_clock(dev, 0); 670 mmcbr_update_ios(dev); 671 for (vccq = vccq_330; ; vccq--) { 672 mmcbr_set_vccq(dev, vccq); 673 if (mmcbr_switch_vccq(dev) == 0 || vccq == vccq_120) 674 break; 675 } 676 mmc_ms_delay(1); 677 678 mmcbr_set_clock(dev, SD_MMC_CARD_ID_FREQUENCY); 679 mmcbr_set_timing(dev, bus_timing_normal); 680 mmcbr_set_power_mode(dev, power_on); 681 mmcbr_update_ios(dev); 682 mmc_ms_delay(2); 683} 684 685static void 686mmc_power_down(struct mmc_softc *sc) 687{ 688 device_t dev = sc->dev; 689 690 mmcbr_set_bus_mode(dev, opendrain); 691 mmcbr_set_chip_select(dev, cs_dontcare); 692 mmcbr_set_bus_width(dev, bus_width_1); 693 mmcbr_set_power_mode(dev, power_off); 694 mmcbr_set_clock(dev, 0); 695 mmcbr_set_timing(dev, bus_timing_normal); 696 mmcbr_update_ios(dev); 697} 698 699static int 700mmc_select_card(struct mmc_softc *sc, uint16_t rca) 701{ 702 int err, flags; 703 704 flags = (rca ? MMC_RSP_R1B : MMC_RSP_NONE) | MMC_CMD_AC; 705 sc->retune_paused++; 706 err = mmc_wait_for_command(sc, MMC_SELECT_CARD, (uint32_t)rca << 16, 707 flags, NULL, CMD_RETRIES); 708 sc->retune_paused--; 709 return (err); 710} 711 712static int 713mmc_sd_switch(struct mmc_softc *sc, uint8_t mode, uint8_t grp, uint8_t value, 714 uint8_t *res) 715{ 716 int err; 717 struct mmc_command cmd; 718 struct mmc_data data; 719 720 memset(&cmd, 0, sizeof(cmd)); 721 memset(&data, 0, sizeof(data)); 722 memset(res, 0, 64); 723 724 cmd.opcode = SD_SWITCH_FUNC; 725 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 726 cmd.arg = mode << 31; /* 0 - check, 1 - set */ 727 cmd.arg |= 0x00FFFFFF; 728 cmd.arg &= ~(0xF << (grp * 4)); 729 cmd.arg |= value << (grp * 4); 730 cmd.data = &data; 731 732 data.data = res; 733 data.len = 64; 734 data.flags = MMC_DATA_READ; 735 736 err = mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, CMD_RETRIES); 737 return (err); 738} 739 740static int 741mmc_set_card_bus_width(struct mmc_softc *sc, struct mmc_ivars *ivar, 742 enum mmc_bus_timing timing) 743{ 744 struct mmc_command cmd; 745 int err; 746 uint8_t value; 747 748 if (mmcbr_get_mode(sc->dev) == mode_sd) { 749 memset(&cmd, 0, sizeof(cmd)); 750 cmd.opcode = ACMD_SET_CLR_CARD_DETECT; 751 cmd.flags = MMC_RSP_R1 | MMC_CMD_AC; 752 cmd.arg = SD_CLR_CARD_DETECT; 753 err = mmc_wait_for_app_cmd(sc->dev, sc->dev, ivar->rca, &cmd, 754 CMD_RETRIES); 755 if (err != 0) 756 return (err); 757 memset(&cmd, 0, sizeof(cmd)); 758 cmd.opcode = ACMD_SET_BUS_WIDTH; 759 cmd.flags = MMC_RSP_R1 | MMC_CMD_AC; 760 switch (ivar->bus_width) { 761 case bus_width_1: 762 cmd.arg = SD_BUS_WIDTH_1; 763 break; 764 case bus_width_4: 765 cmd.arg = SD_BUS_WIDTH_4; 766 break; 767 default: 768 return (MMC_ERR_INVALID); 769 } 770 err = mmc_wait_for_app_cmd(sc->dev, sc->dev, ivar->rca, &cmd, 771 CMD_RETRIES); 772 } else { 773 switch (ivar->bus_width) { 774 case bus_width_1: 775 if (timing == bus_timing_mmc_hs400 || 776 timing == bus_timing_mmc_hs400es) 777 return (MMC_ERR_INVALID); 778 value = EXT_CSD_BUS_WIDTH_1; 779 break; 780 case bus_width_4: 781 switch (timing) { 782 case bus_timing_mmc_ddr52: 783 value = EXT_CSD_BUS_WIDTH_4_DDR; 784 break; 785 case bus_timing_mmc_hs400: 786 case bus_timing_mmc_hs400es: 787 return (MMC_ERR_INVALID); 788 default: 789 value = EXT_CSD_BUS_WIDTH_4; 790 break; 791 } 792 break; 793 case bus_width_8: 794 value = 0; 795 switch (timing) { 796 case bus_timing_mmc_hs400es: 797 value = EXT_CSD_BUS_WIDTH_ES; 798 /* FALLTHROUGH */ 799 case bus_timing_mmc_ddr52: 800 case bus_timing_mmc_hs400: 801 value |= EXT_CSD_BUS_WIDTH_8_DDR; 802 break; 803 default: 804 value = EXT_CSD_BUS_WIDTH_8; 805 break; 806 } 807 break; 808 default: 809 return (MMC_ERR_INVALID); 810 } 811 err = mmc_switch(sc->dev, sc->dev, ivar->rca, 812 EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, value, 813 ivar->cmd6_time, true); 814 } 815 return (err); 816} 817 818static int 819mmc_set_power_class(struct mmc_softc *sc, struct mmc_ivars *ivar) 820{ 821 device_t dev; 822 const uint8_t *ext_csd; 823 uint32_t clock; 824 uint8_t value; 825 enum mmc_bus_timing timing; 826 enum mmc_bus_width bus_width; 827 828 dev = sc->dev; 829 timing = mmcbr_get_timing(dev); 830 bus_width = ivar->bus_width; 831 if (mmcbr_get_mode(dev) != mode_mmc || ivar->csd.spec_vers < 4 || 832 timing == bus_timing_normal || bus_width == bus_width_1) 833 return (MMC_ERR_NONE); 834 835 value = 0; 836 ext_csd = ivar->raw_ext_csd; 837 clock = mmcbr_get_clock(dev); 838 switch (1 << mmcbr_get_vdd(dev)) { 839 case MMC_OCR_LOW_VOLTAGE: 840 if (clock <= MMC_TYPE_HS_26_MAX) 841 value = ext_csd[EXT_CSD_PWR_CL_26_195]; 842 else if (clock <= MMC_TYPE_HS_52_MAX) { 843 if (timing >= bus_timing_mmc_ddr52 && 844 bus_width >= bus_width_4) 845 value = ext_csd[EXT_CSD_PWR_CL_52_195_DDR]; 846 else 847 value = ext_csd[EXT_CSD_PWR_CL_52_195]; 848 } else if (clock <= MMC_TYPE_HS200_HS400ES_MAX) 849 value = ext_csd[EXT_CSD_PWR_CL_200_195]; 850 break; 851 case MMC_OCR_270_280: 852 case MMC_OCR_280_290: 853 case MMC_OCR_290_300: 854 case MMC_OCR_300_310: 855 case MMC_OCR_310_320: 856 case MMC_OCR_320_330: 857 case MMC_OCR_330_340: 858 case MMC_OCR_340_350: 859 case MMC_OCR_350_360: 860 if (clock <= MMC_TYPE_HS_26_MAX) 861 value = ext_csd[EXT_CSD_PWR_CL_26_360]; 862 else if (clock <= MMC_TYPE_HS_52_MAX) { 863 if (timing == bus_timing_mmc_ddr52 && 864 bus_width >= bus_width_4) 865 value = ext_csd[EXT_CSD_PWR_CL_52_360_DDR]; 866 else 867 value = ext_csd[EXT_CSD_PWR_CL_52_360]; 868 } else if (clock <= MMC_TYPE_HS200_HS400ES_MAX) { 869 if (bus_width == bus_width_8) 870 value = ext_csd[EXT_CSD_PWR_CL_200_360_DDR]; 871 else 872 value = ext_csd[EXT_CSD_PWR_CL_200_360]; 873 } 874 break; 875 default: 876 device_printf(dev, "No power class support for VDD 0x%x\n", 877 1 << mmcbr_get_vdd(dev)); 878 return (MMC_ERR_INVALID); 879 } 880 881 if (bus_width == bus_width_8) 882 value = (value & EXT_CSD_POWER_CLASS_8BIT_MASK) >> 883 EXT_CSD_POWER_CLASS_8BIT_SHIFT; 884 else 885 value = (value & EXT_CSD_POWER_CLASS_4BIT_MASK) >> 886 EXT_CSD_POWER_CLASS_4BIT_SHIFT; 887 888 if (value == 0) 889 return (MMC_ERR_NONE); 890 891 return (mmc_switch(dev, dev, ivar->rca, EXT_CSD_CMD_SET_NORMAL, 892 EXT_CSD_POWER_CLASS, value, ivar->cmd6_time, true)); 893} 894 895static int 896mmc_set_timing(struct mmc_softc *sc, struct mmc_ivars *ivar, 897 enum mmc_bus_timing timing) 898{ 899 u_char switch_res[64]; 900 uint8_t value; 901 int err; 902 903 if (mmcbr_get_mode(sc->dev) == mode_sd) { 904 switch (timing) { 905 case bus_timing_normal: 906 value = SD_SWITCH_NORMAL_MODE; 907 break; 908 case bus_timing_hs: 909 value = SD_SWITCH_HS_MODE; 910 break; 911 default: 912 return (MMC_ERR_INVALID); 913 } 914 err = mmc_sd_switch(sc, SD_SWITCH_MODE_SET, SD_SWITCH_GROUP1, 915 value, switch_res); 916 if (err != MMC_ERR_NONE) 917 return (err); 918 if ((switch_res[16] & 0xf) != value) 919 return (MMC_ERR_FAILED); 920 mmcbr_set_timing(sc->dev, timing); 921 mmcbr_update_ios(sc->dev); 922 } else { 923 switch (timing) { 924 case bus_timing_normal: 925 value = EXT_CSD_HS_TIMING_BC; 926 break; 927 case bus_timing_hs: 928 case bus_timing_mmc_ddr52: 929 value = EXT_CSD_HS_TIMING_HS; 930 break; 931 case bus_timing_mmc_hs200: 932 value = EXT_CSD_HS_TIMING_HS200; 933 break; 934 case bus_timing_mmc_hs400: 935 case bus_timing_mmc_hs400es: 936 value = EXT_CSD_HS_TIMING_HS400; 937 break; 938 default: 939 return (MMC_ERR_INVALID); 940 } 941 err = mmc_switch(sc->dev, sc->dev, ivar->rca, 942 EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, value, 943 ivar->cmd6_time, false); 944 if (err != MMC_ERR_NONE) 945 return (err); 946 mmcbr_set_timing(sc->dev, timing); 947 mmcbr_update_ios(sc->dev); 948 err = mmc_switch_status(sc->dev, sc->dev, ivar->rca, 949 ivar->cmd6_time); 950 } 951 return (err); 952} 953 954static int 955mmc_set_vccq(struct mmc_softc *sc, struct mmc_ivars *ivar, 956 enum mmc_bus_timing timing) 957{ 958 959 if (isset(&ivar->vccq_120, timing)) 960 mmcbr_set_vccq(sc->dev, vccq_120); 961 else if (isset(&ivar->vccq_180, timing)) 962 mmcbr_set_vccq(sc->dev, vccq_180); 963 else 964 mmcbr_set_vccq(sc->dev, vccq_330); 965 if (mmcbr_switch_vccq(sc->dev) != 0) 966 return (MMC_ERR_INVALID); 967 else 968 return (MMC_ERR_NONE); 969} 970 971static const uint8_t p8[8] = { 972 0x55, 0xAA, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 973}; 974 975static const uint8_t p8ok[8] = { 976 0xAA, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 977}; 978 979static const uint8_t p4[4] = { 980 0x5A, 0x00, 0x00, 0x00 981}; 982 983static const uint8_t p4ok[4] = { 984 0xA5, 0x00, 0x00, 0x00 985}; 986 987static int 988mmc_test_bus_width(struct mmc_softc *sc) 989{ 990 struct mmc_command cmd; 991 struct mmc_data data; 992 uint8_t buf[8]; 993 int err; 994 995 if (mmcbr_get_caps(sc->dev) & MMC_CAP_8_BIT_DATA) { 996 mmcbr_set_bus_width(sc->dev, bus_width_8); 997 mmcbr_update_ios(sc->dev); 998 999 sc->squelched++; /* Errors are expected, squelch reporting. */ 1000 memset(&cmd, 0, sizeof(cmd)); 1001 memset(&data, 0, sizeof(data)); 1002 cmd.opcode = MMC_BUSTEST_W; 1003 cmd.arg = 0; 1004 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1005 cmd.data = &data; 1006 1007 data.data = __DECONST(void *, p8); 1008 data.len = 8; 1009 data.flags = MMC_DATA_WRITE; 1010 mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, 0); 1011 1012 memset(&cmd, 0, sizeof(cmd)); 1013 memset(&data, 0, sizeof(data)); 1014 cmd.opcode = MMC_BUSTEST_R; 1015 cmd.arg = 0; 1016 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1017 cmd.data = &data; 1018 1019 data.data = buf; 1020 data.len = 8; 1021 data.flags = MMC_DATA_READ; 1022 err = mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, 0); 1023 sc->squelched--; 1024 1025 mmcbr_set_bus_width(sc->dev, bus_width_1); 1026 mmcbr_update_ios(sc->dev); 1027 1028 if (err == MMC_ERR_NONE && memcmp(buf, p8ok, 8) == 0) 1029 return (bus_width_8); 1030 } 1031 1032 if (mmcbr_get_caps(sc->dev) & MMC_CAP_4_BIT_DATA) { 1033 mmcbr_set_bus_width(sc->dev, bus_width_4); 1034 mmcbr_update_ios(sc->dev); 1035 1036 sc->squelched++; /* Errors are expected, squelch reporting. */ 1037 memset(&cmd, 0, sizeof(cmd)); 1038 memset(&data, 0, sizeof(data)); 1039 cmd.opcode = MMC_BUSTEST_W; 1040 cmd.arg = 0; 1041 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1042 cmd.data = &data; 1043 1044 data.data = __DECONST(void *, p4); 1045 data.len = 4; 1046 data.flags = MMC_DATA_WRITE; 1047 mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, 0); 1048 1049 memset(&cmd, 0, sizeof(cmd)); 1050 memset(&data, 0, sizeof(data)); 1051 cmd.opcode = MMC_BUSTEST_R; 1052 cmd.arg = 0; 1053 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1054 cmd.data = &data; 1055 1056 data.data = buf; 1057 data.len = 4; 1058 data.flags = MMC_DATA_READ; 1059 err = mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, 0); 1060 sc->squelched--; 1061 1062 mmcbr_set_bus_width(sc->dev, bus_width_1); 1063 mmcbr_update_ios(sc->dev); 1064 1065 if (err == MMC_ERR_NONE && memcmp(buf, p4ok, 4) == 0) 1066 return (bus_width_4); 1067 } 1068 return (bus_width_1); 1069} 1070 1071static uint32_t 1072mmc_get_bits(uint32_t *bits, int bit_len, int start, int size) 1073{ 1074 const int i = (bit_len / 32) - (start / 32) - 1; 1075 const int shift = start & 31; 1076 uint32_t retval = bits[i] >> shift; 1077 1078 if (size + shift > 32) 1079 retval |= bits[i - 1] << (32 - shift); 1080 return (retval & ((1llu << size) - 1)); 1081} 1082 1083static void 1084mmc_decode_cid_sd(uint32_t *raw_cid, struct mmc_cid *cid) 1085{ 1086 int i; 1087 1088 /* There's no version info, so we take it on faith */ 1089 memset(cid, 0, sizeof(*cid)); 1090 cid->mid = mmc_get_bits(raw_cid, 128, 120, 8); 1091 cid->oid = mmc_get_bits(raw_cid, 128, 104, 16); 1092 for (i = 0; i < 5; i++) 1093 cid->pnm[i] = mmc_get_bits(raw_cid, 128, 96 - i * 8, 8); 1094 cid->pnm[5] = 0; 1095 cid->prv = mmc_get_bits(raw_cid, 128, 56, 8); 1096 cid->psn = mmc_get_bits(raw_cid, 128, 24, 32); 1097 cid->mdt_year = mmc_get_bits(raw_cid, 128, 12, 8) + 2000; 1098 cid->mdt_month = mmc_get_bits(raw_cid, 128, 8, 4); 1099} 1100 1101static void 1102mmc_decode_cid_mmc(uint32_t *raw_cid, struct mmc_cid *cid, bool is_4_41p) 1103{ 1104 int i; 1105 1106 /* There's no version info, so we take it on faith */ 1107 memset(cid, 0, sizeof(*cid)); 1108 cid->mid = mmc_get_bits(raw_cid, 128, 120, 8); 1109 cid->oid = mmc_get_bits(raw_cid, 128, 104, 8); 1110 for (i = 0; i < 6; i++) 1111 cid->pnm[i] = mmc_get_bits(raw_cid, 128, 96 - i * 8, 8); 1112 cid->pnm[6] = 0; 1113 cid->prv = mmc_get_bits(raw_cid, 128, 48, 8); 1114 cid->psn = mmc_get_bits(raw_cid, 128, 16, 32); 1115 cid->mdt_month = mmc_get_bits(raw_cid, 128, 12, 4); 1116 cid->mdt_year = mmc_get_bits(raw_cid, 128, 8, 4); 1117 if (is_4_41p) 1118 cid->mdt_year += 2013; 1119 else 1120 cid->mdt_year += 1997; 1121} 1122 1123static void 1124mmc_format_card_id_string(struct mmc_ivars *ivar) 1125{ 1126 char oidstr[8]; 1127 uint8_t c1; 1128 uint8_t c2; 1129 1130 /* 1131 * Format a card ID string for use by the mmcsd driver, it's what 1132 * appears between the <> in the following: 1133 * mmcsd0: 968MB <SD SD01G 8.0 SN 2686905 MFG 08/2008 by 3 TN> at mmc0 1134 * 22.5MHz/4bit/128-block 1135 * 1136 * Also format just the card serial number, which the mmcsd driver will 1137 * use as the disk->d_ident string. 1138 * 1139 * The card_id_string in mmc_ivars is currently allocated as 64 bytes, 1140 * and our max formatted length is currently 55 bytes if every field 1141 * contains the largest value. 1142 * 1143 * Sometimes the oid is two printable ascii chars; when it's not, 1144 * format it as 0xnnnn instead. 1145 */ 1146 c1 = (ivar->cid.oid >> 8) & 0x0ff; 1147 c2 = ivar->cid.oid & 0x0ff; 1148 if (c1 > 0x1f && c1 < 0x7f && c2 > 0x1f && c2 < 0x7f) 1149 snprintf(oidstr, sizeof(oidstr), "%c%c", c1, c2); 1150 else 1151 snprintf(oidstr, sizeof(oidstr), "0x%04x", ivar->cid.oid); 1152 snprintf(ivar->card_sn_string, sizeof(ivar->card_sn_string), 1153 "%08X", ivar->cid.psn); 1154 snprintf(ivar->card_id_string, sizeof(ivar->card_id_string), 1155 "%s%s %s %d.%d SN %08X MFG %02d/%04d by %d %s", 1156 ivar->mode == mode_sd ? "SD" : "MMC", ivar->high_cap ? "HC" : "", 1157 ivar->cid.pnm, ivar->cid.prv >> 4, ivar->cid.prv & 0x0f, 1158 ivar->cid.psn, ivar->cid.mdt_month, ivar->cid.mdt_year, 1159 ivar->cid.mid, oidstr); 1160} 1161 1162static const int exp[8] = { 1163 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000 1164}; 1165 1166static const int mant[16] = { 1167 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80 1168}; 1169 1170static const int cur_min[8] = { 1171 500, 1000, 5000, 10000, 25000, 35000, 60000, 100000 1172}; 1173 1174static const int cur_max[8] = { 1175 1000, 5000, 10000, 25000, 35000, 45000, 800000, 200000 1176}; 1177 1178static int 1179mmc_decode_csd_sd(uint32_t *raw_csd, struct mmc_csd *csd) 1180{ 1181 int v; 1182 int m; 1183 int e; 1184 1185 memset(csd, 0, sizeof(*csd)); 1186 csd->csd_structure = v = mmc_get_bits(raw_csd, 128, 126, 2); 1187 if (v == 0) { 1188 m = mmc_get_bits(raw_csd, 128, 115, 4); 1189 e = mmc_get_bits(raw_csd, 128, 112, 3); 1190 csd->tacc = (exp[e] * mant[m] + 9) / 10; 1191 csd->nsac = mmc_get_bits(raw_csd, 128, 104, 8) * 100; 1192 m = mmc_get_bits(raw_csd, 128, 99, 4); 1193 e = mmc_get_bits(raw_csd, 128, 96, 3); 1194 csd->tran_speed = exp[e] * 10000 * mant[m]; 1195 csd->ccc = mmc_get_bits(raw_csd, 128, 84, 12); 1196 csd->read_bl_len = 1 << mmc_get_bits(raw_csd, 128, 80, 4); 1197 csd->read_bl_partial = mmc_get_bits(raw_csd, 128, 79, 1); 1198 csd->write_blk_misalign = mmc_get_bits(raw_csd, 128, 78, 1); 1199 csd->read_blk_misalign = mmc_get_bits(raw_csd, 128, 77, 1); 1200 csd->dsr_imp = mmc_get_bits(raw_csd, 128, 76, 1); 1201 csd->vdd_r_curr_min = 1202 cur_min[mmc_get_bits(raw_csd, 128, 59, 3)]; 1203 csd->vdd_r_curr_max = 1204 cur_max[mmc_get_bits(raw_csd, 128, 56, 3)]; 1205 csd->vdd_w_curr_min = 1206 cur_min[mmc_get_bits(raw_csd, 128, 53, 3)]; 1207 csd->vdd_w_curr_max = 1208 cur_max[mmc_get_bits(raw_csd, 128, 50, 3)]; 1209 m = mmc_get_bits(raw_csd, 128, 62, 12); 1210 e = mmc_get_bits(raw_csd, 128, 47, 3); 1211 csd->capacity = ((1 + m) << (e + 2)) * csd->read_bl_len; 1212 csd->erase_blk_en = mmc_get_bits(raw_csd, 128, 46, 1); 1213 csd->erase_sector = mmc_get_bits(raw_csd, 128, 39, 7) + 1; 1214 csd->wp_grp_size = mmc_get_bits(raw_csd, 128, 32, 7); 1215 csd->wp_grp_enable = mmc_get_bits(raw_csd, 128, 31, 1); 1216 csd->r2w_factor = 1 << mmc_get_bits(raw_csd, 128, 26, 3); 1217 csd->write_bl_len = 1 << mmc_get_bits(raw_csd, 128, 22, 4); 1218 csd->write_bl_partial = mmc_get_bits(raw_csd, 128, 21, 1); 1219 return (MMC_ERR_NONE); 1220 } else if (v == 1) { 1221 m = mmc_get_bits(raw_csd, 128, 115, 4); 1222 e = mmc_get_bits(raw_csd, 128, 112, 3); 1223 csd->tacc = (exp[e] * mant[m] + 9) / 10; 1224 csd->nsac = mmc_get_bits(raw_csd, 128, 104, 8) * 100; 1225 m = mmc_get_bits(raw_csd, 128, 99, 4); 1226 e = mmc_get_bits(raw_csd, 128, 96, 3); 1227 csd->tran_speed = exp[e] * 10000 * mant[m]; 1228 csd->ccc = mmc_get_bits(raw_csd, 128, 84, 12); 1229 csd->read_bl_len = 1 << mmc_get_bits(raw_csd, 128, 80, 4); 1230 csd->read_bl_partial = mmc_get_bits(raw_csd, 128, 79, 1); 1231 csd->write_blk_misalign = mmc_get_bits(raw_csd, 128, 78, 1); 1232 csd->read_blk_misalign = mmc_get_bits(raw_csd, 128, 77, 1); 1233 csd->dsr_imp = mmc_get_bits(raw_csd, 128, 76, 1); 1234 csd->capacity = ((uint64_t)mmc_get_bits(raw_csd, 128, 48, 22) + 1235 1) * 512 * 1024; 1236 csd->erase_blk_en = mmc_get_bits(raw_csd, 128, 46, 1); 1237 csd->erase_sector = mmc_get_bits(raw_csd, 128, 39, 7) + 1; 1238 csd->wp_grp_size = mmc_get_bits(raw_csd, 128, 32, 7); 1239 csd->wp_grp_enable = mmc_get_bits(raw_csd, 128, 31, 1); 1240 csd->r2w_factor = 1 << mmc_get_bits(raw_csd, 128, 26, 3); 1241 csd->write_bl_len = 1 << mmc_get_bits(raw_csd, 128, 22, 4); 1242 csd->write_bl_partial = mmc_get_bits(raw_csd, 128, 21, 1); 1243 return (MMC_ERR_NONE); 1244 } 1245 return (MMC_ERR_INVALID); 1246} 1247 1248static void 1249mmc_decode_csd_mmc(uint32_t *raw_csd, struct mmc_csd *csd) 1250{ 1251 int m; 1252 int e; 1253 1254 memset(csd, 0, sizeof(*csd)); 1255 csd->csd_structure = mmc_get_bits(raw_csd, 128, 126, 2); 1256 csd->spec_vers = mmc_get_bits(raw_csd, 128, 122, 4); 1257 m = mmc_get_bits(raw_csd, 128, 115, 4); 1258 e = mmc_get_bits(raw_csd, 128, 112, 3); 1259 csd->tacc = exp[e] * mant[m] + 9 / 10; 1260 csd->nsac = mmc_get_bits(raw_csd, 128, 104, 8) * 100; 1261 m = mmc_get_bits(raw_csd, 128, 99, 4); 1262 e = mmc_get_bits(raw_csd, 128, 96, 3); 1263 csd->tran_speed = exp[e] * 10000 * mant[m]; 1264 csd->ccc = mmc_get_bits(raw_csd, 128, 84, 12); 1265 csd->read_bl_len = 1 << mmc_get_bits(raw_csd, 128, 80, 4); 1266 csd->read_bl_partial = mmc_get_bits(raw_csd, 128, 79, 1); 1267 csd->write_blk_misalign = mmc_get_bits(raw_csd, 128, 78, 1); 1268 csd->read_blk_misalign = mmc_get_bits(raw_csd, 128, 77, 1); 1269 csd->dsr_imp = mmc_get_bits(raw_csd, 128, 76, 1); 1270 csd->vdd_r_curr_min = cur_min[mmc_get_bits(raw_csd, 128, 59, 3)]; 1271 csd->vdd_r_curr_max = cur_max[mmc_get_bits(raw_csd, 128, 56, 3)]; 1272 csd->vdd_w_curr_min = cur_min[mmc_get_bits(raw_csd, 128, 53, 3)]; 1273 csd->vdd_w_curr_max = cur_max[mmc_get_bits(raw_csd, 128, 50, 3)]; 1274 m = mmc_get_bits(raw_csd, 128, 62, 12); 1275 e = mmc_get_bits(raw_csd, 128, 47, 3); 1276 csd->capacity = ((1 + m) << (e + 2)) * csd->read_bl_len; 1277 csd->erase_blk_en = 0; 1278 csd->erase_sector = (mmc_get_bits(raw_csd, 128, 42, 5) + 1) * 1279 (mmc_get_bits(raw_csd, 128, 37, 5) + 1); 1280 csd->wp_grp_size = mmc_get_bits(raw_csd, 128, 32, 5); 1281 csd->wp_grp_enable = mmc_get_bits(raw_csd, 128, 31, 1); 1282 csd->r2w_factor = 1 << mmc_get_bits(raw_csd, 128, 26, 3); 1283 csd->write_bl_len = 1 << mmc_get_bits(raw_csd, 128, 22, 4); 1284 csd->write_bl_partial = mmc_get_bits(raw_csd, 128, 21, 1); 1285} 1286 1287static void 1288mmc_app_decode_scr(uint32_t *raw_scr, struct mmc_scr *scr) 1289{ 1290 unsigned int scr_struct; 1291 1292 memset(scr, 0, sizeof(*scr)); 1293 1294 scr_struct = mmc_get_bits(raw_scr, 64, 60, 4); 1295 if (scr_struct != 0) { 1296 printf("Unrecognised SCR structure version %d\n", 1297 scr_struct); 1298 return; 1299 } 1300 scr->sda_vsn = mmc_get_bits(raw_scr, 64, 56, 4); 1301 scr->bus_widths = mmc_get_bits(raw_scr, 64, 48, 4); 1302} 1303 1304static void 1305mmc_app_decode_sd_status(uint32_t *raw_sd_status, 1306 struct mmc_sd_status *sd_status) 1307{ 1308 1309 memset(sd_status, 0, sizeof(*sd_status)); 1310 1311 sd_status->bus_width = mmc_get_bits(raw_sd_status, 512, 510, 2); 1312 sd_status->secured_mode = mmc_get_bits(raw_sd_status, 512, 509, 1); 1313 sd_status->card_type = mmc_get_bits(raw_sd_status, 512, 480, 16); 1314 sd_status->prot_area = mmc_get_bits(raw_sd_status, 512, 448, 12); 1315 sd_status->speed_class = mmc_get_bits(raw_sd_status, 512, 440, 8); 1316 sd_status->perf_move = mmc_get_bits(raw_sd_status, 512, 432, 8); 1317 sd_status->au_size = mmc_get_bits(raw_sd_status, 512, 428, 4); 1318 sd_status->erase_size = mmc_get_bits(raw_sd_status, 512, 408, 16); 1319 sd_status->erase_timeout = mmc_get_bits(raw_sd_status, 512, 402, 6); 1320 sd_status->erase_offset = mmc_get_bits(raw_sd_status, 512, 400, 2); 1321} 1322 1323static int 1324mmc_all_send_cid(struct mmc_softc *sc, uint32_t *rawcid) 1325{ 1326 struct mmc_command cmd; 1327 int err; 1328 1329 memset(&cmd, 0, sizeof(cmd)); 1330 cmd.opcode = MMC_ALL_SEND_CID; 1331 cmd.arg = 0; 1332 cmd.flags = MMC_RSP_R2 | MMC_CMD_BCR; 1333 cmd.data = NULL; 1334 err = mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, CMD_RETRIES); 1335 memcpy(rawcid, cmd.resp, 4 * sizeof(uint32_t)); 1336 return (err); 1337} 1338 1339static int 1340mmc_send_csd(struct mmc_softc *sc, uint16_t rca, uint32_t *rawcsd) 1341{ 1342 struct mmc_command cmd; 1343 int err; 1344 1345 memset(&cmd, 0, sizeof(cmd)); 1346 cmd.opcode = MMC_SEND_CSD; 1347 cmd.arg = rca << 16; 1348 cmd.flags = MMC_RSP_R2 | MMC_CMD_BCR; 1349 cmd.data = NULL; 1350 err = mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, CMD_RETRIES); 1351 memcpy(rawcsd, cmd.resp, 4 * sizeof(uint32_t)); 1352 return (err); 1353} 1354 1355static int 1356mmc_app_send_scr(struct mmc_softc *sc, uint16_t rca, uint32_t *rawscr) 1357{ 1358 int err; 1359 struct mmc_command cmd; 1360 struct mmc_data data; 1361 1362 memset(&cmd, 0, sizeof(cmd)); 1363 memset(&data, 0, sizeof(data)); 1364 1365 memset(rawscr, 0, 8); 1366 cmd.opcode = ACMD_SEND_SCR; 1367 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1368 cmd.arg = 0; 1369 cmd.data = &data; 1370 1371 data.data = rawscr; 1372 data.len = 8; 1373 data.flags = MMC_DATA_READ; 1374 1375 err = mmc_wait_for_app_cmd(sc->dev, sc->dev, rca, &cmd, CMD_RETRIES); 1376 rawscr[0] = be32toh(rawscr[0]); 1377 rawscr[1] = be32toh(rawscr[1]); 1378 return (err); 1379} 1380 1381static int 1382mmc_app_sd_status(struct mmc_softc *sc, uint16_t rca, uint32_t *rawsdstatus) 1383{ 1384 struct mmc_command cmd; 1385 struct mmc_data data; 1386 int err, i; 1387 1388 memset(&cmd, 0, sizeof(cmd)); 1389 memset(&data, 0, sizeof(data)); 1390 1391 memset(rawsdstatus, 0, 64); 1392 cmd.opcode = ACMD_SD_STATUS; 1393 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1394 cmd.arg = 0; 1395 cmd.data = &data; 1396 1397 data.data = rawsdstatus; 1398 data.len = 64; 1399 data.flags = MMC_DATA_READ; 1400 1401 err = mmc_wait_for_app_cmd(sc->dev, sc->dev, rca, &cmd, CMD_RETRIES); 1402 for (i = 0; i < 16; i++) 1403 rawsdstatus[i] = be32toh(rawsdstatus[i]); 1404 return (err); 1405} 1406 1407static int 1408mmc_set_relative_addr(struct mmc_softc *sc, uint16_t resp) 1409{ 1410 struct mmc_command cmd; 1411 int err; 1412 1413 memset(&cmd, 0, sizeof(cmd)); 1414 cmd.opcode = MMC_SET_RELATIVE_ADDR; 1415 cmd.arg = resp << 16; 1416 cmd.flags = MMC_RSP_R6 | MMC_CMD_BCR; 1417 cmd.data = NULL; 1418 err = mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, CMD_RETRIES); 1419 return (err); 1420} 1421 1422static int 1423mmc_send_relative_addr(struct mmc_softc *sc, uint32_t *resp) 1424{ 1425 struct mmc_command cmd; 1426 int err; 1427 1428 memset(&cmd, 0, sizeof(cmd)); 1429 cmd.opcode = SD_SEND_RELATIVE_ADDR; 1430 cmd.arg = 0; 1431 cmd.flags = MMC_RSP_R6 | MMC_CMD_BCR; 1432 cmd.data = NULL; 1433 err = mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, CMD_RETRIES); 1434 *resp = cmd.resp[0]; 1435 return (err); 1436} 1437 1438static int 1439mmc_set_blocklen(struct mmc_softc *sc, uint32_t len) 1440{ 1441 struct mmc_command cmd; 1442 int err; 1443 1444 memset(&cmd, 0, sizeof(cmd)); 1445 cmd.opcode = MMC_SET_BLOCKLEN; 1446 cmd.arg = len; 1447 cmd.flags = MMC_RSP_R1 | MMC_CMD_AC; 1448 cmd.data = NULL; 1449 err = mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, CMD_RETRIES); 1450 return (err); 1451} 1452 1453static uint32_t 1454mmc_timing_to_dtr(struct mmc_ivars *ivar, enum mmc_bus_timing timing) 1455{ 1456 1457 switch (timing) { 1458 case bus_timing_normal: 1459 return (ivar->tran_speed); 1460 case bus_timing_hs: 1461 return (ivar->hs_tran_speed); 1462 case bus_timing_uhs_sdr12: 1463 return (SD_SDR12_MAX); 1464 case bus_timing_uhs_sdr25: 1465 return (SD_SDR25_MAX); 1466 case bus_timing_uhs_ddr50: 1467 return (SD_DDR50_MAX); 1468 case bus_timing_uhs_sdr50: 1469 return (SD_SDR50_MAX); 1470 case bus_timing_uhs_sdr104: 1471 return (SD_SDR104_MAX); 1472 case bus_timing_mmc_ddr52: 1473 return (MMC_TYPE_DDR52_MAX); 1474 case bus_timing_mmc_hs200: 1475 case bus_timing_mmc_hs400: 1476 case bus_timing_mmc_hs400es: 1477 return (MMC_TYPE_HS200_HS400ES_MAX); 1478 } 1479 return (0); 1480} 1481 1482static const char * 1483mmc_timing_to_string(enum mmc_bus_timing timing) 1484{ 1485 1486 switch (timing) { 1487 case bus_timing_normal: 1488 return ("normal speed"); 1489 case bus_timing_hs: 1490 return ("high speed"); 1491 case bus_timing_uhs_sdr12: 1492 case bus_timing_uhs_sdr25: 1493 case bus_timing_uhs_sdr50: 1494 case bus_timing_uhs_sdr104: 1495 return ("single data rate"); 1496 case bus_timing_uhs_ddr50: 1497 case bus_timing_mmc_ddr52: 1498 return ("dual data rate"); 1499 case bus_timing_mmc_hs200: 1500 return ("HS200"); 1501 case bus_timing_mmc_hs400: 1502 return ("HS400"); 1503 case bus_timing_mmc_hs400es: 1504 return ("HS400 with enhanced strobe"); 1505 } 1506 return (""); 1507} 1508 1509static bool 1510mmc_host_timing(device_t dev, enum mmc_bus_timing timing) 1511{ 1512 int host_caps; 1513 1514 host_caps = mmcbr_get_caps(dev); 1515 1516#define HOST_TIMING_CAP(host_caps, cap) ({ \ 1517 bool retval; \ 1518 if (((host_caps) & (cap)) == (cap)) \ 1519 retval = true; \ 1520 else \ 1521 retval = false; \ 1522 retval; \ 1523}) 1524 1525 switch (timing) { 1526 case bus_timing_normal: 1527 return (true); 1528 case bus_timing_hs: 1529 return (HOST_TIMING_CAP(host_caps, MMC_CAP_HSPEED)); 1530 case bus_timing_uhs_sdr12: 1531 return (HOST_TIMING_CAP(host_caps, MMC_CAP_UHS_SDR12)); 1532 case bus_timing_uhs_sdr25: 1533 return (HOST_TIMING_CAP(host_caps, MMC_CAP_UHS_SDR25)); 1534 case bus_timing_uhs_ddr50: 1535 return (HOST_TIMING_CAP(host_caps, MMC_CAP_UHS_DDR50)); 1536 case bus_timing_uhs_sdr50: 1537 return (HOST_TIMING_CAP(host_caps, MMC_CAP_UHS_SDR50)); 1538 case bus_timing_uhs_sdr104: 1539 return (HOST_TIMING_CAP(host_caps, MMC_CAP_UHS_SDR104)); 1540 case bus_timing_mmc_ddr52: 1541 return (HOST_TIMING_CAP(host_caps, MMC_CAP_MMC_DDR52)); 1542 case bus_timing_mmc_hs200: 1543 return (HOST_TIMING_CAP(host_caps, MMC_CAP_MMC_HS200_120) || 1544 HOST_TIMING_CAP(host_caps, MMC_CAP_MMC_HS200_180)); 1545 case bus_timing_mmc_hs400: 1546 return (HOST_TIMING_CAP(host_caps, MMC_CAP_MMC_HS400_120) || 1547 HOST_TIMING_CAP(host_caps, MMC_CAP_MMC_HS400_180)); 1548 case bus_timing_mmc_hs400es: 1549 return (HOST_TIMING_CAP(host_caps, MMC_CAP_MMC_HS400 | 1550 MMC_CAP_MMC_ENH_STROBE)); 1551 } 1552 1553#undef HOST_TIMING_CAP 1554 1555 return (false); 1556} 1557 1558static void 1559mmc_log_card(device_t dev, struct mmc_ivars *ivar, int newcard) 1560{ 1561 enum mmc_bus_timing timing; 1562 1563 device_printf(dev, "Card at relative address 0x%04x%s:\n", 1564 ivar->rca, newcard ? " added" : ""); 1565 device_printf(dev, " card: %s\n", ivar->card_id_string); 1566 for (timing = bus_timing_max; timing > bus_timing_normal; timing--) { 1567 if (isset(&ivar->timings, timing)) 1568 break; 1569 } 1570 device_printf(dev, " quirks: %b\n", ivar->quirks, MMC_QUIRKS_FMT); 1571 device_printf(dev, " bus: %ubit, %uMHz (%s timing)\n", 1572 (ivar->bus_width == bus_width_1 ? 1 : 1573 (ivar->bus_width == bus_width_4 ? 4 : 8)), 1574 mmc_timing_to_dtr(ivar, timing) / 1000000, 1575 mmc_timing_to_string(timing)); 1576 device_printf(dev, " memory: %u blocks, erase sector %u blocks%s\n", 1577 ivar->sec_count, ivar->erase_sector, 1578 ivar->read_only ? ", read-only" : ""); 1579} 1580 1581static void 1582mmc_discover_cards(struct mmc_softc *sc) 1583{ 1584 u_char switch_res[64]; 1585 uint32_t raw_cid[4]; 1586 struct mmc_ivars *ivar = NULL; 1587 const struct mmc_quirk *quirk; 1588 const uint8_t *ext_csd; 1589 device_t child; 1590 int err, host_caps, i, newcard; 1591 uint32_t resp, sec_count, status; 1592 uint16_t rca = 2; 1593 int16_t rev; 1594 uint8_t card_type; 1595 1596 host_caps = mmcbr_get_caps(sc->dev); 1597 if (bootverbose || mmc_debug) 1598 device_printf(sc->dev, "Probing cards\n"); 1599 while (1) { 1600 child = NULL; 1601 sc->squelched++; /* Errors are expected, squelch reporting. */ 1602 err = mmc_all_send_cid(sc, raw_cid); 1603 sc->squelched--; 1604 if (err == MMC_ERR_TIMEOUT) 1605 break; 1606 if (err != MMC_ERR_NONE) { 1607 device_printf(sc->dev, "Error reading CID %d\n", err); 1608 break; 1609 } 1610 newcard = 1; 1611 for (i = 0; i < sc->child_count; i++) { 1612 ivar = device_get_ivars(sc->child_list[i]); 1613 if (memcmp(ivar->raw_cid, raw_cid, sizeof(raw_cid)) == 1614 0) { 1615 newcard = 0; 1616 break; 1617 } 1618 } 1619 if (bootverbose || mmc_debug) { 1620 device_printf(sc->dev, 1621 "%sard detected (CID %08x%08x%08x%08x)\n", 1622 newcard ? "New c" : "C", 1623 raw_cid[0], raw_cid[1], raw_cid[2], raw_cid[3]); 1624 } 1625 if (newcard) { 1626 ivar = malloc(sizeof(struct mmc_ivars), M_DEVBUF, 1627 M_WAITOK | M_ZERO); 1628 memcpy(ivar->raw_cid, raw_cid, sizeof(raw_cid)); 1629 } 1630 if (mmcbr_get_ro(sc->dev)) 1631 ivar->read_only = 1; 1632 ivar->bus_width = bus_width_1; 1633 setbit(&ivar->timings, bus_timing_normal); 1634 ivar->mode = mmcbr_get_mode(sc->dev); 1635 if (ivar->mode == mode_sd) { 1636 mmc_decode_cid_sd(ivar->raw_cid, &ivar->cid); 1637 err = mmc_send_relative_addr(sc, &resp); 1638 if (err != MMC_ERR_NONE) { 1639 device_printf(sc->dev, 1640 "Error getting RCA %d\n", err); 1641 goto free_ivar; 1642 } 1643 ivar->rca = resp >> 16; 1644 /* Get card CSD. */ 1645 err = mmc_send_csd(sc, ivar->rca, ivar->raw_csd); 1646 if (err != MMC_ERR_NONE) { 1647 device_printf(sc->dev, 1648 "Error getting CSD %d\n", err); 1649 goto free_ivar; 1650 } 1651 if (bootverbose || mmc_debug) 1652 device_printf(sc->dev, 1653 "%sard detected (CSD %08x%08x%08x%08x)\n", 1654 newcard ? "New c" : "C", ivar->raw_csd[0], 1655 ivar->raw_csd[1], ivar->raw_csd[2], 1656 ivar->raw_csd[3]); 1657 err = mmc_decode_csd_sd(ivar->raw_csd, &ivar->csd); 1658 if (err != MMC_ERR_NONE) { 1659 device_printf(sc->dev, "Error decoding CSD\n"); 1660 goto free_ivar; 1661 } 1662 ivar->sec_count = ivar->csd.capacity / MMC_SECTOR_SIZE; 1663 if (ivar->csd.csd_structure > 0) 1664 ivar->high_cap = 1; 1665 ivar->tran_speed = ivar->csd.tran_speed; 1666 ivar->erase_sector = ivar->csd.erase_sector * 1667 ivar->csd.write_bl_len / MMC_SECTOR_SIZE; 1668 1669 err = mmc_send_status(sc->dev, sc->dev, ivar->rca, 1670 &status); 1671 if (err != MMC_ERR_NONE) { 1672 device_printf(sc->dev, 1673 "Error reading card status %d\n", err); 1674 goto free_ivar; 1675 } 1676 if ((status & R1_CARD_IS_LOCKED) != 0) { 1677 device_printf(sc->dev, 1678 "Card is password protected, skipping\n"); 1679 goto free_ivar; 1680 } 1681 1682 /* Get card SCR. Card must be selected to fetch it. */ 1683 err = mmc_select_card(sc, ivar->rca); 1684 if (err != MMC_ERR_NONE) { 1685 device_printf(sc->dev, 1686 "Error selecting card %d\n", err); 1687 goto free_ivar; 1688 } 1689 err = mmc_app_send_scr(sc, ivar->rca, ivar->raw_scr); 1690 if (err != MMC_ERR_NONE) { 1691 device_printf(sc->dev, 1692 "Error reading SCR %d\n", err); 1693 goto free_ivar; 1694 } 1695 mmc_app_decode_scr(ivar->raw_scr, &ivar->scr); 1696 /* Get card switch capabilities (command class 10). */ 1697 if ((ivar->scr.sda_vsn >= 1) && 1698 (ivar->csd.ccc & (1 << 10))) { 1699 err = mmc_sd_switch(sc, SD_SWITCH_MODE_CHECK, 1700 SD_SWITCH_GROUP1, SD_SWITCH_NOCHANGE, 1701 switch_res); 1702 if (err == MMC_ERR_NONE && 1703 switch_res[13] & (1 << SD_SWITCH_HS_MODE)) { 1704 setbit(&ivar->timings, bus_timing_hs); 1705 ivar->hs_tran_speed = SD_HS_MAX; 1706 } 1707 } 1708 1709 /* 1710 * We deselect then reselect the card here. Some cards 1711 * become unselected and timeout with the above two 1712 * commands, although the state tables / diagrams in the 1713 * standard suggest they go back to the transfer state. 1714 * Other cards don't become deselected, and if we 1715 * attempt to blindly re-select them, we get timeout 1716 * errors from some controllers. So we deselect then 1717 * reselect to handle all situations. The only thing we 1718 * use from the sd_status is the erase sector size, but 1719 * it is still nice to get that right. 1720 */ 1721 (void)mmc_select_card(sc, 0); 1722 (void)mmc_select_card(sc, ivar->rca); 1723 (void)mmc_app_sd_status(sc, ivar->rca, 1724 ivar->raw_sd_status); 1725 mmc_app_decode_sd_status(ivar->raw_sd_status, 1726 &ivar->sd_status); 1727 if (ivar->sd_status.au_size != 0) { 1728 ivar->erase_sector = 1729 16 << ivar->sd_status.au_size; 1730 } 1731 /* Find maximum supported bus width. */ 1732 if ((host_caps & MMC_CAP_4_BIT_DATA) && 1733 (ivar->scr.bus_widths & SD_SCR_BUS_WIDTH_4)) 1734 ivar->bus_width = bus_width_4; 1735 1736 goto child_common; 1737 } 1738 ivar->rca = rca++; 1739 err = mmc_set_relative_addr(sc, ivar->rca); 1740 if (err != MMC_ERR_NONE) { 1741 device_printf(sc->dev, "Error setting RCA %d\n", err); 1742 goto free_ivar; 1743 } 1744 /* Get card CSD. */ 1745 err = mmc_send_csd(sc, ivar->rca, ivar->raw_csd); 1746 if (err != MMC_ERR_NONE) { 1747 device_printf(sc->dev, "Error getting CSD %d\n", err); 1748 goto free_ivar; 1749 } 1750 if (bootverbose || mmc_debug) 1751 device_printf(sc->dev, 1752 "%sard detected (CSD %08x%08x%08x%08x)\n", 1753 newcard ? "New c" : "C", ivar->raw_csd[0], 1754 ivar->raw_csd[1], ivar->raw_csd[2], 1755 ivar->raw_csd[3]); 1756 1757 mmc_decode_csd_mmc(ivar->raw_csd, &ivar->csd); 1758 ivar->sec_count = ivar->csd.capacity / MMC_SECTOR_SIZE; 1759 ivar->tran_speed = ivar->csd.tran_speed; 1760 ivar->erase_sector = ivar->csd.erase_sector * 1761 ivar->csd.write_bl_len / MMC_SECTOR_SIZE; 1762 1763 err = mmc_send_status(sc->dev, sc->dev, ivar->rca, &status); 1764 if (err != MMC_ERR_NONE) { 1765 device_printf(sc->dev, 1766 "Error reading card status %d\n", err); 1767 goto free_ivar; 1768 } 1769 if ((status & R1_CARD_IS_LOCKED) != 0) { 1770 device_printf(sc->dev, 1771 "Card is password protected, skipping\n"); 1772 goto free_ivar; 1773 } 1774 1775 err = mmc_select_card(sc, ivar->rca); 1776 if (err != MMC_ERR_NONE) { 1777 device_printf(sc->dev, "Error selecting card %d\n", 1778 err); 1779 goto free_ivar; 1780 } 1781 1782 rev = -1; 1783 /* Only MMC >= 4.x devices support EXT_CSD. */ 1784 if (ivar->csd.spec_vers >= 4) { 1785 err = mmc_send_ext_csd(sc->dev, sc->dev, 1786 ivar->raw_ext_csd); 1787 if (err != MMC_ERR_NONE) { 1788 device_printf(sc->dev, 1789 "Error reading EXT_CSD %d\n", err); 1790 goto free_ivar; 1791 } 1792 ext_csd = ivar->raw_ext_csd; 1793 rev = ext_csd[EXT_CSD_REV]; 1794 /* Handle extended capacity from EXT_CSD */ 1795 sec_count = le32dec(&ext_csd[EXT_CSD_SEC_CNT]); 1796 if (sec_count != 0) { 1797 ivar->sec_count = sec_count; 1798 ivar->high_cap = 1; 1799 } 1800 /* Find maximum supported bus width. */ 1801 ivar->bus_width = mmc_test_bus_width(sc); 1802 /* Get device speeds beyond normal mode. */ 1803 card_type = ext_csd[EXT_CSD_CARD_TYPE]; 1804 if ((card_type & EXT_CSD_CARD_TYPE_HS_52) != 0) { 1805 setbit(&ivar->timings, bus_timing_hs); 1806 ivar->hs_tran_speed = MMC_TYPE_HS_52_MAX; 1807 } else if ((card_type & EXT_CSD_CARD_TYPE_HS_26) != 0) { 1808 setbit(&ivar->timings, bus_timing_hs); 1809 ivar->hs_tran_speed = MMC_TYPE_HS_26_MAX; 1810 } 1811 if ((card_type & EXT_CSD_CARD_TYPE_DDR_52_1_2V) != 0 && 1812 (host_caps & MMC_CAP_SIGNALING_120) != 0) { 1813 setbit(&ivar->timings, bus_timing_mmc_ddr52); 1814 setbit(&ivar->vccq_120, bus_timing_mmc_ddr52); 1815 } 1816 if ((card_type & EXT_CSD_CARD_TYPE_DDR_52_1_8V) != 0 && 1817 (host_caps & MMC_CAP_SIGNALING_180) != 0) { 1818 setbit(&ivar->timings, bus_timing_mmc_ddr52); 1819 setbit(&ivar->vccq_180, bus_timing_mmc_ddr52); 1820 } 1821 if ((card_type & EXT_CSD_CARD_TYPE_HS200_1_2V) != 0 && 1822 (host_caps & MMC_CAP_SIGNALING_120) != 0) { 1823 setbit(&ivar->timings, bus_timing_mmc_hs200); 1824 setbit(&ivar->vccq_120, bus_timing_mmc_hs200); 1825 } 1826 if ((card_type & EXT_CSD_CARD_TYPE_HS200_1_8V) != 0 && 1827 (host_caps & MMC_CAP_SIGNALING_180) != 0) { 1828 setbit(&ivar->timings, bus_timing_mmc_hs200); 1829 setbit(&ivar->vccq_180, bus_timing_mmc_hs200); 1830 } 1831 if ((card_type & EXT_CSD_CARD_TYPE_HS400_1_2V) != 0 && 1832 (host_caps & MMC_CAP_SIGNALING_120) != 0 && 1833 ivar->bus_width == bus_width_8) { 1834 setbit(&ivar->timings, bus_timing_mmc_hs400); 1835 setbit(&ivar->vccq_120, bus_timing_mmc_hs400); 1836 } 1837 if ((card_type & EXT_CSD_CARD_TYPE_HS400_1_8V) != 0 && 1838 (host_caps & MMC_CAP_SIGNALING_180) != 0 && 1839 ivar->bus_width == bus_width_8) { 1840 setbit(&ivar->timings, bus_timing_mmc_hs400); 1841 setbit(&ivar->vccq_180, bus_timing_mmc_hs400); 1842 } 1843 if ((card_type & EXT_CSD_CARD_TYPE_HS400_1_2V) != 0 && 1844 (ext_csd[EXT_CSD_STROBE_SUPPORT] & 1845 EXT_CSD_STROBE_SUPPORT_EN) != 0 && 1846 (host_caps & MMC_CAP_SIGNALING_120) != 0 && 1847 ivar->bus_width == bus_width_8) { 1848 setbit(&ivar->timings, bus_timing_mmc_hs400es); 1849 setbit(&ivar->vccq_120, bus_timing_mmc_hs400es); 1850 } 1851 if ((card_type & EXT_CSD_CARD_TYPE_HS400_1_8V) != 0 && 1852 (ext_csd[EXT_CSD_STROBE_SUPPORT] & 1853 EXT_CSD_STROBE_SUPPORT_EN) != 0 && 1854 (host_caps & MMC_CAP_SIGNALING_180) != 0 && 1855 ivar->bus_width == bus_width_8) { 1856 setbit(&ivar->timings, bus_timing_mmc_hs400es); 1857 setbit(&ivar->vccq_180, bus_timing_mmc_hs400es); 1858 } 1859 /* 1860 * Determine generic switch timeout (provided in 1861 * units of 10 ms), defaulting to 500 ms. 1862 */ 1863 ivar->cmd6_time = 500 * 1000; 1864 if (rev >= 6) 1865 ivar->cmd6_time = 10 * 1866 ext_csd[EXT_CSD_GEN_CMD6_TIME]; 1867 /* Handle HC erase sector size. */ 1868 if (ext_csd[EXT_CSD_ERASE_GRP_SIZE] != 0) { 1869 ivar->erase_sector = 1024 * 1870 ext_csd[EXT_CSD_ERASE_GRP_SIZE]; 1871 err = mmc_switch(sc->dev, sc->dev, ivar->rca, 1872 EXT_CSD_CMD_SET_NORMAL, 1873 EXT_CSD_ERASE_GRP_DEF, 1874 EXT_CSD_ERASE_GRP_DEF_EN, 1875 ivar->cmd6_time, true); 1876 if (err != MMC_ERR_NONE) { 1877 device_printf(sc->dev, 1878 "Error setting erase group %d\n", 1879 err); 1880 goto free_ivar; 1881 } 1882 } 1883 } 1884 1885 mmc_decode_cid_mmc(ivar->raw_cid, &ivar->cid, rev >= 5); 1886 1887child_common: 1888 for (quirk = &mmc_quirks[0]; quirk->mid != 0x0; quirk++) { 1889 if ((quirk->mid == MMC_QUIRK_MID_ANY || 1890 quirk->mid == ivar->cid.mid) && 1891 (quirk->oid == MMC_QUIRK_OID_ANY || 1892 quirk->oid == ivar->cid.oid) && 1893 strncmp(quirk->pnm, ivar->cid.pnm, 1894 sizeof(ivar->cid.pnm)) == 0) { 1895 ivar->quirks = quirk->quirks; 1896 break; 1897 } 1898 } 1899 1900 /* 1901 * Some cards that report maximum I/O block sizes greater 1902 * than 512 require the block length to be set to 512, even 1903 * though that is supposed to be the default. Example: 1904 * 1905 * Transcend 2GB SDSC card, CID: 1906 * mid=0x1b oid=0x534d pnm="00000" prv=1.0 mdt=00.2000 1907 */ 1908 if (ivar->csd.read_bl_len != MMC_SECTOR_SIZE || 1909 ivar->csd.write_bl_len != MMC_SECTOR_SIZE) 1910 mmc_set_blocklen(sc, MMC_SECTOR_SIZE); 1911 1912 mmc_format_card_id_string(ivar); 1913 1914 if (bootverbose || mmc_debug) 1915 mmc_log_card(sc->dev, ivar, newcard); 1916 if (newcard) { 1917 /* Add device. */ 1918 child = device_add_child(sc->dev, NULL, -1); 1919 if (child != NULL) { 1920 device_set_ivars(child, ivar); 1921 sc->child_list = realloc(sc->child_list, 1922 sizeof(device_t) * (sc->child_count + 1), 1923 M_DEVBUF, M_WAITOK); 1924 sc->child_list[sc->child_count++] = child; 1925 } else 1926 device_printf(sc->dev, "Error adding child\n"); 1927 } 1928 1929free_ivar: 1930 if (newcard && child == NULL) 1931 free(ivar, M_DEVBUF); 1932 (void)mmc_select_card(sc, 0); 1933 /* 1934 * Not returning here when one MMC device could no be added 1935 * potentially would mean looping forever when that device 1936 * is broken (in which case it also may impact the remainder 1937 * of the bus anyway, though). 1938 */ 1939 if ((newcard && child == NULL) || 1940 mmcbr_get_mode(sc->dev) == mode_sd) 1941 return; 1942 } 1943} 1944 1945static void 1946mmc_update_child_list(struct mmc_softc *sc) 1947{ 1948 device_t child; 1949 int i, j; 1950 1951 if (sc->child_count == 0) { 1952 free(sc->child_list, M_DEVBUF); 1953 return; 1954 } 1955 for (i = j = 0; i < sc->child_count; i++) { 1956 for (;;) { 1957 child = sc->child_list[j++]; 1958 if (child != NULL) 1959 break; 1960 } 1961 if (i != j) 1962 sc->child_list[i] = child; 1963 } 1964 sc->child_list = realloc(sc->child_list, sizeof(device_t) * 1965 sc->child_count, M_DEVBUF, M_WAITOK); 1966} 1967 1968static void 1969mmc_rescan_cards(struct mmc_softc *sc) 1970{ 1971 struct mmc_ivars *ivar; 1972 int err, i, j; 1973 1974 for (i = j = 0; i < sc->child_count; i++) { 1975 ivar = device_get_ivars(sc->child_list[i]); 1976 if (mmc_select_card(sc, ivar->rca) != MMC_ERR_NONE) { 1977 if (bootverbose || mmc_debug) 1978 device_printf(sc->dev, 1979 "Card at relative address %d lost\n", 1980 ivar->rca); 1981 err = device_delete_child(sc->dev, sc->child_list[i]); 1982 if (err != 0) { 1983 j++; 1984 continue; 1985 } 1986 free(ivar, M_DEVBUF); 1987 } else 1988 j++; 1989 } 1990 if (sc->child_count == j) 1991 goto out; 1992 sc->child_count = j; 1993 mmc_update_child_list(sc); 1994out: 1995 (void)mmc_select_card(sc, 0); 1996} 1997 1998static int 1999mmc_delete_cards(struct mmc_softc *sc, bool final) 2000{ 2001 struct mmc_ivars *ivar; 2002 int err, i, j; 2003 2004 err = 0; 2005 for (i = j = 0; i < sc->child_count; i++) { 2006 ivar = device_get_ivars(sc->child_list[i]); 2007 if (bootverbose || mmc_debug) 2008 device_printf(sc->dev, 2009 "Card at relative address %d deleted\n", 2010 ivar->rca); 2011 err = device_delete_child(sc->dev, sc->child_list[i]); 2012 if (err != 0) { 2013 j++; 2014 if (final == false) 2015 continue; 2016 else 2017 break; 2018 } 2019 free(ivar, M_DEVBUF); 2020 } 2021 sc->child_count = j; 2022 mmc_update_child_list(sc); 2023 return (err); 2024} 2025 2026static void 2027mmc_go_discovery(struct mmc_softc *sc) 2028{ 2029 uint32_t ocr; 2030 device_t dev; 2031 int err; 2032 2033 dev = sc->dev; 2034 if (mmcbr_get_power_mode(dev) != power_on) { 2035 /* 2036 * First, try SD modes 2037 */ 2038 sc->squelched++; /* Errors are expected, squelch reporting. */ 2039 mmcbr_set_mode(dev, mode_sd); 2040 mmc_power_up(sc); 2041 mmcbr_set_bus_mode(dev, pushpull); 2042 if (bootverbose || mmc_debug) 2043 device_printf(sc->dev, "Probing bus\n"); 2044 mmc_idle_cards(sc); 2045 err = mmc_send_if_cond(sc, 1); 2046 if ((bootverbose || mmc_debug) && err == 0) 2047 device_printf(sc->dev, 2048 "SD 2.0 interface conditions: OK\n"); 2049 if (mmc_send_app_op_cond(sc, 0, &ocr) != MMC_ERR_NONE) { 2050 if (bootverbose || mmc_debug) 2051 device_printf(sc->dev, "SD probe: failed\n"); 2052 /* 2053 * Failed, try MMC 2054 */ 2055 mmcbr_set_mode(dev, mode_mmc); 2056 if (mmc_send_op_cond(sc, 0, &ocr) != MMC_ERR_NONE) { 2057 if (bootverbose || mmc_debug) 2058 device_printf(sc->dev, 2059 "MMC probe: failed\n"); 2060 ocr = 0; /* Failed both, powerdown. */ 2061 } else if (bootverbose || mmc_debug) 2062 device_printf(sc->dev, 2063 "MMC probe: OK (OCR: 0x%08x)\n", ocr); 2064 } else if (bootverbose || mmc_debug) 2065 device_printf(sc->dev, "SD probe: OK (OCR: 0x%08x)\n", 2066 ocr); 2067 sc->squelched--; 2068 2069 mmcbr_set_ocr(dev, mmc_select_vdd(sc, ocr)); 2070 if (mmcbr_get_ocr(dev) != 0) 2071 mmc_idle_cards(sc); 2072 } else { 2073 mmcbr_set_bus_mode(dev, opendrain); 2074 mmcbr_set_clock(dev, SD_MMC_CARD_ID_FREQUENCY); 2075 mmcbr_update_ios(dev); 2076 /* XXX recompute vdd based on new cards? */ 2077 } 2078 /* 2079 * Make sure that we have a mutually agreeable voltage to at least 2080 * one card on the bus. 2081 */ 2082 if (bootverbose || mmc_debug) 2083 device_printf(sc->dev, "Current OCR: 0x%08x\n", 2084 mmcbr_get_ocr(dev)); 2085 if (mmcbr_get_ocr(dev) == 0) { 2086 device_printf(sc->dev, "No compatible cards found on bus\n"); 2087 (void)mmc_delete_cards(sc, false); 2088 mmc_power_down(sc); 2089 return; 2090 } 2091 /* 2092 * Reselect the cards after we've idled them above. 2093 */ 2094 if (mmcbr_get_mode(dev) == mode_sd) { 2095 err = mmc_send_if_cond(sc, 1); 2096 mmc_send_app_op_cond(sc, 2097 (err ? 0 : MMC_OCR_CCS) | mmcbr_get_ocr(dev), NULL); 2098 } else 2099 mmc_send_op_cond(sc, MMC_OCR_CCS | mmcbr_get_ocr(dev), NULL); 2100 mmc_discover_cards(sc); 2101 mmc_rescan_cards(sc); 2102 2103 mmcbr_set_bus_mode(dev, pushpull); 2104 mmcbr_update_ios(dev); 2105 mmc_calculate_clock(sc); 2106} 2107 2108static int 2109mmc_calculate_clock(struct mmc_softc *sc) 2110{ 2111 device_t dev; 2112 struct mmc_ivars *ivar; 2113 int i; 2114 uint32_t dtr, max_dtr; 2115 uint16_t rca; 2116 enum mmc_bus_timing max_timing, timing; 2117 bool changed, hs400; 2118 2119 dev = sc->dev; 2120 max_dtr = mmcbr_get_f_max(dev); 2121 max_timing = bus_timing_max; 2122 do { 2123 changed = false; 2124 for (i = 0; i < sc->child_count; i++) { 2125 ivar = device_get_ivars(sc->child_list[i]); 2126 if (isclr(&ivar->timings, max_timing) || 2127 !mmc_host_timing(dev, max_timing)) { 2128 for (timing = max_timing - 1; timing >= 2129 bus_timing_normal; timing--) { 2130 if (isset(&ivar->timings, timing) && 2131 mmc_host_timing(dev, timing)) { 2132 max_timing = timing; 2133 break; 2134 } 2135 } 2136 changed = true; 2137 } 2138 dtr = mmc_timing_to_dtr(ivar, max_timing); 2139 if (dtr < max_dtr) { 2140 max_dtr = dtr; 2141 changed = true; 2142 } 2143 } 2144 } while (changed == true); 2145 2146 if (bootverbose || mmc_debug) { 2147 device_printf(dev, 2148 "setting transfer rate to %d.%03dMHz (%s timing)\n", 2149 max_dtr / 1000000, (max_dtr / 1000) % 1000, 2150 mmc_timing_to_string(max_timing)); 2151 } 2152 2153 /* 2154 * HS400 must be tuned in HS200 mode, so in case of HS400 we begin 2155 * with HS200 following the sequence as described in "6.6.2.2 HS200 2156 * timing mode selection" of the eMMC specification v5.1, too, and 2157 * switch to max_timing later. HS400ES requires no tuning and, thus, 2158 * can be switch to directly, but requires the same detour via high 2159 * speed mode as does HS400 (see mmc_switch_to_hs400()). 2160 */ 2161 hs400 = max_timing == bus_timing_mmc_hs400; 2162 timing = hs400 == true ? bus_timing_mmc_hs200 : max_timing; 2163 for (i = 0; i < sc->child_count; i++) { 2164 ivar = device_get_ivars(sc->child_list[i]); 2165 if ((ivar->timings & ~(1 << bus_timing_normal)) == 0) 2166 goto clock; 2167 2168 rca = ivar->rca; 2169 if (mmc_select_card(sc, rca) != MMC_ERR_NONE) { 2170 device_printf(dev, "Card at relative address %d " 2171 "failed to select\n", rca); 2172 continue; 2173 } 2174 2175 if (timing == bus_timing_mmc_hs200 || /* includes HS400 */ 2176 timing == bus_timing_mmc_hs400es) { 2177 if (mmc_set_vccq(sc, ivar, timing) != MMC_ERR_NONE) { 2178 device_printf(dev, "Failed to set VCCQ for " 2179 "card at relative address %d\n", rca); 2180 continue; 2181 } 2182 } 2183 2184 if (timing == bus_timing_mmc_hs200) { /* includes HS400 */ 2185 /* Set bus width (required for initial tuning). */ 2186 if (mmc_set_card_bus_width(sc, ivar, timing) != 2187 MMC_ERR_NONE) { 2188 device_printf(dev, "Card at relative address " 2189 "%d failed to set bus width\n", rca); 2190 continue; 2191 } 2192 mmcbr_set_bus_width(dev, ivar->bus_width); 2193 mmcbr_update_ios(dev); 2194 } else if (timing == bus_timing_mmc_hs400es) { 2195 if (mmc_switch_to_hs400(sc, ivar, max_dtr, timing) != 2196 MMC_ERR_NONE) { 2197 device_printf(dev, "Card at relative address " 2198 "%d failed to set %s timing\n", rca, 2199 mmc_timing_to_string(timing)); 2200 continue; 2201 } 2202 goto power_class; 2203 } 2204 2205 if (mmc_set_timing(sc, ivar, timing) != MMC_ERR_NONE) { 2206 device_printf(dev, "Card at relative address %d " 2207 "failed to set %s timing\n", rca, 2208 mmc_timing_to_string(timing)); 2209 continue; 2210 } 2211 2212 if (timing == bus_timing_mmc_ddr52) { 2213 /* 2214 * Set EXT_CSD_BUS_WIDTH_n_DDR in EXT_CSD_BUS_WIDTH 2215 * (must be done after switching to EXT_CSD_HS_TIMING). 2216 */ 2217 if (mmc_set_card_bus_width(sc, ivar, timing) != 2218 MMC_ERR_NONE) { 2219 device_printf(dev, "Card at relative address " 2220 "%d failed to set bus width\n", rca); 2221 continue; 2222 } 2223 mmcbr_set_bus_width(dev, ivar->bus_width); 2224 mmcbr_update_ios(dev); 2225 if (mmc_set_vccq(sc, ivar, timing) != MMC_ERR_NONE) { 2226 device_printf(dev, "Failed to set VCCQ for " 2227 "card at relative address %d\n", rca); 2228 continue; 2229 } 2230 } 2231 2232clock: 2233 /* Set clock (must be done before initial tuning). */ 2234 mmcbr_set_clock(dev, max_dtr); 2235 mmcbr_update_ios(dev); 2236 2237 /* 2238 * Don't call into the bridge driver for timings definitely 2239 * not requiring tuning. Note that it's up to the upper 2240 * layer to actually execute tuning otherwise. 2241 */ 2242 if (timing <= bus_timing_uhs_sdr25 || 2243 timing == bus_timing_mmc_ddr52) 2244 goto power_class; 2245 2246 if (mmcbr_tune(dev, hs400) != 0) { 2247 device_printf(dev, "Card at relative address %d " 2248 "failed to execute initial tuning\n", rca); 2249 continue; 2250 } 2251 2252 if (hs400 == true && mmc_switch_to_hs400(sc, ivar, max_dtr, 2253 max_timing) != MMC_ERR_NONE) { 2254 device_printf(dev, "Card at relative address %d " 2255 "failed to set %s timing\n", rca, 2256 mmc_timing_to_string(max_timing)); 2257 continue; 2258 } 2259 2260power_class: 2261 if (mmc_set_power_class(sc, ivar) != MMC_ERR_NONE) { 2262 device_printf(dev, "Card at relative address %d " 2263 "failed to set power class\n", rca); 2264 } 2265 } 2266 (void)mmc_select_card(sc, 0); 2267 return (max_dtr); 2268} 2269 2270/* 2271 * Switch from HS200 to HS400 (either initially or for re-tuning) or directly 2272 * to HS400ES. This follows the sequences described in "6.6.2.3 HS400 timing 2273 * mode selection" of the eMMC specification v5.1. 2274 */ 2275static int 2276mmc_switch_to_hs400(struct mmc_softc *sc, struct mmc_ivars *ivar, 2277 uint32_t clock, enum mmc_bus_timing max_timing) 2278{ 2279 device_t dev; 2280 int err; 2281 2282 dev = sc->dev; 2283 2284 /* 2285 * Both clock and timing must be set as appropriate for high speed 2286 * before eventually switching to HS400/HS400ES; mmc_set_timing() 2287 * will issue mmcbr_update_ios(). 2288 */ 2289 mmcbr_set_clock(dev, ivar->hs_tran_speed); 2290 err = mmc_set_timing(sc, ivar, bus_timing_hs); 2291 if (err != MMC_ERR_NONE) 2292 return (err); 2293 2294 /* 2295 * Set EXT_CSD_BUS_WIDTH_8_DDR in EXT_CSD_BUS_WIDTH (and additionally 2296 * EXT_CSD_BUS_WIDTH_ES for HS400ES). 2297 */ 2298 err = mmc_set_card_bus_width(sc, ivar, max_timing); 2299 if (err != MMC_ERR_NONE) 2300 return (err); 2301 mmcbr_set_bus_width(dev, ivar->bus_width); 2302 mmcbr_update_ios(dev); 2303 2304 /* Finally, switch to HS400/HS400ES mode. */ 2305 err = mmc_set_timing(sc, ivar, max_timing); 2306 if (err != MMC_ERR_NONE) 2307 return (err); 2308 mmcbr_set_clock(dev, clock); 2309 mmcbr_update_ios(dev); 2310 return (MMC_ERR_NONE); 2311} 2312 2313/* 2314 * Switch from HS400 to HS200 (for re-tuning). 2315 */ 2316static int 2317mmc_switch_to_hs200(struct mmc_softc *sc, struct mmc_ivars *ivar, 2318 uint32_t clock) 2319{ 2320 device_t dev; 2321 int err; 2322 2323 dev = sc->dev; 2324 2325 /* 2326 * Both clock and timing must initially be set as appropriate for 2327 * DDR52 before eventually switching to HS200; mmc_set_timing() 2328 * will issue mmcbr_update_ios(). 2329 */ 2330 mmcbr_set_clock(dev, ivar->hs_tran_speed); 2331 err = mmc_set_timing(sc, ivar, bus_timing_mmc_ddr52); 2332 if (err != MMC_ERR_NONE) 2333 return (err); 2334 2335 /* 2336 * Next, switch to high speed. Thus, clear EXT_CSD_BUS_WIDTH_n_DDR 2337 * in EXT_CSD_BUS_WIDTH and update bus width and timing in ios. 2338 */ 2339 err = mmc_set_card_bus_width(sc, ivar, bus_timing_hs); 2340 if (err != MMC_ERR_NONE) 2341 return (err); 2342 mmcbr_set_bus_width(dev, ivar->bus_width); 2343 mmcbr_set_timing(sc->dev, bus_timing_hs); 2344 mmcbr_update_ios(dev); 2345 2346 /* Finally, switch to HS200 mode. */ 2347 err = mmc_set_timing(sc, ivar, bus_timing_mmc_hs200); 2348 if (err != MMC_ERR_NONE) 2349 return (err); 2350 mmcbr_set_clock(dev, clock); 2351 mmcbr_update_ios(dev); 2352 return (MMC_ERR_NONE); 2353} 2354 2355static int 2356mmc_retune(device_t busdev, device_t dev, bool reset) 2357{ 2358 struct mmc_softc *sc; 2359 struct mmc_ivars *ivar; 2360 int err; 2361 uint32_t clock; 2362 enum mmc_bus_timing timing; 2363 2364 if (device_get_parent(dev) != busdev) 2365 return (MMC_ERR_INVALID); 2366 2367 sc = device_get_softc(busdev); 2368 if (sc->retune_needed != 1 && sc->retune_paused != 0) 2369 return (MMC_ERR_INVALID); 2370 2371 timing = mmcbr_get_timing(busdev); 2372 if (timing == bus_timing_mmc_hs400) { 2373 /* 2374 * Controllers use the data strobe line to latch data from 2375 * the devices in HS400 mode so periodic re-tuning isn't 2376 * expected to be required, i. e. only if a CRC or tuning 2377 * error is signaled to the bridge. In these latter cases 2378 * we are asked to reset the tuning circuit and need to do 2379 * the switch timing dance. 2380 */ 2381 if (reset == false) 2382 return (0); 2383 ivar = device_get_ivars(dev); 2384 clock = mmcbr_get_clock(busdev); 2385 if (mmc_switch_to_hs200(sc, ivar, clock) != MMC_ERR_NONE) 2386 return (MMC_ERR_BADCRC); 2387 } 2388 err = mmcbr_retune(busdev, reset); 2389 if (err != 0 && timing == bus_timing_mmc_hs400) 2390 return (MMC_ERR_BADCRC); 2391 switch (err) { 2392 case 0: 2393 break; 2394 case EIO: 2395 return (MMC_ERR_FAILED); 2396 default: 2397 return (MMC_ERR_INVALID); 2398 } 2399 if (timing == bus_timing_mmc_hs400) { 2400 if (mmc_switch_to_hs400(sc, ivar, clock, timing) != 2401 MMC_ERR_NONE) 2402 return (MMC_ERR_BADCRC); 2403 } 2404 return (MMC_ERR_NONE); 2405} 2406 2407static void 2408mmc_retune_pause(device_t busdev, device_t dev, bool retune) 2409{ 2410 struct mmc_softc *sc; 2411 2412 sc = device_get_softc(busdev); 2413 KASSERT(device_get_parent(dev) == busdev, 2414 ("%s: %s is not a child of %s", __func__, device_get_nameunit(dev), 2415 device_get_nameunit(busdev))); 2416 KASSERT(sc->owner != NULL, 2417 ("%s: Request from %s without bus being acquired.", __func__, 2418 device_get_nameunit(dev))); 2419 2420 if (retune == true && sc->retune_paused == 0) 2421 sc->retune_needed = 1; 2422 sc->retune_paused++; 2423} 2424 2425static void 2426mmc_retune_unpause(device_t busdev, device_t dev) 2427{ 2428 struct mmc_softc *sc; 2429 2430 sc = device_get_softc(busdev); 2431 KASSERT(device_get_parent(dev) == busdev, 2432 ("%s: %s is not a child of %s", __func__, device_get_nameunit(dev), 2433 device_get_nameunit(busdev))); 2434 KASSERT(sc->owner != NULL, 2435 ("%s: Request from %s without bus being acquired.", __func__, 2436 device_get_nameunit(dev))); 2437 KASSERT(sc->retune_paused != 0, 2438 ("%s: Re-tune pause count already at 0", __func__)); 2439 2440 sc->retune_paused--; 2441} 2442 2443static void 2444mmc_scan(struct mmc_softc *sc) 2445{ 2446 device_t dev = sc->dev; 2447 int err; 2448 2449 err = mmc_acquire_bus(dev, dev); 2450 if (err != 0) { 2451 device_printf(dev, "Failed to acquire bus for scanning\n"); 2452 return; 2453 } 2454 mmc_go_discovery(sc); 2455 err = mmc_release_bus(dev, dev); 2456 if (err != 0) { 2457 device_printf(dev, "Failed to release bus after scanning\n"); 2458 return; 2459 } 2460 (void)bus_generic_attach(dev); 2461} 2462 2463static int 2464mmc_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 2465{ 2466 struct mmc_ivars *ivar = device_get_ivars(child); 2467 2468 switch (which) { 2469 default: 2470 return (EINVAL); 2471 case MMC_IVAR_SPEC_VERS: 2472 *result = ivar->csd.spec_vers; 2473 break; 2474 case MMC_IVAR_DSR_IMP: 2475 *result = ivar->csd.dsr_imp; 2476 break; 2477 case MMC_IVAR_MEDIA_SIZE: 2478 *result = ivar->sec_count; 2479 break; 2480 case MMC_IVAR_RCA: 2481 *result = ivar->rca; 2482 break; 2483 case MMC_IVAR_SECTOR_SIZE: 2484 *result = MMC_SECTOR_SIZE; 2485 break; 2486 case MMC_IVAR_TRAN_SPEED: 2487 *result = mmcbr_get_clock(bus); 2488 break; 2489 case MMC_IVAR_READ_ONLY: 2490 *result = ivar->read_only; 2491 break; 2492 case MMC_IVAR_HIGH_CAP: 2493 *result = ivar->high_cap; 2494 break; 2495 case MMC_IVAR_CARD_TYPE: 2496 *result = ivar->mode; 2497 break; 2498 case MMC_IVAR_BUS_WIDTH: 2499 *result = ivar->bus_width; 2500 break; 2501 case MMC_IVAR_ERASE_SECTOR: 2502 *result = ivar->erase_sector; 2503 break; 2504 case MMC_IVAR_MAX_DATA: 2505 *result = mmcbr_get_max_data(bus); 2506 break; 2507 case MMC_IVAR_CMD6_TIMEOUT: 2508 *result = ivar->cmd6_time; 2509 break; 2510 case MMC_IVAR_QUIRKS: 2511 *result = ivar->quirks; 2512 break; 2513 case MMC_IVAR_CARD_ID_STRING: 2514 *(char **)result = ivar->card_id_string; 2515 break; 2516 case MMC_IVAR_CARD_SN_STRING: 2517 *(char **)result = ivar->card_sn_string; 2518 break; 2519 } 2520 return (0); 2521} 2522 2523static int 2524mmc_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 2525{ 2526 2527 /* 2528 * None are writable ATM 2529 */ 2530 return (EINVAL); 2531} 2532 2533static void 2534mmc_delayed_attach(void *xsc) 2535{ 2536 struct mmc_softc *sc = xsc; 2537 2538 mmc_scan(sc); 2539 config_intrhook_disestablish(&sc->config_intrhook); 2540} 2541 2542static int 2543mmc_child_location(device_t dev, device_t child, struct sbuf *sb) 2544{ 2545 2546 sbuf_printf(sb, "rca=0x%04x", mmc_get_rca(child)); 2547 return (0); 2548} 2549 2550static device_method_t mmc_methods[] = { 2551 /* device_if */ 2552 DEVMETHOD(device_probe, mmc_probe), 2553 DEVMETHOD(device_attach, mmc_attach), 2554 DEVMETHOD(device_detach, mmc_detach), 2555 DEVMETHOD(device_suspend, mmc_suspend), 2556 DEVMETHOD(device_resume, mmc_resume), 2557 2558 /* Bus interface */ 2559 DEVMETHOD(bus_read_ivar, mmc_read_ivar), 2560 DEVMETHOD(bus_write_ivar, mmc_write_ivar), 2561 DEVMETHOD(bus_child_location, mmc_child_location), 2562 2563 /* MMC Bus interface */ 2564 DEVMETHOD(mmcbus_retune_pause, mmc_retune_pause), 2565 DEVMETHOD(mmcbus_retune_unpause, mmc_retune_unpause), 2566 DEVMETHOD(mmcbus_wait_for_request, mmc_wait_for_request), 2567 DEVMETHOD(mmcbus_acquire_bus, mmc_acquire_bus), 2568 DEVMETHOD(mmcbus_release_bus, mmc_release_bus), 2569 2570 DEVMETHOD_END 2571}; 2572 2573driver_t mmc_driver = { 2574 "mmc", 2575 mmc_methods, 2576 sizeof(struct mmc_softc), 2577}; 2578 2579MODULE_VERSION(mmc, MMC_VERSION); 2580