1/*- 2 * Copyright (c) 2013-2020, Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26#ifndef MLX5_IFC_H 27#define MLX5_IFC_H 28 29#include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h> 30 31enum { 32 MLX5_EVENT_TYPE_NOTIFY_ANY = 0x0, 33 MLX5_EVENT_TYPE_COMP = 0x0, 34 MLX5_EVENT_TYPE_PATH_MIG = 0x1, 35 MLX5_EVENT_TYPE_COMM_EST = 0x2, 36 MLX5_EVENT_TYPE_SQ_DRAINED = 0x3, 37 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 38 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 39 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, 40 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d, 41 MLX5_EVENT_TYPE_CQ_ERROR = 0x4, 42 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x5, 43 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x7, 44 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 45 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 46 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 47 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 48 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x8, 49 MLX5_EVENT_TYPE_PORT_CHANGE = 0x9, 50 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 51 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT = 0x16, 52 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17, 53 MLX5_EVENT_TYPE_XRQ_ERROR = 0x18, 54 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 55 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT = 0x1e, 56 MLX5_EVENT_TYPE_CODING_PPS_EVENT = 0x25, 57 MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT = 0x22, 58 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 59 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 60 MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 61 MLX5_EVENT_TYPE_CMD = 0xa, 62 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 63 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, 64 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20, 65 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21, 66 MLX5_EVENT_TYPE_CODING_GENERAL_OBJ_EVENT = 0x27, 67}; 68 69enum { 70 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 71 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 72 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 73 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3, 74 MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN = 0x4 75}; 76 77enum { 78 MLX5_MODIFY_RQT_BITMASK_RQN_LIST = 0x1, 79}; 80 81enum { 82 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 83 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 84}; 85 86enum { 87 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 88 MLX5_OBJ_TYPE_MKEY = 0xff01, 89 MLX5_OBJ_TYPE_QP = 0xff02, 90 MLX5_OBJ_TYPE_PSV = 0xff03, 91 MLX5_OBJ_TYPE_RMP = 0xff04, 92 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 93 MLX5_OBJ_TYPE_RQ = 0xff06, 94 MLX5_OBJ_TYPE_SQ = 0xff07, 95 MLX5_OBJ_TYPE_TIR = 0xff08, 96 MLX5_OBJ_TYPE_TIS = 0xff09, 97 MLX5_OBJ_TYPE_DCT = 0xff0a, 98 MLX5_OBJ_TYPE_XRQ = 0xff0b, 99 MLX5_OBJ_TYPE_RQT = 0xff0e, 100 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 101 MLX5_OBJ_TYPE_CQ = 0xff10, 102}; 103 104enum { 105 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 106 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 107 MLX5_CMD_OP_INIT_HCA = 0x102, 108 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 109 MLX5_CMD_OP_ENABLE_HCA = 0x104, 110 MLX5_CMD_OP_DISABLE_HCA = 0x105, 111 MLX5_CMD_OP_QUERY_PAGES = 0x107, 112 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 113 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 114 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 115 MLX5_CMD_OP_SET_ISSI = 0x10b, 116 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 117 MLX5_CMD_OP_QUERY_OTHER_HCA_CAP = 0x10e, 118 MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP = 0x10f, 119 MLX5_CMD_OP_CREATE_MKEY = 0x200, 120 MLX5_CMD_OP_QUERY_MKEY = 0x201, 121 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 122 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 123 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 124 MLX5_CMD_OP_CREATE_EQ = 0x301, 125 MLX5_CMD_OP_DESTROY_EQ = 0x302, 126 MLX5_CMD_OP_QUERY_EQ = 0x303, 127 MLX5_CMD_OP_GEN_EQE = 0x304, 128 MLX5_CMD_OP_CREATE_CQ = 0x400, 129 MLX5_CMD_OP_DESTROY_CQ = 0x401, 130 MLX5_CMD_OP_QUERY_CQ = 0x402, 131 MLX5_CMD_OP_MODIFY_CQ = 0x403, 132 MLX5_CMD_OP_CREATE_QP = 0x500, 133 MLX5_CMD_OP_DESTROY_QP = 0x501, 134 MLX5_CMD_OP_RST2INIT_QP = 0x502, 135 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 136 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 137 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 138 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 139 MLX5_CMD_OP_2ERR_QP = 0x507, 140 MLX5_CMD_OP_2RST_QP = 0x50a, 141 MLX5_CMD_OP_QUERY_QP = 0x50b, 142 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 143 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 144 MLX5_CMD_OP_CREATE_PSV = 0x600, 145 MLX5_CMD_OP_DESTROY_PSV = 0x601, 146 MLX5_CMD_OP_CREATE_SRQ = 0x700, 147 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 148 MLX5_CMD_OP_QUERY_SRQ = 0x702, 149 MLX5_CMD_OP_ARM_RQ = 0x703, 150 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 151 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 152 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 153 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 154 MLX5_CMD_OP_CREATE_DCT = 0x710, 155 MLX5_CMD_OP_DESTROY_DCT = 0x711, 156 MLX5_CMD_OP_DRAIN_DCT = 0x712, 157 MLX5_CMD_OP_QUERY_DCT = 0x713, 158 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 159 MLX5_CMD_OP_SET_DC_CNAK_TRACE = 0x715, 160 MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716, 161 MLX5_CMD_OP_CREATE_XRQ = 0x717, 162 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 163 MLX5_CMD_OP_QUERY_XRQ = 0x719, 164 MLX5_CMD_OP_ARM_XRQ = 0x71a, 165 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 166 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 167 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 168 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 169 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 170 171 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 172 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 173 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 174 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 175 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 176 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 177 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 178 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 179 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 180 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 181 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 182 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 183 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 184 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 185 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 186 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 187 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 188 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, 189 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 190 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 191 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 192 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 193 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 194 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 195 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 196 MLX5_CMD_OP_ALLOC_PD = 0x800, 197 MLX5_CMD_OP_DEALLOC_PD = 0x801, 198 MLX5_CMD_OP_ALLOC_UAR = 0x802, 199 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 200 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 201 MLX5_CMD_OP_ACCESS_REG = 0x805, 202 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 203 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 204 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 205 MLX5_CMD_OP_MAD_IFC = 0x50d, 206 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 207 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 208 MLX5_CMD_OP_NOP = 0x80d, 209 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 210 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 211 MLX5_CMD_OP_SET_BURST_SIZE = 0x812, 212 MLX5_CMD_OP_QUERY_BURST_SIZE = 0x813, 213 MLX5_CMD_OP_ACTIVATE_TRACER = 0x814, 214 MLX5_CMD_OP_DEACTIVATE_TRACER = 0x815, 215 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 216 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 217 MLX5_CMD_OP_QUERY_DIAGNOSTIC_PARAMS = 0x819, 218 MLX5_CMD_OP_SET_DIAGNOSTICS = 0x820, 219 MLX5_CMD_OP_QUERY_DIAGNOSTICS = 0x821, 220 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 221 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 222 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 223 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 224 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 225 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 226 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 227 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 228 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 229 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 230 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 231 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 232 MLX5_CMD_OP_CREATE_LAG = 0x840, 233 MLX5_CMD_OP_MODIFY_LAG = 0x841, 234 MLX5_CMD_OP_QUERY_LAG = 0x842, 235 MLX5_CMD_OP_DESTROY_LAG = 0x843, 236 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 237 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 238 MLX5_CMD_OP_CREATE_TIR = 0x900, 239 MLX5_CMD_OP_MODIFY_TIR = 0x901, 240 MLX5_CMD_OP_DESTROY_TIR = 0x902, 241 MLX5_CMD_OP_QUERY_TIR = 0x903, 242 MLX5_CMD_OP_CREATE_SQ = 0x904, 243 MLX5_CMD_OP_MODIFY_SQ = 0x905, 244 MLX5_CMD_OP_DESTROY_SQ = 0x906, 245 MLX5_CMD_OP_QUERY_SQ = 0x907, 246 MLX5_CMD_OP_CREATE_RQ = 0x908, 247 MLX5_CMD_OP_MODIFY_RQ = 0x909, 248 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 249 MLX5_CMD_OP_QUERY_RQ = 0x90b, 250 MLX5_CMD_OP_CREATE_RMP = 0x90c, 251 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 252 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 253 MLX5_CMD_OP_QUERY_RMP = 0x90f, 254 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 255 MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS = 0x911, 256 MLX5_CMD_OP_CREATE_TIS = 0x912, 257 MLX5_CMD_OP_MODIFY_TIS = 0x913, 258 MLX5_CMD_OP_DESTROY_TIS = 0x914, 259 MLX5_CMD_OP_QUERY_TIS = 0x915, 260 MLX5_CMD_OP_CREATE_RQT = 0x916, 261 MLX5_CMD_OP_MODIFY_RQT = 0x917, 262 MLX5_CMD_OP_DESTROY_RQT = 0x918, 263 MLX5_CMD_OP_QUERY_RQT = 0x919, 264 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 265 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 266 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 267 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 268 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 269 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 270 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 271 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 272 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 273 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 274 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 275 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 276 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 277 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 278 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 279 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 280 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 281 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 282 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 283 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 284 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 285 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 286 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 287 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 288 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 289 MLX5_CMD_OP_CREATE_GENERAL_OBJ = 0xa00, 290 MLX5_CMD_OP_MODIFY_GENERAL_OBJ = 0xa01, 291 MLX5_CMD_OP_QUERY_GENERAL_OBJ = 0xa02, 292 MLX5_CMD_OP_DESTROY_GENERAL_OBJ = 0xa03, 293 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 294 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 295 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 296 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 297}; 298 299/* Valid range for general commands that don't work over an object */ 300enum { 301 MLX5_CMD_OP_GENERAL_START = 0xb00, 302 MLX5_CMD_OP_GENERAL_END = 0xd00, 303}; 304 305enum { 306 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 307 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 308}; 309 310enum { 311 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO = 0x8007, 312 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY = 0x8400, 313 MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER = 0x9001, 314 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC = 0x9003, 315 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC = 0x9004, 316 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL = 0x9005, 317 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL = 0x9006, 318 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT = 0x9007, 319 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008, 320 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS = 0x9009, 321 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT = 0x900a, 322 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD = 0xf004 323}; 324 325enum { 326 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 327}; 328 329enum { 330 MLX5_HCA_CAP_GENERAL_OBJ_TYPES_ENCRYPTION_KEY = 1 << 0xc, 331}; 332 333enum { 334 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 335 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 336}; 337 338enum { 339 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1, 340}; 341 342struct mlx5_ifc_flow_table_fields_supported_bits { 343 u8 outer_dmac[0x1]; 344 u8 outer_smac[0x1]; 345 u8 outer_ether_type[0x1]; 346 u8 outer_ip_version[0x1]; 347 u8 outer_first_prio[0x1]; 348 u8 outer_first_cfi[0x1]; 349 u8 outer_first_vid[0x1]; 350 u8 reserved_1[0x1]; 351 u8 outer_second_prio[0x1]; 352 u8 outer_second_cfi[0x1]; 353 u8 outer_second_vid[0x1]; 354 u8 outer_ipv6_flow_label[0x1]; 355 u8 outer_sip[0x1]; 356 u8 outer_dip[0x1]; 357 u8 outer_frag[0x1]; 358 u8 outer_ip_protocol[0x1]; 359 u8 outer_ip_ecn[0x1]; 360 u8 outer_ip_dscp[0x1]; 361 u8 outer_udp_sport[0x1]; 362 u8 outer_udp_dport[0x1]; 363 u8 outer_tcp_sport[0x1]; 364 u8 outer_tcp_dport[0x1]; 365 u8 outer_tcp_flags[0x1]; 366 u8 outer_gre_protocol[0x1]; 367 u8 outer_gre_key[0x1]; 368 u8 outer_vxlan_vni[0x1]; 369 u8 outer_geneve_vni[0x1]; 370 u8 outer_geneve_oam[0x1]; 371 u8 outer_geneve_protocol_type[0x1]; 372 u8 outer_geneve_opt_len[0x1]; 373 u8 reserved_2[0x1]; 374 u8 source_eswitch_port[0x1]; 375 376 u8 inner_dmac[0x1]; 377 u8 inner_smac[0x1]; 378 u8 inner_ether_type[0x1]; 379 u8 inner_ip_version[0x1]; 380 u8 inner_first_prio[0x1]; 381 u8 inner_first_cfi[0x1]; 382 u8 inner_first_vid[0x1]; 383 u8 reserved_4[0x1]; 384 u8 inner_second_prio[0x1]; 385 u8 inner_second_cfi[0x1]; 386 u8 inner_second_vid[0x1]; 387 u8 inner_ipv6_flow_label[0x1]; 388 u8 inner_sip[0x1]; 389 u8 inner_dip[0x1]; 390 u8 inner_frag[0x1]; 391 u8 inner_ip_protocol[0x1]; 392 u8 inner_ip_ecn[0x1]; 393 u8 inner_ip_dscp[0x1]; 394 u8 inner_udp_sport[0x1]; 395 u8 inner_udp_dport[0x1]; 396 u8 inner_tcp_sport[0x1]; 397 u8 inner_tcp_dport[0x1]; 398 u8 inner_tcp_flags[0x1]; 399 u8 reserved_5[0x9]; 400 401 u8 reserved_6[0x1a]; 402 u8 bth_dst_qp[0x1]; 403 u8 reserved_7[0x4]; 404 u8 source_sqn[0x1]; 405 406 u8 reserved_8[0x20]; 407}; 408 409struct mlx5_ifc_eth_discard_cntrs_grp_bits { 410 u8 ingress_general_high[0x20]; 411 412 u8 ingress_general_low[0x20]; 413 414 u8 ingress_policy_engine_high[0x20]; 415 416 u8 ingress_policy_engine_low[0x20]; 417 418 u8 ingress_vlan_membership_high[0x20]; 419 420 u8 ingress_vlan_membership_low[0x20]; 421 422 u8 ingress_tag_frame_type_high[0x20]; 423 424 u8 ingress_tag_frame_type_low[0x20]; 425 426 u8 egress_vlan_membership_high[0x20]; 427 428 u8 egress_vlan_membership_low[0x20]; 429 430 u8 loopback_filter_high[0x20]; 431 432 u8 loopback_filter_low[0x20]; 433 434 u8 egress_general_high[0x20]; 435 436 u8 egress_general_low[0x20]; 437 438 u8 reserved_at_1c0[0x40]; 439 440 u8 egress_hoq_high[0x20]; 441 442 u8 egress_hoq_low[0x20]; 443 444 u8 port_isolation_high[0x20]; 445 446 u8 port_isolation_low[0x20]; 447 448 u8 egress_policy_engine_high[0x20]; 449 450 u8 egress_policy_engine_low[0x20]; 451 452 u8 ingress_tx_link_down_high[0x20]; 453 454 u8 ingress_tx_link_down_low[0x20]; 455 456 u8 egress_stp_filter_high[0x20]; 457 458 u8 egress_stp_filter_low[0x20]; 459 460 u8 egress_hoq_stall_high[0x20]; 461 462 u8 egress_hoq_stall_low[0x20]; 463 464 u8 reserved_at_340[0x440]; 465}; 466struct mlx5_ifc_flow_table_prop_layout_bits { 467 u8 ft_support[0x1]; 468 u8 flow_tag[0x1]; 469 u8 flow_counter[0x1]; 470 u8 flow_modify_en[0x1]; 471 u8 modify_root[0x1]; 472 u8 identified_miss_table[0x1]; 473 u8 flow_table_modify[0x1]; 474 u8 encap[0x1]; 475 u8 decap[0x1]; 476 u8 reset_root_to_default[0x1]; 477 u8 reserved_at_a[0x16]; 478 479 u8 reserved_at_20[0x2]; 480 u8 log_max_ft_size[0x6]; 481 u8 log_max_modify_header_context[0x8]; 482 u8 max_modify_header_actions[0x8]; 483 u8 max_ft_level[0x8]; 484 485 u8 reserved_at_40[0x20]; 486 487 u8 reserved_at_60[0x18]; 488 u8 log_max_ft_num[0x8]; 489 490 u8 reserved_at_80[0x10]; 491 u8 log_max_flow_counter[0x8]; 492 u8 log_max_destination[0x8]; 493 494 u8 reserved_at_a0[0x18]; 495 u8 log_max_flow[0x8]; 496 497 u8 reserved_at_c0[0x40]; 498 499 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 500 501 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 502}; 503 504struct mlx5_ifc_odp_per_transport_service_cap_bits { 505 u8 send[0x1]; 506 u8 receive[0x1]; 507 u8 write[0x1]; 508 u8 read[0x1]; 509 u8 atomic[0x1]; 510 u8 srq_receive[0x1]; 511 u8 reserved_0[0x1a]; 512}; 513 514struct mlx5_ifc_flow_counter_list_bits { 515 u8 reserved_0[0x10]; 516 u8 flow_counter_id[0x10]; 517 518 u8 reserved_1[0x20]; 519}; 520 521enum { 522 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0x0, 523 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 0x1, 524 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 0x2, 525 MLX5_FLOW_CONTEXT_DEST_TYPE_QP = 0x3, 526}; 527 528struct mlx5_ifc_dest_format_struct_bits { 529 u8 destination_type[0x8]; 530 u8 destination_id[0x18]; 531 532 u8 reserved_0[0x8]; 533 u8 destination_table_type[0x8]; 534 u8 reserved_at_1[0x10]; 535}; 536 537struct mlx5_ifc_ipv4_layout_bits { 538 u8 reserved_at_0[0x60]; 539 540 u8 ipv4[0x20]; 541}; 542 543struct mlx5_ifc_ipv6_layout_bits { 544 u8 ipv6[16][0x8]; 545}; 546 547union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 548 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 549 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 550 u8 reserved_at_0[0x80]; 551}; 552 553struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 554 u8 smac_47_16[0x20]; 555 556 u8 smac_15_0[0x10]; 557 u8 ethertype[0x10]; 558 559 u8 dmac_47_16[0x20]; 560 561 u8 dmac_15_0[0x10]; 562 u8 first_prio[0x3]; 563 u8 first_cfi[0x1]; 564 u8 first_vid[0xc]; 565 566 u8 ip_protocol[0x8]; 567 u8 ip_dscp[0x6]; 568 u8 ip_ecn[0x2]; 569 u8 cvlan_tag[0x1]; 570 u8 svlan_tag[0x1]; 571 u8 frag[0x1]; 572 u8 ip_version[0x4]; 573 u8 tcp_flags[0x9]; 574 575 u8 tcp_sport[0x10]; 576 u8 tcp_dport[0x10]; 577 578 u8 reserved_2[0x20]; 579 580 u8 udp_sport[0x10]; 581 u8 udp_dport[0x10]; 582 583 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 584 585 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 586}; 587 588struct mlx5_ifc_fte_match_set_misc_bits { 589 u8 reserved_0[0x8]; 590 u8 source_sqn[0x18]; 591 592 u8 reserved_1[0x10]; 593 u8 source_port[0x10]; 594 595 u8 outer_second_prio[0x3]; 596 u8 outer_second_cfi[0x1]; 597 u8 outer_second_vid[0xc]; 598 u8 inner_second_prio[0x3]; 599 u8 inner_second_cfi[0x1]; 600 u8 inner_second_vid[0xc]; 601 602 u8 outer_second_vlan_tag[0x1]; 603 u8 inner_second_vlan_tag[0x1]; 604 u8 reserved_2[0xe]; 605 u8 gre_protocol[0x10]; 606 607 u8 gre_key_h[0x18]; 608 u8 gre_key_l[0x8]; 609 610 u8 vxlan_vni[0x18]; 611 u8 reserved_3[0x8]; 612 613 u8 geneve_vni[0x18]; 614 u8 reserved4[0x7]; 615 u8 geneve_oam[0x1]; 616 617 u8 reserved_5[0xc]; 618 u8 outer_ipv6_flow_label[0x14]; 619 620 u8 reserved_6[0xc]; 621 u8 inner_ipv6_flow_label[0x14]; 622 623 u8 reserved_7[0xa]; 624 u8 geneve_opt_len[0x6]; 625 u8 geneve_protocol_type[0x10]; 626 627 u8 reserved_8[0x8]; 628 u8 bth_dst_qp[0x18]; 629 630 u8 reserved_9[0xa0]; 631}; 632 633struct mlx5_ifc_cmd_pas_bits { 634 u8 pa_h[0x20]; 635 636 u8 pa_l[0x14]; 637 u8 reserved_0[0xc]; 638}; 639 640struct mlx5_ifc_uint64_bits { 641 u8 hi[0x20]; 642 643 u8 lo[0x20]; 644}; 645 646struct mlx5_ifc_application_prio_entry_bits { 647 u8 reserved_0[0x8]; 648 u8 priority[0x3]; 649 u8 reserved_1[0x2]; 650 u8 sel[0x3]; 651 u8 protocol_id[0x10]; 652}; 653 654struct mlx5_ifc_nodnic_ring_doorbell_bits { 655 u8 reserved_0[0x8]; 656 u8 ring_pi[0x10]; 657 u8 reserved_1[0x8]; 658}; 659 660enum { 661 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 662 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 663 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 664 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 665 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 666 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 667 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 668 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 669 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 670 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 671}; 672 673struct mlx5_ifc_ads_bits { 674 u8 fl[0x1]; 675 u8 free_ar[0x1]; 676 u8 reserved_0[0xe]; 677 u8 pkey_index[0x10]; 678 679 u8 reserved_1[0x8]; 680 u8 grh[0x1]; 681 u8 mlid[0x7]; 682 u8 rlid[0x10]; 683 684 u8 ack_timeout[0x5]; 685 u8 reserved_2[0x3]; 686 u8 src_addr_index[0x8]; 687 u8 log_rtm[0x4]; 688 u8 stat_rate[0x4]; 689 u8 hop_limit[0x8]; 690 691 u8 reserved_3[0x4]; 692 u8 tclass[0x8]; 693 u8 flow_label[0x14]; 694 695 u8 rgid_rip[16][0x8]; 696 697 u8 reserved_4[0x4]; 698 u8 f_dscp[0x1]; 699 u8 f_ecn[0x1]; 700 u8 reserved_5[0x1]; 701 u8 f_eth_prio[0x1]; 702 u8 ecn[0x2]; 703 u8 dscp[0x6]; 704 u8 udp_sport[0x10]; 705 706 u8 dei_cfi[0x1]; 707 u8 eth_prio[0x3]; 708 u8 sl[0x4]; 709 u8 port[0x8]; 710 u8 rmac_47_32[0x10]; 711 712 u8 rmac_31_0[0x20]; 713}; 714 715struct mlx5_ifc_diagnostic_counter_cap_bits { 716 u8 sync[0x1]; 717 u8 reserved_0[0xf]; 718 u8 counter_id[0x10]; 719}; 720 721struct mlx5_ifc_debug_cap_bits { 722 u8 reserved_0[0x18]; 723 u8 log_max_samples[0x8]; 724 725 u8 single[0x1]; 726 u8 repetitive[0x1]; 727 u8 health_mon_rx_activity[0x1]; 728 u8 reserved_1[0x15]; 729 u8 log_min_sample_period[0x8]; 730 731 u8 reserved_2[0x1c0]; 732 733 struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0]; 734}; 735 736struct mlx5_ifc_qos_cap_bits { 737 u8 packet_pacing[0x1]; 738 u8 esw_scheduling[0x1]; 739 u8 esw_bw_share[0x1]; 740 u8 esw_rate_limit[0x1]; 741 u8 hll[0x1]; 742 u8 packet_pacing_burst_bound[0x1]; 743 u8 packet_pacing_typical_size[0x1]; 744 u8 reserved_at_7[0x19]; 745 746 u8 reserved_at_20[0xA]; 747 u8 qos_remap_pp[0x1]; 748 u8 reserved_at_2b[0x15]; 749 750 u8 packet_pacing_max_rate[0x20]; 751 752 u8 packet_pacing_min_rate[0x20]; 753 754 u8 reserved_at_80[0x10]; 755 u8 packet_pacing_rate_table_size[0x10]; 756 757 u8 esw_element_type[0x10]; 758 u8 esw_tsar_type[0x10]; 759 760 u8 reserved_at_c0[0x10]; 761 u8 max_qos_para_vport[0x10]; 762 763 u8 max_tsar_bw_share[0x20]; 764 765 u8 reserved_at_100[0x700]; 766}; 767 768struct mlx5_ifc_snapshot_cap_bits { 769 u8 reserved_0[0x1d]; 770 u8 suspend_qp_uc[0x1]; 771 u8 suspend_qp_ud[0x1]; 772 u8 suspend_qp_rc[0x1]; 773 774 u8 reserved_1[0x1c]; 775 u8 restore_pd[0x1]; 776 u8 restore_uar[0x1]; 777 u8 restore_mkey[0x1]; 778 u8 restore_qp[0x1]; 779 780 u8 reserved_2[0x1e]; 781 u8 named_mkey[0x1]; 782 u8 named_qp[0x1]; 783 784 u8 reserved_3[0x7a0]; 785}; 786 787struct mlx5_ifc_e_switch_cap_bits { 788 u8 vport_svlan_strip[0x1]; 789 u8 vport_cvlan_strip[0x1]; 790 u8 vport_svlan_insert[0x1]; 791 u8 vport_cvlan_insert_if_not_exist[0x1]; 792 u8 vport_cvlan_insert_overwrite[0x1]; 793 u8 reserved_at_5[0x1]; 794 u8 vport_cvlan_insert_always[0x1]; 795 u8 esw_shared_ingress_acl[0x1]; 796 u8 esw_uplink_ingress_acl[0x1]; 797 u8 root_ft_on_other_esw[0x1]; 798 u8 reserved_at_a[0xf]; 799 u8 esw_functions_changed[0x1]; 800 u8 reserved_at_1a[0x1]; 801 u8 ecpf_vport_exists[0x1]; 802 u8 counter_eswitch_affinity[0x1]; 803 u8 merged_eswitch[0x1]; 804 u8 nic_vport_node_guid_modify[0x1]; 805 u8 nic_vport_port_guid_modify[0x1]; 806 807 u8 vxlan_encap_decap[0x1]; 808 u8 nvgre_encap_decap[0x1]; 809 u8 reserved_at_22[0x1]; 810 u8 log_max_fdb_encap_uplink[0x5]; 811 u8 reserved_at_21[0x3]; 812 u8 log_max_packet_reformat_context[0x5]; 813 u8 reserved_2b[0x6]; 814 u8 max_encap_header_size[0xa]; 815 816 u8 reserved_at_40[0xb]; 817 u8 log_max_esw_sf[0x5]; 818 u8 esw_sf_base_id[0x10]; 819 820 u8 reserved_at_60[0x7a0]; 821 822}; 823 824struct mlx5_ifc_flow_table_eswitch_cap_bits { 825 u8 reserved_0[0x200]; 826 827 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 828 829 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 830 831 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 832 833 u8 reserved_1[0x7800]; 834}; 835 836struct mlx5_ifc_flow_table_nic_cap_bits { 837 u8 nic_rx_multi_path_tirs[0x1]; 838 u8 nic_rx_multi_path_tirs_fts[0x1]; 839 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 840 u8 reserved_at_3[0x4]; 841 u8 sw_owner_reformat_supported[0x1]; 842 u8 reserved_at_8[0x18]; 843 844 u8 encap_general_header[0x1]; 845 u8 reserved_at_21[0xa]; 846 u8 log_max_packet_reformat_context[0x5]; 847 u8 reserved_at_30[0x6]; 848 u8 max_encap_header_size[0xa]; 849 u8 reserved_at_40[0x1c0]; 850 851 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 852 853 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 854 855 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 856 857 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 858 859 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 860 861 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 862 863 u8 reserved_1[0x7200]; 864}; 865 866struct mlx5_ifc_pddr_module_info_bits { 867 u8 cable_technology[0x8]; 868 u8 cable_breakout[0x8]; 869 u8 ext_ethernet_compliance_code[0x8]; 870 u8 ethernet_compliance_code[0x8]; 871 872 u8 cable_type[0x4]; 873 u8 cable_vendor[0x4]; 874 u8 cable_length[0x8]; 875 u8 cable_identifier[0x8]; 876 u8 cable_power_class[0x8]; 877 878 u8 reserved_at_40[0x8]; 879 u8 cable_rx_amp[0x8]; 880 u8 cable_rx_emphasis[0x8]; 881 u8 cable_tx_equalization[0x8]; 882 883 u8 reserved_at_60[0x8]; 884 u8 cable_attenuation_12g[0x8]; 885 u8 cable_attenuation_7g[0x8]; 886 u8 cable_attenuation_5g[0x8]; 887 888 u8 reserved_at_80[0x8]; 889 u8 rx_cdr_cap[0x4]; 890 u8 tx_cdr_cap[0x4]; 891 u8 reserved_at_90[0x4]; 892 u8 rx_cdr_state[0x4]; 893 u8 reserved_at_98[0x4]; 894 u8 tx_cdr_state[0x4]; 895 896 u8 vendor_name[16][0x8]; 897 898 u8 vendor_pn[16][0x8]; 899 900 u8 vendor_rev[0x20]; 901 902 u8 fw_version[0x20]; 903 904 u8 vendor_sn[16][0x8]; 905 906 u8 temperature[0x10]; 907 u8 voltage[0x10]; 908 909 u8 rx_power_lane0[0x10]; 910 u8 rx_power_lane1[0x10]; 911 912 u8 rx_power_lane2[0x10]; 913 u8 rx_power_lane3[0x10]; 914 915 u8 reserved_at_2c0[0x40]; 916 917 u8 tx_power_lane0[0x10]; 918 u8 tx_power_lane1[0x10]; 919 920 u8 tx_power_lane2[0x10]; 921 u8 tx_power_lane3[0x10]; 922 923 u8 reserved_at_340[0x40]; 924 925 u8 tx_bias_lane0[0x10]; 926 u8 tx_bias_lane1[0x10]; 927 928 u8 tx_bias_lane2[0x10]; 929 u8 tx_bias_lane3[0x10]; 930 931 u8 reserved_at_3c0[0x40]; 932 933 u8 temperature_high_th[0x10]; 934 u8 temperature_low_th[0x10]; 935 936 u8 voltage_high_th[0x10]; 937 u8 voltage_low_th[0x10]; 938 939 u8 rx_power_high_th[0x10]; 940 u8 rx_power_low_th[0x10]; 941 942 u8 tx_power_high_th[0x10]; 943 u8 tx_power_low_th[0x10]; 944 945 u8 tx_bias_high_th[0x10]; 946 u8 tx_bias_low_th[0x10]; 947 948 u8 reserved_at_4a0[0x10]; 949 u8 wavelength[0x10]; 950 951 u8 reserved_at_4c0[0x300]; 952}; 953 954struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 955 u8 csum_cap[0x1]; 956 u8 vlan_cap[0x1]; 957 u8 lro_cap[0x1]; 958 u8 lro_psh_flag[0x1]; 959 u8 lro_time_stamp[0x1]; 960 u8 lro_max_msg_sz_mode[0x2]; 961 u8 wqe_vlan_insert[0x1]; 962 u8 self_lb_en_modifiable[0x1]; 963 u8 self_lb_mc[0x1]; 964 u8 self_lb_uc[0x1]; 965 u8 max_lso_cap[0x5]; 966 u8 multi_pkt_send_wqe[0x2]; 967 u8 wqe_inline_mode[0x2]; 968 u8 rss_ind_tbl_cap[0x4]; 969 u8 reg_umr_sq[0x1]; 970 u8 scatter_fcs[0x1]; 971 u8 enhanced_multi_pkt_send_wqe[0x1]; 972 u8 tunnel_lso_const_out_ip_id[0x1]; 973 u8 tunnel_lro_gre[0x1]; 974 u8 tunnel_lro_vxlan[0x1]; 975 u8 tunnel_statless_gre[0x1]; 976 u8 tunnel_stateless_vxlan[0x1]; 977 978 u8 swp[0x1]; 979 u8 swp_csum[0x1]; 980 u8 swp_lso[0x1]; 981 u8 reserved_2[0x1b]; 982 u8 max_geneve_opt_len[0x1]; 983 u8 tunnel_stateless_geneve_rx[0x1]; 984 985 u8 reserved_3[0x10]; 986 u8 lro_min_mss_size[0x10]; 987 988 u8 reserved_4[0x120]; 989 990 u8 lro_timer_supported_periods[4][0x20]; 991 992 u8 reserved_5[0x600]; 993}; 994 995enum { 996 MLX5_ROCE_CAP_L3_TYPE_GRH = 0x1, 997 MLX5_ROCE_CAP_L3_TYPE_IPV4 = 0x2, 998 MLX5_ROCE_CAP_L3_TYPE_IPV6 = 0x4, 999}; 1000 1001enum { 1002 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1003 MLX5_QP_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1004 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1005}; 1006 1007struct mlx5_ifc_roce_cap_bits { 1008 u8 roce_apm[0x1]; 1009 u8 rts2rts_primary_eth_prio[0x1]; 1010 u8 roce_rx_allow_untagged[0x1]; 1011 u8 rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1]; 1012 u8 reserved_at_4[0x1a]; 1013 u8 qp_ts_format[0x2]; 1014 1015 u8 reserved_1[0x60]; 1016 1017 u8 reserved_2[0xc]; 1018 u8 l3_type[0x4]; 1019 u8 reserved_3[0x8]; 1020 u8 roce_version[0x8]; 1021 1022 u8 reserved_4[0x10]; 1023 u8 r_roce_dest_udp_port[0x10]; 1024 1025 u8 r_roce_max_src_udp_port[0x10]; 1026 u8 r_roce_min_src_udp_port[0x10]; 1027 1028 u8 reserved_5[0x10]; 1029 u8 roce_address_table_size[0x10]; 1030 1031 u8 reserved_6[0x700]; 1032}; 1033 1034struct mlx5_ifc_device_event_cap_bits { 1035 u8 user_affiliated_events[4][0x40]; 1036 1037 u8 user_unaffiliated_events[4][0x40]; 1038}; 1039 1040enum { 1041 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x1, 1042 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1043 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1044 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1045 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1046 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1047 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1048 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1049 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1050}; 1051 1052enum { 1053 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1054 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1055 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1056 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1057 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1058 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1059 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1060 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1061 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1062}; 1063 1064struct mlx5_ifc_atomic_caps_bits { 1065 u8 reserved_0[0x40]; 1066 1067 u8 atomic_req_8B_endianess_mode[0x2]; 1068 u8 reserved_1[0x4]; 1069 u8 supported_atomic_req_8B_endianess_mode_1[0x1]; 1070 1071 u8 reserved_2[0x19]; 1072 1073 u8 reserved_3[0x20]; 1074 1075 u8 reserved_4[0x10]; 1076 u8 atomic_operations[0x10]; 1077 1078 u8 reserved_5[0x10]; 1079 u8 atomic_size_qp[0x10]; 1080 1081 u8 reserved_6[0x10]; 1082 u8 atomic_size_dc[0x10]; 1083 1084 u8 reserved_7[0x720]; 1085}; 1086 1087struct mlx5_ifc_odp_cap_bits { 1088 u8 reserved_0[0x40]; 1089 1090 u8 sig[0x1]; 1091 u8 reserved_1[0x1f]; 1092 1093 u8 reserved_2[0x20]; 1094 1095 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1096 1097 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1098 1099 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1100 1101 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1102 1103 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1104 1105 u8 reserved_3[0x6e0]; 1106}; 1107 1108enum { 1109 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1110 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1111 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1112 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1113 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1114}; 1115 1116enum { 1117 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1118 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1119 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1120 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1121 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1122 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1123}; 1124 1125enum { 1126 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1127 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1128}; 1129 1130enum { 1131 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1132 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1133 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1134}; 1135 1136enum { 1137 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1138 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1139}; 1140 1141enum { 1142 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1143 MLX5_SQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1144 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1145}; 1146 1147enum { 1148 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1149 MLX5_RQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1150 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1151}; 1152 1153struct mlx5_ifc_cmd_hca_cap_bits { 1154 u8 reserved_0[0x20]; 1155 1156 u8 hca_cap_2[0x1]; 1157 u8 reserved_at_21[0x1f]; 1158 1159 u8 reserved_at_40[0x40]; 1160 1161 u8 log_max_srq_sz[0x8]; 1162 u8 log_max_qp_sz[0x8]; 1163 u8 event_cap[0x1]; 1164 u8 reserved_1[0xa]; 1165 u8 log_max_qp[0x5]; 1166 1167 u8 reserved_2[0xb]; 1168 u8 log_max_srq[0x5]; 1169 u8 reserved_3[0x10]; 1170 1171 u8 reserved_4[0x8]; 1172 u8 log_max_cq_sz[0x8]; 1173 u8 relaxed_ordering_write_umr[0x1]; 1174 u8 relaxed_ordering_read_umr[0x1]; 1175 u8 reserved_5[0x9]; 1176 u8 log_max_cq[0x5]; 1177 1178 u8 log_max_eq_sz[0x8]; 1179 u8 relaxed_ordering_write[0x1]; 1180 u8 relaxed_ordering_read[0x1]; 1181 u8 log_max_mkey[0x6]; 1182 u8 reserved_7[0xb]; 1183 u8 fast_teardown[0x1]; 1184 u8 log_max_eq[0x4]; 1185 1186 u8 max_indirection[0x8]; 1187 u8 reserved_8[0x1]; 1188 u8 log_max_mrw_sz[0x7]; 1189 u8 force_teardown[0x1]; 1190 u8 reserved_9[0x1]; 1191 u8 log_max_bsf_list_size[0x6]; 1192 u8 reserved_10[0x2]; 1193 u8 log_max_klm_list_size[0x6]; 1194 1195 u8 reserved_11[0xa]; 1196 u8 log_max_ra_req_dc[0x6]; 1197 u8 reserved_12[0xa]; 1198 u8 log_max_ra_res_dc[0x6]; 1199 1200 u8 reserved_13[0xa]; 1201 u8 log_max_ra_req_qp[0x6]; 1202 u8 reserved_14[0xa]; 1203 u8 log_max_ra_res_qp[0x6]; 1204 1205 u8 pad_cap[0x1]; 1206 u8 cc_query_allowed[0x1]; 1207 u8 cc_modify_allowed[0x1]; 1208 u8 start_pad[0x1]; 1209 u8 cache_line_128byte[0x1]; 1210 u8 reserved_at_165[0xa]; 1211 u8 qcam_reg[0x1]; 1212 u8 gid_table_size[0x10]; 1213 1214 u8 out_of_seq_cnt[0x1]; 1215 u8 vport_counters[0x1]; 1216 u8 retransmission_q_counters[0x1]; 1217 u8 debug[0x1]; 1218 u8 modify_rq_counters_set_id[0x1]; 1219 u8 rq_delay_drop[0x1]; 1220 u8 max_qp_cnt[0xa]; 1221 u8 pkey_table_size[0x10]; 1222 1223 u8 vport_group_manager[0x1]; 1224 u8 vhca_group_manager[0x1]; 1225 u8 ib_virt[0x1]; 1226 u8 eth_virt[0x1]; 1227 u8 reserved_17[0x1]; 1228 u8 ets[0x1]; 1229 u8 nic_flow_table[0x1]; 1230 u8 eswitch_flow_table[0x1]; 1231 u8 reserved_18[0x1]; 1232 u8 mcam_reg[0x1]; 1233 u8 pcam_reg[0x1]; 1234 u8 local_ca_ack_delay[0x5]; 1235 u8 port_module_event[0x1]; 1236 u8 reserved_19[0x5]; 1237 u8 port_type[0x2]; 1238 u8 num_ports[0x8]; 1239 1240 u8 snapshot[0x1]; 1241 u8 reserved_20[0x2]; 1242 u8 log_max_msg[0x5]; 1243 u8 reserved_21[0x4]; 1244 u8 max_tc[0x4]; 1245 u8 temp_warn_event[0x1]; 1246 u8 dcbx[0x1]; 1247 u8 general_notification_event[0x1]; 1248 u8 reserved_at_1d3[0x2]; 1249 u8 fpga[0x1]; 1250 u8 rol_s[0x1]; 1251 u8 rol_g[0x1]; 1252 u8 reserved_23[0x1]; 1253 u8 wol_s[0x1]; 1254 u8 wol_g[0x1]; 1255 u8 wol_a[0x1]; 1256 u8 wol_b[0x1]; 1257 u8 wol_m[0x1]; 1258 u8 wol_u[0x1]; 1259 u8 wol_p[0x1]; 1260 1261 u8 stat_rate_support[0x10]; 1262 u8 reserved_24[0xc]; 1263 u8 cqe_version[0x4]; 1264 1265 u8 compact_address_vector[0x1]; 1266 u8 striding_rq[0x1]; 1267 u8 reserved_25[0x1]; 1268 u8 ipoib_enhanced_offloads[0x1]; 1269 u8 ipoib_ipoib_offloads[0x1]; 1270 u8 reserved_26[0x8]; 1271 u8 dc_connect_qp[0x1]; 1272 u8 dc_cnak_trace[0x1]; 1273 u8 drain_sigerr[0x1]; 1274 u8 cmdif_checksum[0x2]; 1275 u8 sigerr_cqe[0x1]; 1276 u8 reserved_27[0x1]; 1277 u8 wq_signature[0x1]; 1278 u8 sctr_data_cqe[0x1]; 1279 u8 reserved_28[0x1]; 1280 u8 sho[0x1]; 1281 u8 tph[0x1]; 1282 u8 rf[0x1]; 1283 u8 dct[0x1]; 1284 u8 qos[0x1]; 1285 u8 eth_net_offloads[0x1]; 1286 u8 roce[0x1]; 1287 u8 atomic[0x1]; 1288 u8 reserved_30[0x1]; 1289 1290 u8 cq_oi[0x1]; 1291 u8 cq_resize[0x1]; 1292 u8 cq_moderation[0x1]; 1293 u8 cq_period_mode_modify[0x1]; 1294 u8 cq_invalidate[0x1]; 1295 u8 reserved_at_225[0x1]; 1296 u8 cq_eq_remap[0x1]; 1297 u8 pg[0x1]; 1298 u8 block_lb_mc[0x1]; 1299 u8 exponential_backoff[0x1]; 1300 u8 scqe_break_moderation[0x1]; 1301 u8 cq_period_start_from_cqe[0x1]; 1302 u8 cd[0x1]; 1303 u8 atm[0x1]; 1304 u8 apm[0x1]; 1305 u8 imaicl[0x1]; 1306 u8 reserved_32[0x6]; 1307 u8 qkv[0x1]; 1308 u8 pkv[0x1]; 1309 u8 set_deth_sqpn[0x1]; 1310 u8 reserved_33[0x3]; 1311 u8 xrc[0x1]; 1312 u8 ud[0x1]; 1313 u8 uc[0x1]; 1314 u8 rc[0x1]; 1315 1316 u8 uar_4k[0x1]; 1317 u8 reserved_at_241[0x9]; 1318 u8 uar_sz[0x6]; 1319 u8 reserved_35[0x8]; 1320 u8 log_pg_sz[0x8]; 1321 1322 u8 bf[0x1]; 1323 u8 driver_version[0x1]; 1324 u8 pad_tx_eth_packet[0x1]; 1325 u8 reserved_36[0x8]; 1326 u8 log_bf_reg_size[0x5]; 1327 u8 reserved_37[0x10]; 1328 1329 u8 num_of_diagnostic_counters[0x10]; 1330 u8 max_wqe_sz_sq[0x10]; 1331 1332 u8 reserved_38[0x10]; 1333 u8 max_wqe_sz_rq[0x10]; 1334 1335 u8 reserved_39[0x10]; 1336 u8 max_wqe_sz_sq_dc[0x10]; 1337 1338 u8 reserved_40[0x7]; 1339 u8 max_qp_mcg[0x19]; 1340 1341 u8 reserved_41[0x10]; 1342 u8 flow_counter_bulk_alloc[0x8]; 1343 u8 log_max_mcg[0x8]; 1344 1345 u8 reserved_42[0x3]; 1346 u8 log_max_transport_domain[0x5]; 1347 u8 reserved_43[0x3]; 1348 u8 log_max_pd[0x5]; 1349 u8 reserved_44[0xb]; 1350 u8 log_max_xrcd[0x5]; 1351 1352 u8 nic_receive_steering_discard[0x1]; 1353 u8 reserved_45[0x7]; 1354 u8 log_max_flow_counter_bulk[0x8]; 1355 u8 max_flow_counter[0x10]; 1356 1357 u8 reserved_46[0x3]; 1358 u8 log_max_rq[0x5]; 1359 u8 reserved_47[0x3]; 1360 u8 log_max_sq[0x5]; 1361 u8 reserved_48[0x3]; 1362 u8 log_max_tir[0x5]; 1363 u8 reserved_49[0x3]; 1364 u8 log_max_tis[0x5]; 1365 1366 u8 basic_cyclic_rcv_wqe[0x1]; 1367 u8 reserved_50[0x2]; 1368 u8 log_max_rmp[0x5]; 1369 u8 reserved_51[0x3]; 1370 u8 log_max_rqt[0x5]; 1371 u8 reserved_52[0x3]; 1372 u8 log_max_rqt_size[0x5]; 1373 u8 reserved_53[0x3]; 1374 u8 log_max_tis_per_sq[0x5]; 1375 1376 u8 reserved_54[0x3]; 1377 u8 log_max_stride_sz_rq[0x5]; 1378 u8 reserved_55[0x3]; 1379 u8 log_min_stride_sz_rq[0x5]; 1380 u8 reserved_56[0x3]; 1381 u8 log_max_stride_sz_sq[0x5]; 1382 u8 reserved_57[0x3]; 1383 u8 log_min_stride_sz_sq[0x5]; 1384 1385 u8 reserved_58[0x1b]; 1386 u8 log_max_wq_sz[0x5]; 1387 1388 u8 nic_vport_change_event[0x1]; 1389 u8 disable_local_lb_uc[0x1]; 1390 u8 disable_local_lb_mc[0x1]; 1391 u8 reserved_59[0x8]; 1392 u8 log_max_vlan_list[0x5]; 1393 u8 reserved_60[0x3]; 1394 u8 log_max_current_mc_list[0x5]; 1395 u8 reserved_61[0x3]; 1396 u8 log_max_current_uc_list[0x5]; 1397 1398 u8 general_obj_types[0x40]; 1399 1400 u8 sq_ts_format[0x2]; 1401 u8 rq_ts_format[0x2]; 1402 u8 reserved_at_444[0x4]; 1403 u8 create_qp_start_hint[0x18]; 1404 1405 u8 reserved_at_460[0x3]; 1406 u8 log_max_uctx[0x5]; 1407 u8 reserved_at_468[0x3]; 1408 u8 log_max_umem[0x5]; 1409 u8 max_num_eqs[0x10]; 1410 1411 u8 reserved_at_480[0x1]; 1412 u8 tls_tx[0x1]; 1413 u8 tls_rx[0x1]; 1414 u8 log_max_l2_table[0x5]; 1415 u8 reserved_64[0x8]; 1416 u8 log_uar_page_sz[0x10]; 1417 1418 u8 reserved_65[0x20]; 1419 1420 u8 device_frequency_mhz[0x20]; 1421 1422 u8 device_frequency_khz[0x20]; 1423 1424 u8 reserved_at_500[0x20]; 1425 u8 num_of_uars_per_page[0x20]; 1426 u8 reserved_at_540[0x40]; 1427 1428 u8 log_max_atomic_size_qp[0x8]; 1429 u8 reserved_67[0x10]; 1430 u8 log_max_atomic_size_dc[0x8]; 1431 1432 u8 reserved_at_5a0[0x13]; 1433 u8 log_max_dek[0x5]; 1434 u8 reserved_at_5b8[0x4]; 1435 u8 mini_cqe_resp_stride_index[0x1]; 1436 u8 cqe_128_always[0x1]; 1437 u8 cqe_compression_128b[0x1]; 1438 1439 u8 cqe_compression[0x1]; 1440 1441 u8 cqe_compression_timeout[0x10]; 1442 u8 cqe_compression_max_num[0x10]; 1443 1444 u8 reserved_5e0[0xc0]; 1445 1446 u8 uctx_cap[0x20]; 1447 1448 u8 reserved_6c0[0xc0]; 1449 1450 u8 vhca_tunnel_commands[0x40]; 1451 u8 reserved_at_7c0[0x40]; 1452}; 1453 1454struct mlx5_ifc_cmd_hca_cap_2_bits { 1455 u8 reserved_at_0[0x80]; 1456 1457 u8 migratable[0x1]; 1458 u8 reserved_at_81[0x1f]; 1459 1460 u8 max_reformat_insert_size[0x8]; 1461 u8 max_reformat_insert_offset[0x8]; 1462 u8 max_reformat_remove_size[0x8]; 1463 u8 max_reformat_remove_offset[0x8]; 1464 1465 u8 reserved_at_c0[0x8]; 1466 u8 migration_multi_load[0x1]; 1467 u8 migration_tracking_state[0x1]; 1468 u8 reserved_at_ca[0x16]; 1469 1470 u8 reserved_at_e0[0xc0]; 1471 1472 u8 flow_table_type_2_type[0x8]; 1473 u8 reserved_at_1a8[0x3]; 1474 u8 log_min_mkey_entity_size[0x5]; 1475 u8 reserved_at_1b0[0x10]; 1476 1477 u8 reserved_at_1c0[0x60]; 1478 1479 u8 reserved_at_220[0x1]; 1480 u8 sw_vhca_id_valid[0x1]; 1481 u8 sw_vhca_id[0xe]; 1482 u8 reserved_at_230[0x10]; 1483 1484 u8 reserved_at_240[0xb]; 1485 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 1486 u8 reserved_at_250[0x10]; 1487 1488 u8 reserved_at_260[0x5a0]; 1489}; 1490 1491enum mlx5_flow_destination_type { 1492 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1493 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1494 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1495 MLX5_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 1496}; 1497 1498union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1499 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1500 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1501 u8 reserved_0[0x40]; 1502}; 1503 1504struct mlx5_ifc_fte_match_param_bits { 1505 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1506 1507 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1508 1509 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1510 1511 u8 reserved_0[0xa00]; 1512}; 1513 1514enum { 1515 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1516 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1517 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1518 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1519 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1520}; 1521 1522struct mlx5_ifc_rx_hash_field_select_bits { 1523 u8 l3_prot_type[0x1]; 1524 u8 l4_prot_type[0x1]; 1525 u8 selected_fields[0x1e]; 1526}; 1527 1528struct mlx5_ifc_tls_capabilities_bits { 1529 u8 tls_1_2_aes_gcm_128[0x1]; 1530 u8 tls_1_3_aes_gcm_128[0x1]; 1531 u8 tls_1_2_aes_gcm_256[0x1]; 1532 u8 tls_1_3_aes_gcm_256[0x1]; 1533 u8 reserved_at_4[0x1c]; 1534 1535 u8 reserved_at_20[0x7e0]; 1536}; 1537 1538enum { 1539 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1540 MLX5_WQ_TYPE_CYCLIC = 0x1, 1541 MLX5_WQ_TYPE_STRQ_LINKED_LIST = 0x2, 1542 MLX5_WQ_TYPE_STRQ_CYCLIC = 0x3, 1543}; 1544 1545enum rq_type { 1546 RQ_TYPE_NONE, 1547 RQ_TYPE_STRIDE, 1548}; 1549 1550enum { 1551 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1552 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1553}; 1554 1555struct mlx5_ifc_wq_bits { 1556 u8 wq_type[0x4]; 1557 u8 wq_signature[0x1]; 1558 u8 end_padding_mode[0x2]; 1559 u8 cd_slave[0x1]; 1560 u8 reserved_0[0x18]; 1561 1562 u8 hds_skip_first_sge[0x1]; 1563 u8 log2_hds_buf_size[0x3]; 1564 u8 reserved_1[0x7]; 1565 u8 page_offset[0x5]; 1566 u8 lwm[0x10]; 1567 1568 u8 reserved_2[0x8]; 1569 u8 pd[0x18]; 1570 1571 u8 reserved_3[0x8]; 1572 u8 uar_page[0x18]; 1573 1574 u8 dbr_addr[0x40]; 1575 1576 u8 hw_counter[0x20]; 1577 1578 u8 sw_counter[0x20]; 1579 1580 u8 reserved_4[0xc]; 1581 u8 log_wq_stride[0x4]; 1582 u8 reserved_5[0x3]; 1583 u8 log_wq_pg_sz[0x5]; 1584 u8 reserved_6[0x3]; 1585 u8 log_wq_sz[0x5]; 1586 1587 u8 dbr_umem_valid[0x1]; 1588 u8 wq_umem_valid[0x1]; 1589 u8 reserved_7[0x13]; 1590 u8 single_wqe_log_num_of_strides[0x3]; 1591 u8 two_byte_shift_en[0x1]; 1592 u8 reserved_8[0x4]; 1593 u8 single_stride_log_num_of_bytes[0x3]; 1594 1595 u8 reserved_9[0x4c0]; 1596 1597 struct mlx5_ifc_cmd_pas_bits pas[0]; 1598}; 1599 1600struct mlx5_ifc_rq_num_bits { 1601 u8 reserved_0[0x8]; 1602 u8 rq_num[0x18]; 1603}; 1604 1605struct mlx5_ifc_mac_address_layout_bits { 1606 u8 reserved_0[0x10]; 1607 u8 mac_addr_47_32[0x10]; 1608 1609 u8 mac_addr_31_0[0x20]; 1610}; 1611 1612struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1613 u8 reserved_0[0xa0]; 1614 1615 u8 min_time_between_cnps[0x20]; 1616 1617 u8 reserved_1[0x12]; 1618 u8 cnp_dscp[0x6]; 1619 u8 reserved_2[0x4]; 1620 u8 cnp_prio_mode[0x1]; 1621 u8 cnp_802p_prio[0x3]; 1622 1623 u8 reserved_3[0x720]; 1624}; 1625 1626struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1627 u8 reserved_0[0x60]; 1628 1629 u8 reserved_1[0x4]; 1630 u8 clamp_tgt_rate[0x1]; 1631 u8 reserved_2[0x3]; 1632 u8 clamp_tgt_rate_after_time_inc[0x1]; 1633 u8 reserved_3[0x17]; 1634 1635 u8 reserved_4[0x20]; 1636 1637 u8 rpg_time_reset[0x20]; 1638 1639 u8 rpg_byte_reset[0x20]; 1640 1641 u8 rpg_threshold[0x20]; 1642 1643 u8 rpg_max_rate[0x20]; 1644 1645 u8 rpg_ai_rate[0x20]; 1646 1647 u8 rpg_hai_rate[0x20]; 1648 1649 u8 rpg_gd[0x20]; 1650 1651 u8 rpg_min_dec_fac[0x20]; 1652 1653 u8 rpg_min_rate[0x20]; 1654 1655 u8 reserved_5[0xe0]; 1656 1657 u8 rate_to_set_on_first_cnp[0x20]; 1658 1659 u8 dce_tcp_g[0x20]; 1660 1661 u8 dce_tcp_rtt[0x20]; 1662 1663 u8 rate_reduce_monitor_period[0x20]; 1664 1665 u8 reserved_6[0x20]; 1666 1667 u8 initial_alpha_value[0x20]; 1668 1669 u8 reserved_7[0x4a0]; 1670}; 1671 1672struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1673 u8 reserved_0[0x80]; 1674 1675 u8 rppp_max_rps[0x20]; 1676 1677 u8 rpg_time_reset[0x20]; 1678 1679 u8 rpg_byte_reset[0x20]; 1680 1681 u8 rpg_threshold[0x20]; 1682 1683 u8 rpg_max_rate[0x20]; 1684 1685 u8 rpg_ai_rate[0x20]; 1686 1687 u8 rpg_hai_rate[0x20]; 1688 1689 u8 rpg_gd[0x20]; 1690 1691 u8 rpg_min_dec_fac[0x20]; 1692 1693 u8 rpg_min_rate[0x20]; 1694 1695 u8 reserved_1[0x640]; 1696}; 1697 1698enum { 1699 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1700 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1701 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1702}; 1703 1704struct mlx5_ifc_resize_field_select_bits { 1705 u8 resize_field_select[0x20]; 1706}; 1707 1708enum { 1709 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1710 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1711 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1712 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1713 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE = 0x10, 1714 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS = 0x20, 1715}; 1716 1717struct mlx5_ifc_modify_field_select_bits { 1718 u8 modify_field_select[0x20]; 1719}; 1720 1721struct mlx5_ifc_field_select_r_roce_np_bits { 1722 u8 field_select_r_roce_np[0x20]; 1723}; 1724 1725enum { 1726 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE = 0x2, 1727 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC = 0x4, 1728 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET = 0x8, 1729 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET = 0x10, 1730 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD = 0x20, 1731 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE = 0x40, 1732 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE = 0x80, 1733 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE = 0x100, 1734 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC = 0x200, 1735 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE = 0x400, 1736 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP = 0x800, 1737 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G = 0x1000, 1738 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT = 0x2000, 1739 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD = 0x4000, 1740 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE = 0x8000, 1741}; 1742 1743struct mlx5_ifc_field_select_r_roce_rp_bits { 1744 u8 field_select_r_roce_rp[0x20]; 1745}; 1746 1747enum { 1748 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1749 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1750 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1751 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1752 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1753 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1754 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1755 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1756 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1757 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1758}; 1759 1760struct mlx5_ifc_field_select_802_1qau_rp_bits { 1761 u8 field_select_8021qaurp[0x20]; 1762}; 1763 1764struct mlx5_ifc_pptb_reg_bits { 1765 u8 reserved_at_0[0x2]; 1766 u8 mm[0x2]; 1767 u8 reserved_at_4[0x4]; 1768 u8 local_port[0x8]; 1769 u8 reserved_at_10[0x6]; 1770 u8 cm[0x1]; 1771 u8 um[0x1]; 1772 u8 pm[0x8]; 1773 1774 u8 prio_x_buff[0x20]; 1775 1776 u8 pm_msb[0x8]; 1777 u8 reserved_at_48[0x10]; 1778 u8 ctrl_buff[0x4]; 1779 u8 untagged_buff[0x4]; 1780}; 1781 1782struct mlx5_ifc_dcbx_app_reg_bits { 1783 u8 reserved_0[0x8]; 1784 u8 port_number[0x8]; 1785 u8 reserved_1[0x10]; 1786 1787 u8 reserved_2[0x1a]; 1788 u8 num_app_prio[0x6]; 1789 1790 u8 reserved_3[0x40]; 1791 1792 struct mlx5_ifc_application_prio_entry_bits app_prio[0]; 1793}; 1794 1795struct mlx5_ifc_dcbx_param_reg_bits { 1796 u8 dcbx_cee_cap[0x1]; 1797 u8 dcbx_ieee_cap[0x1]; 1798 u8 dcbx_standby_cap[0x1]; 1799 u8 reserved_0[0x5]; 1800 u8 port_number[0x8]; 1801 u8 reserved_1[0xa]; 1802 u8 max_application_table_size[0x6]; 1803 1804 u8 reserved_2[0x15]; 1805 u8 version_oper[0x3]; 1806 u8 reserved_3[0x5]; 1807 u8 version_admin[0x3]; 1808 1809 u8 willing_admin[0x1]; 1810 u8 reserved_4[0x3]; 1811 u8 pfc_cap_oper[0x4]; 1812 u8 reserved_5[0x4]; 1813 u8 pfc_cap_admin[0x4]; 1814 u8 reserved_6[0x4]; 1815 u8 num_of_tc_oper[0x4]; 1816 u8 reserved_7[0x4]; 1817 u8 num_of_tc_admin[0x4]; 1818 1819 u8 remote_willing[0x1]; 1820 u8 reserved_8[0x3]; 1821 u8 remote_pfc_cap[0x4]; 1822 u8 reserved_9[0x14]; 1823 u8 remote_num_of_tc[0x4]; 1824 1825 u8 reserved_10[0x18]; 1826 u8 error[0x8]; 1827 1828 u8 reserved_11[0x160]; 1829}; 1830 1831struct mlx5_ifc_qhll_bits { 1832 u8 reserved_at_0[0x8]; 1833 u8 local_port[0x8]; 1834 u8 reserved_at_10[0x10]; 1835 1836 u8 reserved_at_20[0x1b]; 1837 u8 hll_time[0x5]; 1838 1839 u8 stall_en[0x1]; 1840 u8 reserved_at_41[0x1c]; 1841 u8 stall_cnt[0x3]; 1842}; 1843 1844struct mlx5_ifc_qetcr_reg_bits { 1845 u8 operation_type[0x2]; 1846 u8 cap_local_admin[0x1]; 1847 u8 cap_remote_admin[0x1]; 1848 u8 reserved_0[0x4]; 1849 u8 port_number[0x8]; 1850 u8 reserved_1[0x10]; 1851 1852 u8 reserved_2[0x20]; 1853 1854 u8 tc[8][0x40]; 1855 1856 u8 global_configuration[0x40]; 1857}; 1858 1859struct mlx5_ifc_nodnic_ring_config_reg_bits { 1860 u8 queue_address_63_32[0x20]; 1861 1862 u8 queue_address_31_12[0x14]; 1863 u8 reserved_0[0x6]; 1864 u8 log_size[0x6]; 1865 1866 struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell; 1867 1868 u8 reserved_1[0x8]; 1869 u8 queue_number[0x18]; 1870 1871 u8 q_key[0x20]; 1872 1873 u8 reserved_2[0x10]; 1874 u8 pkey_index[0x10]; 1875 1876 u8 reserved_3[0x40]; 1877}; 1878 1879struct mlx5_ifc_nodnic_cq_arming_word_bits { 1880 u8 reserved_0[0x8]; 1881 u8 cq_ci[0x10]; 1882 u8 reserved_1[0x8]; 1883}; 1884 1885enum { 1886 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND = 0x0, 1887 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET = 0x1, 1888}; 1889 1890enum { 1891 MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN = 0x0, 1892 MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE = 0x1, 1893 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED = 0x2, 1894 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE = 0x3, 1895}; 1896 1897struct mlx5_ifc_nodnic_event_word_bits { 1898 u8 driver_reset_needed[0x1]; 1899 u8 port_management_change_event[0x1]; 1900 u8 reserved_0[0x19]; 1901 u8 link_type[0x1]; 1902 u8 port_state[0x4]; 1903}; 1904 1905struct mlx5_ifc_nic_vport_change_event_bits { 1906 u8 reserved_0[0x10]; 1907 u8 vport_num[0x10]; 1908 1909 u8 reserved_1[0xc0]; 1910}; 1911 1912struct mlx5_ifc_pages_req_event_bits { 1913 u8 reserved_0[0x10]; 1914 u8 function_id[0x10]; 1915 1916 u8 num_pages[0x20]; 1917 1918 u8 reserved_1[0xa0]; 1919}; 1920 1921struct mlx5_ifc_cmd_inter_comp_event_bits { 1922 u8 command_completion_vector[0x20]; 1923 1924 u8 reserved_0[0xc0]; 1925}; 1926 1927struct mlx5_ifc_stall_vl_event_bits { 1928 u8 reserved_0[0x18]; 1929 u8 port_num[0x1]; 1930 u8 reserved_1[0x3]; 1931 u8 vl[0x4]; 1932 1933 u8 reserved_2[0xa0]; 1934}; 1935 1936struct mlx5_ifc_db_bf_congestion_event_bits { 1937 u8 event_subtype[0x8]; 1938 u8 reserved_0[0x8]; 1939 u8 congestion_level[0x8]; 1940 u8 reserved_1[0x8]; 1941 1942 u8 reserved_2[0xa0]; 1943}; 1944 1945struct mlx5_ifc_gpio_event_bits { 1946 u8 reserved_0[0x60]; 1947 1948 u8 gpio_event_hi[0x20]; 1949 1950 u8 gpio_event_lo[0x20]; 1951 1952 u8 reserved_1[0x40]; 1953}; 1954 1955struct mlx5_ifc_port_state_change_event_bits { 1956 u8 reserved_0[0x40]; 1957 1958 u8 port_num[0x4]; 1959 u8 reserved_1[0x1c]; 1960 1961 u8 reserved_2[0x80]; 1962}; 1963 1964struct mlx5_ifc_dropped_packet_logged_bits { 1965 u8 reserved_0[0xe0]; 1966}; 1967 1968enum { 1969 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1970 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1971}; 1972 1973struct mlx5_ifc_cq_error_bits { 1974 u8 reserved_0[0x8]; 1975 u8 cqn[0x18]; 1976 1977 u8 reserved_1[0x20]; 1978 1979 u8 reserved_2[0x18]; 1980 u8 syndrome[0x8]; 1981 1982 u8 reserved_3[0x80]; 1983}; 1984 1985struct mlx5_ifc_rdma_page_fault_event_bits { 1986 u8 bytes_commited[0x20]; 1987 1988 u8 r_key[0x20]; 1989 1990 u8 reserved_0[0x10]; 1991 u8 packet_len[0x10]; 1992 1993 u8 rdma_op_len[0x20]; 1994 1995 u8 rdma_va[0x40]; 1996 1997 u8 reserved_1[0x5]; 1998 u8 rdma[0x1]; 1999 u8 write[0x1]; 2000 u8 requestor[0x1]; 2001 u8 qp_number[0x18]; 2002}; 2003 2004struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2005 u8 bytes_committed[0x20]; 2006 2007 u8 reserved_0[0x10]; 2008 u8 wqe_index[0x10]; 2009 2010 u8 reserved_1[0x10]; 2011 u8 len[0x10]; 2012 2013 u8 reserved_2[0x60]; 2014 2015 u8 reserved_3[0x5]; 2016 u8 rdma[0x1]; 2017 u8 write_read[0x1]; 2018 u8 requestor[0x1]; 2019 u8 qpn[0x18]; 2020}; 2021 2022enum { 2023 MLX5_QP_EVENTS_TYPE_QP = 0x0, 2024 MLX5_QP_EVENTS_TYPE_RQ = 0x1, 2025 MLX5_QP_EVENTS_TYPE_SQ = 0x2, 2026}; 2027 2028struct mlx5_ifc_qp_events_bits { 2029 u8 reserved_0[0xa0]; 2030 2031 u8 type[0x8]; 2032 u8 reserved_1[0x18]; 2033 2034 u8 reserved_2[0x8]; 2035 u8 qpn_rqn_sqn[0x18]; 2036}; 2037 2038struct mlx5_ifc_dct_events_bits { 2039 u8 reserved_0[0xc0]; 2040 2041 u8 reserved_1[0x8]; 2042 u8 dct_number[0x18]; 2043}; 2044 2045struct mlx5_ifc_comp_event_bits { 2046 u8 reserved_0[0xc0]; 2047 2048 u8 reserved_1[0x8]; 2049 u8 cq_number[0x18]; 2050}; 2051 2052struct mlx5_ifc_fw_version_bits { 2053 u8 major[0x10]; 2054 u8 reserved_0[0x10]; 2055 2056 u8 minor[0x10]; 2057 u8 subminor[0x10]; 2058 2059 u8 second[0x8]; 2060 u8 minute[0x8]; 2061 u8 hour[0x8]; 2062 u8 reserved_1[0x8]; 2063 2064 u8 year[0x10]; 2065 u8 month[0x8]; 2066 u8 day[0x8]; 2067}; 2068 2069enum { 2070 MLX5_QPC_STATE_RST = 0x0, 2071 MLX5_QPC_STATE_INIT = 0x1, 2072 MLX5_QPC_STATE_RTR = 0x2, 2073 MLX5_QPC_STATE_RTS = 0x3, 2074 MLX5_QPC_STATE_SQER = 0x4, 2075 MLX5_QPC_STATE_SQD = 0x5, 2076 MLX5_QPC_STATE_ERR = 0x6, 2077 MLX5_QPC_STATE_SUSPENDED = 0x9, 2078}; 2079 2080enum { 2081 MLX5_QPC_ST_RC = 0x0, 2082 MLX5_QPC_ST_UC = 0x1, 2083 MLX5_QPC_ST_UD = 0x2, 2084 MLX5_QPC_ST_XRC = 0x3, 2085 MLX5_QPC_ST_DCI = 0x5, 2086 MLX5_QPC_ST_QP0 = 0x7, 2087 MLX5_QPC_ST_QP1 = 0x8, 2088 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2089 MLX5_QPC_ST_REG_UMR = 0xc, 2090}; 2091 2092enum { 2093 MLX5_QP_PM_ARMED = 0x0, 2094 MLX5_QP_PM_REARM = 0x1, 2095 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2096 MLX5_QP_PM_MIGRATED = 0x3, 2097}; 2098 2099enum { 2100 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2101 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2102}; 2103 2104enum { 2105 MLX5_QPC_MTU_256_BYTES = 0x1, 2106 MLX5_QPC_MTU_512_BYTES = 0x2, 2107 MLX5_QPC_MTU_1K_BYTES = 0x3, 2108 MLX5_QPC_MTU_2K_BYTES = 0x4, 2109 MLX5_QPC_MTU_4K_BYTES = 0x5, 2110 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2111}; 2112 2113enum { 2114 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2115 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2116 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2117 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2118 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2119 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2120 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2121 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2122}; 2123 2124enum { 2125 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2126 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2127 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2128}; 2129 2130enum { 2131 MLX5_QPC_CS_RES_DISABLE = 0x0, 2132 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2133 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2134}; 2135 2136enum { 2137 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 2138 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 2139 MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 2140}; 2141 2142struct mlx5_ifc_qpc_bits { 2143 u8 state[0x4]; 2144 u8 lag_tx_port_affinity[0x4]; 2145 u8 st[0x8]; 2146 u8 reserved_1[0x3]; 2147 u8 pm_state[0x2]; 2148 u8 reserved_2[0x7]; 2149 u8 end_padding_mode[0x2]; 2150 u8 reserved_3[0x2]; 2151 2152 u8 wq_signature[0x1]; 2153 u8 block_lb_mc[0x1]; 2154 u8 atomic_like_write_en[0x1]; 2155 u8 latency_sensitive[0x1]; 2156 u8 reserved_4[0x1]; 2157 u8 drain_sigerr[0x1]; 2158 u8 reserved_5[0x2]; 2159 u8 pd[0x18]; 2160 2161 u8 mtu[0x3]; 2162 u8 log_msg_max[0x5]; 2163 u8 reserved_6[0x1]; 2164 u8 log_rq_size[0x4]; 2165 u8 log_rq_stride[0x3]; 2166 u8 no_sq[0x1]; 2167 u8 log_sq_size[0x4]; 2168 u8 reserved_at_55[0x3]; 2169 u8 ts_format[0x2]; 2170 u8 reserved_at_5a[0x1]; 2171 u8 rlky[0x1]; 2172 u8 ulp_stateless_offload_mode[0x4]; 2173 2174 u8 counter_set_id[0x8]; 2175 u8 uar_page[0x18]; 2176 2177 u8 reserved_8[0x8]; 2178 u8 user_index[0x18]; 2179 2180 u8 reserved_9[0x3]; 2181 u8 log_page_size[0x5]; 2182 u8 remote_qpn[0x18]; 2183 2184 struct mlx5_ifc_ads_bits primary_address_path; 2185 2186 struct mlx5_ifc_ads_bits secondary_address_path; 2187 2188 u8 log_ack_req_freq[0x4]; 2189 u8 reserved_10[0x4]; 2190 u8 log_sra_max[0x3]; 2191 u8 reserved_11[0x2]; 2192 u8 retry_count[0x3]; 2193 u8 rnr_retry[0x3]; 2194 u8 reserved_12[0x1]; 2195 u8 fre[0x1]; 2196 u8 cur_rnr_retry[0x3]; 2197 u8 cur_retry_count[0x3]; 2198 u8 reserved_13[0x5]; 2199 2200 u8 reserved_14[0x20]; 2201 2202 u8 reserved_15[0x8]; 2203 u8 next_send_psn[0x18]; 2204 2205 u8 reserved_16[0x8]; 2206 u8 cqn_snd[0x18]; 2207 2208 u8 reserved_at_400[0x8]; 2209 2210 u8 deth_sqpn[0x18]; 2211 u8 reserved_17[0x20]; 2212 2213 u8 reserved_18[0x8]; 2214 u8 last_acked_psn[0x18]; 2215 2216 u8 reserved_19[0x8]; 2217 u8 ssn[0x18]; 2218 2219 u8 reserved_20[0x8]; 2220 u8 log_rra_max[0x3]; 2221 u8 reserved_21[0x1]; 2222 u8 atomic_mode[0x4]; 2223 u8 rre[0x1]; 2224 u8 rwe[0x1]; 2225 u8 rae[0x1]; 2226 u8 reserved_22[0x1]; 2227 u8 page_offset[0x6]; 2228 u8 reserved_23[0x3]; 2229 u8 cd_slave_receive[0x1]; 2230 u8 cd_slave_send[0x1]; 2231 u8 cd_master[0x1]; 2232 2233 u8 reserved_24[0x3]; 2234 u8 min_rnr_nak[0x5]; 2235 u8 next_rcv_psn[0x18]; 2236 2237 u8 reserved_25[0x8]; 2238 u8 xrcd[0x18]; 2239 2240 u8 reserved_26[0x8]; 2241 u8 cqn_rcv[0x18]; 2242 2243 u8 dbr_addr[0x40]; 2244 2245 u8 q_key[0x20]; 2246 2247 u8 reserved_27[0x5]; 2248 u8 rq_type[0x3]; 2249 u8 srqn_rmpn[0x18]; 2250 2251 u8 reserved_28[0x8]; 2252 u8 rmsn[0x18]; 2253 2254 u8 hw_sq_wqebb_counter[0x10]; 2255 u8 sw_sq_wqebb_counter[0x10]; 2256 2257 u8 hw_rq_counter[0x20]; 2258 2259 u8 sw_rq_counter[0x20]; 2260 2261 u8 reserved_29[0x20]; 2262 2263 u8 reserved_30[0xf]; 2264 u8 cgs[0x1]; 2265 u8 cs_req[0x8]; 2266 u8 cs_res[0x8]; 2267 2268 u8 dc_access_key[0x40]; 2269 2270 u8 reserved_at_680[0x3]; 2271 u8 dbr_umem_valid[0x1]; 2272 2273 u8 reserved_at_684[0xbc]; 2274}; 2275 2276struct mlx5_ifc_roce_addr_layout_bits { 2277 u8 source_l3_address[16][0x8]; 2278 2279 u8 reserved_0[0x3]; 2280 u8 vlan_valid[0x1]; 2281 u8 vlan_id[0xc]; 2282 u8 source_mac_47_32[0x10]; 2283 2284 u8 source_mac_31_0[0x20]; 2285 2286 u8 reserved_1[0x14]; 2287 u8 roce_l3_type[0x4]; 2288 u8 roce_version[0x8]; 2289 2290 u8 reserved_2[0x20]; 2291}; 2292 2293struct mlx5_ifc_rdbc_bits { 2294 u8 reserved_0[0x1c]; 2295 u8 type[0x4]; 2296 2297 u8 reserved_1[0x20]; 2298 2299 u8 reserved_2[0x8]; 2300 u8 psn[0x18]; 2301 2302 u8 rkey[0x20]; 2303 2304 u8 address[0x40]; 2305 2306 u8 byte_count[0x20]; 2307 2308 u8 reserved_3[0x20]; 2309 2310 u8 atomic_resp[32][0x8]; 2311}; 2312 2313enum { 2314 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2315 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2316 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2317 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2318 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 2319 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2320}; 2321 2322struct mlx5_ifc_flow_context_bits { 2323 u8 reserved_0[0x20]; 2324 2325 u8 group_id[0x20]; 2326 2327 u8 reserved_1[0x8]; 2328 u8 flow_tag[0x18]; 2329 2330 u8 reserved_2[0x10]; 2331 u8 action[0x10]; 2332 2333 u8 reserved_3[0x8]; 2334 u8 destination_list_size[0x18]; 2335 2336 u8 reserved_4[0x8]; 2337 u8 flow_counter_list_size[0x18]; 2338 2339 u8 packet_reformat_id[0x20]; 2340 2341 u8 modify_header_id[0x20]; 2342 2343 u8 reserved_6[0x100]; 2344 2345 struct mlx5_ifc_fte_match_param_bits match_value; 2346 2347 u8 reserved_7[0x600]; 2348 2349 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2350}; 2351 2352enum { 2353 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2354 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2355}; 2356 2357struct mlx5_ifc_xrc_srqc_bits { 2358 u8 state[0x4]; 2359 u8 log_xrc_srq_size[0x4]; 2360 u8 reserved_0[0x18]; 2361 2362 u8 wq_signature[0x1]; 2363 u8 cont_srq[0x1]; 2364 u8 reserved_1[0x1]; 2365 u8 rlky[0x1]; 2366 u8 basic_cyclic_rcv_wqe[0x1]; 2367 u8 log_rq_stride[0x3]; 2368 u8 xrcd[0x18]; 2369 2370 u8 page_offset[0x6]; 2371 u8 reserved_at_46[0x1]; 2372 u8 dbr_umem_valid[0x1]; 2373 u8 cqn[0x18]; 2374 2375 u8 reserved_3[0x20]; 2376 2377 u8 reserved_4[0x2]; 2378 u8 log_page_size[0x6]; 2379 u8 user_index[0x18]; 2380 2381 u8 reserved_5[0x20]; 2382 2383 u8 reserved_6[0x8]; 2384 u8 pd[0x18]; 2385 2386 u8 lwm[0x10]; 2387 u8 wqe_cnt[0x10]; 2388 2389 u8 reserved_7[0x40]; 2390 2391 u8 db_record_addr_h[0x20]; 2392 2393 u8 db_record_addr_l[0x1e]; 2394 u8 reserved_8[0x2]; 2395 2396 u8 reserved_9[0x80]; 2397}; 2398 2399struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2400 u8 counter_error_queues[0x20]; 2401 2402 u8 total_error_queues[0x20]; 2403 2404 u8 send_queue_priority_update_flow[0x20]; 2405 2406 u8 reserved_at_60[0x20]; 2407 2408 u8 nic_receive_steering_discard[0x40]; 2409 2410 u8 receive_discard_vport_down[0x40]; 2411 2412 u8 transmit_discard_vport_down[0x40]; 2413 2414 u8 reserved_at_140[0xec0]; 2415}; 2416 2417struct mlx5_ifc_traffic_counter_bits { 2418 u8 packets[0x40]; 2419 2420 u8 octets[0x40]; 2421}; 2422 2423struct mlx5_ifc_tisc_bits { 2424 u8 strict_lag_tx_port_affinity[0x1]; 2425 u8 tls_en[0x1]; 2426 u8 reserved_at_2[0x2]; 2427 u8 lag_tx_port_affinity[0x04]; 2428 2429 u8 reserved_at_8[0x4]; 2430 u8 prio[0x4]; 2431 u8 reserved_1[0x10]; 2432 2433 u8 reserved_2[0x100]; 2434 2435 u8 reserved_3[0x8]; 2436 u8 transport_domain[0x18]; 2437 2438 u8 reserved_4[0x8]; 2439 u8 underlay_qpn[0x18]; 2440 2441 u8 reserved_5[0x8]; 2442 u8 pd[0x18]; 2443 2444 u8 reserved_6[0x380]; 2445}; 2446 2447enum { 2448 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2449 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2450}; 2451 2452enum { 2453 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2454 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2455}; 2456 2457enum { 2458 MLX5_TIRC_RX_HASH_FN_HASH_NONE = 0x0, 2459 MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8 = 0x1, 2460 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ = 0x2, 2461}; 2462 2463enum { 2464 MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST = 0x1, 2465 MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST = 0x2, 2466}; 2467 2468struct mlx5_ifc_tirc_bits { 2469 u8 reserved_0[0x20]; 2470 2471 u8 disp_type[0x4]; 2472 u8 tls_en[0x1]; 2473 u8 reserved_at_25[0x1b]; 2474 2475 u8 reserved_2[0x40]; 2476 2477 u8 reserved_3[0x4]; 2478 u8 lro_timeout_period_usecs[0x10]; 2479 u8 lro_enable_mask[0x4]; 2480 u8 lro_max_msg_sz[0x8]; 2481 2482 u8 reserved_4[0x40]; 2483 2484 u8 reserved_5[0x8]; 2485 u8 inline_rqn[0x18]; 2486 2487 u8 rx_hash_symmetric[0x1]; 2488 u8 reserved_6[0x1]; 2489 u8 tunneled_offload_en[0x1]; 2490 u8 reserved_7[0x5]; 2491 u8 indirect_table[0x18]; 2492 2493 u8 rx_hash_fn[0x4]; 2494 u8 reserved_8[0x2]; 2495 u8 self_lb_en[0x2]; 2496 u8 transport_domain[0x18]; 2497 2498 u8 rx_hash_toeplitz_key[10][0x20]; 2499 2500 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2501 2502 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2503 2504 u8 reserved_9[0x4c0]; 2505}; 2506 2507enum { 2508 MLX5_SRQC_STATE_GOOD = 0x0, 2509 MLX5_SRQC_STATE_ERROR = 0x1, 2510}; 2511 2512struct mlx5_ifc_srqc_bits { 2513 u8 state[0x4]; 2514 u8 log_srq_size[0x4]; 2515 u8 reserved_0[0x18]; 2516 2517 u8 wq_signature[0x1]; 2518 u8 cont_srq[0x1]; 2519 u8 reserved_1[0x1]; 2520 u8 rlky[0x1]; 2521 u8 reserved_2[0x1]; 2522 u8 log_rq_stride[0x3]; 2523 u8 xrcd[0x18]; 2524 2525 u8 page_offset[0x6]; 2526 u8 reserved_3[0x2]; 2527 u8 cqn[0x18]; 2528 2529 u8 reserved_4[0x20]; 2530 2531 u8 reserved_5[0x2]; 2532 u8 log_page_size[0x6]; 2533 u8 reserved_6[0x18]; 2534 2535 u8 reserved_7[0x20]; 2536 2537 u8 reserved_8[0x8]; 2538 u8 pd[0x18]; 2539 2540 u8 lwm[0x10]; 2541 u8 wqe_cnt[0x10]; 2542 2543 u8 reserved_9[0x40]; 2544 2545 u8 dbr_addr[0x40]; 2546 2547 u8 reserved_10[0x80]; 2548}; 2549 2550enum { 2551 MLX5_SQC_STATE_RST = 0x0, 2552 MLX5_SQC_STATE_RDY = 0x1, 2553 MLX5_SQC_STATE_ERR = 0x3, 2554}; 2555 2556enum { 2557 MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 2558 MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 2559 MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 2560}; 2561 2562struct mlx5_ifc_sqc_bits { 2563 u8 rlkey[0x1]; 2564 u8 cd_master[0x1]; 2565 u8 fre[0x1]; 2566 u8 flush_in_error_en[0x1]; 2567 u8 allow_multi_pkt_send_wqe[0x1]; 2568 u8 min_wqe_inline_mode[0x3]; 2569 u8 state[0x4]; 2570 u8 reg_umr[0x1]; 2571 u8 allow_swp[0x1]; 2572 u8 reserved_at_e[0x4]; 2573 u8 qos_remap_en[0x1]; 2574 u8 reserved_at_d[0x7]; 2575 u8 ts_format[0x2]; 2576 u8 reserved_at_1c[0x4]; 2577 2578 u8 reserved_1[0x8]; 2579 u8 user_index[0x18]; 2580 2581 u8 reserved_2[0x8]; 2582 u8 cqn[0x18]; 2583 2584 u8 reserved_3[0x80]; 2585 2586 u8 qos_para_vport_number[0x10]; 2587 u8 packet_pacing_rate_limit_index[0x10]; 2588 2589 u8 tis_lst_sz[0x10]; 2590 u8 qos_queue_group_id[0x10]; 2591 2592 u8 reserved_4[0x8]; 2593 u8 queue_handle[0x18]; 2594 2595 u8 reserved_5[0x20]; 2596 2597 u8 reserved_6[0x8]; 2598 u8 tis_num_0[0x18]; 2599 2600 struct mlx5_ifc_wq_bits wq; 2601}; 2602 2603struct mlx5_ifc_query_pp_rate_limit_in_bits { 2604 u8 opcode[0x10]; 2605 u8 uid[0x10]; 2606 2607 u8 reserved1[0x10]; 2608 u8 op_mod[0x10]; 2609 2610 u8 reserved2[0x10]; 2611 u8 rate_limit_index[0x10]; 2612 2613 u8 reserved_3[0x20]; 2614}; 2615 2616struct mlx5_ifc_pp_context_bits { 2617 u8 rate_limit[0x20]; 2618 2619 u8 burst_upper_bound[0x20]; 2620 2621 u8 reserved_1[0xc]; 2622 u8 rate_mode[0x4]; 2623 u8 typical_packet_size[0x10]; 2624 2625 u8 reserved_2[0x8]; 2626 u8 qos_handle[0x18]; 2627 2628 u8 reserved_3[0x40]; 2629}; 2630 2631struct mlx5_ifc_query_pp_rate_limit_out_bits { 2632 u8 status[0x8]; 2633 u8 reserved_1[0x18]; 2634 2635 u8 syndrome[0x20]; 2636 2637 u8 reserved_2[0x40]; 2638 2639 struct mlx5_ifc_pp_context_bits pp_context; 2640}; 2641 2642enum { 2643 MLX5_TSAR_TYPE_DWRR = 0, 2644 MLX5_TSAR_TYPE_ROUND_ROUBIN = 1, 2645 MLX5_TSAR_TYPE_ETS = 2 2646}; 2647 2648struct mlx5_ifc_tsar_element_attributes_bits { 2649 u8 reserved_0[0x8]; 2650 u8 tsar_type[0x8]; 2651 u8 reserved_1[0x10]; 2652}; 2653 2654struct mlx5_ifc_vport_element_attributes_bits { 2655 u8 reserved_0[0x10]; 2656 u8 vport_number[0x10]; 2657}; 2658 2659struct mlx5_ifc_vport_tc_element_attributes_bits { 2660 u8 traffic_class[0x10]; 2661 u8 vport_number[0x10]; 2662}; 2663 2664struct mlx5_ifc_para_vport_tc_element_attributes_bits { 2665 u8 reserved_0[0x0C]; 2666 u8 traffic_class[0x04]; 2667 u8 qos_para_vport_number[0x10]; 2668}; 2669 2670enum { 2671 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2672 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2673 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2674 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2675}; 2676 2677struct mlx5_ifc_scheduling_context_bits { 2678 u8 element_type[0x8]; 2679 u8 reserved_at_8[0x18]; 2680 2681 u8 element_attributes[0x20]; 2682 2683 u8 parent_element_id[0x20]; 2684 2685 u8 reserved_at_60[0x40]; 2686 2687 u8 bw_share[0x20]; 2688 2689 u8 max_average_bw[0x20]; 2690 2691 u8 reserved_at_e0[0x120]; 2692}; 2693 2694struct mlx5_ifc_rqtc_bits { 2695 u8 reserved_0[0xa0]; 2696 2697 u8 reserved_1[0x10]; 2698 u8 rqt_max_size[0x10]; 2699 2700 u8 reserved_2[0x10]; 2701 u8 rqt_actual_size[0x10]; 2702 2703 u8 reserved_3[0x6a0]; 2704 2705 struct mlx5_ifc_rq_num_bits rq_num[0]; 2706}; 2707 2708enum { 2709 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2710 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2711}; 2712 2713enum { 2714 MLX5_RQC_STATE_RST = 0x0, 2715 MLX5_RQC_STATE_RDY = 0x1, 2716 MLX5_RQC_STATE_ERR = 0x3, 2717}; 2718 2719enum { 2720 MLX5_RQC_DROPLESS_MODE_DISABLE = 0x0, 2721 MLX5_RQC_DROPLESS_MODE_ENABLE = 0x1, 2722}; 2723 2724enum { 2725 MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 2726 MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 2727 MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 2728}; 2729 2730struct mlx5_ifc_rqc_bits { 2731 u8 rlkey[0x1]; 2732 u8 delay_drop_en[0x1]; 2733 u8 scatter_fcs[0x1]; 2734 u8 vlan_strip_disable[0x1]; 2735 u8 mem_rq_type[0x4]; 2736 u8 state[0x4]; 2737 u8 reserved_1[0x1]; 2738 u8 flush_in_error_en[0x1]; 2739 u8 reserved_at_e[0xc]; 2740 u8 ts_format[0x2]; 2741 u8 reserved_at_1c[0x4]; 2742 2743 u8 reserved_3[0x8]; 2744 u8 user_index[0x18]; 2745 2746 u8 reserved_4[0x8]; 2747 u8 cqn[0x18]; 2748 2749 u8 counter_set_id[0x8]; 2750 u8 reserved_5[0x18]; 2751 2752 u8 reserved_6[0x8]; 2753 u8 rmpn[0x18]; 2754 2755 u8 reserved_7[0xe0]; 2756 2757 struct mlx5_ifc_wq_bits wq; 2758}; 2759 2760enum { 2761 MLX5_RMPC_STATE_RDY = 0x1, 2762 MLX5_RMPC_STATE_ERR = 0x3, 2763}; 2764 2765struct mlx5_ifc_rmpc_bits { 2766 u8 reserved_0[0x8]; 2767 u8 state[0x4]; 2768 u8 reserved_1[0x14]; 2769 2770 u8 basic_cyclic_rcv_wqe[0x1]; 2771 u8 reserved_2[0x1f]; 2772 2773 u8 reserved_3[0x140]; 2774 2775 struct mlx5_ifc_wq_bits wq; 2776}; 2777 2778enum { 2779 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0, 2780 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS = 0x1, 2781 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST = 0x2, 2782}; 2783 2784struct mlx5_ifc_nic_vport_context_bits { 2785 u8 reserved_0[0x5]; 2786 u8 min_wqe_inline_mode[0x3]; 2787 u8 reserved_1[0x15]; 2788 u8 disable_mc_local_lb[0x1]; 2789 u8 disable_uc_local_lb[0x1]; 2790 u8 roce_en[0x1]; 2791 2792 u8 arm_change_event[0x1]; 2793 u8 reserved_2[0x1a]; 2794 u8 event_on_mtu[0x1]; 2795 u8 event_on_promisc_change[0x1]; 2796 u8 event_on_vlan_change[0x1]; 2797 u8 event_on_mc_address_change[0x1]; 2798 u8 event_on_uc_address_change[0x1]; 2799 2800 u8 reserved_3[0xe0]; 2801 2802 u8 reserved_4[0x10]; 2803 u8 mtu[0x10]; 2804 2805 u8 system_image_guid[0x40]; 2806 2807 u8 port_guid[0x40]; 2808 2809 u8 node_guid[0x40]; 2810 2811 u8 reserved_5[0x140]; 2812 2813 u8 qkey_violation_counter[0x10]; 2814 u8 reserved_6[0x10]; 2815 2816 u8 reserved_7[0x420]; 2817 2818 u8 promisc_uc[0x1]; 2819 u8 promisc_mc[0x1]; 2820 u8 promisc_all[0x1]; 2821 u8 reserved_8[0x2]; 2822 u8 allowed_list_type[0x3]; 2823 u8 reserved_9[0xc]; 2824 u8 allowed_list_size[0xc]; 2825 2826 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2827 2828 u8 reserved_10[0x20]; 2829 2830 u8 current_uc_mac_address[0][0x40]; 2831}; 2832 2833enum { 2834 MLX5_ACCESS_MODE_PA = 0x0, 2835 MLX5_ACCESS_MODE_MTT = 0x1, 2836 MLX5_ACCESS_MODE_KLM = 0x2, 2837 MLX5_ACCESS_MODE_KSM = 0x3, 2838 MLX5_ACCESS_MODE_SW_ICM = 0x4, 2839 MLX5_ACCESS_MODE_MEMIC = 0x5, 2840}; 2841 2842struct mlx5_ifc_mkc_bits { 2843 u8 reserved_at_0[0x1]; 2844 u8 free[0x1]; 2845 u8 reserved_at_2[0x1]; 2846 u8 access_mode_4_2[0x3]; 2847 u8 reserved_at_6[0x7]; 2848 u8 relaxed_ordering_write[0x1]; 2849 u8 reserved_at_e[0x1]; 2850 u8 small_fence_on_rdma_read_response[0x1]; 2851 u8 umr_en[0x1]; 2852 u8 a[0x1]; 2853 u8 rw[0x1]; 2854 u8 rr[0x1]; 2855 u8 lw[0x1]; 2856 u8 lr[0x1]; 2857 u8 access_mode[0x2]; 2858 u8 reserved_2[0x8]; 2859 2860 u8 qpn[0x18]; 2861 u8 mkey_7_0[0x8]; 2862 2863 u8 reserved_3[0x20]; 2864 2865 u8 length64[0x1]; 2866 u8 bsf_en[0x1]; 2867 u8 sync_umr[0x1]; 2868 u8 reserved_4[0x2]; 2869 u8 expected_sigerr_count[0x1]; 2870 u8 reserved_5[0x1]; 2871 u8 en_rinval[0x1]; 2872 u8 pd[0x18]; 2873 2874 u8 start_addr[0x40]; 2875 2876 u8 len[0x40]; 2877 2878 u8 bsf_octword_size[0x20]; 2879 2880 u8 reserved_6[0x80]; 2881 2882 u8 translations_octword_size[0x20]; 2883 2884 u8 reserved_at_1c0[0x19]; 2885 u8 relaxed_ordering_read[0x1]; 2886 u8 reserved_at_1d9[0x1]; 2887 u8 log_page_size[0x5]; 2888 2889 u8 reserved_8[0x20]; 2890}; 2891 2892struct mlx5_ifc_pkey_bits { 2893 u8 reserved_0[0x10]; 2894 u8 pkey[0x10]; 2895}; 2896 2897struct mlx5_ifc_array128_auto_bits { 2898 u8 array128_auto[16][0x8]; 2899}; 2900 2901enum { 2902 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID = 0x0, 2903 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID = 0x1, 2904 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY = 0x2, 2905}; 2906 2907enum { 2908 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP = 0x1, 2909 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING = 0x2, 2910 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED = 0x3, 2911 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING = 0x4, 2912 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP = 0x5, 2913 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY = 0x6, 2914 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST = 0x7, 2915}; 2916 2917enum { 2918 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN = 0x0, 2919 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP = 0x1, 2920 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW = 0x2, 2921}; 2922 2923enum { 2924 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN = 0x1, 2925 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT = 0x2, 2926 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM = 0x3, 2927 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE = 0x4, 2928}; 2929 2930enum { 2931 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN = 0x1, 2932 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT = 0x2, 2933 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM = 0x3, 2934 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE = 0x4, 2935}; 2936 2937struct mlx5_ifc_hca_vport_context_bits { 2938 u8 field_select[0x20]; 2939 2940 u8 reserved_0[0xe0]; 2941 2942 u8 sm_virt_aware[0x1]; 2943 u8 has_smi[0x1]; 2944 u8 has_raw[0x1]; 2945 u8 grh_required[0x1]; 2946 u8 reserved_1[0x1]; 2947 u8 min_wqe_inline_mode[0x3]; 2948 u8 reserved_2[0x8]; 2949 u8 port_physical_state[0x4]; 2950 u8 vport_state_policy[0x4]; 2951 u8 port_state[0x4]; 2952 u8 vport_state[0x4]; 2953 2954 u8 reserved_3[0x20]; 2955 2956 u8 system_image_guid[0x40]; 2957 2958 u8 port_guid[0x40]; 2959 2960 u8 node_guid[0x40]; 2961 2962 u8 cap_mask1[0x20]; 2963 2964 u8 cap_mask1_field_select[0x20]; 2965 2966 u8 cap_mask2[0x20]; 2967 2968 u8 cap_mask2_field_select[0x20]; 2969 2970 u8 reserved_4[0x80]; 2971 2972 u8 lid[0x10]; 2973 u8 reserved_5[0x4]; 2974 u8 init_type_reply[0x4]; 2975 u8 lmc[0x3]; 2976 u8 subnet_timeout[0x5]; 2977 2978 u8 sm_lid[0x10]; 2979 u8 sm_sl[0x4]; 2980 u8 reserved_6[0xc]; 2981 2982 u8 qkey_violation_counter[0x10]; 2983 u8 pkey_violation_counter[0x10]; 2984 2985 u8 reserved_7[0xca0]; 2986}; 2987 2988union mlx5_ifc_hca_cap_union_bits { 2989 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2990 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 2991 struct mlx5_ifc_odp_cap_bits odp_cap; 2992 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2993 struct mlx5_ifc_roce_cap_bits roce_cap; 2994 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2995 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2996 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2997 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2998 struct mlx5_ifc_snapshot_cap_bits snapshot_cap; 2999 struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap; 3000 struct mlx5_ifc_qos_cap_bits qos_cap; 3001 struct mlx5_ifc_tls_capabilities_bits tls_capabilities; 3002 u8 reserved_0[0x8000]; 3003}; 3004 3005enum { 3006 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0, 3007 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1, 3008}; 3009 3010struct mlx5_ifc_flow_table_context_bits { 3011 u8 reformat_en[0x1]; 3012 u8 decap_en[0x1]; 3013 u8 reserved_at_2[0x2]; 3014 u8 table_miss_action[0x4]; 3015 u8 level[0x8]; 3016 u8 reserved_at_10[0x8]; 3017 u8 log_size[0x8]; 3018 3019 u8 reserved_at_20[0x8]; 3020 u8 table_miss_id[0x18]; 3021 3022 u8 reserved_at_40[0x8]; 3023 u8 lag_master_next_table_id[0x18]; 3024 3025 u8 reserved_at_60[0xe0]; 3026}; 3027 3028struct mlx5_ifc_esw_vport_context_bits { 3029 u8 reserved_0[0x3]; 3030 u8 vport_svlan_strip[0x1]; 3031 u8 vport_cvlan_strip[0x1]; 3032 u8 vport_svlan_insert[0x1]; 3033 u8 vport_cvlan_insert[0x2]; 3034 u8 reserved_1[0x18]; 3035 3036 u8 reserved_2[0x20]; 3037 3038 u8 svlan_cfi[0x1]; 3039 u8 svlan_pcp[0x3]; 3040 u8 svlan_id[0xc]; 3041 u8 cvlan_cfi[0x1]; 3042 u8 cvlan_pcp[0x3]; 3043 u8 cvlan_id[0xc]; 3044 3045 u8 reserved_3[0x7a0]; 3046}; 3047 3048enum { 3049 MLX5_EQC_STATUS_OK = 0x0, 3050 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3051}; 3052 3053enum { 3054 MLX5_EQ_STATE_ARMED = 0x9, 3055 MLX5_EQ_STATE_FIRED = 0xa, 3056}; 3057 3058struct mlx5_ifc_eqc_bits { 3059 u8 status[0x4]; 3060 u8 reserved_0[0x9]; 3061 u8 ec[0x1]; 3062 u8 oi[0x1]; 3063 u8 reserved_1[0x5]; 3064 u8 st[0x4]; 3065 u8 reserved_2[0x8]; 3066 3067 u8 reserved_3[0x20]; 3068 3069 u8 reserved_4[0x14]; 3070 u8 page_offset[0x6]; 3071 u8 reserved_5[0x6]; 3072 3073 u8 reserved_6[0x3]; 3074 u8 log_eq_size[0x5]; 3075 u8 uar_page[0x18]; 3076 3077 u8 reserved_7[0x20]; 3078 3079 u8 reserved_8[0x18]; 3080 u8 intr[0x8]; 3081 3082 u8 reserved_9[0x3]; 3083 u8 log_page_size[0x5]; 3084 u8 reserved_10[0x18]; 3085 3086 u8 reserved_11[0x60]; 3087 3088 u8 reserved_12[0x8]; 3089 u8 consumer_counter[0x18]; 3090 3091 u8 reserved_13[0x8]; 3092 u8 producer_counter[0x18]; 3093 3094 u8 reserved_14[0x80]; 3095}; 3096 3097enum { 3098 MLX5_DCTC_STATE_ACTIVE = 0x0, 3099 MLX5_DCTC_STATE_DRAINING = 0x1, 3100 MLX5_DCTC_STATE_DRAINED = 0x2, 3101}; 3102 3103enum { 3104 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3105 MLX5_DCTC_CS_RES_NA = 0x1, 3106 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3107}; 3108 3109enum { 3110 MLX5_DCTC_MTU_256_BYTES = 0x1, 3111 MLX5_DCTC_MTU_512_BYTES = 0x2, 3112 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3113 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3114 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3115}; 3116 3117struct mlx5_ifc_dctc_bits { 3118 u8 reserved_0[0x4]; 3119 u8 state[0x4]; 3120 u8 reserved_1[0x18]; 3121 3122 u8 reserved_2[0x8]; 3123 u8 user_index[0x18]; 3124 3125 u8 reserved_3[0x8]; 3126 u8 cqn[0x18]; 3127 3128 u8 counter_set_id[0x8]; 3129 u8 atomic_mode[0x4]; 3130 u8 rre[0x1]; 3131 u8 rwe[0x1]; 3132 u8 rae[0x1]; 3133 u8 atomic_like_write_en[0x1]; 3134 u8 latency_sensitive[0x1]; 3135 u8 rlky[0x1]; 3136 u8 reserved_4[0xe]; 3137 3138 u8 reserved_5[0x8]; 3139 u8 cs_res[0x8]; 3140 u8 reserved_6[0x3]; 3141 u8 min_rnr_nak[0x5]; 3142 u8 reserved_7[0x8]; 3143 3144 u8 reserved_8[0x8]; 3145 u8 srqn[0x18]; 3146 3147 u8 reserved_9[0x8]; 3148 u8 pd[0x18]; 3149 3150 u8 tclass[0x8]; 3151 u8 reserved_10[0x4]; 3152 u8 flow_label[0x14]; 3153 3154 u8 dc_access_key[0x40]; 3155 3156 u8 reserved_11[0x5]; 3157 u8 mtu[0x3]; 3158 u8 port[0x8]; 3159 u8 pkey_index[0x10]; 3160 3161 u8 reserved_12[0x8]; 3162 u8 my_addr_index[0x8]; 3163 u8 reserved_13[0x8]; 3164 u8 hop_limit[0x8]; 3165 3166 u8 dc_access_key_violation_count[0x20]; 3167 3168 u8 reserved_14[0x14]; 3169 u8 dei_cfi[0x1]; 3170 u8 eth_prio[0x3]; 3171 u8 ecn[0x2]; 3172 u8 dscp[0x6]; 3173 3174 u8 reserved_15[0x40]; 3175}; 3176 3177enum { 3178 MLX5_CQC_STATUS_OK = 0x0, 3179 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3180 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3181}; 3182 3183enum { 3184 CQE_SIZE_64 = 0x0, 3185 CQE_SIZE_128 = 0x1, 3186}; 3187 3188enum { 3189 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3190 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3191}; 3192 3193enum { 3194 MLX5_CQ_STATE_SOLICITED_ARMED = 0x6, 3195 MLX5_CQ_STATE_ARMED = 0x9, 3196 MLX5_CQ_STATE_FIRED = 0xa, 3197}; 3198 3199struct mlx5_ifc_cqc_bits { 3200 u8 status[0x4]; 3201 u8 reserved_at_4[0x2]; 3202 u8 dbr_umem_valid[0x1]; 3203 u8 reserved_at_7[0x1]; 3204 u8 cqe_sz[0x3]; 3205 u8 cc[0x1]; 3206 u8 reserved_1[0x1]; 3207 u8 scqe_break_moderation_en[0x1]; 3208 u8 oi[0x1]; 3209 u8 cq_period_mode[0x2]; 3210 u8 cqe_compression_en[0x1]; 3211 u8 mini_cqe_res_format[0x2]; 3212 u8 st[0x4]; 3213 u8 reserved_2[0x8]; 3214 3215 u8 reserved_3[0x20]; 3216 3217 u8 reserved_4[0x14]; 3218 u8 page_offset[0x6]; 3219 u8 reserved_5[0x6]; 3220 3221 u8 reserved_6[0x3]; 3222 u8 log_cq_size[0x5]; 3223 u8 uar_page[0x18]; 3224 3225 u8 reserved_7[0x4]; 3226 u8 cq_period[0xc]; 3227 u8 cq_max_count[0x10]; 3228 3229 u8 reserved_8[0x18]; 3230 u8 c_eqn[0x8]; 3231 3232 u8 reserved_9[0x3]; 3233 u8 log_page_size[0x5]; 3234 u8 reserved_10[0x18]; 3235 3236 u8 reserved_11[0x20]; 3237 3238 u8 reserved_12[0x8]; 3239 u8 last_notified_index[0x18]; 3240 3241 u8 reserved_13[0x8]; 3242 u8 last_solicit_index[0x18]; 3243 3244 u8 reserved_14[0x8]; 3245 u8 consumer_counter[0x18]; 3246 3247 u8 reserved_15[0x8]; 3248 u8 producer_counter[0x18]; 3249 3250 u8 reserved_16[0x40]; 3251 3252 u8 dbr_addr[0x40]; 3253}; 3254 3255union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3256 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3257 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3258 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3259 u8 reserved_0[0x800]; 3260}; 3261 3262struct mlx5_ifc_query_adapter_param_block_bits { 3263 u8 reserved_0[0xc0]; 3264 3265 u8 reserved_1[0x8]; 3266 u8 ieee_vendor_id[0x18]; 3267 3268 u8 reserved_2[0x10]; 3269 u8 vsd_vendor_id[0x10]; 3270 3271 u8 vsd[208][0x8]; 3272 3273 u8 vsd_contd_psid[16][0x8]; 3274}; 3275 3276union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3277 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3278 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3279 u8 reserved_0[0x20]; 3280}; 3281 3282union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3283 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3284 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3285 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3286 u8 reserved_0[0x20]; 3287}; 3288 3289struct mlx5_ifc_bufferx_reg_bits { 3290 u8 reserved_0[0x6]; 3291 u8 lossy[0x1]; 3292 u8 epsb[0x1]; 3293 u8 reserved_1[0xc]; 3294 u8 size[0xc]; 3295 3296 u8 xoff_threshold[0x10]; 3297 u8 xon_threshold[0x10]; 3298}; 3299 3300struct mlx5_ifc_config_item_bits { 3301 u8 valid[0x2]; 3302 u8 reserved_0[0x2]; 3303 u8 header_type[0x2]; 3304 u8 reserved_1[0x2]; 3305 u8 default_location[0x1]; 3306 u8 reserved_2[0x7]; 3307 u8 version[0x4]; 3308 u8 reserved_3[0x3]; 3309 u8 length[0x9]; 3310 3311 u8 type[0x20]; 3312 3313 u8 reserved_4[0x10]; 3314 u8 crc16[0x10]; 3315}; 3316 3317enum { 3318 MLX5_XRQC_STATE_GOOD = 0x0, 3319 MLX5_XRQC_STATE_ERROR = 0x1, 3320}; 3321 3322enum { 3323 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3324 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3325}; 3326 3327enum { 3328 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3329}; 3330 3331struct mlx5_ifc_tag_matching_topology_context_bits { 3332 u8 log_matching_list_sz[0x4]; 3333 u8 reserved_at_4[0xc]; 3334 u8 append_next_index[0x10]; 3335 3336 u8 sw_phase_cnt[0x10]; 3337 u8 hw_phase_cnt[0x10]; 3338 3339 u8 reserved_at_40[0x40]; 3340}; 3341 3342struct mlx5_ifc_xrqc_bits { 3343 u8 state[0x4]; 3344 u8 rlkey[0x1]; 3345 u8 reserved_at_5[0xf]; 3346 u8 topology[0x4]; 3347 u8 reserved_at_18[0x4]; 3348 u8 offload[0x4]; 3349 3350 u8 reserved_at_20[0x8]; 3351 u8 user_index[0x18]; 3352 3353 u8 reserved_at_40[0x8]; 3354 u8 cqn[0x18]; 3355 3356 u8 reserved_at_60[0xa0]; 3357 3358 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3359 3360 u8 reserved_at_180[0x280]; 3361 3362 struct mlx5_ifc_wq_bits wq; 3363}; 3364 3365struct mlx5_ifc_nodnic_port_config_reg_bits { 3366 struct mlx5_ifc_nodnic_event_word_bits event; 3367 3368 u8 network_en[0x1]; 3369 u8 dma_en[0x1]; 3370 u8 promisc_en[0x1]; 3371 u8 promisc_multicast_en[0x1]; 3372 u8 reserved_0[0x17]; 3373 u8 receive_filter_en[0x5]; 3374 3375 u8 reserved_1[0x10]; 3376 u8 mac_47_32[0x10]; 3377 3378 u8 mac_31_0[0x20]; 3379 3380 u8 receive_filters_mgid_mac[64][0x8]; 3381 3382 u8 gid[16][0x8]; 3383 3384 u8 reserved_2[0x10]; 3385 u8 lid[0x10]; 3386 3387 u8 reserved_3[0xc]; 3388 u8 sm_sl[0x4]; 3389 u8 sm_lid[0x10]; 3390 3391 u8 completion_address_63_32[0x20]; 3392 3393 u8 completion_address_31_12[0x14]; 3394 u8 reserved_4[0x6]; 3395 u8 log_cq_size[0x6]; 3396 3397 u8 working_buffer_address_63_32[0x20]; 3398 3399 u8 working_buffer_address_31_12[0x14]; 3400 u8 reserved_5[0xc]; 3401 3402 struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq; 3403 3404 u8 pkey_index[0x10]; 3405 u8 pkey[0x10]; 3406 3407 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0; 3408 3409 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1; 3410 3411 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0; 3412 3413 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1; 3414 3415 u8 reserved_6[0x400]; 3416}; 3417 3418union mlx5_ifc_event_auto_bits { 3419 struct mlx5_ifc_comp_event_bits comp_event; 3420 struct mlx5_ifc_dct_events_bits dct_events; 3421 struct mlx5_ifc_qp_events_bits qp_events; 3422 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3423 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3424 struct mlx5_ifc_cq_error_bits cq_error; 3425 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3426 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3427 struct mlx5_ifc_gpio_event_bits gpio_event; 3428 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3429 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3430 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3431 struct mlx5_ifc_pages_req_event_bits pages_req_event; 3432 struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event; 3433 u8 reserved_0[0xe0]; 3434}; 3435 3436struct mlx5_ifc_health_buffer_bits { 3437 u8 reserved_0[0x100]; 3438 3439 u8 assert_existptr[0x20]; 3440 3441 u8 assert_callra[0x20]; 3442 3443 u8 reserved_1[0x40]; 3444 3445 u8 fw_version[0x20]; 3446 3447 u8 hw_id[0x20]; 3448 3449 u8 reserved_2[0x20]; 3450 3451 u8 irisc_index[0x8]; 3452 u8 synd[0x8]; 3453 u8 ext_synd[0x10]; 3454}; 3455 3456struct mlx5_ifc_register_loopback_control_bits { 3457 u8 no_lb[0x1]; 3458 u8 reserved_0[0x7]; 3459 u8 port[0x8]; 3460 u8 reserved_1[0x10]; 3461 3462 u8 reserved_2[0x60]; 3463}; 3464 3465struct mlx5_ifc_lrh_bits { 3466 u8 vl[4]; 3467 u8 lver[4]; 3468 u8 sl[4]; 3469 u8 reserved2[2]; 3470 u8 lnh[2]; 3471 u8 dlid[16]; 3472 u8 reserved5[5]; 3473 u8 pkt_len[11]; 3474 u8 slid[16]; 3475}; 3476 3477struct mlx5_ifc_icmd_set_wol_rol_out_bits { 3478 u8 reserved_0[0x40]; 3479 3480 u8 reserved_1[0x10]; 3481 u8 rol_mode[0x8]; 3482 u8 wol_mode[0x8]; 3483}; 3484 3485struct mlx5_ifc_icmd_set_wol_rol_in_bits { 3486 u8 reserved_0[0x40]; 3487 3488 u8 rol_mode_valid[0x1]; 3489 u8 wol_mode_valid[0x1]; 3490 u8 reserved_1[0xe]; 3491 u8 rol_mode[0x8]; 3492 u8 wol_mode[0x8]; 3493 3494 u8 reserved_2[0x7a0]; 3495}; 3496 3497struct mlx5_ifc_icmd_set_virtual_mac_in_bits { 3498 u8 virtual_mac_en[0x1]; 3499 u8 mac_aux_v[0x1]; 3500 u8 reserved_0[0x1e]; 3501 3502 u8 reserved_1[0x40]; 3503 3504 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3505 3506 u8 reserved_2[0x760]; 3507}; 3508 3509struct mlx5_ifc_icmd_query_virtual_mac_out_bits { 3510 u8 virtual_mac_en[0x1]; 3511 u8 mac_aux_v[0x1]; 3512 u8 reserved_0[0x1e]; 3513 3514 struct mlx5_ifc_mac_address_layout_bits permanent_mac; 3515 3516 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3517 3518 u8 reserved_1[0x760]; 3519}; 3520 3521struct mlx5_ifc_icmd_query_fw_info_out_bits { 3522 struct mlx5_ifc_fw_version_bits fw_version; 3523 3524 u8 reserved_0[0x10]; 3525 u8 hash_signature[0x10]; 3526 3527 u8 psid[16][0x8]; 3528 3529 u8 reserved_1[0x6e0]; 3530}; 3531 3532struct mlx5_ifc_icmd_query_cap_in_bits { 3533 u8 reserved_0[0x10]; 3534 u8 capability_group[0x10]; 3535}; 3536 3537struct mlx5_ifc_icmd_query_cap_general_bits { 3538 u8 nv_access[0x1]; 3539 u8 fw_info_psid[0x1]; 3540 u8 reserved_0[0x1e]; 3541 3542 u8 reserved_1[0x16]; 3543 u8 rol_s[0x1]; 3544 u8 rol_g[0x1]; 3545 u8 reserved_2[0x1]; 3546 u8 wol_s[0x1]; 3547 u8 wol_g[0x1]; 3548 u8 wol_a[0x1]; 3549 u8 wol_b[0x1]; 3550 u8 wol_m[0x1]; 3551 u8 wol_u[0x1]; 3552 u8 wol_p[0x1]; 3553}; 3554 3555struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits { 3556 u8 status[0x8]; 3557 u8 reserved_0[0x18]; 3558 3559 u8 reserved_1[0x7e0]; 3560}; 3561 3562struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits { 3563 u8 status[0x8]; 3564 u8 reserved_0[0x18]; 3565 3566 u8 reserved_1[0x7e0]; 3567}; 3568 3569struct mlx5_ifc_icmd_ocbb_init_in_bits { 3570 u8 address_hi[0x20]; 3571 3572 u8 address_lo[0x20]; 3573 3574 u8 reserved_0[0x7c0]; 3575}; 3576 3577struct mlx5_ifc_icmd_init_ocsd_in_bits { 3578 u8 reserved_0[0x20]; 3579 3580 u8 address_hi[0x20]; 3581 3582 u8 address_lo[0x20]; 3583 3584 u8 reserved_1[0x7a0]; 3585}; 3586 3587struct mlx5_ifc_icmd_access_reg_out_bits { 3588 u8 reserved_0[0x11]; 3589 u8 status[0x7]; 3590 u8 reserved_1[0x8]; 3591 3592 u8 register_id[0x10]; 3593 u8 reserved_2[0x10]; 3594 3595 u8 reserved_3[0x40]; 3596 3597 u8 reserved_4[0x5]; 3598 u8 len[0xb]; 3599 u8 reserved_5[0x10]; 3600 3601 u8 register_data[0][0x20]; 3602}; 3603 3604enum { 3605 MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY = 0x1, 3606 MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE = 0x2, 3607}; 3608 3609struct mlx5_ifc_icmd_access_reg_in_bits { 3610 u8 constant_1[0x5]; 3611 u8 constant_2[0xb]; 3612 u8 reserved_0[0x10]; 3613 3614 u8 register_id[0x10]; 3615 u8 reserved_1[0x1]; 3616 u8 method[0x7]; 3617 u8 constant_3[0x8]; 3618 3619 u8 reserved_2[0x40]; 3620 3621 u8 constant_4[0x5]; 3622 u8 len[0xb]; 3623 u8 reserved_3[0x10]; 3624 3625 u8 register_data[0][0x20]; 3626}; 3627 3628enum { 3629 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3630 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3631}; 3632 3633struct mlx5_ifc_teardown_hca_out_bits { 3634 u8 status[0x8]; 3635 u8 reserved_0[0x18]; 3636 3637 u8 syndrome[0x20]; 3638 3639 u8 reserved_1[0x3f]; 3640 3641 u8 state[0x1]; 3642}; 3643 3644enum { 3645 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3646 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3647 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3648}; 3649 3650struct mlx5_ifc_teardown_hca_in_bits { 3651 u8 opcode[0x10]; 3652 u8 reserved_0[0x10]; 3653 3654 u8 reserved_1[0x10]; 3655 u8 op_mod[0x10]; 3656 3657 u8 reserved_2[0x10]; 3658 u8 profile[0x10]; 3659 3660 u8 reserved_3[0x20]; 3661}; 3662 3663struct mlx5_ifc_set_delay_drop_params_out_bits { 3664 u8 status[0x8]; 3665 u8 reserved_at_8[0x18]; 3666 3667 u8 syndrome[0x20]; 3668 3669 u8 reserved_at_40[0x40]; 3670}; 3671 3672struct mlx5_ifc_set_delay_drop_params_in_bits { 3673 u8 opcode[0x10]; 3674 u8 reserved_at_10[0x10]; 3675 3676 u8 reserved_at_20[0x10]; 3677 u8 op_mod[0x10]; 3678 3679 u8 reserved_at_40[0x20]; 3680 3681 u8 reserved_at_60[0x10]; 3682 u8 delay_drop_timeout[0x10]; 3683}; 3684 3685struct mlx5_ifc_query_delay_drop_params_out_bits { 3686 u8 status[0x8]; 3687 u8 reserved_at_8[0x18]; 3688 3689 u8 syndrome[0x20]; 3690 3691 u8 reserved_at_40[0x20]; 3692 3693 u8 reserved_at_60[0x10]; 3694 u8 delay_drop_timeout[0x10]; 3695}; 3696 3697struct mlx5_ifc_query_delay_drop_params_in_bits { 3698 u8 opcode[0x10]; 3699 u8 reserved_at_10[0x10]; 3700 3701 u8 reserved_at_20[0x10]; 3702 u8 op_mod[0x10]; 3703 3704 u8 reserved_at_40[0x40]; 3705}; 3706 3707struct mlx5_ifc_suspend_qp_out_bits { 3708 u8 status[0x8]; 3709 u8 reserved_0[0x18]; 3710 3711 u8 syndrome[0x20]; 3712 3713 u8 reserved_1[0x40]; 3714}; 3715 3716struct mlx5_ifc_suspend_qp_in_bits { 3717 u8 opcode[0x10]; 3718 u8 reserved_0[0x10]; 3719 3720 u8 reserved_1[0x10]; 3721 u8 op_mod[0x10]; 3722 3723 u8 reserved_2[0x8]; 3724 u8 qpn[0x18]; 3725 3726 u8 reserved_3[0x20]; 3727}; 3728 3729struct mlx5_ifc_sqerr2rts_qp_out_bits { 3730 u8 status[0x8]; 3731 u8 reserved_0[0x18]; 3732 3733 u8 syndrome[0x20]; 3734 3735 u8 reserved_1[0x40]; 3736}; 3737 3738struct mlx5_ifc_sqerr2rts_qp_in_bits { 3739 u8 opcode[0x10]; 3740 u8 uid[0x10]; 3741 3742 u8 reserved_1[0x10]; 3743 u8 op_mod[0x10]; 3744 3745 u8 reserved_2[0x8]; 3746 u8 qpn[0x18]; 3747 3748 u8 reserved_3[0x20]; 3749 3750 u8 opt_param_mask[0x20]; 3751 3752 u8 reserved_4[0x20]; 3753 3754 struct mlx5_ifc_qpc_bits qpc; 3755 3756 u8 reserved_5[0x80]; 3757}; 3758 3759struct mlx5_ifc_sqd2rts_qp_out_bits { 3760 u8 status[0x8]; 3761 u8 reserved_0[0x18]; 3762 3763 u8 syndrome[0x20]; 3764 3765 u8 reserved_1[0x40]; 3766}; 3767 3768struct mlx5_ifc_sqd2rts_qp_in_bits { 3769 u8 opcode[0x10]; 3770 u8 uid[0x10]; 3771 3772 u8 reserved_1[0x10]; 3773 u8 op_mod[0x10]; 3774 3775 u8 reserved_2[0x8]; 3776 u8 qpn[0x18]; 3777 3778 u8 reserved_3[0x20]; 3779 3780 u8 opt_param_mask[0x20]; 3781 3782 u8 reserved_4[0x20]; 3783 3784 struct mlx5_ifc_qpc_bits qpc; 3785 3786 u8 reserved_5[0x80]; 3787}; 3788 3789struct mlx5_ifc_set_wol_rol_out_bits { 3790 u8 status[0x8]; 3791 u8 reserved_0[0x18]; 3792 3793 u8 syndrome[0x20]; 3794 3795 u8 reserved_1[0x40]; 3796}; 3797 3798struct mlx5_ifc_set_wol_rol_in_bits { 3799 u8 opcode[0x10]; 3800 u8 reserved_0[0x10]; 3801 3802 u8 reserved_1[0x10]; 3803 u8 op_mod[0x10]; 3804 3805 u8 rol_mode_valid[0x1]; 3806 u8 wol_mode_valid[0x1]; 3807 u8 reserved_2[0xe]; 3808 u8 rol_mode[0x8]; 3809 u8 wol_mode[0x8]; 3810 3811 u8 reserved_3[0x20]; 3812}; 3813 3814struct mlx5_ifc_set_roce_address_out_bits { 3815 u8 status[0x8]; 3816 u8 reserved_0[0x18]; 3817 3818 u8 syndrome[0x20]; 3819 3820 u8 reserved_1[0x40]; 3821}; 3822 3823struct mlx5_ifc_set_roce_address_in_bits { 3824 u8 opcode[0x10]; 3825 u8 reserved_0[0x10]; 3826 3827 u8 reserved_1[0x10]; 3828 u8 op_mod[0x10]; 3829 3830 u8 roce_address_index[0x10]; 3831 u8 reserved_2[0x10]; 3832 3833 u8 reserved_3[0x20]; 3834 3835 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3836}; 3837 3838struct mlx5_ifc_set_rdb_out_bits { 3839 u8 status[0x8]; 3840 u8 reserved_0[0x18]; 3841 3842 u8 syndrome[0x20]; 3843 3844 u8 reserved_1[0x40]; 3845}; 3846 3847struct mlx5_ifc_set_rdb_in_bits { 3848 u8 opcode[0x10]; 3849 u8 reserved_0[0x10]; 3850 3851 u8 reserved_1[0x10]; 3852 u8 op_mod[0x10]; 3853 3854 u8 reserved_2[0x8]; 3855 u8 qpn[0x18]; 3856 3857 u8 reserved_3[0x18]; 3858 u8 rdb_list_size[0x8]; 3859 3860 struct mlx5_ifc_rdbc_bits rdb_context[0]; 3861}; 3862 3863struct mlx5_ifc_set_mad_demux_out_bits { 3864 u8 status[0x8]; 3865 u8 reserved_0[0x18]; 3866 3867 u8 syndrome[0x20]; 3868 3869 u8 reserved_1[0x40]; 3870}; 3871 3872enum { 3873 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3874 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3875}; 3876 3877struct mlx5_ifc_set_mad_demux_in_bits { 3878 u8 opcode[0x10]; 3879 u8 reserved_0[0x10]; 3880 3881 u8 reserved_1[0x10]; 3882 u8 op_mod[0x10]; 3883 3884 u8 reserved_2[0x20]; 3885 3886 u8 reserved_3[0x6]; 3887 u8 demux_mode[0x2]; 3888 u8 reserved_4[0x18]; 3889}; 3890 3891struct mlx5_ifc_set_l2_table_entry_out_bits { 3892 u8 status[0x8]; 3893 u8 reserved_0[0x18]; 3894 3895 u8 syndrome[0x20]; 3896 3897 u8 reserved_1[0x40]; 3898}; 3899 3900struct mlx5_ifc_set_l2_table_entry_in_bits { 3901 u8 opcode[0x10]; 3902 u8 reserved_0[0x10]; 3903 3904 u8 reserved_1[0x10]; 3905 u8 op_mod[0x10]; 3906 3907 u8 reserved_2[0x60]; 3908 3909 u8 reserved_3[0x8]; 3910 u8 table_index[0x18]; 3911 3912 u8 reserved_4[0x20]; 3913 3914 u8 reserved_5[0x13]; 3915 u8 vlan_valid[0x1]; 3916 u8 vlan[0xc]; 3917 3918 struct mlx5_ifc_mac_address_layout_bits mac_address; 3919 3920 u8 reserved_6[0xc0]; 3921}; 3922 3923struct mlx5_ifc_set_issi_out_bits { 3924 u8 status[0x8]; 3925 u8 reserved_0[0x18]; 3926 3927 u8 syndrome[0x20]; 3928 3929 u8 reserved_1[0x40]; 3930}; 3931 3932struct mlx5_ifc_set_issi_in_bits { 3933 u8 opcode[0x10]; 3934 u8 reserved_0[0x10]; 3935 3936 u8 reserved_1[0x10]; 3937 u8 op_mod[0x10]; 3938 3939 u8 reserved_2[0x10]; 3940 u8 current_issi[0x10]; 3941 3942 u8 reserved_3[0x20]; 3943}; 3944 3945struct mlx5_ifc_set_hca_cap_out_bits { 3946 u8 status[0x8]; 3947 u8 reserved_0[0x18]; 3948 3949 u8 syndrome[0x20]; 3950 3951 u8 reserved_1[0x40]; 3952}; 3953 3954struct mlx5_ifc_set_hca_cap_in_bits { 3955 u8 opcode[0x10]; 3956 u8 reserved_0[0x10]; 3957 3958 u8 reserved_1[0x10]; 3959 u8 op_mod[0x10]; 3960 3961 u8 reserved_2[0x40]; 3962 3963 union mlx5_ifc_hca_cap_union_bits capability; 3964}; 3965 3966enum { 3967 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3968 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3969 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3970 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3971}; 3972 3973struct mlx5_ifc_set_flow_table_root_out_bits { 3974 u8 status[0x8]; 3975 u8 reserved_0[0x18]; 3976 3977 u8 syndrome[0x20]; 3978 3979 u8 reserved_1[0x40]; 3980}; 3981 3982struct mlx5_ifc_set_flow_table_root_in_bits { 3983 u8 opcode[0x10]; 3984 u8 reserved_0[0x10]; 3985 3986 u8 reserved_1[0x10]; 3987 u8 op_mod[0x10]; 3988 3989 u8 other_vport[0x1]; 3990 u8 reserved_2[0xf]; 3991 u8 vport_number[0x10]; 3992 3993 u8 reserved_3[0x20]; 3994 3995 u8 table_type[0x8]; 3996 u8 reserved_4[0x18]; 3997 3998 u8 reserved_5[0x8]; 3999 u8 table_id[0x18]; 4000 4001 u8 reserved_6[0x8]; 4002 u8 underlay_qpn[0x18]; 4003 4004 u8 reserved_7[0x120]; 4005}; 4006 4007struct mlx5_ifc_set_fte_out_bits { 4008 u8 status[0x8]; 4009 u8 reserved_0[0x18]; 4010 4011 u8 syndrome[0x20]; 4012 4013 u8 reserved_1[0x40]; 4014}; 4015 4016struct mlx5_ifc_set_fte_in_bits { 4017 u8 opcode[0x10]; 4018 u8 reserved_0[0x10]; 4019 4020 u8 reserved_1[0x10]; 4021 u8 op_mod[0x10]; 4022 4023 u8 other_vport[0x1]; 4024 u8 reserved_2[0xf]; 4025 u8 vport_number[0x10]; 4026 4027 u8 reserved_3[0x20]; 4028 4029 u8 table_type[0x8]; 4030 u8 reserved_4[0x18]; 4031 4032 u8 reserved_5[0x8]; 4033 u8 table_id[0x18]; 4034 4035 u8 reserved_6[0x18]; 4036 u8 modify_enable_mask[0x8]; 4037 4038 u8 reserved_7[0x20]; 4039 4040 u8 flow_index[0x20]; 4041 4042 u8 reserved_8[0xe0]; 4043 4044 struct mlx5_ifc_flow_context_bits flow_context; 4045}; 4046 4047struct mlx5_ifc_set_driver_version_out_bits { 4048 u8 status[0x8]; 4049 u8 reserved_0[0x18]; 4050 4051 u8 syndrome[0x20]; 4052 4053 u8 reserved_1[0x40]; 4054}; 4055 4056struct mlx5_ifc_set_driver_version_in_bits { 4057 u8 opcode[0x10]; 4058 u8 reserved_0[0x10]; 4059 4060 u8 reserved_1[0x10]; 4061 u8 op_mod[0x10]; 4062 4063 u8 reserved_2[0x40]; 4064 4065 u8 driver_version[64][0x8]; 4066}; 4067 4068struct mlx5_ifc_set_dc_cnak_trace_out_bits { 4069 u8 status[0x8]; 4070 u8 reserved_0[0x18]; 4071 4072 u8 syndrome[0x20]; 4073 4074 u8 reserved_1[0x40]; 4075}; 4076 4077struct mlx5_ifc_set_dc_cnak_trace_in_bits { 4078 u8 opcode[0x10]; 4079 u8 reserved_0[0x10]; 4080 4081 u8 reserved_1[0x10]; 4082 u8 op_mod[0x10]; 4083 4084 u8 enable[0x1]; 4085 u8 reserved_2[0x1f]; 4086 4087 u8 reserved_3[0x160]; 4088 4089 struct mlx5_ifc_cmd_pas_bits pas; 4090}; 4091 4092struct mlx5_ifc_set_burst_size_out_bits { 4093 u8 status[0x8]; 4094 u8 reserved_0[0x18]; 4095 4096 u8 syndrome[0x20]; 4097 4098 u8 reserved_1[0x40]; 4099}; 4100 4101struct mlx5_ifc_set_burst_size_in_bits { 4102 u8 opcode[0x10]; 4103 u8 reserved_0[0x10]; 4104 4105 u8 reserved_1[0x10]; 4106 u8 op_mod[0x10]; 4107 4108 u8 reserved_2[0x20]; 4109 4110 u8 reserved_3[0x9]; 4111 u8 device_burst_size[0x17]; 4112}; 4113 4114struct mlx5_ifc_rts2rts_qp_out_bits { 4115 u8 status[0x8]; 4116 u8 reserved_0[0x18]; 4117 4118 u8 syndrome[0x20]; 4119 4120 u8 reserved_1[0x40]; 4121}; 4122 4123struct mlx5_ifc_rts2rts_qp_in_bits { 4124 u8 opcode[0x10]; 4125 u8 uid[0x10]; 4126 4127 u8 reserved_1[0x10]; 4128 u8 op_mod[0x10]; 4129 4130 u8 reserved_2[0x8]; 4131 u8 qpn[0x18]; 4132 4133 u8 reserved_3[0x20]; 4134 4135 u8 opt_param_mask[0x20]; 4136 4137 u8 reserved_4[0x20]; 4138 4139 struct mlx5_ifc_qpc_bits qpc; 4140 4141 u8 reserved_5[0x80]; 4142}; 4143 4144struct mlx5_ifc_rtr2rts_qp_out_bits { 4145 u8 status[0x8]; 4146 u8 reserved_0[0x18]; 4147 4148 u8 syndrome[0x20]; 4149 4150 u8 reserved_1[0x40]; 4151}; 4152 4153struct mlx5_ifc_rtr2rts_qp_in_bits { 4154 u8 opcode[0x10]; 4155 u8 uid[0x10]; 4156 4157 u8 reserved_1[0x10]; 4158 u8 op_mod[0x10]; 4159 4160 u8 reserved_2[0x8]; 4161 u8 qpn[0x18]; 4162 4163 u8 reserved_3[0x20]; 4164 4165 u8 opt_param_mask[0x20]; 4166 4167 u8 reserved_4[0x20]; 4168 4169 struct mlx5_ifc_qpc_bits qpc; 4170 4171 u8 reserved_5[0x80]; 4172}; 4173 4174struct mlx5_ifc_rst2init_qp_out_bits { 4175 u8 status[0x8]; 4176 u8 reserved_0[0x18]; 4177 4178 u8 syndrome[0x20]; 4179 4180 u8 reserved_1[0x40]; 4181}; 4182 4183struct mlx5_ifc_rst2init_qp_in_bits { 4184 u8 opcode[0x10]; 4185 u8 uid[0x10]; 4186 4187 u8 reserved_1[0x10]; 4188 u8 op_mod[0x10]; 4189 4190 u8 reserved_2[0x8]; 4191 u8 qpn[0x18]; 4192 4193 u8 reserved_3[0x20]; 4194 4195 u8 opt_param_mask[0x20]; 4196 4197 u8 reserved_4[0x20]; 4198 4199 struct mlx5_ifc_qpc_bits qpc; 4200 4201 u8 reserved_5[0x80]; 4202}; 4203 4204struct mlx5_ifc_query_xrq_out_bits { 4205 u8 status[0x8]; 4206 u8 reserved_at_8[0x18]; 4207 4208 u8 syndrome[0x20]; 4209 4210 u8 reserved_at_40[0x40]; 4211 4212 struct mlx5_ifc_xrqc_bits xrq_context; 4213}; 4214 4215struct mlx5_ifc_query_xrq_in_bits { 4216 u8 opcode[0x10]; 4217 u8 reserved_at_10[0x10]; 4218 4219 u8 reserved_at_20[0x10]; 4220 u8 op_mod[0x10]; 4221 4222 u8 reserved_at_40[0x8]; 4223 u8 xrqn[0x18]; 4224 4225 u8 reserved_at_60[0x20]; 4226}; 4227 4228struct mlx5_ifc_resume_qp_out_bits { 4229 u8 status[0x8]; 4230 u8 reserved_0[0x18]; 4231 4232 u8 syndrome[0x20]; 4233 4234 u8 reserved_1[0x40]; 4235}; 4236 4237struct mlx5_ifc_resume_qp_in_bits { 4238 u8 opcode[0x10]; 4239 u8 reserved_0[0x10]; 4240 4241 u8 reserved_1[0x10]; 4242 u8 op_mod[0x10]; 4243 4244 u8 reserved_2[0x8]; 4245 u8 qpn[0x18]; 4246 4247 u8 reserved_3[0x20]; 4248}; 4249 4250struct mlx5_ifc_query_xrc_srq_out_bits { 4251 u8 status[0x8]; 4252 u8 reserved_0[0x18]; 4253 4254 u8 syndrome[0x20]; 4255 4256 u8 reserved_1[0x40]; 4257 4258 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4259 4260 u8 reserved_2[0x600]; 4261 4262 u8 pas[0][0x40]; 4263}; 4264 4265struct mlx5_ifc_query_xrc_srq_in_bits { 4266 u8 opcode[0x10]; 4267 u8 uid[0x10]; 4268 4269 u8 reserved_1[0x10]; 4270 u8 op_mod[0x10]; 4271 4272 u8 reserved_2[0x8]; 4273 u8 xrc_srqn[0x18]; 4274 4275 u8 reserved_3[0x20]; 4276}; 4277 4278struct mlx5_ifc_query_wol_rol_out_bits { 4279 u8 status[0x8]; 4280 u8 reserved_0[0x18]; 4281 4282 u8 syndrome[0x20]; 4283 4284 u8 reserved_1[0x10]; 4285 u8 rol_mode[0x8]; 4286 u8 wol_mode[0x8]; 4287 4288 u8 reserved_2[0x20]; 4289}; 4290 4291struct mlx5_ifc_query_wol_rol_in_bits { 4292 u8 opcode[0x10]; 4293 u8 reserved_0[0x10]; 4294 4295 u8 reserved_1[0x10]; 4296 u8 op_mod[0x10]; 4297 4298 u8 reserved_2[0x40]; 4299}; 4300 4301enum { 4302 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4303 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4304}; 4305 4306struct mlx5_ifc_query_vport_state_out_bits { 4307 u8 status[0x8]; 4308 u8 reserved_0[0x18]; 4309 4310 u8 syndrome[0x20]; 4311 4312 u8 reserved_1[0x20]; 4313 4314 u8 reserved_2[0x18]; 4315 u8 admin_state[0x4]; 4316 u8 state[0x4]; 4317}; 4318 4319enum { 4320 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 4321 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 4322 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 4323}; 4324 4325struct mlx5_ifc_query_vport_state_in_bits { 4326 u8 opcode[0x10]; 4327 u8 reserved_0[0x10]; 4328 4329 u8 reserved_1[0x10]; 4330 u8 op_mod[0x10]; 4331 4332 u8 other_vport[0x1]; 4333 u8 reserved_2[0xf]; 4334 u8 vport_number[0x10]; 4335 4336 u8 reserved_3[0x20]; 4337}; 4338 4339struct mlx5_ifc_query_vnic_env_out_bits { 4340 u8 status[0x8]; 4341 u8 reserved_at_8[0x18]; 4342 4343 u8 syndrome[0x20]; 4344 4345 u8 reserved_at_40[0x40]; 4346 4347 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4348}; 4349 4350enum { 4351 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4352}; 4353 4354struct mlx5_ifc_query_vnic_env_in_bits { 4355 u8 opcode[0x10]; 4356 u8 reserved_at_10[0x10]; 4357 4358 u8 reserved_at_20[0x10]; 4359 u8 op_mod[0x10]; 4360 4361 u8 other_vport[0x1]; 4362 u8 reserved_at_41[0xf]; 4363 u8 vport_number[0x10]; 4364 4365 u8 reserved_at_60[0x20]; 4366}; 4367 4368struct mlx5_ifc_query_vport_counter_out_bits { 4369 u8 status[0x8]; 4370 u8 reserved_0[0x18]; 4371 4372 u8 syndrome[0x20]; 4373 4374 u8 reserved_1[0x40]; 4375 4376 struct mlx5_ifc_traffic_counter_bits received_errors; 4377 4378 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4379 4380 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4381 4382 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4383 4384 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4385 4386 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4387 4388 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4389 4390 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4391 4392 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4393 4394 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4395 4396 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4397 4398 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4399 4400 u8 reserved_2[0xa00]; 4401}; 4402 4403enum { 4404 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4405}; 4406 4407struct mlx5_ifc_query_vport_counter_in_bits { 4408 u8 opcode[0x10]; 4409 u8 reserved_0[0x10]; 4410 4411 u8 reserved_1[0x10]; 4412 u8 op_mod[0x10]; 4413 4414 u8 other_vport[0x1]; 4415 u8 reserved_2[0xb]; 4416 u8 port_num[0x4]; 4417 u8 vport_number[0x10]; 4418 4419 u8 reserved_3[0x60]; 4420 4421 u8 clear[0x1]; 4422 u8 reserved_4[0x1f]; 4423 4424 u8 reserved_5[0x20]; 4425}; 4426 4427struct mlx5_ifc_query_tis_out_bits { 4428 u8 status[0x8]; 4429 u8 reserved_0[0x18]; 4430 4431 u8 syndrome[0x20]; 4432 4433 u8 reserved_1[0x40]; 4434 4435 struct mlx5_ifc_tisc_bits tis_context; 4436}; 4437 4438struct mlx5_ifc_query_tis_in_bits { 4439 u8 opcode[0x10]; 4440 u8 reserved_0[0x10]; 4441 4442 u8 reserved_1[0x10]; 4443 u8 op_mod[0x10]; 4444 4445 u8 reserved_2[0x8]; 4446 u8 tisn[0x18]; 4447 4448 u8 reserved_3[0x20]; 4449}; 4450 4451struct mlx5_ifc_query_tir_out_bits { 4452 u8 status[0x8]; 4453 u8 reserved_0[0x18]; 4454 4455 u8 syndrome[0x20]; 4456 4457 u8 reserved_1[0xc0]; 4458 4459 struct mlx5_ifc_tirc_bits tir_context; 4460}; 4461 4462struct mlx5_ifc_query_tir_in_bits { 4463 u8 opcode[0x10]; 4464 u8 reserved_0[0x10]; 4465 4466 u8 reserved_1[0x10]; 4467 u8 op_mod[0x10]; 4468 4469 u8 reserved_2[0x8]; 4470 u8 tirn[0x18]; 4471 4472 u8 reserved_3[0x20]; 4473}; 4474 4475struct mlx5_ifc_query_srq_out_bits { 4476 u8 status[0x8]; 4477 u8 reserved_0[0x18]; 4478 4479 u8 syndrome[0x20]; 4480 4481 u8 reserved_1[0x40]; 4482 4483 struct mlx5_ifc_srqc_bits srq_context_entry; 4484 4485 u8 reserved_2[0x600]; 4486 4487 u8 pas[0][0x40]; 4488}; 4489 4490struct mlx5_ifc_query_srq_in_bits { 4491 u8 opcode[0x10]; 4492 u8 reserved_0[0x10]; 4493 4494 u8 reserved_1[0x10]; 4495 u8 op_mod[0x10]; 4496 4497 u8 reserved_2[0x8]; 4498 u8 srqn[0x18]; 4499 4500 u8 reserved_3[0x20]; 4501}; 4502 4503struct mlx5_ifc_query_sq_out_bits { 4504 u8 status[0x8]; 4505 u8 reserved_0[0x18]; 4506 4507 u8 syndrome[0x20]; 4508 4509 u8 reserved_1[0xc0]; 4510 4511 struct mlx5_ifc_sqc_bits sq_context; 4512}; 4513 4514struct mlx5_ifc_query_sq_in_bits { 4515 u8 opcode[0x10]; 4516 u8 reserved_0[0x10]; 4517 4518 u8 reserved_1[0x10]; 4519 u8 op_mod[0x10]; 4520 4521 u8 reserved_2[0x8]; 4522 u8 sqn[0x18]; 4523 4524 u8 reserved_3[0x20]; 4525}; 4526 4527struct mlx5_ifc_query_special_contexts_out_bits { 4528 u8 status[0x8]; 4529 u8 reserved_0[0x18]; 4530 4531 u8 syndrome[0x20]; 4532 4533 u8 dump_fill_mkey[0x20]; 4534 4535 u8 resd_lkey[0x20]; 4536}; 4537 4538struct mlx5_ifc_query_special_contexts_in_bits { 4539 u8 opcode[0x10]; 4540 u8 reserved_0[0x10]; 4541 4542 u8 reserved_1[0x10]; 4543 u8 op_mod[0x10]; 4544 4545 u8 reserved_2[0x40]; 4546}; 4547 4548struct mlx5_ifc_query_scheduling_element_out_bits { 4549 u8 status[0x8]; 4550 u8 reserved_at_8[0x18]; 4551 4552 u8 syndrome[0x20]; 4553 4554 u8 reserved_at_40[0xc0]; 4555 4556 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4557 4558 u8 reserved_at_300[0x100]; 4559}; 4560 4561enum { 4562 MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2, 4563}; 4564 4565struct mlx5_ifc_query_scheduling_element_in_bits { 4566 u8 opcode[0x10]; 4567 u8 reserved_at_10[0x10]; 4568 4569 u8 reserved_at_20[0x10]; 4570 u8 op_mod[0x10]; 4571 4572 u8 scheduling_hierarchy[0x8]; 4573 u8 reserved_at_48[0x18]; 4574 4575 u8 scheduling_element_id[0x20]; 4576 4577 u8 reserved_at_80[0x180]; 4578}; 4579 4580struct mlx5_ifc_query_rqt_out_bits { 4581 u8 status[0x8]; 4582 u8 reserved_0[0x18]; 4583 4584 u8 syndrome[0x20]; 4585 4586 u8 reserved_1[0xc0]; 4587 4588 struct mlx5_ifc_rqtc_bits rqt_context; 4589}; 4590 4591struct mlx5_ifc_query_rqt_in_bits { 4592 u8 opcode[0x10]; 4593 u8 reserved_0[0x10]; 4594 4595 u8 reserved_1[0x10]; 4596 u8 op_mod[0x10]; 4597 4598 u8 reserved_2[0x8]; 4599 u8 rqtn[0x18]; 4600 4601 u8 reserved_3[0x20]; 4602}; 4603 4604struct mlx5_ifc_query_rq_out_bits { 4605 u8 status[0x8]; 4606 u8 reserved_0[0x18]; 4607 4608 u8 syndrome[0x20]; 4609 4610 u8 reserved_1[0xc0]; 4611 4612 struct mlx5_ifc_rqc_bits rq_context; 4613}; 4614 4615struct mlx5_ifc_query_rq_in_bits { 4616 u8 opcode[0x10]; 4617 u8 reserved_0[0x10]; 4618 4619 u8 reserved_1[0x10]; 4620 u8 op_mod[0x10]; 4621 4622 u8 reserved_2[0x8]; 4623 u8 rqn[0x18]; 4624 4625 u8 reserved_3[0x20]; 4626}; 4627 4628struct mlx5_ifc_query_roce_address_out_bits { 4629 u8 status[0x8]; 4630 u8 reserved_0[0x18]; 4631 4632 u8 syndrome[0x20]; 4633 4634 u8 reserved_1[0x40]; 4635 4636 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4637}; 4638 4639struct mlx5_ifc_query_roce_address_in_bits { 4640 u8 opcode[0x10]; 4641 u8 reserved_0[0x10]; 4642 4643 u8 reserved_1[0x10]; 4644 u8 op_mod[0x10]; 4645 4646 u8 roce_address_index[0x10]; 4647 u8 reserved_2[0x10]; 4648 4649 u8 reserved_3[0x20]; 4650}; 4651 4652struct mlx5_ifc_query_rmp_out_bits { 4653 u8 status[0x8]; 4654 u8 reserved_0[0x18]; 4655 4656 u8 syndrome[0x20]; 4657 4658 u8 reserved_1[0xc0]; 4659 4660 struct mlx5_ifc_rmpc_bits rmp_context; 4661}; 4662 4663struct mlx5_ifc_query_rmp_in_bits { 4664 u8 opcode[0x10]; 4665 u8 reserved_0[0x10]; 4666 4667 u8 reserved_1[0x10]; 4668 u8 op_mod[0x10]; 4669 4670 u8 reserved_2[0x8]; 4671 u8 rmpn[0x18]; 4672 4673 u8 reserved_3[0x20]; 4674}; 4675 4676struct mlx5_ifc_query_rdb_out_bits { 4677 u8 status[0x8]; 4678 u8 reserved_0[0x18]; 4679 4680 u8 syndrome[0x20]; 4681 4682 u8 reserved_1[0x20]; 4683 4684 u8 reserved_2[0x18]; 4685 u8 rdb_list_size[0x8]; 4686 4687 struct mlx5_ifc_rdbc_bits rdb_context[0]; 4688}; 4689 4690struct mlx5_ifc_query_rdb_in_bits { 4691 u8 opcode[0x10]; 4692 u8 reserved_0[0x10]; 4693 4694 u8 reserved_1[0x10]; 4695 u8 op_mod[0x10]; 4696 4697 u8 reserved_2[0x8]; 4698 u8 qpn[0x18]; 4699 4700 u8 reserved_3[0x20]; 4701}; 4702 4703struct mlx5_ifc_query_qp_out_bits { 4704 u8 status[0x8]; 4705 u8 reserved_0[0x18]; 4706 4707 u8 syndrome[0x20]; 4708 4709 u8 reserved_1[0x40]; 4710 4711 u8 opt_param_mask[0x20]; 4712 4713 u8 reserved_2[0x20]; 4714 4715 struct mlx5_ifc_qpc_bits qpc; 4716 4717 u8 reserved_3[0x80]; 4718 4719 u8 pas[0][0x40]; 4720}; 4721 4722struct mlx5_ifc_query_qp_in_bits { 4723 u8 opcode[0x10]; 4724 u8 reserved_0[0x10]; 4725 4726 u8 reserved_1[0x10]; 4727 u8 op_mod[0x10]; 4728 4729 u8 reserved_2[0x8]; 4730 u8 qpn[0x18]; 4731 4732 u8 reserved_3[0x20]; 4733}; 4734 4735struct mlx5_ifc_query_q_counter_out_bits { 4736 u8 status[0x8]; 4737 u8 reserved_0[0x18]; 4738 4739 u8 syndrome[0x20]; 4740 4741 u8 reserved_1[0x40]; 4742 4743 u8 rx_write_requests[0x20]; 4744 4745 u8 reserved_2[0x20]; 4746 4747 u8 rx_read_requests[0x20]; 4748 4749 u8 reserved_3[0x20]; 4750 4751 u8 rx_atomic_requests[0x20]; 4752 4753 u8 reserved_4[0x20]; 4754 4755 u8 rx_dct_connect[0x20]; 4756 4757 u8 reserved_5[0x20]; 4758 4759 u8 out_of_buffer[0x20]; 4760 4761 u8 reserved_7[0x20]; 4762 4763 u8 out_of_sequence[0x20]; 4764 4765 u8 reserved_8[0x20]; 4766 4767 u8 duplicate_request[0x20]; 4768 4769 u8 reserved_9[0x20]; 4770 4771 u8 rnr_nak_retry_err[0x20]; 4772 4773 u8 reserved_10[0x20]; 4774 4775 u8 packet_seq_err[0x20]; 4776 4777 u8 reserved_11[0x20]; 4778 4779 u8 implied_nak_seq_err[0x20]; 4780 4781 u8 reserved_12[0x20]; 4782 4783 u8 local_ack_timeout_err[0x20]; 4784 4785 u8 reserved_13[0x20]; 4786 4787 u8 resp_rnr_nak[0x20]; 4788 4789 u8 reserved_14[0x20]; 4790 4791 u8 req_rnr_retries_exceeded[0x20]; 4792 4793 u8 reserved_15[0x460]; 4794}; 4795 4796struct mlx5_ifc_query_q_counter_in_bits { 4797 u8 opcode[0x10]; 4798 u8 reserved_0[0x10]; 4799 4800 u8 reserved_1[0x10]; 4801 u8 op_mod[0x10]; 4802 4803 u8 reserved_2[0x80]; 4804 4805 u8 clear[0x1]; 4806 u8 reserved_3[0x1f]; 4807 4808 u8 reserved_4[0x18]; 4809 u8 counter_set_id[0x8]; 4810}; 4811 4812struct mlx5_ifc_query_pages_out_bits { 4813 u8 status[0x8]; 4814 u8 reserved_0[0x18]; 4815 4816 u8 syndrome[0x20]; 4817 4818 u8 reserved_1[0x10]; 4819 u8 function_id[0x10]; 4820 4821 u8 num_pages[0x20]; 4822}; 4823 4824enum { 4825 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4826 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4827 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4828}; 4829 4830struct mlx5_ifc_query_pages_in_bits { 4831 u8 opcode[0x10]; 4832 u8 reserved_0[0x10]; 4833 4834 u8 reserved_1[0x10]; 4835 u8 op_mod[0x10]; 4836 4837 u8 reserved_2[0x10]; 4838 u8 function_id[0x10]; 4839 4840 u8 reserved_3[0x20]; 4841}; 4842 4843struct mlx5_ifc_query_nic_vport_context_out_bits { 4844 u8 status[0x8]; 4845 u8 reserved_0[0x18]; 4846 4847 u8 syndrome[0x20]; 4848 4849 u8 reserved_1[0x40]; 4850 4851 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4852}; 4853 4854struct mlx5_ifc_query_nic_vport_context_in_bits { 4855 u8 opcode[0x10]; 4856 u8 reserved_0[0x10]; 4857 4858 u8 reserved_1[0x10]; 4859 u8 op_mod[0x10]; 4860 4861 u8 other_vport[0x1]; 4862 u8 reserved_2[0xf]; 4863 u8 vport_number[0x10]; 4864 4865 u8 reserved_3[0x5]; 4866 u8 allowed_list_type[0x3]; 4867 u8 reserved_4[0x18]; 4868}; 4869 4870struct mlx5_ifc_query_mkey_out_bits { 4871 u8 status[0x8]; 4872 u8 reserved_0[0x18]; 4873 4874 u8 syndrome[0x20]; 4875 4876 u8 reserved_1[0x40]; 4877 4878 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4879 4880 u8 reserved_2[0x600]; 4881 4882 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4883 4884 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4885}; 4886 4887struct mlx5_ifc_query_mkey_in_bits { 4888 u8 opcode[0x10]; 4889 u8 reserved_0[0x10]; 4890 4891 u8 reserved_1[0x10]; 4892 u8 op_mod[0x10]; 4893 4894 u8 reserved_2[0x8]; 4895 u8 mkey_index[0x18]; 4896 4897 u8 pg_access[0x1]; 4898 u8 reserved_3[0x1f]; 4899}; 4900 4901struct mlx5_ifc_query_mad_demux_out_bits { 4902 u8 status[0x8]; 4903 u8 reserved_0[0x18]; 4904 4905 u8 syndrome[0x20]; 4906 4907 u8 reserved_1[0x40]; 4908 4909 u8 mad_dumux_parameters_block[0x20]; 4910}; 4911 4912struct mlx5_ifc_query_mad_demux_in_bits { 4913 u8 opcode[0x10]; 4914 u8 reserved_0[0x10]; 4915 4916 u8 reserved_1[0x10]; 4917 u8 op_mod[0x10]; 4918 4919 u8 reserved_2[0x40]; 4920}; 4921 4922struct mlx5_ifc_query_l2_table_entry_out_bits { 4923 u8 status[0x8]; 4924 u8 reserved_0[0x18]; 4925 4926 u8 syndrome[0x20]; 4927 4928 u8 reserved_1[0xa0]; 4929 4930 u8 reserved_2[0x13]; 4931 u8 vlan_valid[0x1]; 4932 u8 vlan[0xc]; 4933 4934 struct mlx5_ifc_mac_address_layout_bits mac_address; 4935 4936 u8 reserved_3[0xc0]; 4937}; 4938 4939struct mlx5_ifc_query_l2_table_entry_in_bits { 4940 u8 opcode[0x10]; 4941 u8 reserved_0[0x10]; 4942 4943 u8 reserved_1[0x10]; 4944 u8 op_mod[0x10]; 4945 4946 u8 reserved_2[0x60]; 4947 4948 u8 reserved_3[0x8]; 4949 u8 table_index[0x18]; 4950 4951 u8 reserved_4[0x140]; 4952}; 4953 4954struct mlx5_ifc_query_issi_out_bits { 4955 u8 status[0x8]; 4956 u8 reserved_0[0x18]; 4957 4958 u8 syndrome[0x20]; 4959 4960 u8 reserved_1[0x10]; 4961 u8 current_issi[0x10]; 4962 4963 u8 reserved_2[0xa0]; 4964 4965 u8 supported_issi_reserved[76][0x8]; 4966 u8 supported_issi_dw0[0x20]; 4967}; 4968 4969struct mlx5_ifc_query_issi_in_bits { 4970 u8 opcode[0x10]; 4971 u8 reserved_0[0x10]; 4972 4973 u8 reserved_1[0x10]; 4974 u8 op_mod[0x10]; 4975 4976 u8 reserved_2[0x40]; 4977}; 4978 4979struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4980 u8 status[0x8]; 4981 u8 reserved_0[0x18]; 4982 4983 u8 syndrome[0x20]; 4984 4985 u8 reserved_1[0x40]; 4986 4987 struct mlx5_ifc_pkey_bits pkey[0]; 4988}; 4989 4990struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4991 u8 opcode[0x10]; 4992 u8 reserved_0[0x10]; 4993 4994 u8 reserved_1[0x10]; 4995 u8 op_mod[0x10]; 4996 4997 u8 other_vport[0x1]; 4998 u8 reserved_2[0xb]; 4999 u8 port_num[0x4]; 5000 u8 vport_number[0x10]; 5001 5002 u8 reserved_3[0x10]; 5003 u8 pkey_index[0x10]; 5004}; 5005 5006struct mlx5_ifc_query_hca_vport_gid_out_bits { 5007 u8 status[0x8]; 5008 u8 reserved_0[0x18]; 5009 5010 u8 syndrome[0x20]; 5011 5012 u8 reserved_1[0x20]; 5013 5014 u8 gids_num[0x10]; 5015 u8 reserved_2[0x10]; 5016 5017 struct mlx5_ifc_array128_auto_bits gid[0]; 5018}; 5019 5020struct mlx5_ifc_query_hca_vport_gid_in_bits { 5021 u8 opcode[0x10]; 5022 u8 reserved_0[0x10]; 5023 5024 u8 reserved_1[0x10]; 5025 u8 op_mod[0x10]; 5026 5027 u8 other_vport[0x1]; 5028 u8 reserved_2[0xb]; 5029 u8 port_num[0x4]; 5030 u8 vport_number[0x10]; 5031 5032 u8 reserved_3[0x10]; 5033 u8 gid_index[0x10]; 5034}; 5035 5036struct mlx5_ifc_query_hca_vport_context_out_bits { 5037 u8 status[0x8]; 5038 u8 reserved_0[0x18]; 5039 5040 u8 syndrome[0x20]; 5041 5042 u8 reserved_1[0x40]; 5043 5044 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5045}; 5046 5047struct mlx5_ifc_query_hca_vport_context_in_bits { 5048 u8 opcode[0x10]; 5049 u8 reserved_0[0x10]; 5050 5051 u8 reserved_1[0x10]; 5052 u8 op_mod[0x10]; 5053 5054 u8 other_vport[0x1]; 5055 u8 reserved_2[0xb]; 5056 u8 port_num[0x4]; 5057 u8 vport_number[0x10]; 5058 5059 u8 reserved_3[0x20]; 5060}; 5061 5062struct mlx5_ifc_query_hca_cap_out_bits { 5063 u8 status[0x8]; 5064 u8 reserved_0[0x18]; 5065 5066 u8 syndrome[0x20]; 5067 5068 u8 reserved_1[0x40]; 5069 5070 union mlx5_ifc_hca_cap_union_bits capability; 5071}; 5072 5073struct mlx5_ifc_query_hca_cap_in_bits { 5074 u8 opcode[0x10]; 5075 u8 reserved_0[0x10]; 5076 5077 u8 reserved_1[0x10]; 5078 u8 op_mod[0x10]; 5079 5080 u8 reserved_2[0x40]; 5081}; 5082 5083struct mlx5_ifc_query_flow_table_out_bits { 5084 u8 status[0x8]; 5085 u8 reserved_at_8[0x18]; 5086 5087 u8 syndrome[0x20]; 5088 5089 u8 reserved_at_40[0x80]; 5090 5091 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5092}; 5093 5094struct mlx5_ifc_query_flow_table_in_bits { 5095 u8 opcode[0x10]; 5096 u8 reserved_0[0x10]; 5097 5098 u8 reserved_1[0x10]; 5099 u8 op_mod[0x10]; 5100 5101 u8 other_vport[0x1]; 5102 u8 reserved_2[0xf]; 5103 u8 vport_number[0x10]; 5104 5105 u8 reserved_3[0x20]; 5106 5107 u8 table_type[0x8]; 5108 u8 reserved_4[0x18]; 5109 5110 u8 reserved_5[0x8]; 5111 u8 table_id[0x18]; 5112 5113 u8 reserved_6[0x140]; 5114}; 5115 5116struct mlx5_ifc_query_fte_out_bits { 5117 u8 status[0x8]; 5118 u8 reserved_0[0x18]; 5119 5120 u8 syndrome[0x20]; 5121 5122 u8 reserved_1[0x1c0]; 5123 5124 struct mlx5_ifc_flow_context_bits flow_context; 5125}; 5126 5127struct mlx5_ifc_query_fte_in_bits { 5128 u8 opcode[0x10]; 5129 u8 reserved_0[0x10]; 5130 5131 u8 reserved_1[0x10]; 5132 u8 op_mod[0x10]; 5133 5134 u8 other_vport[0x1]; 5135 u8 reserved_2[0xf]; 5136 u8 vport_number[0x10]; 5137 5138 u8 reserved_3[0x20]; 5139 5140 u8 table_type[0x8]; 5141 u8 reserved_4[0x18]; 5142 5143 u8 reserved_5[0x8]; 5144 u8 table_id[0x18]; 5145 5146 u8 reserved_6[0x40]; 5147 5148 u8 flow_index[0x20]; 5149 5150 u8 reserved_7[0xe0]; 5151}; 5152 5153enum { 5154 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5155 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5156 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5157}; 5158 5159struct mlx5_ifc_query_flow_group_out_bits { 5160 u8 status[0x8]; 5161 u8 reserved_0[0x18]; 5162 5163 u8 syndrome[0x20]; 5164 5165 u8 reserved_1[0xa0]; 5166 5167 u8 start_flow_index[0x20]; 5168 5169 u8 reserved_2[0x20]; 5170 5171 u8 end_flow_index[0x20]; 5172 5173 u8 reserved_3[0xa0]; 5174 5175 u8 reserved_4[0x18]; 5176 u8 match_criteria_enable[0x8]; 5177 5178 struct mlx5_ifc_fte_match_param_bits match_criteria; 5179 5180 u8 reserved_5[0xe00]; 5181}; 5182 5183struct mlx5_ifc_query_flow_group_in_bits { 5184 u8 opcode[0x10]; 5185 u8 reserved_0[0x10]; 5186 5187 u8 reserved_1[0x10]; 5188 u8 op_mod[0x10]; 5189 5190 u8 other_vport[0x1]; 5191 u8 reserved_2[0xf]; 5192 u8 vport_number[0x10]; 5193 5194 u8 reserved_3[0x20]; 5195 5196 u8 table_type[0x8]; 5197 u8 reserved_4[0x18]; 5198 5199 u8 reserved_5[0x8]; 5200 u8 table_id[0x18]; 5201 5202 u8 group_id[0x20]; 5203 5204 u8 reserved_6[0x120]; 5205}; 5206 5207struct mlx5_ifc_query_flow_counter_out_bits { 5208 u8 status[0x8]; 5209 u8 reserved_at_8[0x18]; 5210 5211 u8 syndrome[0x20]; 5212 5213 u8 reserved_at_40[0x40]; 5214 5215 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 5216}; 5217 5218struct mlx5_ifc_query_flow_counter_in_bits { 5219 u8 opcode[0x10]; 5220 u8 reserved_at_10[0x10]; 5221 5222 u8 reserved_at_20[0x10]; 5223 u8 op_mod[0x10]; 5224 5225 u8 reserved_at_40[0x80]; 5226 5227 u8 clear[0x1]; 5228 u8 reserved_at_c1[0xf]; 5229 u8 num_of_counters[0x10]; 5230 5231 u8 reserved_at_e0[0x10]; 5232 u8 flow_counter_id[0x10]; 5233}; 5234 5235struct mlx5_ifc_query_esw_vport_context_out_bits { 5236 u8 status[0x8]; 5237 u8 reserved_0[0x18]; 5238 5239 u8 syndrome[0x20]; 5240 5241 u8 reserved_1[0x40]; 5242 5243 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5244}; 5245 5246struct mlx5_ifc_query_esw_vport_context_in_bits { 5247 u8 opcode[0x10]; 5248 u8 reserved_0[0x10]; 5249 5250 u8 reserved_1[0x10]; 5251 u8 op_mod[0x10]; 5252 5253 u8 other_vport[0x1]; 5254 u8 reserved_2[0xf]; 5255 u8 vport_number[0x10]; 5256 5257 u8 reserved_3[0x20]; 5258}; 5259 5260struct mlx5_ifc_query_eq_out_bits { 5261 u8 status[0x8]; 5262 u8 reserved_0[0x18]; 5263 5264 u8 syndrome[0x20]; 5265 5266 u8 reserved_1[0x40]; 5267 5268 struct mlx5_ifc_eqc_bits eq_context_entry; 5269 5270 u8 reserved_2[0x40]; 5271 5272 u8 event_bitmask[0x40]; 5273 5274 u8 reserved_3[0x580]; 5275 5276 u8 pas[0][0x40]; 5277}; 5278 5279struct mlx5_ifc_query_eq_in_bits { 5280 u8 opcode[0x10]; 5281 u8 reserved_0[0x10]; 5282 5283 u8 reserved_1[0x10]; 5284 u8 op_mod[0x10]; 5285 5286 u8 reserved_2[0x18]; 5287 u8 eq_number[0x8]; 5288 5289 u8 reserved_3[0x20]; 5290}; 5291 5292struct mlx5_ifc_set_action_in_bits { 5293 u8 action_type[0x4]; 5294 u8 field[0xc]; 5295 u8 reserved_at_10[0x3]; 5296 u8 offset[0x5]; 5297 u8 reserved_at_18[0x3]; 5298 u8 length[0x5]; 5299 5300 u8 data[0x20]; 5301}; 5302 5303struct mlx5_ifc_add_action_in_bits { 5304 u8 action_type[0x4]; 5305 u8 field[0xc]; 5306 u8 reserved_at_10[0x10]; 5307 5308 u8 data[0x20]; 5309}; 5310 5311struct mlx5_ifc_copy_action_in_bits { 5312 u8 action_type[0x4]; 5313 u8 src_field[0xc]; 5314 u8 reserved_at_10[0x3]; 5315 u8 src_offset[0x5]; 5316 u8 reserved_at_18[0x3]; 5317 u8 length[0x5]; 5318 5319 u8 reserved_at_20[0x4]; 5320 u8 dst_field[0xc]; 5321 u8 reserved_at_30[0x3]; 5322 u8 dst_offset[0x5]; 5323 u8 reserved_at_38[0x8]; 5324}; 5325 5326union mlx5_ifc_set_add_copy_action_in_auto_bits { 5327 struct mlx5_ifc_set_action_in_bits set_action_in; 5328 struct mlx5_ifc_add_action_in_bits add_action_in; 5329 struct mlx5_ifc_copy_action_in_bits copy_action_in; 5330 u8 reserved_at_0[0x40]; 5331}; 5332 5333enum { 5334 MLX5_ACTION_TYPE_SET = 0x1, 5335 MLX5_ACTION_TYPE_ADD = 0x2, 5336 MLX5_ACTION_TYPE_COPY = 0x3, 5337}; 5338 5339enum { 5340 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5341 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5342 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5343 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5344 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5345 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5346 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5347 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5348 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5349 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5350 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5351 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5352 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5353 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5354 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5355 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5356 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5357 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5358 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5359 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5360 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5361 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5362 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 5363 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5364 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 5365 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 5366 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 5367 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 5368 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 5369 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 5370 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 5371 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 5372 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 5373 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 5374 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 5375 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 5376 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 5377 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 5378 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 5379}; 5380 5381struct mlx5_ifc_alloc_modify_header_context_out_bits { 5382 u8 status[0x8]; 5383 u8 reserved_at_8[0x18]; 5384 5385 u8 syndrome[0x20]; 5386 5387 u8 modify_header_id[0x20]; 5388 5389 u8 reserved_at_60[0x20]; 5390}; 5391 5392struct mlx5_ifc_alloc_modify_header_context_in_bits { 5393 u8 opcode[0x10]; 5394 u8 reserved_at_10[0x10]; 5395 5396 u8 reserved_at_20[0x10]; 5397 u8 op_mod[0x10]; 5398 5399 u8 reserved_at_40[0x20]; 5400 5401 u8 table_type[0x8]; 5402 u8 reserved_at_68[0x10]; 5403 u8 num_of_actions[0x8]; 5404 5405 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 5406}; 5407 5408struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5409 u8 status[0x8]; 5410 u8 reserved_at_8[0x18]; 5411 5412 u8 syndrome[0x20]; 5413 5414 u8 reserved_at_40[0x40]; 5415}; 5416 5417struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5418 u8 opcode[0x10]; 5419 u8 reserved_at_10[0x10]; 5420 5421 u8 reserved_at_20[0x10]; 5422 u8 op_mod[0x10]; 5423 5424 u8 modify_header_id[0x20]; 5425 5426 u8 reserved_at_60[0x20]; 5427}; 5428 5429struct mlx5_ifc_query_modify_header_context_in_bits { 5430 u8 opcode[0x10]; 5431 u8 uid[0x10]; 5432 5433 u8 reserved_at_20[0x10]; 5434 u8 op_mod[0x10]; 5435 5436 u8 modify_header_id[0x20]; 5437 5438 u8 reserved_at_60[0xa0]; 5439}; 5440 5441struct mlx5_ifc_query_dct_out_bits { 5442 u8 status[0x8]; 5443 u8 reserved_0[0x18]; 5444 5445 u8 syndrome[0x20]; 5446 5447 u8 reserved_1[0x40]; 5448 5449 struct mlx5_ifc_dctc_bits dct_context_entry; 5450 5451 u8 reserved_2[0x180]; 5452}; 5453 5454struct mlx5_ifc_query_dct_in_bits { 5455 u8 opcode[0x10]; 5456 u8 reserved_0[0x10]; 5457 5458 u8 reserved_1[0x10]; 5459 u8 op_mod[0x10]; 5460 5461 u8 reserved_2[0x8]; 5462 u8 dctn[0x18]; 5463 5464 u8 reserved_3[0x20]; 5465}; 5466 5467struct mlx5_ifc_query_dc_cnak_trace_out_bits { 5468 u8 status[0x8]; 5469 u8 reserved_0[0x18]; 5470 5471 u8 syndrome[0x20]; 5472 5473 u8 enable[0x1]; 5474 u8 reserved_1[0x1f]; 5475 5476 u8 reserved_2[0x160]; 5477 5478 struct mlx5_ifc_cmd_pas_bits pas; 5479}; 5480 5481struct mlx5_ifc_query_dc_cnak_trace_in_bits { 5482 u8 opcode[0x10]; 5483 u8 reserved_0[0x10]; 5484 5485 u8 reserved_1[0x10]; 5486 u8 op_mod[0x10]; 5487 5488 u8 reserved_2[0x40]; 5489}; 5490 5491struct mlx5_ifc_packet_reformat_context_in_bits { 5492 u8 reformat_type[0x8]; 5493 u8 reserved_at_8[0x4]; 5494 u8 reformat_param_0[0x4]; 5495 u8 reserved_at_10[0x6]; 5496 u8 reformat_data_size[0xa]; 5497 5498 u8 reformat_param_1[0x8]; 5499 u8 reserved_at_28[0x8]; 5500 u8 reformat_data[2][0x8]; 5501 5502 u8 more_reformat_data[][0x8]; 5503}; 5504 5505struct mlx5_ifc_query_packet_reformat_context_out_bits { 5506 u8 status[0x8]; 5507 u8 reserved_at_8[0x18]; 5508 5509 u8 syndrome[0x20]; 5510 5511 u8 reserved_at_40[0xa0]; 5512 5513 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0]; 5514}; 5515 5516struct mlx5_ifc_query_packet_reformat_context_in_bits { 5517 u8 opcode[0x10]; 5518 u8 reserved_at_10[0x10]; 5519 5520 u8 reserved_at_20[0x10]; 5521 u8 op_mod[0x10]; 5522 5523 u8 packet_reformat_id[0x20]; 5524 5525 u8 reserved_at_60[0xa0]; 5526}; 5527 5528struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5529 u8 status[0x8]; 5530 u8 reserved_at_8[0x18]; 5531 5532 u8 syndrome[0x20]; 5533 5534 u8 packet_reformat_id[0x20]; 5535 5536 u8 reserved_at_60[0x20]; 5537}; 5538 5539enum mlx5_reformat_ctx_type { 5540 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5541 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5542 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5543 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5544 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5545}; 5546 5547struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5548 u8 opcode[0x10]; 5549 u8 reserved_at_10[0x10]; 5550 5551 u8 reserved_at_20[0x10]; 5552 u8 op_mod[0x10]; 5553 5554 u8 reserved_at_40[0xa0]; 5555 5556 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5557}; 5558 5559struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5560 u8 status[0x8]; 5561 u8 reserved_at_8[0x18]; 5562 5563 u8 syndrome[0x20]; 5564 5565 u8 reserved_at_40[0x40]; 5566}; 5567 5568struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5569 u8 opcode[0x10]; 5570 u8 reserved_at_10[0x10]; 5571 5572 u8 reserved_20[0x10]; 5573 u8 op_mod[0x10]; 5574 5575 u8 packet_reformat_id[0x20]; 5576 5577 u8 reserved_60[0x20]; 5578}; 5579 5580struct mlx5_ifc_diagnostic_cntr_struct_bits { 5581 u8 counter_id[0x10]; 5582 u8 sample_id[0x10]; 5583 5584 u8 time_stamp_31_0[0x20]; 5585 5586 u8 counter_value_h[0x20]; 5587 5588 u8 counter_value_l[0x20]; 5589}; 5590 5591enum { 5592 MLX5_DIAGNOSTIC_PARAMS_CONTEXT_ENABLE_ENABLE = 0x1, 5593 MLX5_DIAGNOSTIC_PARAMS_CONTEXT_ENABLE_DISABLE = 0x0, 5594}; 5595 5596struct mlx5_ifc_query_cq_out_bits { 5597 u8 status[0x8]; 5598 u8 reserved_0[0x18]; 5599 5600 u8 syndrome[0x20]; 5601 5602 u8 reserved_1[0x40]; 5603 5604 struct mlx5_ifc_cqc_bits cq_context; 5605 5606 u8 reserved_2[0x600]; 5607 5608 u8 pas[0][0x40]; 5609}; 5610 5611struct mlx5_ifc_query_cq_in_bits { 5612 u8 opcode[0x10]; 5613 u8 reserved_0[0x10]; 5614 5615 u8 reserved_1[0x10]; 5616 u8 op_mod[0x10]; 5617 5618 u8 reserved_2[0x8]; 5619 u8 cqn[0x18]; 5620 5621 u8 reserved_3[0x20]; 5622}; 5623 5624struct mlx5_ifc_query_cong_status_out_bits { 5625 u8 status[0x8]; 5626 u8 reserved_0[0x18]; 5627 5628 u8 syndrome[0x20]; 5629 5630 u8 reserved_1[0x20]; 5631 5632 u8 enable[0x1]; 5633 u8 tag_enable[0x1]; 5634 u8 reserved_2[0x1e]; 5635}; 5636 5637struct mlx5_ifc_query_cong_status_in_bits { 5638 u8 opcode[0x10]; 5639 u8 reserved_0[0x10]; 5640 5641 u8 reserved_1[0x10]; 5642 u8 op_mod[0x10]; 5643 5644 u8 reserved_2[0x18]; 5645 u8 priority[0x4]; 5646 u8 cong_protocol[0x4]; 5647 5648 u8 reserved_3[0x20]; 5649}; 5650 5651struct mlx5_ifc_query_cong_statistics_out_bits { 5652 u8 status[0x8]; 5653 u8 reserved_0[0x18]; 5654 5655 u8 syndrome[0x20]; 5656 5657 u8 reserved_1[0x40]; 5658 5659 u8 rp_cur_flows[0x20]; 5660 5661 u8 sum_flows[0x20]; 5662 5663 u8 rp_cnp_ignored_high[0x20]; 5664 5665 u8 rp_cnp_ignored_low[0x20]; 5666 5667 u8 rp_cnp_handled_high[0x20]; 5668 5669 u8 rp_cnp_handled_low[0x20]; 5670 5671 u8 reserved_2[0x100]; 5672 5673 u8 time_stamp_high[0x20]; 5674 5675 u8 time_stamp_low[0x20]; 5676 5677 u8 accumulators_period[0x20]; 5678 5679 u8 np_ecn_marked_roce_packets_high[0x20]; 5680 5681 u8 np_ecn_marked_roce_packets_low[0x20]; 5682 5683 u8 np_cnp_sent_high[0x20]; 5684 5685 u8 np_cnp_sent_low[0x20]; 5686 5687 u8 reserved_3[0x560]; 5688}; 5689 5690struct mlx5_ifc_query_cong_statistics_in_bits { 5691 u8 opcode[0x10]; 5692 u8 reserved_0[0x10]; 5693 5694 u8 reserved_1[0x10]; 5695 u8 op_mod[0x10]; 5696 5697 u8 clear[0x1]; 5698 u8 reserved_2[0x1f]; 5699 5700 u8 reserved_3[0x20]; 5701}; 5702 5703struct mlx5_ifc_query_cong_params_out_bits { 5704 u8 status[0x8]; 5705 u8 reserved_0[0x18]; 5706 5707 u8 syndrome[0x20]; 5708 5709 u8 reserved_1[0x40]; 5710 5711 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5712}; 5713 5714struct mlx5_ifc_query_cong_params_in_bits { 5715 u8 opcode[0x10]; 5716 u8 reserved_0[0x10]; 5717 5718 u8 reserved_1[0x10]; 5719 u8 op_mod[0x10]; 5720 5721 u8 reserved_2[0x1c]; 5722 u8 cong_protocol[0x4]; 5723 5724 u8 reserved_3[0x20]; 5725}; 5726 5727struct mlx5_ifc_query_burst_size_out_bits { 5728 u8 status[0x8]; 5729 u8 reserved_0[0x18]; 5730 5731 u8 syndrome[0x20]; 5732 5733 u8 reserved_1[0x20]; 5734 5735 u8 reserved_2[0x9]; 5736 u8 device_burst_size[0x17]; 5737}; 5738 5739struct mlx5_ifc_query_burst_size_in_bits { 5740 u8 opcode[0x10]; 5741 u8 reserved_0[0x10]; 5742 5743 u8 reserved_1[0x10]; 5744 u8 op_mod[0x10]; 5745 5746 u8 reserved_2[0x40]; 5747}; 5748 5749struct mlx5_ifc_query_adapter_out_bits { 5750 u8 status[0x8]; 5751 u8 reserved_0[0x18]; 5752 5753 u8 syndrome[0x20]; 5754 5755 u8 reserved_1[0x40]; 5756 5757 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5758}; 5759 5760struct mlx5_ifc_query_adapter_in_bits { 5761 u8 opcode[0x10]; 5762 u8 reserved_0[0x10]; 5763 5764 u8 reserved_1[0x10]; 5765 u8 op_mod[0x10]; 5766 5767 u8 reserved_2[0x40]; 5768}; 5769 5770struct mlx5_ifc_qp_2rst_out_bits { 5771 u8 status[0x8]; 5772 u8 reserved_0[0x18]; 5773 5774 u8 syndrome[0x20]; 5775 5776 u8 reserved_1[0x40]; 5777}; 5778 5779struct mlx5_ifc_qp_2rst_in_bits { 5780 u8 opcode[0x10]; 5781 u8 uid[0x10]; 5782 5783 u8 reserved_1[0x10]; 5784 u8 op_mod[0x10]; 5785 5786 u8 reserved_2[0x8]; 5787 u8 qpn[0x18]; 5788 5789 u8 reserved_3[0x20]; 5790}; 5791 5792struct mlx5_ifc_qp_2err_out_bits { 5793 u8 status[0x8]; 5794 u8 reserved_0[0x18]; 5795 5796 u8 syndrome[0x20]; 5797 5798 u8 reserved_1[0x40]; 5799}; 5800 5801struct mlx5_ifc_qp_2err_in_bits { 5802 u8 opcode[0x10]; 5803 u8 uid[0x10]; 5804 5805 u8 reserved_1[0x10]; 5806 u8 op_mod[0x10]; 5807 5808 u8 reserved_2[0x8]; 5809 u8 qpn[0x18]; 5810 5811 u8 reserved_3[0x20]; 5812}; 5813 5814struct mlx5_ifc_para_vport_element_bits { 5815 u8 reserved_at_0[0xc]; 5816 u8 traffic_class[0x4]; 5817 u8 qos_para_vport_number[0x10]; 5818}; 5819 5820struct mlx5_ifc_page_fault_resume_out_bits { 5821 u8 status[0x8]; 5822 u8 reserved_0[0x18]; 5823 5824 u8 syndrome[0x20]; 5825 5826 u8 reserved_1[0x40]; 5827}; 5828 5829struct mlx5_ifc_page_fault_resume_in_bits { 5830 u8 opcode[0x10]; 5831 u8 reserved_0[0x10]; 5832 5833 u8 reserved_1[0x10]; 5834 u8 op_mod[0x10]; 5835 5836 u8 error[0x1]; 5837 u8 reserved_2[0x4]; 5838 u8 rdma[0x1]; 5839 u8 read_write[0x1]; 5840 u8 req_res[0x1]; 5841 u8 qpn[0x18]; 5842 5843 u8 reserved_3[0x20]; 5844}; 5845 5846struct mlx5_ifc_nop_out_bits { 5847 u8 status[0x8]; 5848 u8 reserved_0[0x18]; 5849 5850 u8 syndrome[0x20]; 5851 5852 u8 reserved_1[0x40]; 5853}; 5854 5855struct mlx5_ifc_nop_in_bits { 5856 u8 opcode[0x10]; 5857 u8 reserved_0[0x10]; 5858 5859 u8 reserved_1[0x10]; 5860 u8 op_mod[0x10]; 5861 5862 u8 reserved_2[0x40]; 5863}; 5864 5865struct mlx5_ifc_modify_vport_state_out_bits { 5866 u8 status[0x8]; 5867 u8 reserved_0[0x18]; 5868 5869 u8 syndrome[0x20]; 5870 5871 u8 reserved_1[0x40]; 5872}; 5873 5874enum { 5875 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT = 0x0, 5876 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 5877 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 5878}; 5879 5880enum { 5881 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN = 0x0, 5882 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP = 0x1, 5883 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW = 0x2, 5884}; 5885 5886struct mlx5_ifc_modify_vport_state_in_bits { 5887 u8 opcode[0x10]; 5888 u8 reserved_0[0x10]; 5889 5890 u8 reserved_1[0x10]; 5891 u8 op_mod[0x10]; 5892 5893 u8 other_vport[0x1]; 5894 u8 reserved_2[0xf]; 5895 u8 vport_number[0x10]; 5896 5897 u8 reserved_3[0x18]; 5898 u8 admin_state[0x4]; 5899 u8 reserved_4[0x4]; 5900}; 5901 5902struct mlx5_ifc_modify_tis_out_bits { 5903 u8 status[0x8]; 5904 u8 reserved_0[0x18]; 5905 5906 u8 syndrome[0x20]; 5907 5908 u8 reserved_1[0x40]; 5909}; 5910 5911struct mlx5_ifc_modify_tis_bitmask_bits { 5912 u8 reserved_at_0[0x20]; 5913 5914 u8 reserved_at_20[0x1d]; 5915 u8 lag_tx_port_affinity[0x1]; 5916 u8 strict_lag_tx_port_affinity[0x1]; 5917 u8 prio[0x1]; 5918}; 5919 5920struct mlx5_ifc_modify_tis_in_bits { 5921 u8 opcode[0x10]; 5922 u8 uid[0x10]; 5923 5924 u8 reserved_1[0x10]; 5925 u8 op_mod[0x10]; 5926 5927 u8 reserved_2[0x8]; 5928 u8 tisn[0x18]; 5929 5930 u8 reserved_3[0x20]; 5931 5932 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5933 5934 u8 reserved_4[0x40]; 5935 5936 struct mlx5_ifc_tisc_bits ctx; 5937}; 5938 5939struct mlx5_ifc_modify_tir_out_bits { 5940 u8 status[0x8]; 5941 u8 reserved_0[0x18]; 5942 5943 u8 syndrome[0x20]; 5944 5945 u8 reserved_1[0x40]; 5946}; 5947 5948enum 5949{ 5950 MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0, 5951 MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER = 0x1 << 1 5952}; 5953 5954struct mlx5_ifc_modify_tir_in_bits { 5955 u8 opcode[0x10]; 5956 u8 uid[0x10]; 5957 5958 u8 reserved_1[0x10]; 5959 u8 op_mod[0x10]; 5960 5961 u8 reserved_2[0x8]; 5962 u8 tirn[0x18]; 5963 5964 u8 reserved_3[0x20]; 5965 5966 u8 modify_bitmask[0x40]; 5967 5968 u8 reserved_4[0x40]; 5969 5970 struct mlx5_ifc_tirc_bits tir_context; 5971}; 5972 5973struct mlx5_ifc_modify_sq_out_bits { 5974 u8 status[0x8]; 5975 u8 reserved_0[0x18]; 5976 5977 u8 syndrome[0x20]; 5978 5979 u8 reserved_1[0x40]; 5980}; 5981 5982struct mlx5_ifc_modify_sq_in_bits { 5983 u8 opcode[0x10]; 5984 u8 uid[0x10]; 5985 5986 u8 reserved_1[0x10]; 5987 u8 op_mod[0x10]; 5988 5989 u8 sq_state[0x4]; 5990 u8 reserved_2[0x4]; 5991 u8 sqn[0x18]; 5992 5993 u8 reserved_3[0x20]; 5994 5995 u8 modify_bitmask[0x40]; 5996 5997 u8 reserved_4[0x40]; 5998 5999 struct mlx5_ifc_sqc_bits ctx; 6000}; 6001 6002struct mlx5_ifc_modify_scheduling_element_out_bits { 6003 u8 status[0x8]; 6004 u8 reserved_at_8[0x18]; 6005 6006 u8 syndrome[0x20]; 6007 6008 u8 reserved_at_40[0x1c0]; 6009}; 6010 6011enum { 6012 MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6013}; 6014 6015enum { 6016 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE = 0x1, 6017 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW = 0x2, 6018}; 6019 6020struct mlx5_ifc_modify_scheduling_element_in_bits { 6021 u8 opcode[0x10]; 6022 u8 reserved_at_10[0x10]; 6023 6024 u8 reserved_at_20[0x10]; 6025 u8 op_mod[0x10]; 6026 6027 u8 scheduling_hierarchy[0x8]; 6028 u8 reserved_at_48[0x18]; 6029 6030 u8 scheduling_element_id[0x20]; 6031 6032 u8 reserved_at_80[0x20]; 6033 6034 u8 modify_bitmask[0x20]; 6035 6036 u8 reserved_at_c0[0x40]; 6037 6038 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6039 6040 u8 reserved_at_300[0x100]; 6041}; 6042 6043struct mlx5_ifc_modify_rqt_out_bits { 6044 u8 status[0x8]; 6045 u8 reserved_0[0x18]; 6046 6047 u8 syndrome[0x20]; 6048 6049 u8 reserved_1[0x40]; 6050}; 6051 6052struct mlx5_ifc_rqt_bitmask_bits { 6053 u8 reserved_at_0[0x20]; 6054 6055 u8 reserved_at_20[0x1f]; 6056 u8 rqn_list[0x1]; 6057}; 6058 6059 6060struct mlx5_ifc_modify_rqt_in_bits { 6061 u8 opcode[0x10]; 6062 u8 uid[0x10]; 6063 6064 u8 reserved_1[0x10]; 6065 u8 op_mod[0x10]; 6066 6067 u8 reserved_2[0x8]; 6068 u8 rqtn[0x18]; 6069 6070 u8 reserved_3[0x20]; 6071 6072 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6073 6074 u8 reserved_4[0x40]; 6075 6076 struct mlx5_ifc_rqtc_bits ctx; 6077}; 6078 6079struct mlx5_ifc_modify_rq_out_bits { 6080 u8 status[0x8]; 6081 u8 reserved_0[0x18]; 6082 6083 u8 syndrome[0x20]; 6084 6085 u8 reserved_1[0x40]; 6086}; 6087 6088enum { 6089 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6090 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3, 6091}; 6092 6093struct mlx5_ifc_modify_rq_in_bits { 6094 u8 opcode[0x10]; 6095 u8 uid[0x10]; 6096 6097 u8 reserved_1[0x10]; 6098 u8 op_mod[0x10]; 6099 6100 u8 rq_state[0x4]; 6101 u8 reserved_2[0x4]; 6102 u8 rqn[0x18]; 6103 6104 u8 reserved_3[0x20]; 6105 6106 u8 modify_bitmask[0x40]; 6107 6108 u8 reserved_4[0x40]; 6109 6110 struct mlx5_ifc_rqc_bits ctx; 6111}; 6112 6113struct mlx5_ifc_modify_rmp_out_bits { 6114 u8 status[0x8]; 6115 u8 reserved_0[0x18]; 6116 6117 u8 syndrome[0x20]; 6118 6119 u8 reserved_1[0x40]; 6120}; 6121 6122struct mlx5_ifc_rmp_bitmask_bits { 6123 u8 reserved[0x20]; 6124 6125 u8 reserved1[0x1f]; 6126 u8 lwm[0x1]; 6127}; 6128 6129struct mlx5_ifc_modify_rmp_in_bits { 6130 u8 opcode[0x10]; 6131 u8 uid[0x10]; 6132 6133 u8 reserved_1[0x10]; 6134 u8 op_mod[0x10]; 6135 6136 u8 rmp_state[0x4]; 6137 u8 reserved_2[0x4]; 6138 u8 rmpn[0x18]; 6139 6140 u8 reserved_3[0x20]; 6141 6142 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6143 6144 u8 reserved_4[0x40]; 6145 6146 struct mlx5_ifc_rmpc_bits ctx; 6147}; 6148 6149struct mlx5_ifc_modify_nic_vport_context_out_bits { 6150 u8 status[0x8]; 6151 u8 reserved_0[0x18]; 6152 6153 u8 syndrome[0x20]; 6154 6155 u8 reserved_1[0x40]; 6156}; 6157 6158struct mlx5_ifc_modify_nic_vport_field_select_bits { 6159 u8 reserved_0[0x14]; 6160 u8 disable_uc_local_lb[0x1]; 6161 u8 disable_mc_local_lb[0x1]; 6162 u8 node_guid[0x1]; 6163 u8 port_guid[0x1]; 6164 u8 min_wqe_inline_mode[0x1]; 6165 u8 mtu[0x1]; 6166 u8 change_event[0x1]; 6167 u8 promisc[0x1]; 6168 u8 permanent_address[0x1]; 6169 u8 addresses_list[0x1]; 6170 u8 roce_en[0x1]; 6171 u8 reserved_1[0x1]; 6172}; 6173 6174struct mlx5_ifc_modify_nic_vport_context_in_bits { 6175 u8 opcode[0x10]; 6176 u8 reserved_0[0x10]; 6177 6178 u8 reserved_1[0x10]; 6179 u8 op_mod[0x10]; 6180 6181 u8 other_vport[0x1]; 6182 u8 reserved_2[0xf]; 6183 u8 vport_number[0x10]; 6184 6185 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 6186 6187 u8 reserved_3[0x780]; 6188 6189 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6190}; 6191 6192struct mlx5_ifc_modify_hca_vport_context_out_bits { 6193 u8 status[0x8]; 6194 u8 reserved_0[0x18]; 6195 6196 u8 syndrome[0x20]; 6197 6198 u8 reserved_1[0x40]; 6199}; 6200 6201struct mlx5_ifc_grh_bits { 6202 u8 ip_version[4]; 6203 u8 traffic_class[8]; 6204 u8 flow_label[20]; 6205 u8 payload_length[16]; 6206 u8 next_header[8]; 6207 u8 hop_limit[8]; 6208 u8 sgid[128]; 6209 u8 dgid[128]; 6210}; 6211 6212struct mlx5_ifc_bth_bits { 6213 u8 opcode[8]; 6214 u8 se[1]; 6215 u8 migreq[1]; 6216 u8 pad_count[2]; 6217 u8 tver[4]; 6218 u8 p_key[16]; 6219 u8 reserved8[8]; 6220 u8 dest_qp[24]; 6221 u8 ack_req[1]; 6222 u8 reserved7[7]; 6223 u8 psn[24]; 6224}; 6225 6226struct mlx5_ifc_aeth_bits { 6227 u8 syndrome[8]; 6228 u8 msn[24]; 6229}; 6230 6231struct mlx5_ifc_dceth_bits { 6232 u8 reserved0[8]; 6233 u8 session_id[24]; 6234 u8 reserved1[8]; 6235 u8 dci_dct[24]; 6236}; 6237 6238struct mlx5_ifc_modify_hca_vport_context_in_bits { 6239 u8 opcode[0x10]; 6240 u8 reserved_0[0x10]; 6241 6242 u8 reserved_1[0x10]; 6243 u8 op_mod[0x10]; 6244 6245 u8 other_vport[0x1]; 6246 u8 reserved_2[0xb]; 6247 u8 port_num[0x4]; 6248 u8 vport_number[0x10]; 6249 6250 u8 reserved_3[0x20]; 6251 6252 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6253}; 6254 6255struct mlx5_ifc_modify_flow_table_out_bits { 6256 u8 status[0x8]; 6257 u8 reserved_at_8[0x18]; 6258 6259 u8 syndrome[0x20]; 6260 6261 u8 reserved_at_40[0x40]; 6262}; 6263 6264enum { 6265 MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1, 6266 MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000, 6267}; 6268 6269struct mlx5_ifc_modify_flow_table_in_bits { 6270 u8 opcode[0x10]; 6271 u8 reserved_at_10[0x10]; 6272 6273 u8 reserved_at_20[0x10]; 6274 u8 op_mod[0x10]; 6275 6276 u8 other_vport[0x1]; 6277 u8 reserved_at_41[0xf]; 6278 u8 vport_number[0x10]; 6279 6280 u8 reserved_at_60[0x10]; 6281 u8 modify_field_select[0x10]; 6282 6283 u8 table_type[0x8]; 6284 u8 reserved_at_88[0x18]; 6285 6286 u8 reserved_at_a0[0x8]; 6287 u8 table_id[0x18]; 6288 6289 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6290}; 6291 6292struct mlx5_ifc_modify_esw_vport_context_out_bits { 6293 u8 status[0x8]; 6294 u8 reserved_0[0x18]; 6295 6296 u8 syndrome[0x20]; 6297 6298 u8 reserved_1[0x40]; 6299}; 6300 6301struct mlx5_ifc_esw_vport_context_fields_select_bits { 6302 u8 reserved[0x1c]; 6303 u8 vport_cvlan_insert[0x1]; 6304 u8 vport_svlan_insert[0x1]; 6305 u8 vport_cvlan_strip[0x1]; 6306 u8 vport_svlan_strip[0x1]; 6307}; 6308 6309struct mlx5_ifc_modify_esw_vport_context_in_bits { 6310 u8 opcode[0x10]; 6311 u8 reserved_0[0x10]; 6312 6313 u8 reserved_1[0x10]; 6314 u8 op_mod[0x10]; 6315 6316 u8 other_vport[0x1]; 6317 u8 reserved_2[0xf]; 6318 u8 vport_number[0x10]; 6319 6320 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6321 6322 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6323}; 6324 6325struct mlx5_ifc_modify_cq_out_bits { 6326 u8 status[0x8]; 6327 u8 reserved_0[0x18]; 6328 6329 u8 syndrome[0x20]; 6330 6331 u8 reserved_1[0x40]; 6332}; 6333 6334enum { 6335 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 6336 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 6337}; 6338 6339struct mlx5_ifc_modify_cq_in_bits { 6340 u8 opcode[0x10]; 6341 u8 uid[0x10]; 6342 6343 u8 reserved_1[0x10]; 6344 u8 op_mod[0x10]; 6345 6346 u8 reserved_2[0x8]; 6347 u8 cqn[0x18]; 6348 6349 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 6350 6351 struct mlx5_ifc_cqc_bits cq_context; 6352 6353 u8 reserved_at_280[0x60]; 6354 6355 u8 cq_umem_valid[0x1]; 6356 u8 reserved_at_2e1[0x1f]; 6357 6358 u8 reserved_at_300[0x580]; 6359 6360 u8 pas[0][0x40]; 6361}; 6362 6363struct mlx5_ifc_modify_cong_status_out_bits { 6364 u8 status[0x8]; 6365 u8 reserved_0[0x18]; 6366 6367 u8 syndrome[0x20]; 6368 6369 u8 reserved_1[0x40]; 6370}; 6371 6372struct mlx5_ifc_modify_cong_status_in_bits { 6373 u8 opcode[0x10]; 6374 u8 reserved_0[0x10]; 6375 6376 u8 reserved_1[0x10]; 6377 u8 op_mod[0x10]; 6378 6379 u8 reserved_2[0x18]; 6380 u8 priority[0x4]; 6381 u8 cong_protocol[0x4]; 6382 6383 u8 enable[0x1]; 6384 u8 tag_enable[0x1]; 6385 u8 reserved_3[0x1e]; 6386}; 6387 6388struct mlx5_ifc_modify_cong_params_out_bits { 6389 u8 status[0x8]; 6390 u8 reserved_0[0x18]; 6391 6392 u8 syndrome[0x20]; 6393 6394 u8 reserved_1[0x40]; 6395}; 6396 6397struct mlx5_ifc_modify_cong_params_in_bits { 6398 u8 opcode[0x10]; 6399 u8 reserved_0[0x10]; 6400 6401 u8 reserved_1[0x10]; 6402 u8 op_mod[0x10]; 6403 6404 u8 reserved_2[0x1c]; 6405 u8 cong_protocol[0x4]; 6406 6407 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 6408 6409 u8 reserved_3[0x80]; 6410 6411 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6412}; 6413 6414struct mlx5_ifc_manage_pages_out_bits { 6415 u8 status[0x8]; 6416 u8 reserved_0[0x18]; 6417 6418 u8 syndrome[0x20]; 6419 6420 u8 output_num_entries[0x20]; 6421 6422 u8 reserved_1[0x20]; 6423 6424 u8 pas[0][0x40]; 6425}; 6426 6427enum { 6428 MLX5_PAGES_CANT_GIVE = 0x0, 6429 MLX5_PAGES_GIVE = 0x1, 6430 MLX5_PAGES_TAKE = 0x2, 6431}; 6432 6433struct mlx5_ifc_manage_pages_in_bits { 6434 u8 opcode[0x10]; 6435 u8 reserved_0[0x10]; 6436 6437 u8 reserved_1[0x10]; 6438 u8 op_mod[0x10]; 6439 6440 u8 reserved_2[0x10]; 6441 u8 function_id[0x10]; 6442 6443 u8 input_num_entries[0x20]; 6444 6445 u8 pas[0][0x40]; 6446}; 6447 6448struct mlx5_ifc_mad_ifc_out_bits { 6449 u8 status[0x8]; 6450 u8 reserved_0[0x18]; 6451 6452 u8 syndrome[0x20]; 6453 6454 u8 reserved_1[0x40]; 6455 6456 u8 response_mad_packet[256][0x8]; 6457}; 6458 6459struct mlx5_ifc_mad_ifc_in_bits { 6460 u8 opcode[0x10]; 6461 u8 reserved_0[0x10]; 6462 6463 u8 reserved_1[0x10]; 6464 u8 op_mod[0x10]; 6465 6466 u8 remote_lid[0x10]; 6467 u8 reserved_2[0x8]; 6468 u8 port[0x8]; 6469 6470 u8 reserved_3[0x20]; 6471 6472 u8 mad[256][0x8]; 6473}; 6474 6475struct mlx5_ifc_init_hca_out_bits { 6476 u8 status[0x8]; 6477 u8 reserved_0[0x18]; 6478 6479 u8 syndrome[0x20]; 6480 6481 u8 reserved_1[0x40]; 6482}; 6483 6484enum { 6485 MLX5_INIT_HCA_IN_OP_MOD_INIT = 0x0, 6486 MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT = 0x1, 6487}; 6488 6489struct mlx5_ifc_init_hca_in_bits { 6490 u8 opcode[0x10]; 6491 u8 reserved_0[0x10]; 6492 6493 u8 reserved_1[0x10]; 6494 u8 op_mod[0x10]; 6495 6496 u8 reserved_2[0x40]; 6497}; 6498 6499struct mlx5_ifc_init2rtr_qp_out_bits { 6500 u8 status[0x8]; 6501 u8 reserved_0[0x18]; 6502 6503 u8 syndrome[0x20]; 6504 6505 u8 reserved_1[0x40]; 6506}; 6507 6508struct mlx5_ifc_init2rtr_qp_in_bits { 6509 u8 opcode[0x10]; 6510 u8 uid[0x10]; 6511 6512 u8 reserved_1[0x10]; 6513 u8 op_mod[0x10]; 6514 6515 u8 reserved_2[0x8]; 6516 u8 qpn[0x18]; 6517 6518 u8 reserved_3[0x20]; 6519 6520 u8 opt_param_mask[0x20]; 6521 6522 u8 reserved_4[0x20]; 6523 6524 struct mlx5_ifc_qpc_bits qpc; 6525 6526 u8 reserved_5[0x80]; 6527}; 6528 6529struct mlx5_ifc_init2init_qp_out_bits { 6530 u8 status[0x8]; 6531 u8 reserved_0[0x18]; 6532 6533 u8 syndrome[0x20]; 6534 6535 u8 reserved_1[0x40]; 6536}; 6537 6538struct mlx5_ifc_init2init_qp_in_bits { 6539 u8 opcode[0x10]; 6540 u8 uid[0x10]; 6541 6542 u8 reserved_1[0x10]; 6543 u8 op_mod[0x10]; 6544 6545 u8 reserved_2[0x8]; 6546 u8 qpn[0x18]; 6547 6548 u8 reserved_3[0x20]; 6549 6550 u8 opt_param_mask[0x20]; 6551 6552 u8 reserved_4[0x20]; 6553 6554 struct mlx5_ifc_qpc_bits qpc; 6555 6556 u8 reserved_5[0x80]; 6557}; 6558 6559struct mlx5_ifc_get_dropped_packet_log_out_bits { 6560 u8 status[0x8]; 6561 u8 reserved_0[0x18]; 6562 6563 u8 syndrome[0x20]; 6564 6565 u8 reserved_1[0x40]; 6566 6567 u8 packet_headers_log[128][0x8]; 6568 6569 u8 packet_syndrome[64][0x8]; 6570}; 6571 6572struct mlx5_ifc_get_dropped_packet_log_in_bits { 6573 u8 opcode[0x10]; 6574 u8 reserved_0[0x10]; 6575 6576 u8 reserved_1[0x10]; 6577 u8 op_mod[0x10]; 6578 6579 u8 reserved_2[0x40]; 6580}; 6581 6582struct mlx5_ifc_encryption_key_obj_bits { 6583 u8 modify_field_select[0x40]; 6584 6585 u8 reserved_at_40[0x14]; 6586 u8 key_size[0x4]; 6587 u8 reserved_at_58[0x4]; 6588 u8 key_type[0x4]; 6589 6590 u8 reserved_at_60[0x8]; 6591 u8 pd[0x18]; 6592 6593 u8 reserved_at_80[0x180]; 6594 6595 u8 key[8][0x20]; 6596 6597 u8 reserved_at_300[0x500]; 6598}; 6599 6600struct mlx5_ifc_gen_eqe_in_bits { 6601 u8 opcode[0x10]; 6602 u8 reserved_0[0x10]; 6603 6604 u8 reserved_1[0x10]; 6605 u8 op_mod[0x10]; 6606 6607 u8 reserved_2[0x18]; 6608 u8 eq_number[0x8]; 6609 6610 u8 reserved_3[0x20]; 6611 6612 u8 eqe[64][0x8]; 6613}; 6614 6615struct mlx5_ifc_gen_eq_out_bits { 6616 u8 status[0x8]; 6617 u8 reserved_0[0x18]; 6618 6619 u8 syndrome[0x20]; 6620 6621 u8 reserved_1[0x40]; 6622}; 6623 6624struct mlx5_ifc_enable_hca_out_bits { 6625 u8 status[0x8]; 6626 u8 reserved_0[0x18]; 6627 6628 u8 syndrome[0x20]; 6629 6630 u8 reserved_1[0x20]; 6631}; 6632 6633struct mlx5_ifc_enable_hca_in_bits { 6634 u8 opcode[0x10]; 6635 u8 reserved_0[0x10]; 6636 6637 u8 reserved_1[0x10]; 6638 u8 op_mod[0x10]; 6639 6640 u8 reserved_2[0x10]; 6641 u8 function_id[0x10]; 6642 6643 u8 reserved_3[0x20]; 6644}; 6645 6646struct mlx5_ifc_drain_dct_out_bits { 6647 u8 status[0x8]; 6648 u8 reserved_0[0x18]; 6649 6650 u8 syndrome[0x20]; 6651 6652 u8 reserved_1[0x40]; 6653}; 6654 6655struct mlx5_ifc_drain_dct_in_bits { 6656 u8 opcode[0x10]; 6657 u8 uid[0x10]; 6658 6659 u8 reserved_1[0x10]; 6660 u8 op_mod[0x10]; 6661 6662 u8 reserved_2[0x8]; 6663 u8 dctn[0x18]; 6664 6665 u8 reserved_3[0x20]; 6666}; 6667 6668struct mlx5_ifc_disable_hca_out_bits { 6669 u8 status[0x8]; 6670 u8 reserved_0[0x18]; 6671 6672 u8 syndrome[0x20]; 6673 6674 u8 reserved_1[0x20]; 6675}; 6676 6677struct mlx5_ifc_disable_hca_in_bits { 6678 u8 opcode[0x10]; 6679 u8 reserved_0[0x10]; 6680 6681 u8 reserved_1[0x10]; 6682 u8 op_mod[0x10]; 6683 6684 u8 reserved_2[0x10]; 6685 u8 function_id[0x10]; 6686 6687 u8 reserved_3[0x20]; 6688}; 6689 6690struct mlx5_ifc_detach_from_mcg_out_bits { 6691 u8 status[0x8]; 6692 u8 reserved_0[0x18]; 6693 6694 u8 syndrome[0x20]; 6695 6696 u8 reserved_1[0x40]; 6697}; 6698 6699struct mlx5_ifc_detach_from_mcg_in_bits { 6700 u8 opcode[0x10]; 6701 u8 uid[0x10]; 6702 6703 u8 reserved_1[0x10]; 6704 u8 op_mod[0x10]; 6705 6706 u8 reserved_2[0x8]; 6707 u8 qpn[0x18]; 6708 6709 u8 reserved_3[0x20]; 6710 6711 u8 multicast_gid[16][0x8]; 6712}; 6713 6714struct mlx5_ifc_destroy_xrc_srq_out_bits { 6715 u8 status[0x8]; 6716 u8 reserved_0[0x18]; 6717 6718 u8 syndrome[0x20]; 6719 6720 u8 reserved_1[0x40]; 6721}; 6722 6723struct mlx5_ifc_destroy_xrc_srq_in_bits { 6724 u8 opcode[0x10]; 6725 u8 uid[0x10]; 6726 6727 u8 reserved_1[0x10]; 6728 u8 op_mod[0x10]; 6729 6730 u8 reserved_2[0x8]; 6731 u8 xrc_srqn[0x18]; 6732 6733 u8 reserved_3[0x20]; 6734}; 6735 6736struct mlx5_ifc_destroy_tis_out_bits { 6737 u8 status[0x8]; 6738 u8 reserved_0[0x18]; 6739 6740 u8 syndrome[0x20]; 6741 6742 u8 reserved_1[0x40]; 6743}; 6744 6745struct mlx5_ifc_destroy_tis_in_bits { 6746 u8 opcode[0x10]; 6747 u8 uid[0x10]; 6748 6749 u8 reserved_1[0x10]; 6750 u8 op_mod[0x10]; 6751 6752 u8 reserved_2[0x8]; 6753 u8 tisn[0x18]; 6754 6755 u8 reserved_3[0x20]; 6756}; 6757 6758struct mlx5_ifc_destroy_tir_out_bits { 6759 u8 status[0x8]; 6760 u8 reserved_0[0x18]; 6761 6762 u8 syndrome[0x20]; 6763 6764 u8 reserved_1[0x40]; 6765}; 6766 6767struct mlx5_ifc_destroy_tir_in_bits { 6768 u8 opcode[0x10]; 6769 u8 uid[0x10]; 6770 6771 u8 reserved_1[0x10]; 6772 u8 op_mod[0x10]; 6773 6774 u8 reserved_2[0x8]; 6775 u8 tirn[0x18]; 6776 6777 u8 reserved_3[0x20]; 6778}; 6779 6780struct mlx5_ifc_destroy_srq_out_bits { 6781 u8 status[0x8]; 6782 u8 reserved_0[0x18]; 6783 6784 u8 syndrome[0x20]; 6785 6786 u8 reserved_1[0x40]; 6787}; 6788 6789struct mlx5_ifc_destroy_srq_in_bits { 6790 u8 opcode[0x10]; 6791 u8 uid[0x10]; 6792 6793 u8 reserved_1[0x10]; 6794 u8 op_mod[0x10]; 6795 6796 u8 reserved_2[0x8]; 6797 u8 srqn[0x18]; 6798 6799 u8 reserved_3[0x20]; 6800}; 6801 6802struct mlx5_ifc_destroy_sq_out_bits { 6803 u8 status[0x8]; 6804 u8 reserved_0[0x18]; 6805 6806 u8 syndrome[0x20]; 6807 6808 u8 reserved_1[0x40]; 6809}; 6810 6811struct mlx5_ifc_destroy_sq_in_bits { 6812 u8 opcode[0x10]; 6813 u8 uid[0x10]; 6814 6815 u8 reserved_1[0x10]; 6816 u8 op_mod[0x10]; 6817 6818 u8 reserved_2[0x8]; 6819 u8 sqn[0x18]; 6820 6821 u8 reserved_3[0x20]; 6822}; 6823 6824struct mlx5_ifc_destroy_scheduling_element_out_bits { 6825 u8 status[0x8]; 6826 u8 reserved_at_8[0x18]; 6827 6828 u8 syndrome[0x20]; 6829 6830 u8 reserved_at_40[0x1c0]; 6831}; 6832 6833enum { 6834 MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6835}; 6836 6837struct mlx5_ifc_destroy_scheduling_element_in_bits { 6838 u8 opcode[0x10]; 6839 u8 reserved_at_10[0x10]; 6840 6841 u8 reserved_at_20[0x10]; 6842 u8 op_mod[0x10]; 6843 6844 u8 scheduling_hierarchy[0x8]; 6845 u8 reserved_at_48[0x18]; 6846 6847 u8 scheduling_element_id[0x20]; 6848 6849 u8 reserved_at_80[0x180]; 6850}; 6851 6852struct mlx5_ifc_destroy_rqt_out_bits { 6853 u8 status[0x8]; 6854 u8 reserved_0[0x18]; 6855 6856 u8 syndrome[0x20]; 6857 6858 u8 reserved_1[0x40]; 6859}; 6860 6861struct mlx5_ifc_destroy_rqt_in_bits { 6862 u8 opcode[0x10]; 6863 u8 uid[0x10]; 6864 6865 u8 reserved_1[0x10]; 6866 u8 op_mod[0x10]; 6867 6868 u8 reserved_2[0x8]; 6869 u8 rqtn[0x18]; 6870 6871 u8 reserved_3[0x20]; 6872}; 6873 6874struct mlx5_ifc_destroy_rq_out_bits { 6875 u8 status[0x8]; 6876 u8 reserved_0[0x18]; 6877 6878 u8 syndrome[0x20]; 6879 6880 u8 reserved_1[0x40]; 6881}; 6882 6883struct mlx5_ifc_destroy_rq_in_bits { 6884 u8 opcode[0x10]; 6885 u8 uid[0x10]; 6886 6887 u8 reserved_1[0x10]; 6888 u8 op_mod[0x10]; 6889 6890 u8 reserved_2[0x8]; 6891 u8 rqn[0x18]; 6892 6893 u8 reserved_3[0x20]; 6894}; 6895 6896struct mlx5_ifc_destroy_rmp_out_bits { 6897 u8 status[0x8]; 6898 u8 reserved_0[0x18]; 6899 6900 u8 syndrome[0x20]; 6901 6902 u8 reserved_1[0x40]; 6903}; 6904 6905struct mlx5_ifc_destroy_rmp_in_bits { 6906 u8 opcode[0x10]; 6907 u8 reserved_0[0x10]; 6908 6909 u8 reserved_1[0x10]; 6910 u8 op_mod[0x10]; 6911 6912 u8 reserved_2[0x8]; 6913 u8 rmpn[0x18]; 6914 6915 u8 reserved_3[0x20]; 6916}; 6917 6918struct mlx5_ifc_destroy_qp_out_bits { 6919 u8 status[0x8]; 6920 u8 reserved_0[0x18]; 6921 6922 u8 syndrome[0x20]; 6923 6924 u8 reserved_1[0x40]; 6925}; 6926 6927struct mlx5_ifc_destroy_qp_in_bits { 6928 u8 opcode[0x10]; 6929 u8 uid[0x10]; 6930 6931 u8 reserved_1[0x10]; 6932 u8 op_mod[0x10]; 6933 6934 u8 reserved_2[0x8]; 6935 u8 qpn[0x18]; 6936 6937 u8 reserved_3[0x20]; 6938}; 6939 6940struct mlx5_ifc_destroy_qos_para_vport_out_bits { 6941 u8 status[0x8]; 6942 u8 reserved_at_8[0x18]; 6943 6944 u8 syndrome[0x20]; 6945 6946 u8 reserved_at_40[0x1c0]; 6947}; 6948 6949struct mlx5_ifc_destroy_qos_para_vport_in_bits { 6950 u8 opcode[0x10]; 6951 u8 reserved_at_10[0x10]; 6952 6953 u8 reserved_at_20[0x10]; 6954 u8 op_mod[0x10]; 6955 6956 u8 reserved_at_40[0x20]; 6957 6958 u8 reserved_at_60[0x10]; 6959 u8 qos_para_vport_number[0x10]; 6960 6961 u8 reserved_at_80[0x180]; 6962}; 6963 6964struct mlx5_ifc_destroy_psv_out_bits { 6965 u8 status[0x8]; 6966 u8 reserved_0[0x18]; 6967 6968 u8 syndrome[0x20]; 6969 6970 u8 reserved_1[0x40]; 6971}; 6972 6973struct mlx5_ifc_destroy_psv_in_bits { 6974 u8 opcode[0x10]; 6975 u8 reserved_0[0x10]; 6976 6977 u8 reserved_1[0x10]; 6978 u8 op_mod[0x10]; 6979 6980 u8 reserved_2[0x8]; 6981 u8 psvn[0x18]; 6982 6983 u8 reserved_3[0x20]; 6984}; 6985 6986struct mlx5_ifc_destroy_mkey_out_bits { 6987 u8 status[0x8]; 6988 u8 reserved_0[0x18]; 6989 6990 u8 syndrome[0x20]; 6991 6992 u8 reserved_1[0x40]; 6993}; 6994 6995struct mlx5_ifc_destroy_mkey_in_bits { 6996 u8 opcode[0x10]; 6997 u8 reserved_0[0x10]; 6998 6999 u8 reserved_1[0x10]; 7000 u8 op_mod[0x10]; 7001 7002 u8 reserved_2[0x8]; 7003 u8 mkey_index[0x18]; 7004 7005 u8 reserved_3[0x20]; 7006}; 7007 7008struct mlx5_ifc_destroy_flow_table_out_bits { 7009 u8 status[0x8]; 7010 u8 reserved_0[0x18]; 7011 7012 u8 syndrome[0x20]; 7013 7014 u8 reserved_1[0x40]; 7015}; 7016 7017struct mlx5_ifc_destroy_flow_table_in_bits { 7018 u8 opcode[0x10]; 7019 u8 reserved_0[0x10]; 7020 7021 u8 reserved_1[0x10]; 7022 u8 op_mod[0x10]; 7023 7024 u8 other_vport[0x1]; 7025 u8 reserved_2[0xf]; 7026 u8 vport_number[0x10]; 7027 7028 u8 reserved_3[0x20]; 7029 7030 u8 table_type[0x8]; 7031 u8 reserved_4[0x18]; 7032 7033 u8 reserved_5[0x8]; 7034 u8 table_id[0x18]; 7035 7036 u8 reserved_6[0x140]; 7037}; 7038 7039struct mlx5_ifc_destroy_flow_group_out_bits { 7040 u8 status[0x8]; 7041 u8 reserved_0[0x18]; 7042 7043 u8 syndrome[0x20]; 7044 7045 u8 reserved_1[0x40]; 7046}; 7047 7048struct mlx5_ifc_destroy_flow_group_in_bits { 7049 u8 opcode[0x10]; 7050 u8 reserved_0[0x10]; 7051 7052 u8 reserved_1[0x10]; 7053 u8 op_mod[0x10]; 7054 7055 u8 other_vport[0x1]; 7056 u8 reserved_2[0xf]; 7057 u8 vport_number[0x10]; 7058 7059 u8 reserved_3[0x20]; 7060 7061 u8 table_type[0x8]; 7062 u8 reserved_4[0x18]; 7063 7064 u8 reserved_5[0x8]; 7065 u8 table_id[0x18]; 7066 7067 u8 group_id[0x20]; 7068 7069 u8 reserved_6[0x120]; 7070}; 7071 7072struct mlx5_ifc_destroy_encryption_key_out_bits { 7073 u8 status[0x8]; 7074 u8 reserved_at_8[0x18]; 7075 7076 u8 syndrome[0x20]; 7077 7078 u8 reserved_at_40[0x40]; 7079}; 7080 7081struct mlx5_ifc_destroy_encryption_key_in_bits { 7082 u8 opcode[0x10]; 7083 u8 reserved_at_10[0x10]; 7084 7085 u8 reserved_at_20[0x10]; 7086 u8 obj_type[0x10]; 7087 7088 u8 obj_id[0x20]; 7089 7090 u8 reserved_at_60[0x20]; 7091}; 7092 7093struct mlx5_ifc_destroy_eq_out_bits { 7094 u8 status[0x8]; 7095 u8 reserved_0[0x18]; 7096 7097 u8 syndrome[0x20]; 7098 7099 u8 reserved_1[0x40]; 7100}; 7101 7102struct mlx5_ifc_destroy_eq_in_bits { 7103 u8 opcode[0x10]; 7104 u8 reserved_0[0x10]; 7105 7106 u8 reserved_1[0x10]; 7107 u8 op_mod[0x10]; 7108 7109 u8 reserved_2[0x18]; 7110 u8 eq_number[0x8]; 7111 7112 u8 reserved_3[0x20]; 7113}; 7114 7115struct mlx5_ifc_destroy_dct_out_bits { 7116 u8 status[0x8]; 7117 u8 reserved_0[0x18]; 7118 7119 u8 syndrome[0x20]; 7120 7121 u8 reserved_1[0x40]; 7122}; 7123 7124struct mlx5_ifc_destroy_dct_in_bits { 7125 u8 opcode[0x10]; 7126 u8 uid[0x10]; 7127 7128 u8 reserved_1[0x10]; 7129 u8 op_mod[0x10]; 7130 7131 u8 reserved_2[0x8]; 7132 u8 dctn[0x18]; 7133 7134 u8 reserved_3[0x20]; 7135}; 7136 7137struct mlx5_ifc_destroy_cq_out_bits { 7138 u8 status[0x8]; 7139 u8 reserved_0[0x18]; 7140 7141 u8 syndrome[0x20]; 7142 7143 u8 reserved_1[0x40]; 7144}; 7145 7146struct mlx5_ifc_destroy_cq_in_bits { 7147 u8 opcode[0x10]; 7148 u8 uid[0x10]; 7149 7150 u8 reserved_1[0x10]; 7151 u8 op_mod[0x10]; 7152 7153 u8 reserved_2[0x8]; 7154 u8 cqn[0x18]; 7155 7156 u8 reserved_3[0x20]; 7157}; 7158 7159struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7160 u8 status[0x8]; 7161 u8 reserved_0[0x18]; 7162 7163 u8 syndrome[0x20]; 7164 7165 u8 reserved_1[0x40]; 7166}; 7167 7168struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7169 u8 opcode[0x10]; 7170 u8 reserved_0[0x10]; 7171 7172 u8 reserved_1[0x10]; 7173 u8 op_mod[0x10]; 7174 7175 u8 reserved_2[0x20]; 7176 7177 u8 reserved_3[0x10]; 7178 u8 vxlan_udp_port[0x10]; 7179}; 7180 7181struct mlx5_ifc_delete_l2_table_entry_out_bits { 7182 u8 status[0x8]; 7183 u8 reserved_0[0x18]; 7184 7185 u8 syndrome[0x20]; 7186 7187 u8 reserved_1[0x40]; 7188}; 7189 7190struct mlx5_ifc_delete_l2_table_entry_in_bits { 7191 u8 opcode[0x10]; 7192 u8 reserved_0[0x10]; 7193 7194 u8 reserved_1[0x10]; 7195 u8 op_mod[0x10]; 7196 7197 u8 reserved_2[0x60]; 7198 7199 u8 reserved_3[0x8]; 7200 u8 table_index[0x18]; 7201 7202 u8 reserved_4[0x140]; 7203}; 7204 7205struct mlx5_ifc_delete_fte_out_bits { 7206 u8 status[0x8]; 7207 u8 reserved_0[0x18]; 7208 7209 u8 syndrome[0x20]; 7210 7211 u8 reserved_1[0x40]; 7212}; 7213 7214struct mlx5_ifc_delete_fte_in_bits { 7215 u8 opcode[0x10]; 7216 u8 reserved_0[0x10]; 7217 7218 u8 reserved_1[0x10]; 7219 u8 op_mod[0x10]; 7220 7221 u8 other_vport[0x1]; 7222 u8 reserved_2[0xf]; 7223 u8 vport_number[0x10]; 7224 7225 u8 reserved_3[0x20]; 7226 7227 u8 table_type[0x8]; 7228 u8 reserved_4[0x18]; 7229 7230 u8 reserved_5[0x8]; 7231 u8 table_id[0x18]; 7232 7233 u8 reserved_6[0x40]; 7234 7235 u8 flow_index[0x20]; 7236 7237 u8 reserved_7[0xe0]; 7238}; 7239 7240struct mlx5_ifc_dealloc_xrcd_out_bits { 7241 u8 status[0x8]; 7242 u8 reserved_0[0x18]; 7243 7244 u8 syndrome[0x20]; 7245 7246 u8 reserved_1[0x40]; 7247}; 7248 7249struct mlx5_ifc_dealloc_xrcd_in_bits { 7250 u8 opcode[0x10]; 7251 u8 uid[0x10]; 7252 7253 u8 reserved_1[0x10]; 7254 u8 op_mod[0x10]; 7255 7256 u8 reserved_2[0x8]; 7257 u8 xrcd[0x18]; 7258 7259 u8 reserved_3[0x20]; 7260}; 7261 7262struct mlx5_ifc_dealloc_uar_out_bits { 7263 u8 status[0x8]; 7264 u8 reserved_0[0x18]; 7265 7266 u8 syndrome[0x20]; 7267 7268 u8 reserved_1[0x40]; 7269}; 7270 7271struct mlx5_ifc_dealloc_uar_in_bits { 7272 u8 opcode[0x10]; 7273 u8 reserved_0[0x10]; 7274 7275 u8 reserved_1[0x10]; 7276 u8 op_mod[0x10]; 7277 7278 u8 reserved_2[0x8]; 7279 u8 uar[0x18]; 7280 7281 u8 reserved_3[0x20]; 7282}; 7283 7284struct mlx5_ifc_dealloc_transport_domain_out_bits { 7285 u8 status[0x8]; 7286 u8 reserved_0[0x18]; 7287 7288 u8 syndrome[0x20]; 7289 7290 u8 reserved_1[0x40]; 7291}; 7292 7293struct mlx5_ifc_dealloc_transport_domain_in_bits { 7294 u8 opcode[0x10]; 7295 u8 uid[0x10]; 7296 7297 u8 reserved_1[0x10]; 7298 u8 op_mod[0x10]; 7299 7300 u8 reserved_2[0x8]; 7301 u8 transport_domain[0x18]; 7302 7303 u8 reserved_3[0x20]; 7304}; 7305 7306struct mlx5_ifc_dealloc_q_counter_out_bits { 7307 u8 status[0x8]; 7308 u8 reserved_0[0x18]; 7309 7310 u8 syndrome[0x20]; 7311 7312 u8 reserved_1[0x40]; 7313}; 7314 7315struct mlx5_ifc_counter_id_bits { 7316 u8 reserved[0x10]; 7317 u8 counter_id[0x10]; 7318}; 7319 7320struct mlx5_ifc_diagnostic_params_context_bits { 7321 u8 num_of_counters[0x10]; 7322 u8 reserved_2[0x8]; 7323 u8 log_num_of_samples[0x8]; 7324 7325 u8 single[0x1]; 7326 u8 repetitive[0x1]; 7327 u8 sync[0x1]; 7328 u8 clear[0x1]; 7329 u8 on_demand[0x1]; 7330 u8 enable[0x1]; 7331 u8 reserved_3[0x12]; 7332 u8 log_sample_period[0x8]; 7333 7334 u8 reserved_4[0x80]; 7335 7336 struct mlx5_ifc_counter_id_bits counter_id[0]; 7337}; 7338 7339struct mlx5_ifc_query_diagnostic_params_in_bits { 7340 u8 opcode[0x10]; 7341 u8 reserved_at_10[0x10]; 7342 7343 u8 reserved_at_20[0x10]; 7344 u8 op_mod[0x10]; 7345 7346 u8 reserved_at_40[0x40]; 7347}; 7348 7349struct mlx5_ifc_query_diagnostic_params_out_bits { 7350 u8 status[0x8]; 7351 u8 reserved_at_8[0x18]; 7352 7353 u8 syndrome[0x20]; 7354 7355 struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx; 7356}; 7357 7358struct mlx5_ifc_set_diagnostic_params_in_bits { 7359 u8 opcode[0x10]; 7360 u8 reserved_0[0x10]; 7361 7362 u8 reserved_1[0x10]; 7363 u8 op_mod[0x10]; 7364 7365 struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx; 7366}; 7367 7368struct mlx5_ifc_set_diagnostic_params_out_bits { 7369 u8 status[0x8]; 7370 u8 reserved_0[0x18]; 7371 7372 u8 syndrome[0x20]; 7373 7374 u8 reserved_1[0x40]; 7375}; 7376 7377struct mlx5_ifc_query_diagnostic_counters_in_bits { 7378 u8 opcode[0x10]; 7379 u8 reserved_0[0x10]; 7380 7381 u8 reserved_1[0x10]; 7382 u8 op_mod[0x10]; 7383 7384 u8 num_of_samples[0x10]; 7385 u8 sample_index[0x10]; 7386 7387 u8 reserved_2[0x20]; 7388}; 7389 7390struct mlx5_ifc_diagnostic_counter_bits { 7391 u8 counter_id[0x10]; 7392 u8 sample_id[0x10]; 7393 7394 u8 time_stamp_31_0[0x20]; 7395 7396 u8 counter_value_h[0x20]; 7397 7398 u8 counter_value_l[0x20]; 7399}; 7400 7401struct mlx5_ifc_query_diagnostic_counters_out_bits { 7402 u8 status[0x8]; 7403 u8 reserved_0[0x18]; 7404 7405 u8 syndrome[0x20]; 7406 7407 u8 reserved_1[0x40]; 7408 7409 struct mlx5_ifc_diagnostic_counter_bits diag_counter[0]; 7410}; 7411 7412struct mlx5_ifc_dealloc_q_counter_in_bits { 7413 u8 opcode[0x10]; 7414 u8 reserved_0[0x10]; 7415 7416 u8 reserved_1[0x10]; 7417 u8 op_mod[0x10]; 7418 7419 u8 reserved_2[0x18]; 7420 u8 counter_set_id[0x8]; 7421 7422 u8 reserved_3[0x20]; 7423}; 7424 7425struct mlx5_ifc_dealloc_pd_out_bits { 7426 u8 status[0x8]; 7427 u8 reserved_0[0x18]; 7428 7429 u8 syndrome[0x20]; 7430 7431 u8 reserved_1[0x40]; 7432}; 7433 7434struct mlx5_ifc_dealloc_pd_in_bits { 7435 u8 opcode[0x10]; 7436 u8 uid[0x10]; 7437 7438 u8 reserved_1[0x10]; 7439 u8 op_mod[0x10]; 7440 7441 u8 reserved_2[0x8]; 7442 u8 pd[0x18]; 7443 7444 u8 reserved_3[0x20]; 7445}; 7446 7447struct mlx5_ifc_dealloc_flow_counter_out_bits { 7448 u8 status[0x8]; 7449 u8 reserved_0[0x18]; 7450 7451 u8 syndrome[0x20]; 7452 7453 u8 reserved_1[0x40]; 7454}; 7455 7456struct mlx5_ifc_dealloc_flow_counter_in_bits { 7457 u8 opcode[0x10]; 7458 u8 reserved_0[0x10]; 7459 7460 u8 reserved_1[0x10]; 7461 u8 op_mod[0x10]; 7462 7463 u8 flow_counter_id[0x20]; 7464 7465 u8 reserved_3[0x20]; 7466}; 7467 7468struct mlx5_ifc_create_xrq_out_bits { 7469 u8 status[0x8]; 7470 u8 reserved_at_8[0x18]; 7471 7472 u8 syndrome[0x20]; 7473 7474 u8 reserved_at_40[0x8]; 7475 u8 xrqn[0x18]; 7476 7477 u8 reserved_at_60[0x20]; 7478}; 7479 7480struct mlx5_ifc_create_xrq_in_bits { 7481 u8 opcode[0x10]; 7482 u8 uid[0x10]; 7483 7484 u8 reserved_at_20[0x10]; 7485 u8 op_mod[0x10]; 7486 7487 u8 reserved_at_40[0x40]; 7488 7489 struct mlx5_ifc_xrqc_bits xrq_context; 7490}; 7491 7492struct mlx5_ifc_deactivate_tracer_out_bits { 7493 u8 status[0x8]; 7494 u8 reserved_0[0x18]; 7495 7496 u8 syndrome[0x20]; 7497 7498 u8 reserved_1[0x40]; 7499}; 7500 7501struct mlx5_ifc_deactivate_tracer_in_bits { 7502 u8 opcode[0x10]; 7503 u8 reserved_0[0x10]; 7504 7505 u8 reserved_1[0x10]; 7506 u8 op_mod[0x10]; 7507 7508 u8 mkey[0x20]; 7509 7510 u8 reserved_2[0x20]; 7511}; 7512 7513struct mlx5_ifc_create_xrc_srq_out_bits { 7514 u8 status[0x8]; 7515 u8 reserved_0[0x18]; 7516 7517 u8 syndrome[0x20]; 7518 7519 u8 reserved_1[0x8]; 7520 u8 xrc_srqn[0x18]; 7521 7522 u8 reserved_2[0x20]; 7523}; 7524 7525struct mlx5_ifc_create_xrc_srq_in_bits { 7526 u8 opcode[0x10]; 7527 u8 uid[0x10]; 7528 7529 u8 reserved_1[0x10]; 7530 u8 op_mod[0x10]; 7531 7532 u8 reserved_2[0x40]; 7533 7534 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 7535 7536 u8 reserved_at_280[0x60]; 7537 7538 u8 xrc_srq_umem_valid[0x1]; 7539 u8 reserved_at_2e1[0x1f]; 7540 7541 u8 reserved_at_300[0x580]; 7542 7543 u8 pas[0][0x40]; 7544}; 7545 7546struct mlx5_ifc_create_tis_out_bits { 7547 u8 status[0x8]; 7548 u8 reserved_0[0x18]; 7549 7550 u8 syndrome[0x20]; 7551 7552 u8 reserved_1[0x8]; 7553 u8 tisn[0x18]; 7554 7555 u8 reserved_2[0x20]; 7556}; 7557 7558struct mlx5_ifc_create_tis_in_bits { 7559 u8 opcode[0x10]; 7560 u8 uid[0x10]; 7561 7562 u8 reserved_1[0x10]; 7563 u8 op_mod[0x10]; 7564 7565 u8 reserved_2[0xc0]; 7566 7567 struct mlx5_ifc_tisc_bits ctx; 7568}; 7569 7570struct mlx5_ifc_create_tir_out_bits { 7571 u8 status[0x8]; 7572 u8 reserved_0[0x18]; 7573 7574 u8 syndrome[0x20]; 7575 7576 u8 reserved_1[0x8]; 7577 u8 tirn[0x18]; 7578 7579 u8 reserved_2[0x20]; 7580}; 7581 7582struct mlx5_ifc_create_tir_in_bits { 7583 u8 opcode[0x10]; 7584 u8 uid[0x10]; 7585 7586 u8 reserved_1[0x10]; 7587 u8 op_mod[0x10]; 7588 7589 u8 reserved_2[0xc0]; 7590 7591 struct mlx5_ifc_tirc_bits tir_context; 7592}; 7593 7594struct mlx5_ifc_create_srq_out_bits { 7595 u8 status[0x8]; 7596 u8 reserved_0[0x18]; 7597 7598 u8 syndrome[0x20]; 7599 7600 u8 reserved_1[0x8]; 7601 u8 srqn[0x18]; 7602 7603 u8 reserved_2[0x20]; 7604}; 7605 7606struct mlx5_ifc_create_srq_in_bits { 7607 u8 opcode[0x10]; 7608 u8 uid[0x10]; 7609 7610 u8 reserved_1[0x10]; 7611 u8 op_mod[0x10]; 7612 7613 u8 reserved_2[0x40]; 7614 7615 struct mlx5_ifc_srqc_bits srq_context_entry; 7616 7617 u8 reserved_3[0x600]; 7618 7619 u8 pas[0][0x40]; 7620}; 7621 7622struct mlx5_ifc_create_sq_out_bits { 7623 u8 status[0x8]; 7624 u8 reserved_0[0x18]; 7625 7626 u8 syndrome[0x20]; 7627 7628 u8 reserved_1[0x8]; 7629 u8 sqn[0x18]; 7630 7631 u8 reserved_2[0x20]; 7632}; 7633 7634struct mlx5_ifc_create_sq_in_bits { 7635 u8 opcode[0x10]; 7636 u8 uid[0x10]; 7637 7638 u8 reserved_1[0x10]; 7639 u8 op_mod[0x10]; 7640 7641 u8 reserved_2[0xc0]; 7642 7643 struct mlx5_ifc_sqc_bits ctx; 7644}; 7645 7646struct mlx5_ifc_create_scheduling_element_out_bits { 7647 u8 status[0x8]; 7648 u8 reserved_at_8[0x18]; 7649 7650 u8 syndrome[0x20]; 7651 7652 u8 reserved_at_40[0x40]; 7653 7654 u8 scheduling_element_id[0x20]; 7655 7656 u8 reserved_at_a0[0x160]; 7657}; 7658 7659enum { 7660 MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 7661}; 7662 7663struct mlx5_ifc_create_scheduling_element_in_bits { 7664 u8 opcode[0x10]; 7665 u8 reserved_at_10[0x10]; 7666 7667 u8 reserved_at_20[0x10]; 7668 u8 op_mod[0x10]; 7669 7670 u8 scheduling_hierarchy[0x8]; 7671 u8 reserved_at_48[0x18]; 7672 7673 u8 reserved_at_60[0xa0]; 7674 7675 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7676 7677 u8 reserved_at_300[0x100]; 7678}; 7679 7680struct mlx5_ifc_create_rqt_out_bits { 7681 u8 status[0x8]; 7682 u8 reserved_0[0x18]; 7683 7684 u8 syndrome[0x20]; 7685 7686 u8 reserved_1[0x8]; 7687 u8 rqtn[0x18]; 7688 7689 u8 reserved_2[0x20]; 7690}; 7691 7692struct mlx5_ifc_create_rqt_in_bits { 7693 u8 opcode[0x10]; 7694 u8 uid[0x10]; 7695 7696 u8 reserved_1[0x10]; 7697 u8 op_mod[0x10]; 7698 7699 u8 reserved_2[0xc0]; 7700 7701 struct mlx5_ifc_rqtc_bits rqt_context; 7702}; 7703 7704struct mlx5_ifc_create_rq_out_bits { 7705 u8 status[0x8]; 7706 u8 reserved_0[0x18]; 7707 7708 u8 syndrome[0x20]; 7709 7710 u8 reserved_1[0x8]; 7711 u8 rqn[0x18]; 7712 7713 u8 reserved_2[0x20]; 7714}; 7715 7716struct mlx5_ifc_create_rq_in_bits { 7717 u8 opcode[0x10]; 7718 u8 uid[0x10]; 7719 7720 u8 reserved_1[0x10]; 7721 u8 op_mod[0x10]; 7722 7723 u8 reserved_2[0xc0]; 7724 7725 struct mlx5_ifc_rqc_bits ctx; 7726}; 7727 7728struct mlx5_ifc_create_rmp_out_bits { 7729 u8 status[0x8]; 7730 u8 reserved_0[0x18]; 7731 7732 u8 syndrome[0x20]; 7733 7734 u8 reserved_1[0x8]; 7735 u8 rmpn[0x18]; 7736 7737 u8 reserved_2[0x20]; 7738}; 7739 7740struct mlx5_ifc_create_rmp_in_bits { 7741 u8 opcode[0x10]; 7742 u8 uid[0x10]; 7743 7744 u8 reserved_1[0x10]; 7745 u8 op_mod[0x10]; 7746 7747 u8 reserved_2[0xc0]; 7748 7749 struct mlx5_ifc_rmpc_bits ctx; 7750}; 7751 7752struct mlx5_ifc_create_qp_out_bits { 7753 u8 status[0x8]; 7754 u8 reserved_0[0x18]; 7755 7756 u8 syndrome[0x20]; 7757 7758 u8 reserved_1[0x8]; 7759 u8 qpn[0x18]; 7760 7761 u8 reserved_2[0x20]; 7762}; 7763 7764struct mlx5_ifc_create_qp_in_bits { 7765 u8 opcode[0x10]; 7766 u8 uid[0x10]; 7767 7768 u8 reserved_1[0x10]; 7769 u8 op_mod[0x10]; 7770 7771 u8 reserved_2[0x8]; 7772 u8 input_qpn[0x18]; 7773 7774 u8 reserved_3[0x20]; 7775 7776 u8 opt_param_mask[0x20]; 7777 7778 u8 reserved_4[0x20]; 7779 7780 struct mlx5_ifc_qpc_bits qpc; 7781 7782 u8 reserved_at_800[0x60]; 7783 7784 u8 wq_umem_valid[0x1]; 7785 u8 reserved_at_861[0x1f]; 7786 7787 u8 pas[0][0x40]; 7788}; 7789 7790struct mlx5_ifc_create_qos_para_vport_out_bits { 7791 u8 status[0x8]; 7792 u8 reserved_at_8[0x18]; 7793 7794 u8 syndrome[0x20]; 7795 7796 u8 reserved_at_40[0x20]; 7797 7798 u8 reserved_at_60[0x10]; 7799 u8 qos_para_vport_number[0x10]; 7800 7801 u8 reserved_at_80[0x180]; 7802}; 7803 7804struct mlx5_ifc_create_qos_para_vport_in_bits { 7805 u8 opcode[0x10]; 7806 u8 reserved_at_10[0x10]; 7807 7808 u8 reserved_at_20[0x10]; 7809 u8 op_mod[0x10]; 7810 7811 u8 reserved_at_40[0x1c0]; 7812}; 7813 7814struct mlx5_ifc_create_psv_out_bits { 7815 u8 status[0x8]; 7816 u8 reserved_0[0x18]; 7817 7818 u8 syndrome[0x20]; 7819 7820 u8 reserved_1[0x40]; 7821 7822 u8 reserved_2[0x8]; 7823 u8 psv0_index[0x18]; 7824 7825 u8 reserved_3[0x8]; 7826 u8 psv1_index[0x18]; 7827 7828 u8 reserved_4[0x8]; 7829 u8 psv2_index[0x18]; 7830 7831 u8 reserved_5[0x8]; 7832 u8 psv3_index[0x18]; 7833}; 7834 7835struct mlx5_ifc_create_psv_in_bits { 7836 u8 opcode[0x10]; 7837 u8 reserved_0[0x10]; 7838 7839 u8 reserved_1[0x10]; 7840 u8 op_mod[0x10]; 7841 7842 u8 num_psv[0x4]; 7843 u8 reserved_2[0x4]; 7844 u8 pd[0x18]; 7845 7846 u8 reserved_3[0x20]; 7847}; 7848 7849struct mlx5_ifc_create_mkey_out_bits { 7850 u8 status[0x8]; 7851 u8 reserved_0[0x18]; 7852 7853 u8 syndrome[0x20]; 7854 7855 u8 reserved_1[0x8]; 7856 u8 mkey_index[0x18]; 7857 7858 u8 reserved_2[0x20]; 7859}; 7860 7861struct mlx5_ifc_create_mkey_in_bits { 7862 u8 opcode[0x10]; 7863 u8 reserved_0[0x10]; 7864 7865 u8 reserved_1[0x10]; 7866 u8 op_mod[0x10]; 7867 7868 u8 reserved_2[0x20]; 7869 7870 u8 pg_access[0x1]; 7871 u8 mkey_umem_valid[0x1]; 7872 u8 reserved_at_62[0x1e]; 7873 7874 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7875 7876 u8 reserved_4[0x80]; 7877 7878 u8 translations_octword_actual_size[0x20]; 7879 7880 u8 reserved_5[0x560]; 7881 7882 u8 klm_pas_mtt[0][0x20]; 7883}; 7884 7885struct mlx5_ifc_create_flow_table_out_bits { 7886 u8 status[0x8]; 7887 u8 reserved_0[0x18]; 7888 7889 u8 syndrome[0x20]; 7890 7891 u8 reserved_1[0x8]; 7892 u8 table_id[0x18]; 7893 7894 u8 reserved_2[0x20]; 7895}; 7896 7897struct mlx5_ifc_create_flow_table_in_bits { 7898 u8 opcode[0x10]; 7899 u8 reserved_at_10[0x10]; 7900 7901 u8 reserved_at_20[0x10]; 7902 u8 op_mod[0x10]; 7903 7904 u8 other_vport[0x1]; 7905 u8 reserved_at_41[0xf]; 7906 u8 vport_number[0x10]; 7907 7908 u8 reserved_at_60[0x20]; 7909 7910 u8 table_type[0x8]; 7911 u8 reserved_at_88[0x18]; 7912 7913 u8 reserved_at_a0[0x20]; 7914 7915 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7916}; 7917 7918struct mlx5_ifc_create_flow_group_out_bits { 7919 u8 status[0x8]; 7920 u8 reserved_0[0x18]; 7921 7922 u8 syndrome[0x20]; 7923 7924 u8 reserved_1[0x8]; 7925 u8 group_id[0x18]; 7926 7927 u8 reserved_2[0x20]; 7928}; 7929 7930enum { 7931 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7932 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7933 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7934}; 7935 7936struct mlx5_ifc_create_flow_group_in_bits { 7937 u8 opcode[0x10]; 7938 u8 reserved_0[0x10]; 7939 7940 u8 reserved_1[0x10]; 7941 u8 op_mod[0x10]; 7942 7943 u8 other_vport[0x1]; 7944 u8 reserved_2[0xf]; 7945 u8 vport_number[0x10]; 7946 7947 u8 reserved_3[0x20]; 7948 7949 u8 table_type[0x8]; 7950 u8 reserved_4[0x18]; 7951 7952 u8 reserved_5[0x8]; 7953 u8 table_id[0x18]; 7954 7955 u8 reserved_6[0x20]; 7956 7957 u8 start_flow_index[0x20]; 7958 7959 u8 reserved_7[0x20]; 7960 7961 u8 end_flow_index[0x20]; 7962 7963 u8 reserved_8[0xa0]; 7964 7965 u8 reserved_9[0x18]; 7966 u8 match_criteria_enable[0x8]; 7967 7968 struct mlx5_ifc_fte_match_param_bits match_criteria; 7969 7970 u8 reserved_10[0xe00]; 7971}; 7972 7973struct mlx5_ifc_create_encryption_key_out_bits { 7974 u8 status[0x8]; 7975 u8 reserved_at_8[0x18]; 7976 7977 u8 syndrome[0x20]; 7978 7979 u8 obj_id[0x20]; 7980 7981 u8 reserved_at_60[0x20]; 7982}; 7983 7984struct mlx5_ifc_create_encryption_key_in_bits { 7985 u8 opcode[0x10]; 7986 u8 reserved_at_10[0x10]; 7987 7988 u8 reserved_at_20[0x10]; 7989 u8 obj_type[0x10]; 7990 7991 u8 reserved_at_40[0x40]; 7992 7993 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 7994}; 7995 7996struct mlx5_ifc_create_eq_out_bits { 7997 u8 status[0x8]; 7998 u8 reserved_0[0x18]; 7999 8000 u8 syndrome[0x20]; 8001 8002 u8 reserved_1[0x18]; 8003 u8 eq_number[0x8]; 8004 8005 u8 reserved_2[0x20]; 8006}; 8007 8008struct mlx5_ifc_create_eq_in_bits { 8009 u8 opcode[0x10]; 8010 u8 reserved_0[0x10]; 8011 8012 u8 reserved_1[0x10]; 8013 u8 op_mod[0x10]; 8014 8015 u8 reserved_2[0x40]; 8016 8017 struct mlx5_ifc_eqc_bits eq_context_entry; 8018 8019 u8 reserved_3[0x40]; 8020 8021 u8 event_bitmask[0x40]; 8022 8023 u8 reserved_4[0x580]; 8024 8025 u8 pas[0][0x40]; 8026}; 8027 8028struct mlx5_ifc_create_dct_out_bits { 8029 u8 status[0x8]; 8030 u8 reserved_0[0x18]; 8031 8032 u8 syndrome[0x20]; 8033 8034 u8 reserved_1[0x8]; 8035 u8 dctn[0x18]; 8036 8037 u8 reserved_2[0x20]; 8038}; 8039 8040struct mlx5_ifc_create_dct_in_bits { 8041 u8 opcode[0x10]; 8042 u8 uid[0x10]; 8043 8044 u8 reserved_1[0x10]; 8045 u8 op_mod[0x10]; 8046 8047 u8 reserved_2[0x40]; 8048 8049 struct mlx5_ifc_dctc_bits dct_context_entry; 8050 8051 u8 reserved_3[0x180]; 8052}; 8053 8054struct mlx5_ifc_create_cq_out_bits { 8055 u8 status[0x8]; 8056 u8 reserved_0[0x18]; 8057 8058 u8 syndrome[0x20]; 8059 8060 u8 reserved_1[0x8]; 8061 u8 cqn[0x18]; 8062 8063 u8 reserved_2[0x20]; 8064}; 8065 8066struct mlx5_ifc_create_cq_in_bits { 8067 u8 opcode[0x10]; 8068 u8 uid[0x10]; 8069 8070 u8 reserved_1[0x10]; 8071 u8 op_mod[0x10]; 8072 8073 u8 reserved_2[0x40]; 8074 8075 struct mlx5_ifc_cqc_bits cq_context; 8076 8077 u8 reserved_at_280[0x60]; 8078 8079 u8 cq_umem_valid[0x1]; 8080 u8 reserved_at_2e1[0x59f]; 8081 8082 u8 pas[0][0x40]; 8083}; 8084 8085struct mlx5_ifc_config_int_moderation_out_bits { 8086 u8 status[0x8]; 8087 u8 reserved_0[0x18]; 8088 8089 u8 syndrome[0x20]; 8090 8091 u8 reserved_1[0x4]; 8092 u8 min_delay[0xc]; 8093 u8 int_vector[0x10]; 8094 8095 u8 reserved_2[0x20]; 8096}; 8097 8098enum { 8099 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8100 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8101}; 8102 8103struct mlx5_ifc_config_int_moderation_in_bits { 8104 u8 opcode[0x10]; 8105 u8 reserved_0[0x10]; 8106 8107 u8 reserved_1[0x10]; 8108 u8 op_mod[0x10]; 8109 8110 u8 reserved_2[0x4]; 8111 u8 min_delay[0xc]; 8112 u8 int_vector[0x10]; 8113 8114 u8 reserved_3[0x20]; 8115}; 8116 8117struct mlx5_ifc_attach_to_mcg_out_bits { 8118 u8 status[0x8]; 8119 u8 reserved_0[0x18]; 8120 8121 u8 syndrome[0x20]; 8122 8123 u8 reserved_1[0x40]; 8124}; 8125 8126struct mlx5_ifc_attach_to_mcg_in_bits { 8127 u8 opcode[0x10]; 8128 u8 uid[0x10]; 8129 8130 u8 reserved_1[0x10]; 8131 u8 op_mod[0x10]; 8132 8133 u8 reserved_2[0x8]; 8134 u8 qpn[0x18]; 8135 8136 u8 reserved_3[0x20]; 8137 8138 u8 multicast_gid[16][0x8]; 8139}; 8140 8141struct mlx5_ifc_arm_xrq_out_bits { 8142 u8 status[0x8]; 8143 u8 reserved_at_8[0x18]; 8144 8145 u8 syndrome[0x20]; 8146 8147 u8 reserved_at_40[0x40]; 8148}; 8149 8150struct mlx5_ifc_arm_xrq_in_bits { 8151 u8 opcode[0x10]; 8152 u8 reserved_at_10[0x10]; 8153 8154 u8 reserved_at_20[0x10]; 8155 u8 op_mod[0x10]; 8156 8157 u8 reserved_at_40[0x8]; 8158 u8 xrqn[0x18]; 8159 8160 u8 reserved_at_60[0x10]; 8161 u8 lwm[0x10]; 8162}; 8163 8164struct mlx5_ifc_arm_xrc_srq_out_bits { 8165 u8 status[0x8]; 8166 u8 reserved_0[0x18]; 8167 8168 u8 syndrome[0x20]; 8169 8170 u8 reserved_1[0x40]; 8171}; 8172 8173enum { 8174 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8175}; 8176 8177struct mlx5_ifc_arm_xrc_srq_in_bits { 8178 u8 opcode[0x10]; 8179 u8 uid[0x10]; 8180 8181 u8 reserved_1[0x10]; 8182 u8 op_mod[0x10]; 8183 8184 u8 reserved_2[0x8]; 8185 u8 xrc_srqn[0x18]; 8186 8187 u8 reserved_3[0x10]; 8188 u8 lwm[0x10]; 8189}; 8190 8191struct mlx5_ifc_arm_rq_out_bits { 8192 u8 status[0x8]; 8193 u8 reserved_0[0x18]; 8194 8195 u8 syndrome[0x20]; 8196 8197 u8 reserved_1[0x40]; 8198}; 8199 8200enum { 8201 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8202}; 8203 8204struct mlx5_ifc_arm_rq_in_bits { 8205 u8 opcode[0x10]; 8206 u8 uid[0x10]; 8207 8208 u8 reserved_1[0x10]; 8209 u8 op_mod[0x10]; 8210 8211 u8 reserved_2[0x8]; 8212 u8 srq_number[0x18]; 8213 8214 u8 reserved_3[0x10]; 8215 u8 lwm[0x10]; 8216}; 8217 8218struct mlx5_ifc_arm_dct_out_bits { 8219 u8 status[0x8]; 8220 u8 reserved_0[0x18]; 8221 8222 u8 syndrome[0x20]; 8223 8224 u8 reserved_1[0x40]; 8225}; 8226 8227struct mlx5_ifc_arm_dct_in_bits { 8228 u8 opcode[0x10]; 8229 u8 reserved_0[0x10]; 8230 8231 u8 reserved_1[0x10]; 8232 u8 op_mod[0x10]; 8233 8234 u8 reserved_2[0x8]; 8235 u8 dctn[0x18]; 8236 8237 u8 reserved_3[0x20]; 8238}; 8239 8240struct mlx5_ifc_alloc_xrcd_out_bits { 8241 u8 status[0x8]; 8242 u8 reserved_0[0x18]; 8243 8244 u8 syndrome[0x20]; 8245 8246 u8 reserved_1[0x8]; 8247 u8 xrcd[0x18]; 8248 8249 u8 reserved_2[0x20]; 8250}; 8251 8252struct mlx5_ifc_alloc_xrcd_in_bits { 8253 u8 opcode[0x10]; 8254 u8 uid[0x10]; 8255 8256 u8 reserved_1[0x10]; 8257 u8 op_mod[0x10]; 8258 8259 u8 reserved_2[0x40]; 8260}; 8261 8262struct mlx5_ifc_alloc_uar_out_bits { 8263 u8 status[0x8]; 8264 u8 reserved_0[0x18]; 8265 8266 u8 syndrome[0x20]; 8267 8268 u8 reserved_1[0x8]; 8269 u8 uar[0x18]; 8270 8271 u8 reserved_2[0x20]; 8272}; 8273 8274struct mlx5_ifc_alloc_uar_in_bits { 8275 u8 opcode[0x10]; 8276 u8 reserved_0[0x10]; 8277 8278 u8 reserved_1[0x10]; 8279 u8 op_mod[0x10]; 8280 8281 u8 reserved_2[0x40]; 8282}; 8283 8284struct mlx5_ifc_alloc_transport_domain_out_bits { 8285 u8 status[0x8]; 8286 u8 reserved_0[0x18]; 8287 8288 u8 syndrome[0x20]; 8289 8290 u8 reserved_1[0x8]; 8291 u8 transport_domain[0x18]; 8292 8293 u8 reserved_2[0x20]; 8294}; 8295 8296struct mlx5_ifc_alloc_transport_domain_in_bits { 8297 u8 opcode[0x10]; 8298 u8 uid[0x10]; 8299 8300 u8 reserved_1[0x10]; 8301 u8 op_mod[0x10]; 8302 8303 u8 reserved_2[0x40]; 8304}; 8305 8306struct mlx5_ifc_alloc_q_counter_out_bits { 8307 u8 status[0x8]; 8308 u8 reserved_0[0x18]; 8309 8310 u8 syndrome[0x20]; 8311 8312 u8 reserved_1[0x18]; 8313 u8 counter_set_id[0x8]; 8314 8315 u8 reserved_2[0x20]; 8316}; 8317 8318struct mlx5_ifc_alloc_q_counter_in_bits { 8319 u8 opcode[0x10]; 8320 u8 uid[0x10]; 8321 8322 u8 reserved_1[0x10]; 8323 u8 op_mod[0x10]; 8324 8325 u8 reserved_2[0x40]; 8326}; 8327 8328struct mlx5_ifc_alloc_pd_out_bits { 8329 u8 status[0x8]; 8330 u8 reserved_0[0x18]; 8331 8332 u8 syndrome[0x20]; 8333 8334 u8 reserved_1[0x8]; 8335 u8 pd[0x18]; 8336 8337 u8 reserved_2[0x20]; 8338}; 8339 8340struct mlx5_ifc_alloc_pd_in_bits { 8341 u8 opcode[0x10]; 8342 u8 uid[0x10]; 8343 8344 u8 reserved_1[0x10]; 8345 u8 op_mod[0x10]; 8346 8347 u8 reserved_2[0x40]; 8348}; 8349 8350struct mlx5_ifc_alloc_flow_counter_out_bits { 8351 u8 status[0x8]; 8352 u8 reserved_at_8[0x18]; 8353 8354 u8 syndrome[0x20]; 8355 8356 u8 flow_counter_id[0x20]; 8357 8358 u8 reserved_at_60[0x20]; 8359}; 8360 8361struct mlx5_ifc_alloc_flow_counter_in_bits { 8362 u8 opcode[0x10]; 8363 u8 reserved_at_10[0x10]; 8364 8365 u8 reserved_at_20[0x10]; 8366 u8 op_mod[0x10]; 8367 8368 u8 reserved_at_40[0x38]; 8369 u8 flow_counter_bulk[0x8]; 8370}; 8371 8372struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8373 u8 status[0x8]; 8374 u8 reserved_0[0x18]; 8375 8376 u8 syndrome[0x20]; 8377 8378 u8 reserved_1[0x40]; 8379}; 8380 8381struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8382 u8 opcode[0x10]; 8383 u8 reserved_0[0x10]; 8384 8385 u8 reserved_1[0x10]; 8386 u8 op_mod[0x10]; 8387 8388 u8 reserved_2[0x20]; 8389 8390 u8 reserved_3[0x10]; 8391 u8 vxlan_udp_port[0x10]; 8392}; 8393 8394struct mlx5_ifc_activate_tracer_out_bits { 8395 u8 status[0x8]; 8396 u8 reserved_0[0x18]; 8397 8398 u8 syndrome[0x20]; 8399 8400 u8 reserved_1[0x40]; 8401}; 8402 8403struct mlx5_ifc_activate_tracer_in_bits { 8404 u8 opcode[0x10]; 8405 u8 reserved_0[0x10]; 8406 8407 u8 reserved_1[0x10]; 8408 u8 op_mod[0x10]; 8409 8410 u8 mkey[0x20]; 8411 8412 u8 reserved_2[0x20]; 8413}; 8414 8415struct mlx5_ifc_set_rate_limit_out_bits { 8416 u8 status[0x8]; 8417 u8 reserved_at_8[0x18]; 8418 8419 u8 syndrome[0x20]; 8420 8421 u8 reserved_at_40[0x40]; 8422}; 8423 8424struct mlx5_ifc_set_rate_limit_in_bits { 8425 u8 opcode[0x10]; 8426 u8 uid[0x10]; 8427 8428 u8 reserved_at_20[0x10]; 8429 u8 op_mod[0x10]; 8430 8431 u8 reserved_at_40[0x10]; 8432 u8 rate_limit_index[0x10]; 8433 8434 u8 reserved_at_60[0x20]; 8435 8436 u8 rate_limit[0x20]; 8437 8438 u8 burst_upper_bound[0x20]; 8439 8440 u8 reserved_at_c0[0x10]; 8441 u8 typical_packet_size[0x10]; 8442 8443 u8 reserved_at_e0[0x120]; 8444}; 8445 8446struct mlx5_ifc_access_register_out_bits { 8447 u8 status[0x8]; 8448 u8 reserved_0[0x18]; 8449 8450 u8 syndrome[0x20]; 8451 8452 u8 reserved_1[0x40]; 8453 8454 u8 register_data[0][0x20]; 8455}; 8456 8457enum { 8458 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8459 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8460}; 8461 8462struct mlx5_ifc_access_register_in_bits { 8463 u8 opcode[0x10]; 8464 u8 reserved_0[0x10]; 8465 8466 u8 reserved_1[0x10]; 8467 u8 op_mod[0x10]; 8468 8469 u8 reserved_2[0x10]; 8470 u8 register_id[0x10]; 8471 8472 u8 argument[0x20]; 8473 8474 u8 register_data[0][0x20]; 8475}; 8476 8477struct mlx5_ifc_sltp_reg_bits { 8478 u8 status[0x4]; 8479 u8 version[0x4]; 8480 u8 local_port[0x8]; 8481 u8 pnat[0x2]; 8482 u8 reserved_0[0x2]; 8483 u8 lane[0x4]; 8484 u8 reserved_1[0x8]; 8485 8486 u8 reserved_2[0x20]; 8487 8488 u8 reserved_3[0x7]; 8489 u8 polarity[0x1]; 8490 u8 ob_tap0[0x8]; 8491 u8 ob_tap1[0x8]; 8492 u8 ob_tap2[0x8]; 8493 8494 u8 reserved_4[0xc]; 8495 u8 ob_preemp_mode[0x4]; 8496 u8 ob_reg[0x8]; 8497 u8 ob_bias[0x8]; 8498 8499 u8 reserved_5[0x20]; 8500}; 8501 8502struct mlx5_ifc_slrp_reg_bits { 8503 u8 status[0x4]; 8504 u8 version[0x4]; 8505 u8 local_port[0x8]; 8506 u8 pnat[0x2]; 8507 u8 reserved_0[0x2]; 8508 u8 lane[0x4]; 8509 u8 reserved_1[0x8]; 8510 8511 u8 ib_sel[0x2]; 8512 u8 reserved_2[0x11]; 8513 u8 dp_sel[0x1]; 8514 u8 dp90sel[0x4]; 8515 u8 mix90phase[0x8]; 8516 8517 u8 ffe_tap0[0x8]; 8518 u8 ffe_tap1[0x8]; 8519 u8 ffe_tap2[0x8]; 8520 u8 ffe_tap3[0x8]; 8521 8522 u8 ffe_tap4[0x8]; 8523 u8 ffe_tap5[0x8]; 8524 u8 ffe_tap6[0x8]; 8525 u8 ffe_tap7[0x8]; 8526 8527 u8 ffe_tap8[0x8]; 8528 u8 mixerbias_tap_amp[0x8]; 8529 u8 reserved_3[0x7]; 8530 u8 ffe_tap_en[0x9]; 8531 8532 u8 ffe_tap_offset0[0x8]; 8533 u8 ffe_tap_offset1[0x8]; 8534 u8 slicer_offset0[0x10]; 8535 8536 u8 mixer_offset0[0x10]; 8537 u8 mixer_offset1[0x10]; 8538 8539 u8 mixerbgn_inp[0x8]; 8540 u8 mixerbgn_inn[0x8]; 8541 u8 mixerbgn_refp[0x8]; 8542 u8 mixerbgn_refn[0x8]; 8543 8544 u8 sel_slicer_lctrl_h[0x1]; 8545 u8 sel_slicer_lctrl_l[0x1]; 8546 u8 reserved_4[0x1]; 8547 u8 ref_mixer_vreg[0x5]; 8548 u8 slicer_gctrl[0x8]; 8549 u8 lctrl_input[0x8]; 8550 u8 mixer_offset_cm1[0x8]; 8551 8552 u8 common_mode[0x6]; 8553 u8 reserved_5[0x1]; 8554 u8 mixer_offset_cm0[0x9]; 8555 u8 reserved_6[0x7]; 8556 u8 slicer_offset_cm[0x9]; 8557}; 8558 8559struct mlx5_ifc_slrg_reg_bits { 8560 u8 status[0x4]; 8561 u8 version[0x4]; 8562 u8 local_port[0x8]; 8563 u8 pnat[0x2]; 8564 u8 reserved_0[0x2]; 8565 u8 lane[0x4]; 8566 u8 reserved_1[0x8]; 8567 8568 u8 time_to_link_up[0x10]; 8569 u8 reserved_2[0xc]; 8570 u8 grade_lane_speed[0x4]; 8571 8572 u8 grade_version[0x8]; 8573 u8 grade[0x18]; 8574 8575 u8 reserved_3[0x4]; 8576 u8 height_grade_type[0x4]; 8577 u8 height_grade[0x18]; 8578 8579 u8 height_dz[0x10]; 8580 u8 height_dv[0x10]; 8581 8582 u8 reserved_4[0x10]; 8583 u8 height_sigma[0x10]; 8584 8585 u8 reserved_5[0x20]; 8586 8587 u8 reserved_6[0x4]; 8588 u8 phase_grade_type[0x4]; 8589 u8 phase_grade[0x18]; 8590 8591 u8 reserved_7[0x8]; 8592 u8 phase_eo_pos[0x8]; 8593 u8 reserved_8[0x8]; 8594 u8 phase_eo_neg[0x8]; 8595 8596 u8 ffe_set_tested[0x10]; 8597 u8 test_errors_per_lane[0x10]; 8598}; 8599 8600struct mlx5_ifc_pvlc_reg_bits { 8601 u8 reserved_0[0x8]; 8602 u8 local_port[0x8]; 8603 u8 reserved_1[0x10]; 8604 8605 u8 reserved_2[0x1c]; 8606 u8 vl_hw_cap[0x4]; 8607 8608 u8 reserved_3[0x1c]; 8609 u8 vl_admin[0x4]; 8610 8611 u8 reserved_4[0x1c]; 8612 u8 vl_operational[0x4]; 8613}; 8614 8615struct mlx5_ifc_pude_reg_bits { 8616 u8 swid[0x8]; 8617 u8 local_port[0x8]; 8618 u8 reserved_0[0x4]; 8619 u8 admin_status[0x4]; 8620 u8 reserved_1[0x4]; 8621 u8 oper_status[0x4]; 8622 8623 u8 reserved_2[0x60]; 8624}; 8625 8626enum { 8627 MLX5_PTYS_REG_PROTO_MASK_INFINIBAND = 0x1, 8628 MLX5_PTYS_REG_PROTO_MASK_ETHERNET = 0x4, 8629}; 8630 8631struct mlx5_ifc_ptys_reg_bits { 8632 u8 reserved_0[0x1]; 8633 u8 an_disable_admin[0x1]; 8634 u8 an_disable_cap[0x1]; 8635 u8 reserved_1[0x4]; 8636 u8 force_tx_aba_param[0x1]; 8637 u8 local_port[0x8]; 8638 u8 reserved_2[0xd]; 8639 u8 proto_mask[0x3]; 8640 8641 u8 an_status[0x4]; 8642 u8 reserved_3[0xc]; 8643 u8 data_rate_oper[0x10]; 8644 8645 u8 ext_eth_proto_capability[0x20]; 8646 8647 u8 eth_proto_capability[0x20]; 8648 8649 u8 ib_link_width_capability[0x10]; 8650 u8 ib_proto_capability[0x10]; 8651 8652 u8 ext_eth_proto_admin[0x20]; 8653 8654 u8 eth_proto_admin[0x20]; 8655 8656 u8 ib_link_width_admin[0x10]; 8657 u8 ib_proto_admin[0x10]; 8658 8659 u8 ext_eth_proto_oper[0x20]; 8660 8661 u8 eth_proto_oper[0x20]; 8662 8663 u8 ib_link_width_oper[0x10]; 8664 u8 ib_proto_oper[0x10]; 8665 8666 u8 reserved_4[0x1c]; 8667 u8 connector_type[0x4]; 8668 8669 u8 eth_proto_lp_advertise[0x20]; 8670 8671 u8 reserved_5[0x60]; 8672}; 8673 8674struct mlx5_ifc_ptas_reg_bits { 8675 u8 reserved_0[0x20]; 8676 8677 u8 algorithm_options[0x10]; 8678 u8 reserved_1[0x4]; 8679 u8 repetitions_mode[0x4]; 8680 u8 num_of_repetitions[0x8]; 8681 8682 u8 grade_version[0x8]; 8683 u8 height_grade_type[0x4]; 8684 u8 phase_grade_type[0x4]; 8685 u8 height_grade_weight[0x8]; 8686 u8 phase_grade_weight[0x8]; 8687 8688 u8 gisim_measure_bits[0x10]; 8689 u8 adaptive_tap_measure_bits[0x10]; 8690 8691 u8 ber_bath_high_error_threshold[0x10]; 8692 u8 ber_bath_mid_error_threshold[0x10]; 8693 8694 u8 ber_bath_low_error_threshold[0x10]; 8695 u8 one_ratio_high_threshold[0x10]; 8696 8697 u8 one_ratio_high_mid_threshold[0x10]; 8698 u8 one_ratio_low_mid_threshold[0x10]; 8699 8700 u8 one_ratio_low_threshold[0x10]; 8701 u8 ndeo_error_threshold[0x10]; 8702 8703 u8 mixer_offset_step_size[0x10]; 8704 u8 reserved_2[0x8]; 8705 u8 mix90_phase_for_voltage_bath[0x8]; 8706 8707 u8 mixer_offset_start[0x10]; 8708 u8 mixer_offset_end[0x10]; 8709 8710 u8 reserved_3[0x15]; 8711 u8 ber_test_time[0xb]; 8712}; 8713 8714struct mlx5_ifc_pspa_reg_bits { 8715 u8 swid[0x8]; 8716 u8 local_port[0x8]; 8717 u8 sub_port[0x8]; 8718 u8 reserved_0[0x8]; 8719 8720 u8 reserved_1[0x20]; 8721}; 8722 8723struct mlx5_ifc_ppsc_reg_bits { 8724 u8 reserved_0[0x8]; 8725 u8 local_port[0x8]; 8726 u8 reserved_1[0x10]; 8727 8728 u8 reserved_2[0x60]; 8729 8730 u8 reserved_3[0x1c]; 8731 u8 wrps_admin[0x4]; 8732 8733 u8 reserved_4[0x1c]; 8734 u8 wrps_status[0x4]; 8735 8736 u8 up_th_vld[0x1]; 8737 u8 down_th_vld[0x1]; 8738 u8 reserved_5[0x6]; 8739 u8 up_threshold[0x8]; 8740 u8 reserved_6[0x8]; 8741 u8 down_threshold[0x8]; 8742 8743 u8 reserved_7[0x20]; 8744 8745 u8 reserved_8[0x1c]; 8746 u8 srps_admin[0x4]; 8747 8748 u8 reserved_9[0x60]; 8749}; 8750 8751struct mlx5_ifc_pplr_reg_bits { 8752 u8 reserved_0[0x8]; 8753 u8 local_port[0x8]; 8754 u8 reserved_1[0x10]; 8755 8756 u8 reserved_2[0x8]; 8757 u8 lb_cap[0x8]; 8758 u8 reserved_3[0x8]; 8759 u8 lb_en[0x8]; 8760}; 8761 8762struct mlx5_ifc_pplm_reg_bits { 8763 u8 reserved_at_0[0x8]; 8764 u8 local_port[0x8]; 8765 u8 reserved_at_10[0x10]; 8766 8767 u8 reserved_at_20[0x20]; 8768 8769 u8 port_profile_mode[0x8]; 8770 u8 static_port_profile[0x8]; 8771 u8 active_port_profile[0x8]; 8772 u8 reserved_at_58[0x8]; 8773 8774 u8 retransmission_active[0x8]; 8775 u8 fec_mode_active[0x18]; 8776 8777 u8 rs_fec_correction_bypass_cap[0x4]; 8778 u8 reserved_at_84[0x8]; 8779 u8 fec_override_cap_56g[0x4]; 8780 u8 fec_override_cap_100g[0x4]; 8781 u8 fec_override_cap_50g[0x4]; 8782 u8 fec_override_cap_25g[0x4]; 8783 u8 fec_override_cap_10g_40g[0x4]; 8784 8785 u8 rs_fec_correction_bypass_admin[0x4]; 8786 u8 reserved_at_a4[0x8]; 8787 u8 fec_override_admin_56g[0x4]; 8788 u8 fec_override_admin_100g[0x4]; 8789 u8 fec_override_admin_50g[0x4]; 8790 u8 fec_override_admin_25g[0x4]; 8791 u8 fec_override_admin_10g_40g[0x4]; 8792 8793 u8 fec_override_cap_400g_8x[0x10]; 8794 u8 fec_override_cap_200g_4x[0x10]; 8795 u8 fec_override_cap_100g_2x[0x10]; 8796 u8 fec_override_cap_50g_1x[0x10]; 8797 8798 u8 fec_override_admin_400g_8x[0x10]; 8799 u8 fec_override_admin_200g_4x[0x10]; 8800 u8 fec_override_admin_100g_2x[0x10]; 8801 u8 fec_override_admin_50g_1x[0x10]; 8802 8803 u8 reserved_at_140[0x140]; 8804}; 8805 8806struct mlx5_ifc_ppll_reg_bits { 8807 u8 num_pll_groups[0x8]; 8808 u8 pll_group[0x8]; 8809 u8 reserved_0[0x4]; 8810 u8 num_plls[0x4]; 8811 u8 reserved_1[0x8]; 8812 8813 u8 reserved_2[0x1f]; 8814 u8 ae[0x1]; 8815 8816 u8 pll_status[4][0x40]; 8817}; 8818 8819struct mlx5_ifc_ppad_reg_bits { 8820 u8 reserved_0[0x3]; 8821 u8 single_mac[0x1]; 8822 u8 reserved_1[0x4]; 8823 u8 local_port[0x8]; 8824 u8 mac_47_32[0x10]; 8825 8826 u8 mac_31_0[0x20]; 8827 8828 u8 reserved_2[0x40]; 8829}; 8830 8831struct mlx5_ifc_pmtu_reg_bits { 8832 u8 reserved_0[0x8]; 8833 u8 local_port[0x8]; 8834 u8 reserved_1[0x10]; 8835 8836 u8 max_mtu[0x10]; 8837 u8 reserved_2[0x10]; 8838 8839 u8 admin_mtu[0x10]; 8840 u8 reserved_3[0x10]; 8841 8842 u8 oper_mtu[0x10]; 8843 u8 reserved_4[0x10]; 8844}; 8845 8846struct mlx5_ifc_pmpr_reg_bits { 8847 u8 reserved_0[0x8]; 8848 u8 module[0x8]; 8849 u8 reserved_1[0x10]; 8850 8851 u8 reserved_2[0x18]; 8852 u8 attenuation_5g[0x8]; 8853 8854 u8 reserved_3[0x18]; 8855 u8 attenuation_7g[0x8]; 8856 8857 u8 reserved_4[0x18]; 8858 u8 attenuation_12g[0x8]; 8859}; 8860 8861struct mlx5_ifc_pmpe_reg_bits { 8862 u8 reserved_0[0x8]; 8863 u8 module[0x8]; 8864 u8 reserved_1[0xc]; 8865 u8 module_status[0x4]; 8866 8867 u8 reserved_2[0x14]; 8868 u8 error_type[0x4]; 8869 u8 reserved_3[0x8]; 8870 8871 u8 reserved_4[0x40]; 8872}; 8873 8874struct mlx5_ifc_pmpc_reg_bits { 8875 u8 module_state_updated[32][0x8]; 8876}; 8877 8878struct mlx5_ifc_pmlpn_reg_bits { 8879 u8 reserved_0[0x4]; 8880 u8 mlpn_status[0x4]; 8881 u8 local_port[0x8]; 8882 u8 reserved_1[0x10]; 8883 8884 u8 e[0x1]; 8885 u8 reserved_2[0x1f]; 8886}; 8887 8888struct mlx5_ifc_pmlp_reg_bits { 8889 u8 rxtx[0x1]; 8890 u8 reserved_0[0x7]; 8891 u8 local_port[0x8]; 8892 u8 reserved_1[0x8]; 8893 u8 width[0x8]; 8894 8895 u8 lane0_module_mapping[0x20]; 8896 8897 u8 lane1_module_mapping[0x20]; 8898 8899 u8 lane2_module_mapping[0x20]; 8900 8901 u8 lane3_module_mapping[0x20]; 8902 8903 u8 reserved_2[0x160]; 8904}; 8905 8906struct mlx5_ifc_pmaos_reg_bits { 8907 u8 reserved_0[0x8]; 8908 u8 module[0x8]; 8909 u8 reserved_1[0x4]; 8910 u8 admin_status[0x4]; 8911 u8 reserved_2[0x4]; 8912 u8 oper_status[0x4]; 8913 8914 u8 ase[0x1]; 8915 u8 ee[0x1]; 8916 u8 reserved_3[0x12]; 8917 u8 error_type[0x4]; 8918 u8 reserved_4[0x6]; 8919 u8 e[0x2]; 8920 8921 u8 reserved_5[0x40]; 8922}; 8923 8924struct mlx5_ifc_plpc_reg_bits { 8925 u8 reserved_0[0x4]; 8926 u8 profile_id[0xc]; 8927 u8 reserved_1[0x4]; 8928 u8 proto_mask[0x4]; 8929 u8 reserved_2[0x8]; 8930 8931 u8 reserved_3[0x10]; 8932 u8 lane_speed[0x10]; 8933 8934 u8 reserved_4[0x17]; 8935 u8 lpbf[0x1]; 8936 u8 fec_mode_policy[0x8]; 8937 8938 u8 retransmission_capability[0x8]; 8939 u8 fec_mode_capability[0x18]; 8940 8941 u8 retransmission_support_admin[0x8]; 8942 u8 fec_mode_support_admin[0x18]; 8943 8944 u8 retransmission_request_admin[0x8]; 8945 u8 fec_mode_request_admin[0x18]; 8946 8947 u8 reserved_5[0x80]; 8948}; 8949 8950struct mlx5_ifc_pll_status_data_bits { 8951 u8 reserved_0[0x1]; 8952 u8 lock_cal[0x1]; 8953 u8 lock_status[0x2]; 8954 u8 reserved_1[0x2]; 8955 u8 algo_f_ctrl[0xa]; 8956 u8 analog_algo_num_var[0x6]; 8957 u8 f_ctrl_measure[0xa]; 8958 8959 u8 reserved_2[0x2]; 8960 u8 analog_var[0x6]; 8961 u8 reserved_3[0x2]; 8962 u8 high_var[0x6]; 8963 u8 reserved_4[0x2]; 8964 u8 low_var[0x6]; 8965 u8 reserved_5[0x2]; 8966 u8 mid_val[0x6]; 8967}; 8968 8969struct mlx5_ifc_plib_reg_bits { 8970 u8 reserved_0[0x8]; 8971 u8 local_port[0x8]; 8972 u8 reserved_1[0x8]; 8973 u8 ib_port[0x8]; 8974 8975 u8 reserved_2[0x60]; 8976}; 8977 8978struct mlx5_ifc_plbf_reg_bits { 8979 u8 reserved_0[0x8]; 8980 u8 local_port[0x8]; 8981 u8 reserved_1[0xd]; 8982 u8 lbf_mode[0x3]; 8983 8984 u8 reserved_2[0x20]; 8985}; 8986 8987struct mlx5_ifc_pipg_reg_bits { 8988 u8 reserved_0[0x8]; 8989 u8 local_port[0x8]; 8990 u8 reserved_1[0x10]; 8991 8992 u8 dic[0x1]; 8993 u8 reserved_2[0x19]; 8994 u8 ipg[0x4]; 8995 u8 reserved_3[0x2]; 8996}; 8997 8998struct mlx5_ifc_pifr_reg_bits { 8999 u8 reserved_0[0x8]; 9000 u8 local_port[0x8]; 9001 u8 reserved_1[0x10]; 9002 9003 u8 reserved_2[0xe0]; 9004 9005 u8 port_filter[8][0x20]; 9006 9007 u8 port_filter_update_en[8][0x20]; 9008}; 9009 9010struct mlx5_ifc_phys_layer_cntrs_bits { 9011 u8 time_since_last_clear_high[0x20]; 9012 9013 u8 time_since_last_clear_low[0x20]; 9014 9015 u8 symbol_errors_high[0x20]; 9016 9017 u8 symbol_errors_low[0x20]; 9018 9019 u8 sync_headers_errors_high[0x20]; 9020 9021 u8 sync_headers_errors_low[0x20]; 9022 9023 u8 edpl_bip_errors_lane0_high[0x20]; 9024 9025 u8 edpl_bip_errors_lane0_low[0x20]; 9026 9027 u8 edpl_bip_errors_lane1_high[0x20]; 9028 9029 u8 edpl_bip_errors_lane1_low[0x20]; 9030 9031 u8 edpl_bip_errors_lane2_high[0x20]; 9032 9033 u8 edpl_bip_errors_lane2_low[0x20]; 9034 9035 u8 edpl_bip_errors_lane3_high[0x20]; 9036 9037 u8 edpl_bip_errors_lane3_low[0x20]; 9038 9039 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 9040 9041 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 9042 9043 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 9044 9045 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 9046 9047 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 9048 9049 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 9050 9051 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 9052 9053 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 9054 9055 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 9056 9057 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 9058 9059 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 9060 9061 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 9062 9063 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 9064 9065 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 9066 9067 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 9068 9069 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 9070 9071 u8 rs_fec_corrected_blocks_high[0x20]; 9072 9073 u8 rs_fec_corrected_blocks_low[0x20]; 9074 9075 u8 rs_fec_uncorrectable_blocks_high[0x20]; 9076 9077 u8 rs_fec_uncorrectable_blocks_low[0x20]; 9078 9079 u8 rs_fec_no_errors_blocks_high[0x20]; 9080 9081 u8 rs_fec_no_errors_blocks_low[0x20]; 9082 9083 u8 rs_fec_single_error_blocks_high[0x20]; 9084 9085 u8 rs_fec_single_error_blocks_low[0x20]; 9086 9087 u8 rs_fec_corrected_symbols_total_high[0x20]; 9088 9089 u8 rs_fec_corrected_symbols_total_low[0x20]; 9090 9091 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 9092 9093 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 9094 9095 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 9096 9097 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 9098 9099 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 9100 9101 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 9102 9103 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 9104 9105 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 9106 9107 u8 link_down_events[0x20]; 9108 9109 u8 successful_recovery_events[0x20]; 9110 9111 u8 reserved_0[0x180]; 9112}; 9113 9114struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 9115 u8 symbol_error_counter[0x10]; 9116 9117 u8 link_error_recovery_counter[0x8]; 9118 9119 u8 link_downed_counter[0x8]; 9120 9121 u8 port_rcv_errors[0x10]; 9122 9123 u8 port_rcv_remote_physical_errors[0x10]; 9124 9125 u8 port_rcv_switch_relay_errors[0x10]; 9126 9127 u8 port_xmit_discards[0x10]; 9128 9129 u8 port_xmit_constraint_errors[0x8]; 9130 9131 u8 port_rcv_constraint_errors[0x8]; 9132 9133 u8 reserved_at_70[0x8]; 9134 9135 u8 link_overrun_errors[0x8]; 9136 9137 u8 reserved_at_80[0x10]; 9138 9139 u8 vl_15_dropped[0x10]; 9140 9141 u8 reserved_at_a0[0xa0]; 9142}; 9143 9144struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 9145 u8 time_since_last_clear_high[0x20]; 9146 9147 u8 time_since_last_clear_low[0x20]; 9148 9149 u8 phy_received_bits_high[0x20]; 9150 9151 u8 phy_received_bits_low[0x20]; 9152 9153 u8 phy_symbol_errors_high[0x20]; 9154 9155 u8 phy_symbol_errors_low[0x20]; 9156 9157 u8 phy_corrected_bits_high[0x20]; 9158 9159 u8 phy_corrected_bits_low[0x20]; 9160 9161 u8 phy_corrected_bits_lane0_high[0x20]; 9162 9163 u8 phy_corrected_bits_lane0_low[0x20]; 9164 9165 u8 phy_corrected_bits_lane1_high[0x20]; 9166 9167 u8 phy_corrected_bits_lane1_low[0x20]; 9168 9169 u8 phy_corrected_bits_lane2_high[0x20]; 9170 9171 u8 phy_corrected_bits_lane2_low[0x20]; 9172 9173 u8 phy_corrected_bits_lane3_high[0x20]; 9174 9175 u8 phy_corrected_bits_lane3_low[0x20]; 9176 9177 u8 reserved_at_200[0x5c0]; 9178}; 9179 9180struct mlx5_ifc_infiniband_port_cntrs_bits { 9181 u8 symbol_error_counter[0x10]; 9182 u8 link_error_recovery_counter[0x8]; 9183 u8 link_downed_counter[0x8]; 9184 9185 u8 port_rcv_errors[0x10]; 9186 u8 port_rcv_remote_physical_errors[0x10]; 9187 9188 u8 port_rcv_switch_relay_errors[0x10]; 9189 u8 port_xmit_discards[0x10]; 9190 9191 u8 port_xmit_constraint_errors[0x8]; 9192 u8 port_rcv_constraint_errors[0x8]; 9193 u8 reserved_0[0x8]; 9194 u8 local_link_integrity_errors[0x4]; 9195 u8 excessive_buffer_overrun_errors[0x4]; 9196 9197 u8 reserved_1[0x10]; 9198 u8 vl_15_dropped[0x10]; 9199 9200 u8 port_xmit_data[0x20]; 9201 9202 u8 port_rcv_data[0x20]; 9203 9204 u8 port_xmit_pkts[0x20]; 9205 9206 u8 port_rcv_pkts[0x20]; 9207 9208 u8 port_xmit_wait[0x20]; 9209 9210 u8 reserved_2[0x680]; 9211}; 9212 9213struct mlx5_ifc_phrr_reg_bits { 9214 u8 clr[0x1]; 9215 u8 reserved_0[0x7]; 9216 u8 local_port[0x8]; 9217 u8 reserved_1[0x10]; 9218 9219 u8 hist_group[0x8]; 9220 u8 reserved_2[0x10]; 9221 u8 hist_id[0x8]; 9222 9223 u8 reserved_3[0x40]; 9224 9225 u8 time_since_last_clear_high[0x20]; 9226 9227 u8 time_since_last_clear_low[0x20]; 9228 9229 u8 bin[10][0x20]; 9230}; 9231 9232struct mlx5_ifc_phbr_for_prio_reg_bits { 9233 u8 reserved_0[0x18]; 9234 u8 prio[0x8]; 9235}; 9236 9237struct mlx5_ifc_phbr_for_port_tclass_reg_bits { 9238 u8 reserved_0[0x18]; 9239 u8 tclass[0x8]; 9240}; 9241 9242struct mlx5_ifc_phbr_binding_reg_bits { 9243 u8 opcode[0x4]; 9244 u8 reserved_0[0x4]; 9245 u8 local_port[0x8]; 9246 u8 pnat[0x2]; 9247 u8 reserved_1[0xe]; 9248 9249 u8 hist_group[0x8]; 9250 u8 reserved_2[0x10]; 9251 u8 hist_id[0x8]; 9252 9253 u8 reserved_3[0x10]; 9254 u8 hist_type[0x10]; 9255 9256 u8 hist_parameters[0x20]; 9257 9258 u8 hist_min_value[0x20]; 9259 9260 u8 hist_max_value[0x20]; 9261 9262 u8 sample_time[0x20]; 9263}; 9264 9265enum { 9266 MLX5_PFCC_REG_PPAN_DISABLED = 0x0, 9267 MLX5_PFCC_REG_PPAN_ENABLED = 0x1, 9268}; 9269 9270struct mlx5_ifc_pfcc_reg_bits { 9271 u8 dcbx_operation_type[0x2]; 9272 u8 cap_local_admin[0x1]; 9273 u8 cap_remote_admin[0x1]; 9274 u8 reserved_0[0x4]; 9275 u8 local_port[0x8]; 9276 u8 pnat[0x2]; 9277 u8 reserved_1[0xc]; 9278 u8 shl_cap[0x1]; 9279 u8 shl_opr[0x1]; 9280 9281 u8 ppan[0x4]; 9282 u8 reserved_2[0x4]; 9283 u8 prio_mask_tx[0x8]; 9284 u8 reserved_3[0x8]; 9285 u8 prio_mask_rx[0x8]; 9286 9287 u8 pptx[0x1]; 9288 u8 aptx[0x1]; 9289 u8 reserved_4[0x6]; 9290 u8 pfctx[0x8]; 9291 u8 reserved_5[0x8]; 9292 u8 cbftx[0x8]; 9293 9294 u8 pprx[0x1]; 9295 u8 aprx[0x1]; 9296 u8 reserved_6[0x6]; 9297 u8 pfcrx[0x8]; 9298 u8 reserved_7[0x8]; 9299 u8 cbfrx[0x8]; 9300 9301 u8 device_stall_minor_watermark[0x10]; 9302 u8 device_stall_critical_watermark[0x10]; 9303 9304 u8 reserved_8[0x60]; 9305}; 9306 9307struct mlx5_ifc_pelc_reg_bits { 9308 u8 op[0x4]; 9309 u8 reserved_0[0x4]; 9310 u8 local_port[0x8]; 9311 u8 reserved_1[0x10]; 9312 9313 u8 op_admin[0x8]; 9314 u8 op_capability[0x8]; 9315 u8 op_request[0x8]; 9316 u8 op_active[0x8]; 9317 9318 u8 admin[0x40]; 9319 9320 u8 capability[0x40]; 9321 9322 u8 request[0x40]; 9323 9324 u8 active[0x40]; 9325 9326 u8 reserved_2[0x80]; 9327}; 9328 9329struct mlx5_ifc_peir_reg_bits { 9330 u8 reserved_0[0x8]; 9331 u8 local_port[0x8]; 9332 u8 reserved_1[0x10]; 9333 9334 u8 reserved_2[0xc]; 9335 u8 error_count[0x4]; 9336 u8 reserved_3[0x10]; 9337 9338 u8 reserved_4[0xc]; 9339 u8 lane[0x4]; 9340 u8 reserved_5[0x8]; 9341 u8 error_type[0x8]; 9342}; 9343 9344struct mlx5_ifc_qcam_access_reg_cap_mask { 9345 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9346 u8 qpdpm[0x1]; 9347 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9348 u8 qdpm[0x1]; 9349 u8 qpts[0x1]; 9350 u8 qcap[0x1]; 9351 u8 qcam_access_reg_cap_mask_0[0x1]; 9352}; 9353 9354struct mlx5_ifc_qcam_qos_feature_cap_mask { 9355 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9356 u8 qpts_trust_both[0x1]; 9357}; 9358 9359struct mlx5_ifc_qcam_reg_bits { 9360 u8 reserved_at_0[0x8]; 9361 u8 feature_group[0x8]; 9362 u8 reserved_at_10[0x8]; 9363 u8 access_reg_group[0x8]; 9364 u8 reserved_at_20[0x20]; 9365 9366 union { 9367 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9368 u8 reserved_at_0[0x80]; 9369 } qos_access_reg_cap_mask; 9370 9371 u8 reserved_at_c0[0x80]; 9372 9373 union { 9374 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9375 u8 reserved_at_0[0x80]; 9376 } qos_feature_cap_mask; 9377 9378 u8 reserved_at_1c0[0x80]; 9379}; 9380 9381struct mlx5_ifc_pcam_enhanced_features_bits { 9382 u8 reserved_at_0[0x6d]; 9383 u8 rx_icrc_encapsulated_counter[0x1]; 9384 u8 reserved_at_6e[0x4]; 9385 u8 ptys_extended_ethernet[0x1]; 9386 u8 reserved_at_73[0x3]; 9387 u8 pfcc_mask[0x1]; 9388 u8 reserved_at_77[0x3]; 9389 u8 per_lane_error_counters[0x1]; 9390 u8 rx_buffer_fullness_counters[0x1]; 9391 u8 ptys_connector_type[0x1]; 9392 u8 reserved_at_7d[0x1]; 9393 u8 ppcnt_discard_group[0x1]; 9394 u8 ppcnt_statistical_group[0x1]; 9395}; 9396 9397struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9398 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9399 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9400 9401 u8 reserved_at_40[0xe]; 9402 u8 pddr[0x1]; 9403 u8 reserved_at_4f[0xd]; 9404 9405 u8 pplm[0x1]; 9406 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9407 9408 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9409 u8 pbmc[0x1]; 9410 u8 pptb[0x1]; 9411 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9412 u8 ppcnt[0x1]; 9413 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9414}; 9415 9416struct mlx5_ifc_pcam_reg_bits { 9417 u8 reserved_at_0[0x8]; 9418 u8 feature_group[0x8]; 9419 u8 reserved_at_10[0x8]; 9420 u8 access_reg_group[0x8]; 9421 9422 u8 reserved_at_20[0x20]; 9423 9424 union { 9425 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9426 u8 reserved_at_0[0x80]; 9427 } port_access_reg_cap_mask; 9428 9429 u8 reserved_at_c0[0x80]; 9430 9431 union { 9432 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9433 u8 reserved_at_0[0x80]; 9434 } feature_cap_mask; 9435 9436 u8 reserved_at_1c0[0xc0]; 9437}; 9438 9439struct mlx5_ifc_mcam_enhanced_features_bits { 9440 u8 reserved_at_0[0x6e]; 9441 u8 pcie_status_and_power[0x1]; 9442 u8 reserved_at_111[0x10]; 9443 u8 pcie_performance_group[0x1]; 9444}; 9445 9446struct mlx5_ifc_mcam_access_reg_bits { 9447 u8 reserved_at_0[0x1c]; 9448 u8 mcda[0x1]; 9449 u8 mcc[0x1]; 9450 u8 mcqi[0x1]; 9451 u8 reserved_at_1f[0x1]; 9452 9453 u8 regs_95_to_64[0x20]; 9454 u8 regs_63_to_32[0x20]; 9455 u8 regs_31_to_0[0x20]; 9456}; 9457 9458struct mlx5_ifc_mcam_reg_bits { 9459 u8 reserved_at_0[0x8]; 9460 u8 feature_group[0x8]; 9461 u8 reserved_at_10[0x8]; 9462 u8 access_reg_group[0x8]; 9463 9464 u8 reserved_at_20[0x20]; 9465 9466 union { 9467 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9468 u8 reserved_at_0[0x80]; 9469 } mng_access_reg_cap_mask; 9470 9471 u8 reserved_at_c0[0x80]; 9472 9473 union { 9474 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9475 u8 reserved_at_0[0x80]; 9476 } mng_feature_cap_mask; 9477 9478 u8 reserved_at_1c0[0x80]; 9479}; 9480 9481struct mlx5_ifc_pcap_reg_bits { 9482 u8 reserved_0[0x8]; 9483 u8 local_port[0x8]; 9484 u8 reserved_1[0x10]; 9485 9486 u8 port_capability_mask[4][0x20]; 9487}; 9488 9489struct mlx5_ifc_pbmc_reg_bits { 9490 u8 reserved_at_0[0x8]; 9491 u8 local_port[0x8]; 9492 u8 reserved_at_10[0x10]; 9493 9494 u8 xoff_timer_value[0x10]; 9495 u8 xoff_refresh[0x10]; 9496 9497 u8 reserved_at_40[0x9]; 9498 u8 fullness_threshold[0x7]; 9499 u8 port_buffer_size[0x10]; 9500 9501 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 9502 9503 u8 reserved_at_2e0[0x80]; 9504}; 9505 9506struct mlx5_ifc_paos_reg_bits { 9507 u8 swid[0x8]; 9508 u8 local_port[0x8]; 9509 u8 reserved_0[0x4]; 9510 u8 admin_status[0x4]; 9511 u8 reserved_1[0x4]; 9512 u8 oper_status[0x4]; 9513 9514 u8 ase[0x1]; 9515 u8 ee[0x1]; 9516 u8 reserved_2[0x1c]; 9517 u8 e[0x2]; 9518 9519 u8 reserved_3[0x40]; 9520}; 9521 9522struct mlx5_ifc_pamp_reg_bits { 9523 u8 reserved_0[0x8]; 9524 u8 opamp_group[0x8]; 9525 u8 reserved_1[0xc]; 9526 u8 opamp_group_type[0x4]; 9527 9528 u8 start_index[0x10]; 9529 u8 reserved_2[0x4]; 9530 u8 num_of_indices[0xc]; 9531 9532 u8 index_data[18][0x10]; 9533}; 9534 9535struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits { 9536 u8 llr_rx_cells_high[0x20]; 9537 9538 u8 llr_rx_cells_low[0x20]; 9539 9540 u8 llr_rx_error_high[0x20]; 9541 9542 u8 llr_rx_error_low[0x20]; 9543 9544 u8 llr_rx_crc_error_high[0x20]; 9545 9546 u8 llr_rx_crc_error_low[0x20]; 9547 9548 u8 llr_tx_cells_high[0x20]; 9549 9550 u8 llr_tx_cells_low[0x20]; 9551 9552 u8 llr_tx_ret_cells_high[0x20]; 9553 9554 u8 llr_tx_ret_cells_low[0x20]; 9555 9556 u8 llr_tx_ret_events_high[0x20]; 9557 9558 u8 llr_tx_ret_events_low[0x20]; 9559 9560 u8 reserved_0[0x640]; 9561}; 9562 9563struct mlx5_ifc_mtmp_reg_bits { 9564 u8 i[0x1]; 9565 u8 reserved_at_1[0x18]; 9566 u8 sensor_index[0x7]; 9567 9568 u8 reserved_at_20[0x10]; 9569 u8 temperature[0x10]; 9570 9571 u8 mte[0x1]; 9572 u8 mtr[0x1]; 9573 u8 reserved_at_42[0x0e]; 9574 u8 max_temperature[0x10]; 9575 9576 u8 tee[0x2]; 9577 u8 reserved_at_62[0x0e]; 9578 u8 temperature_threshold_hi[0x10]; 9579 9580 u8 reserved_at_80[0x10]; 9581 u8 temperature_threshold_lo[0x10]; 9582 9583 u8 reserved_at_100[0x20]; 9584 9585 u8 sensor_name[0x40]; 9586}; 9587 9588struct mlx5_ifc_lane_2_module_mapping_bits { 9589 u8 reserved_0[0x6]; 9590 u8 rx_lane[0x2]; 9591 u8 reserved_1[0x6]; 9592 u8 tx_lane[0x2]; 9593 u8 reserved_2[0x8]; 9594 u8 module[0x8]; 9595}; 9596 9597struct mlx5_ifc_eth_per_traffic_class_layout_bits { 9598 u8 transmit_queue_high[0x20]; 9599 9600 u8 transmit_queue_low[0x20]; 9601 9602 u8 reserved_0[0x780]; 9603}; 9604 9605struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits { 9606 u8 no_buffer_discard_uc_high[0x20]; 9607 9608 u8 no_buffer_discard_uc_low[0x20]; 9609 9610 u8 wred_discard_high[0x20]; 9611 9612 u8 wred_discard_low[0x20]; 9613 9614 u8 reserved_0[0x740]; 9615}; 9616 9617struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 9618 u8 rx_octets_high[0x20]; 9619 9620 u8 rx_octets_low[0x20]; 9621 9622 u8 reserved_0[0xc0]; 9623 9624 u8 rx_frames_high[0x20]; 9625 9626 u8 rx_frames_low[0x20]; 9627 9628 u8 tx_octets_high[0x20]; 9629 9630 u8 tx_octets_low[0x20]; 9631 9632 u8 reserved_1[0xc0]; 9633 9634 u8 tx_frames_high[0x20]; 9635 9636 u8 tx_frames_low[0x20]; 9637 9638 u8 rx_pause_high[0x20]; 9639 9640 u8 rx_pause_low[0x20]; 9641 9642 u8 rx_pause_duration_high[0x20]; 9643 9644 u8 rx_pause_duration_low[0x20]; 9645 9646 u8 tx_pause_high[0x20]; 9647 9648 u8 tx_pause_low[0x20]; 9649 9650 u8 tx_pause_duration_high[0x20]; 9651 9652 u8 tx_pause_duration_low[0x20]; 9653 9654 u8 rx_pause_transition_high[0x20]; 9655 9656 u8 rx_pause_transition_low[0x20]; 9657 9658 u8 rx_discards_high[0x20]; 9659 9660 u8 rx_discards_low[0x20]; 9661 9662 u8 device_stall_minor_watermark_cnt_high[0x20]; 9663 9664 u8 device_stall_minor_watermark_cnt_low[0x20]; 9665 9666 u8 device_stall_critical_watermark_cnt_high[0x20]; 9667 9668 u8 device_stall_critical_watermark_cnt_low[0x20]; 9669 9670 u8 reserved_2[0x340]; 9671}; 9672 9673struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 9674 u8 port_transmit_wait_high[0x20]; 9675 9676 u8 port_transmit_wait_low[0x20]; 9677 9678 u8 ecn_marked_high[0x20]; 9679 9680 u8 ecn_marked_low[0x20]; 9681 9682 u8 no_buffer_discard_mc_high[0x20]; 9683 9684 u8 no_buffer_discard_mc_low[0x20]; 9685 9686 u8 rx_ebp_high[0x20]; 9687 9688 u8 rx_ebp_low[0x20]; 9689 9690 u8 tx_ebp_high[0x20]; 9691 9692 u8 tx_ebp_low[0x20]; 9693 9694 u8 rx_buffer_almost_full_high[0x20]; 9695 9696 u8 rx_buffer_almost_full_low[0x20]; 9697 9698 u8 rx_buffer_full_high[0x20]; 9699 9700 u8 rx_buffer_full_low[0x20]; 9701 9702 u8 rx_icrc_encapsulated_high[0x20]; 9703 9704 u8 rx_icrc_encapsulated_low[0x20]; 9705 9706 u8 reserved_0[0x80]; 9707 9708 u8 tx_stats_pkts64octets_high[0x20]; 9709 9710 u8 tx_stats_pkts64octets_low[0x20]; 9711 9712 u8 tx_stats_pkts65to127octets_high[0x20]; 9713 9714 u8 tx_stats_pkts65to127octets_low[0x20]; 9715 9716 u8 tx_stats_pkts128to255octets_high[0x20]; 9717 9718 u8 tx_stats_pkts128to255octets_low[0x20]; 9719 9720 u8 tx_stats_pkts256to511octets_high[0x20]; 9721 9722 u8 tx_stats_pkts256to511octets_low[0x20]; 9723 9724 u8 tx_stats_pkts512to1023octets_high[0x20]; 9725 9726 u8 tx_stats_pkts512to1023octets_low[0x20]; 9727 9728 u8 tx_stats_pkts1024to1518octets_high[0x20]; 9729 9730 u8 tx_stats_pkts1024to1518octets_low[0x20]; 9731 9732 u8 tx_stats_pkts1519to2047octets_high[0x20]; 9733 9734 u8 tx_stats_pkts1519to2047octets_low[0x20]; 9735 9736 u8 tx_stats_pkts2048to4095octets_high[0x20]; 9737 9738 u8 tx_stats_pkts2048to4095octets_low[0x20]; 9739 9740 u8 tx_stats_pkts4096to8191octets_high[0x20]; 9741 9742 u8 tx_stats_pkts4096to8191octets_low[0x20]; 9743 9744 u8 tx_stats_pkts8192to10239octets_high[0x20]; 9745 9746 u8 tx_stats_pkts8192to10239octets_low[0x20]; 9747 9748 u8 reserved_1[0x2C0]; 9749}; 9750 9751struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 9752 u8 a_frames_transmitted_ok_high[0x20]; 9753 9754 u8 a_frames_transmitted_ok_low[0x20]; 9755 9756 u8 a_frames_received_ok_high[0x20]; 9757 9758 u8 a_frames_received_ok_low[0x20]; 9759 9760 u8 a_frame_check_sequence_errors_high[0x20]; 9761 9762 u8 a_frame_check_sequence_errors_low[0x20]; 9763 9764 u8 a_alignment_errors_high[0x20]; 9765 9766 u8 a_alignment_errors_low[0x20]; 9767 9768 u8 a_octets_transmitted_ok_high[0x20]; 9769 9770 u8 a_octets_transmitted_ok_low[0x20]; 9771 9772 u8 a_octets_received_ok_high[0x20]; 9773 9774 u8 a_octets_received_ok_low[0x20]; 9775 9776 u8 a_multicast_frames_xmitted_ok_high[0x20]; 9777 9778 u8 a_multicast_frames_xmitted_ok_low[0x20]; 9779 9780 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 9781 9782 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 9783 9784 u8 a_multicast_frames_received_ok_high[0x20]; 9785 9786 u8 a_multicast_frames_received_ok_low[0x20]; 9787 9788 u8 a_broadcast_frames_recieved_ok_high[0x20]; 9789 9790 u8 a_broadcast_frames_recieved_ok_low[0x20]; 9791 9792 u8 a_in_range_length_errors_high[0x20]; 9793 9794 u8 a_in_range_length_errors_low[0x20]; 9795 9796 u8 a_out_of_range_length_field_high[0x20]; 9797 9798 u8 a_out_of_range_length_field_low[0x20]; 9799 9800 u8 a_frame_too_long_errors_high[0x20]; 9801 9802 u8 a_frame_too_long_errors_low[0x20]; 9803 9804 u8 a_symbol_error_during_carrier_high[0x20]; 9805 9806 u8 a_symbol_error_during_carrier_low[0x20]; 9807 9808 u8 a_mac_control_frames_transmitted_high[0x20]; 9809 9810 u8 a_mac_control_frames_transmitted_low[0x20]; 9811 9812 u8 a_mac_control_frames_received_high[0x20]; 9813 9814 u8 a_mac_control_frames_received_low[0x20]; 9815 9816 u8 a_unsupported_opcodes_received_high[0x20]; 9817 9818 u8 a_unsupported_opcodes_received_low[0x20]; 9819 9820 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 9821 9822 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 9823 9824 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 9825 9826 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 9827 9828 u8 reserved_0[0x300]; 9829}; 9830 9831struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 9832 u8 dot3stats_alignment_errors_high[0x20]; 9833 9834 u8 dot3stats_alignment_errors_low[0x20]; 9835 9836 u8 dot3stats_fcs_errors_high[0x20]; 9837 9838 u8 dot3stats_fcs_errors_low[0x20]; 9839 9840 u8 dot3stats_single_collision_frames_high[0x20]; 9841 9842 u8 dot3stats_single_collision_frames_low[0x20]; 9843 9844 u8 dot3stats_multiple_collision_frames_high[0x20]; 9845 9846 u8 dot3stats_multiple_collision_frames_low[0x20]; 9847 9848 u8 dot3stats_sqe_test_errors_high[0x20]; 9849 9850 u8 dot3stats_sqe_test_errors_low[0x20]; 9851 9852 u8 dot3stats_deferred_transmissions_high[0x20]; 9853 9854 u8 dot3stats_deferred_transmissions_low[0x20]; 9855 9856 u8 dot3stats_late_collisions_high[0x20]; 9857 9858 u8 dot3stats_late_collisions_low[0x20]; 9859 9860 u8 dot3stats_excessive_collisions_high[0x20]; 9861 9862 u8 dot3stats_excessive_collisions_low[0x20]; 9863 9864 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 9865 9866 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 9867 9868 u8 dot3stats_carrier_sense_errors_high[0x20]; 9869 9870 u8 dot3stats_carrier_sense_errors_low[0x20]; 9871 9872 u8 dot3stats_frame_too_longs_high[0x20]; 9873 9874 u8 dot3stats_frame_too_longs_low[0x20]; 9875 9876 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 9877 9878 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 9879 9880 u8 dot3stats_symbol_errors_high[0x20]; 9881 9882 u8 dot3stats_symbol_errors_low[0x20]; 9883 9884 u8 dot3control_in_unknown_opcodes_high[0x20]; 9885 9886 u8 dot3control_in_unknown_opcodes_low[0x20]; 9887 9888 u8 dot3in_pause_frames_high[0x20]; 9889 9890 u8 dot3in_pause_frames_low[0x20]; 9891 9892 u8 dot3out_pause_frames_high[0x20]; 9893 9894 u8 dot3out_pause_frames_low[0x20]; 9895 9896 u8 reserved_0[0x3c0]; 9897}; 9898 9899struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 9900 u8 if_in_octets_high[0x20]; 9901 9902 u8 if_in_octets_low[0x20]; 9903 9904 u8 if_in_ucast_pkts_high[0x20]; 9905 9906 u8 if_in_ucast_pkts_low[0x20]; 9907 9908 u8 if_in_discards_high[0x20]; 9909 9910 u8 if_in_discards_low[0x20]; 9911 9912 u8 if_in_errors_high[0x20]; 9913 9914 u8 if_in_errors_low[0x20]; 9915 9916 u8 if_in_unknown_protos_high[0x20]; 9917 9918 u8 if_in_unknown_protos_low[0x20]; 9919 9920 u8 if_out_octets_high[0x20]; 9921 9922 u8 if_out_octets_low[0x20]; 9923 9924 u8 if_out_ucast_pkts_high[0x20]; 9925 9926 u8 if_out_ucast_pkts_low[0x20]; 9927 9928 u8 if_out_discards_high[0x20]; 9929 9930 u8 if_out_discards_low[0x20]; 9931 9932 u8 if_out_errors_high[0x20]; 9933 9934 u8 if_out_errors_low[0x20]; 9935 9936 u8 if_in_multicast_pkts_high[0x20]; 9937 9938 u8 if_in_multicast_pkts_low[0x20]; 9939 9940 u8 if_in_broadcast_pkts_high[0x20]; 9941 9942 u8 if_in_broadcast_pkts_low[0x20]; 9943 9944 u8 if_out_multicast_pkts_high[0x20]; 9945 9946 u8 if_out_multicast_pkts_low[0x20]; 9947 9948 u8 if_out_broadcast_pkts_high[0x20]; 9949 9950 u8 if_out_broadcast_pkts_low[0x20]; 9951 9952 u8 reserved_0[0x480]; 9953}; 9954 9955struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 9956 u8 ether_stats_drop_events_high[0x20]; 9957 9958 u8 ether_stats_drop_events_low[0x20]; 9959 9960 u8 ether_stats_octets_high[0x20]; 9961 9962 u8 ether_stats_octets_low[0x20]; 9963 9964 u8 ether_stats_pkts_high[0x20]; 9965 9966 u8 ether_stats_pkts_low[0x20]; 9967 9968 u8 ether_stats_broadcast_pkts_high[0x20]; 9969 9970 u8 ether_stats_broadcast_pkts_low[0x20]; 9971 9972 u8 ether_stats_multicast_pkts_high[0x20]; 9973 9974 u8 ether_stats_multicast_pkts_low[0x20]; 9975 9976 u8 ether_stats_crc_align_errors_high[0x20]; 9977 9978 u8 ether_stats_crc_align_errors_low[0x20]; 9979 9980 u8 ether_stats_undersize_pkts_high[0x20]; 9981 9982 u8 ether_stats_undersize_pkts_low[0x20]; 9983 9984 u8 ether_stats_oversize_pkts_high[0x20]; 9985 9986 u8 ether_stats_oversize_pkts_low[0x20]; 9987 9988 u8 ether_stats_fragments_high[0x20]; 9989 9990 u8 ether_stats_fragments_low[0x20]; 9991 9992 u8 ether_stats_jabbers_high[0x20]; 9993 9994 u8 ether_stats_jabbers_low[0x20]; 9995 9996 u8 ether_stats_collisions_high[0x20]; 9997 9998 u8 ether_stats_collisions_low[0x20]; 9999 10000 u8 ether_stats_pkts64octets_high[0x20]; 10001 10002 u8 ether_stats_pkts64octets_low[0x20]; 10003 10004 u8 ether_stats_pkts65to127octets_high[0x20]; 10005 10006 u8 ether_stats_pkts65to127octets_low[0x20]; 10007 10008 u8 ether_stats_pkts128to255octets_high[0x20]; 10009 10010 u8 ether_stats_pkts128to255octets_low[0x20]; 10011 10012 u8 ether_stats_pkts256to511octets_high[0x20]; 10013 10014 u8 ether_stats_pkts256to511octets_low[0x20]; 10015 10016 u8 ether_stats_pkts512to1023octets_high[0x20]; 10017 10018 u8 ether_stats_pkts512to1023octets_low[0x20]; 10019 10020 u8 ether_stats_pkts1024to1518octets_high[0x20]; 10021 10022 u8 ether_stats_pkts1024to1518octets_low[0x20]; 10023 10024 u8 ether_stats_pkts1519to2047octets_high[0x20]; 10025 10026 u8 ether_stats_pkts1519to2047octets_low[0x20]; 10027 10028 u8 ether_stats_pkts2048to4095octets_high[0x20]; 10029 10030 u8 ether_stats_pkts2048to4095octets_low[0x20]; 10031 10032 u8 ether_stats_pkts4096to8191octets_high[0x20]; 10033 10034 u8 ether_stats_pkts4096to8191octets_low[0x20]; 10035 10036 u8 ether_stats_pkts8192to10239octets_high[0x20]; 10037 10038 u8 ether_stats_pkts8192to10239octets_low[0x20]; 10039 10040 u8 reserved_0[0x280]; 10041}; 10042 10043struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits { 10044 u8 symbol_error_counter[0x10]; 10045 u8 link_error_recovery_counter[0x8]; 10046 u8 link_downed_counter[0x8]; 10047 10048 u8 port_rcv_errors[0x10]; 10049 u8 port_rcv_remote_physical_errors[0x10]; 10050 10051 u8 port_rcv_switch_relay_errors[0x10]; 10052 u8 port_xmit_discards[0x10]; 10053 10054 u8 port_xmit_constraint_errors[0x8]; 10055 u8 port_rcv_constraint_errors[0x8]; 10056 u8 reserved_0[0x8]; 10057 u8 local_link_integrity_errors[0x4]; 10058 u8 excessive_buffer_overrun_errors[0x4]; 10059 10060 u8 reserved_1[0x10]; 10061 u8 vl_15_dropped[0x10]; 10062 10063 u8 port_xmit_data[0x20]; 10064 10065 u8 port_rcv_data[0x20]; 10066 10067 u8 port_xmit_pkts[0x20]; 10068 10069 u8 port_rcv_pkts[0x20]; 10070 10071 u8 port_xmit_wait[0x20]; 10072 10073 u8 reserved_2[0x680]; 10074}; 10075 10076struct mlx5_ifc_trc_tlb_reg_bits { 10077 u8 reserved_0[0x80]; 10078 10079 u8 tlb_addr[0][0x40]; 10080}; 10081 10082struct mlx5_ifc_trc_read_fifo_reg_bits { 10083 u8 reserved_0[0x10]; 10084 u8 requested_event_num[0x10]; 10085 10086 u8 reserved_1[0x20]; 10087 10088 u8 reserved_2[0x10]; 10089 u8 acual_event_num[0x10]; 10090 10091 u8 reserved_3[0x20]; 10092 10093 u8 event[0][0x40]; 10094}; 10095 10096struct mlx5_ifc_trc_lock_reg_bits { 10097 u8 reserved_0[0x1f]; 10098 u8 lock[0x1]; 10099 10100 u8 reserved_1[0x60]; 10101}; 10102 10103struct mlx5_ifc_trc_filter_reg_bits { 10104 u8 status[0x1]; 10105 u8 reserved_0[0xf]; 10106 u8 filter_index[0x10]; 10107 10108 u8 reserved_1[0x20]; 10109 10110 u8 filter_val[0x20]; 10111 10112 u8 reserved_2[0x1a0]; 10113}; 10114 10115struct mlx5_ifc_trc_event_reg_bits { 10116 u8 status[0x1]; 10117 u8 reserved_0[0xf]; 10118 u8 event_index[0x10]; 10119 10120 u8 reserved_1[0x20]; 10121 10122 u8 event_id[0x20]; 10123 10124 u8 event_selector_val[0x10]; 10125 u8 event_selector_size[0x10]; 10126 10127 u8 reserved_2[0x180]; 10128}; 10129 10130struct mlx5_ifc_trc_conf_reg_bits { 10131 u8 limit_en[0x1]; 10132 u8 reserved_0[0x3]; 10133 u8 dump_mode[0x4]; 10134 u8 reserved_1[0x15]; 10135 u8 state[0x3]; 10136 10137 u8 reserved_2[0x20]; 10138 10139 u8 limit_event_index[0x20]; 10140 10141 u8 mkey[0x20]; 10142 10143 u8 fifo_ready_ev_num[0x20]; 10144 10145 u8 reserved_3[0x160]; 10146}; 10147 10148struct mlx5_ifc_trc_cap_reg_bits { 10149 u8 reserved_0[0x18]; 10150 u8 dump_mode[0x8]; 10151 10152 u8 reserved_1[0x20]; 10153 10154 u8 num_of_events[0x10]; 10155 u8 num_of_filters[0x10]; 10156 10157 u8 fifo_size[0x20]; 10158 10159 u8 tlb_size[0x10]; 10160 u8 event_size[0x10]; 10161 10162 u8 reserved_2[0x160]; 10163}; 10164 10165struct mlx5_ifc_set_node_in_bits { 10166 u8 node_description[64][0x8]; 10167}; 10168 10169struct mlx5_ifc_register_power_settings_bits { 10170 u8 reserved_0[0x18]; 10171 u8 power_settings_level[0x8]; 10172 10173 u8 reserved_1[0x60]; 10174}; 10175 10176struct mlx5_ifc_register_host_endianess_bits { 10177 u8 he[0x1]; 10178 u8 reserved_0[0x1f]; 10179 10180 u8 reserved_1[0x60]; 10181}; 10182 10183struct mlx5_ifc_register_diag_buffer_ctrl_bits { 10184 u8 physical_address[0x40]; 10185}; 10186 10187struct mlx5_ifc_qtct_reg_bits { 10188 u8 operation_type[0x2]; 10189 u8 cap_local_admin[0x1]; 10190 u8 cap_remote_admin[0x1]; 10191 u8 reserved_0[0x4]; 10192 u8 port_number[0x8]; 10193 u8 reserved_1[0xd]; 10194 u8 prio[0x3]; 10195 10196 u8 reserved_2[0x1d]; 10197 u8 tclass[0x3]; 10198}; 10199 10200struct mlx5_ifc_qpdp_reg_bits { 10201 u8 reserved_0[0x8]; 10202 u8 port_number[0x8]; 10203 u8 reserved_1[0x10]; 10204 10205 u8 reserved_2[0x1d]; 10206 u8 pprio[0x3]; 10207}; 10208 10209struct mlx5_ifc_port_info_ro_fields_param_bits { 10210 u8 reserved_0[0x8]; 10211 u8 port[0x8]; 10212 u8 max_gid[0x10]; 10213 10214 u8 reserved_1[0x20]; 10215 10216 u8 port_guid[0x40]; 10217}; 10218 10219struct mlx5_ifc_nvqc_reg_bits { 10220 u8 type[0x20]; 10221 10222 u8 reserved_0[0x18]; 10223 u8 version[0x4]; 10224 u8 reserved_1[0x2]; 10225 u8 support_wr[0x1]; 10226 u8 support_rd[0x1]; 10227}; 10228 10229struct mlx5_ifc_nvia_reg_bits { 10230 u8 reserved_0[0x1d]; 10231 u8 target[0x3]; 10232 10233 u8 reserved_1[0x20]; 10234}; 10235 10236struct mlx5_ifc_nvdi_reg_bits { 10237 struct mlx5_ifc_config_item_bits configuration_item_header; 10238}; 10239 10240struct mlx5_ifc_nvda_reg_bits { 10241 struct mlx5_ifc_config_item_bits configuration_item_header; 10242 10243 u8 configuration_item_data[0x20]; 10244}; 10245 10246struct mlx5_ifc_node_info_ro_fields_param_bits { 10247 u8 system_image_guid[0x40]; 10248 10249 u8 reserved_0[0x40]; 10250 10251 u8 node_guid[0x40]; 10252 10253 u8 reserved_1[0x10]; 10254 u8 max_pkey[0x10]; 10255 10256 u8 reserved_2[0x20]; 10257}; 10258 10259struct mlx5_ifc_ets_tcn_config_reg_bits { 10260 u8 g[0x1]; 10261 u8 b[0x1]; 10262 u8 r[0x1]; 10263 u8 reserved_0[0x9]; 10264 u8 group[0x4]; 10265 u8 reserved_1[0x9]; 10266 u8 bw_allocation[0x7]; 10267 10268 u8 reserved_2[0xc]; 10269 u8 max_bw_units[0x4]; 10270 u8 reserved_3[0x8]; 10271 u8 max_bw_value[0x8]; 10272}; 10273 10274struct mlx5_ifc_ets_global_config_reg_bits { 10275 u8 reserved_0[0x2]; 10276 u8 r[0x1]; 10277 u8 reserved_1[0x1d]; 10278 10279 u8 reserved_2[0xc]; 10280 u8 max_bw_units[0x4]; 10281 u8 reserved_3[0x8]; 10282 u8 max_bw_value[0x8]; 10283}; 10284 10285struct mlx5_ifc_qetc_reg_bits { 10286 u8 reserved_at_0[0x8]; 10287 u8 port_number[0x8]; 10288 u8 reserved_at_10[0x30]; 10289 10290 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10291 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10292}; 10293 10294struct mlx5_ifc_nodnic_mac_filters_bits { 10295 struct mlx5_ifc_mac_address_layout_bits mac_filter0; 10296 10297 struct mlx5_ifc_mac_address_layout_bits mac_filter1; 10298 10299 struct mlx5_ifc_mac_address_layout_bits mac_filter2; 10300 10301 struct mlx5_ifc_mac_address_layout_bits mac_filter3; 10302 10303 struct mlx5_ifc_mac_address_layout_bits mac_filter4; 10304 10305 u8 reserved_0[0xc0]; 10306}; 10307 10308struct mlx5_ifc_nodnic_gid_filters_bits { 10309 u8 mgid_filter0[16][0x8]; 10310 10311 u8 mgid_filter1[16][0x8]; 10312 10313 u8 mgid_filter2[16][0x8]; 10314 10315 u8 mgid_filter3[16][0x8]; 10316}; 10317 10318enum { 10319 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT = 0x0, 10320 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT = 0x1, 10321}; 10322 10323enum { 10324 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE = 0x0, 10325 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE = 0x1, 10326}; 10327 10328struct mlx5_ifc_nodnic_config_reg_bits { 10329 u8 no_dram_nic_revision[0x8]; 10330 u8 hardware_format[0x8]; 10331 u8 support_receive_filter[0x1]; 10332 u8 support_promisc_filter[0x1]; 10333 u8 support_promisc_multicast_filter[0x1]; 10334 u8 reserved_0[0x2]; 10335 u8 log_working_buffer_size[0x3]; 10336 u8 log_pkey_table_size[0x4]; 10337 u8 reserved_1[0x3]; 10338 u8 num_ports[0x1]; 10339 10340 u8 reserved_2[0x2]; 10341 u8 log_max_ring_size[0x6]; 10342 u8 reserved_3[0x18]; 10343 10344 u8 lkey[0x20]; 10345 10346 u8 cqe_format[0x4]; 10347 u8 reserved_4[0x1c]; 10348 10349 u8 node_guid[0x40]; 10350 10351 u8 reserved_5[0x740]; 10352 10353 struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings; 10354 10355 struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings; 10356}; 10357 10358struct mlx5_ifc_vlan_layout_bits { 10359 u8 reserved_0[0x14]; 10360 u8 vlan[0xc]; 10361 10362 u8 reserved_1[0x20]; 10363}; 10364 10365struct mlx5_ifc_umr_pointer_desc_argument_bits { 10366 u8 reserved_0[0x20]; 10367 10368 u8 mkey[0x20]; 10369 10370 u8 addressh_63_32[0x20]; 10371 10372 u8 addressl_31_0[0x20]; 10373}; 10374 10375struct mlx5_ifc_ud_adrs_vector_bits { 10376 u8 dc_key[0x40]; 10377 10378 u8 ext[0x1]; 10379 u8 reserved_0[0x7]; 10380 u8 destination_qp_dct[0x18]; 10381 10382 u8 static_rate[0x4]; 10383 u8 sl_eth_prio[0x4]; 10384 u8 fl[0x1]; 10385 u8 mlid[0x7]; 10386 u8 rlid_udp_sport[0x10]; 10387 10388 u8 reserved_1[0x20]; 10389 10390 u8 rmac_47_16[0x20]; 10391 10392 u8 rmac_15_0[0x10]; 10393 u8 tclass[0x8]; 10394 u8 hop_limit[0x8]; 10395 10396 u8 reserved_2[0x1]; 10397 u8 grh[0x1]; 10398 u8 reserved_3[0x2]; 10399 u8 src_addr_index[0x8]; 10400 u8 flow_label[0x14]; 10401 10402 u8 rgid_rip[16][0x8]; 10403}; 10404 10405struct mlx5_ifc_port_module_event_bits { 10406 u8 reserved_0[0x8]; 10407 u8 module[0x8]; 10408 u8 reserved_1[0xc]; 10409 u8 module_status[0x4]; 10410 10411 u8 reserved_2[0x14]; 10412 u8 error_type[0x4]; 10413 u8 reserved_3[0x8]; 10414 10415 u8 reserved_4[0xa0]; 10416}; 10417 10418struct mlx5_ifc_icmd_control_bits { 10419 u8 opcode[0x10]; 10420 u8 status[0x8]; 10421 u8 reserved_0[0x7]; 10422 u8 busy[0x1]; 10423}; 10424 10425struct mlx5_ifc_eqe_bits { 10426 u8 reserved_0[0x8]; 10427 u8 event_type[0x8]; 10428 u8 reserved_1[0x8]; 10429 u8 event_sub_type[0x8]; 10430 10431 u8 reserved_2[0xe0]; 10432 10433 union mlx5_ifc_event_auto_bits event_data; 10434 10435 u8 reserved_3[0x10]; 10436 u8 signature[0x8]; 10437 u8 reserved_4[0x7]; 10438 u8 owner[0x1]; 10439}; 10440 10441enum { 10442 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10443}; 10444 10445struct mlx5_ifc_cmd_queue_entry_bits { 10446 u8 type[0x8]; 10447 u8 reserved_0[0x18]; 10448 10449 u8 input_length[0x20]; 10450 10451 u8 input_mailbox_pointer_63_32[0x20]; 10452 10453 u8 input_mailbox_pointer_31_9[0x17]; 10454 u8 reserved_1[0x9]; 10455 10456 u8 command_input_inline_data[16][0x8]; 10457 10458 u8 command_output_inline_data[16][0x8]; 10459 10460 u8 output_mailbox_pointer_63_32[0x20]; 10461 10462 u8 output_mailbox_pointer_31_9[0x17]; 10463 u8 reserved_2[0x9]; 10464 10465 u8 output_length[0x20]; 10466 10467 u8 token[0x8]; 10468 u8 signature[0x8]; 10469 u8 reserved_3[0x8]; 10470 u8 status[0x7]; 10471 u8 ownership[0x1]; 10472}; 10473 10474struct mlx5_ifc_cmd_out_bits { 10475 u8 status[0x8]; 10476 u8 reserved_0[0x18]; 10477 10478 u8 syndrome[0x20]; 10479 10480 u8 command_output[0x20]; 10481}; 10482 10483struct mlx5_ifc_cmd_in_bits { 10484 u8 opcode[0x10]; 10485 u8 reserved_0[0x10]; 10486 10487 u8 reserved_1[0x10]; 10488 u8 op_mod[0x10]; 10489 10490 u8 command[0][0x20]; 10491}; 10492 10493struct mlx5_ifc_cmd_if_box_bits { 10494 u8 mailbox_data[512][0x8]; 10495 10496 u8 reserved_0[0x180]; 10497 10498 u8 next_pointer_63_32[0x20]; 10499 10500 u8 next_pointer_31_10[0x16]; 10501 u8 reserved_1[0xa]; 10502 10503 u8 block_number[0x20]; 10504 10505 u8 reserved_2[0x8]; 10506 u8 token[0x8]; 10507 u8 ctrl_signature[0x8]; 10508 u8 signature[0x8]; 10509}; 10510 10511struct mlx5_ifc_mtt_bits { 10512 u8 ptag_63_32[0x20]; 10513 10514 u8 ptag_31_8[0x18]; 10515 u8 reserved_0[0x6]; 10516 u8 wr_en[0x1]; 10517 u8 rd_en[0x1]; 10518}; 10519 10520struct mlx5_ifc_tls_progress_params_bits { 10521 u8 valid[0x1]; 10522 u8 reserved_at_1[0x7]; 10523 u8 pd[0x18]; 10524 10525 u8 next_record_tcp_sn[0x20]; 10526 10527 u8 hw_resync_tcp_sn[0x20]; 10528 10529 u8 record_tracker_state[0x2]; 10530 u8 auth_state[0x2]; 10531 u8 reserved_at_64[0x4]; 10532 u8 hw_offset_record_number[0x18]; 10533}; 10534 10535struct mlx5_ifc_tls_static_params_bits { 10536 u8 const_2[0x2]; 10537 u8 tls_version[0x4]; 10538 u8 const_1[0x2]; 10539 u8 reserved_at_8[0x14]; 10540 u8 encryption_standard[0x4]; 10541 10542 u8 reserved_at_20[0x20]; 10543 10544 u8 initial_record_number[0x40]; 10545 10546 u8 resync_tcp_sn[0x20]; 10547 10548 u8 gcm_iv[0x20]; 10549 10550 u8 implicit_iv[0x40]; 10551 10552 u8 reserved_at_100[0x8]; 10553 u8 dek_index[0x18]; 10554 10555 u8 reserved_at_120[0xe0]; 10556}; 10557 10558/* Vendor Specific Capabilities, VSC */ 10559enum { 10560 MLX5_VSC_DOMAIN_ICMD = 0x1, 10561 MLX5_VSC_DOMAIN_PROTECTED_CRSPACE = 0x6, 10562 MLX5_VSC_DOMAIN_SCAN_CRSPACE = 0x7, 10563 MLX5_VSC_DOMAIN_SEMAPHORES = 0xA, 10564}; 10565 10566struct mlx5_ifc_vendor_specific_cap_bits { 10567 u8 type[0x8]; 10568 u8 length[0x8]; 10569 u8 next_pointer[0x8]; 10570 u8 capability_id[0x8]; 10571 10572 u8 status[0x3]; 10573 u8 reserved_0[0xd]; 10574 u8 space[0x10]; 10575 10576 u8 counter[0x20]; 10577 10578 u8 semaphore[0x20]; 10579 10580 u8 flag[0x1]; 10581 u8 reserved_1[0x1]; 10582 u8 address[0x1e]; 10583 10584 u8 data[0x20]; 10585}; 10586 10587struct mlx5_ifc_vsc_space_bits { 10588 u8 status[0x3]; 10589 u8 reserved0[0xd]; 10590 u8 space[0x10]; 10591}; 10592 10593struct mlx5_ifc_vsc_addr_bits { 10594 u8 flag[0x1]; 10595 u8 reserved0[0x1]; 10596 u8 address[0x1e]; 10597}; 10598 10599enum { 10600 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10601 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10602 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10603}; 10604 10605enum { 10606 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10607 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10608 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10609}; 10610 10611enum { 10612 MLX5_HEALTH_SYNDR_FW_ERR = 0x1, 10613 MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7, 10614 MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8, 10615 MLX5_HEALTH_SYNDR_CRC_ERR = 0x9, 10616 MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa, 10617 MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb, 10618 MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc, 10619 MLX5_HEALTH_SYNDR_EQ_ERR = 0xd, 10620 MLX5_HEALTH_SYNDR_EQ_INV = 0xe, 10621 MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf, 10622 MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10, 10623}; 10624 10625struct mlx5_ifc_initial_seg_bits { 10626 u8 fw_rev_minor[0x10]; 10627 u8 fw_rev_major[0x10]; 10628 10629 u8 cmd_interface_rev[0x10]; 10630 u8 fw_rev_subminor[0x10]; 10631 10632 u8 reserved_0[0x40]; 10633 10634 u8 cmdq_phy_addr_63_32[0x20]; 10635 10636 u8 cmdq_phy_addr_31_12[0x14]; 10637 u8 reserved_1[0x2]; 10638 u8 nic_interface[0x2]; 10639 u8 log_cmdq_size[0x4]; 10640 u8 log_cmdq_stride[0x4]; 10641 10642 u8 command_doorbell_vector[0x20]; 10643 10644 u8 reserved_2[0xf00]; 10645 10646 u8 initializing[0x1]; 10647 u8 reserved_3[0x4]; 10648 u8 nic_interface_supported[0x3]; 10649 u8 reserved_4[0x18]; 10650 10651 struct mlx5_ifc_health_buffer_bits health_buffer; 10652 10653 u8 no_dram_nic_offset[0x20]; 10654 10655 u8 reserved_5[0x6de0]; 10656 10657 u8 internal_timer_h[0x20]; 10658 10659 u8 internal_timer_l[0x20]; 10660 10661 u8 reserved_6[0x20]; 10662 10663 u8 reserved_7[0x1f]; 10664 u8 clear_int[0x1]; 10665 10666 u8 health_syndrome[0x8]; 10667 u8 health_counter[0x18]; 10668 10669 u8 reserved_8[0x17fc0]; 10670}; 10671 10672union mlx5_ifc_icmd_interface_document_bits { 10673 struct mlx5_ifc_fw_version_bits fw_version; 10674 struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in; 10675 struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out; 10676 struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in; 10677 struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in; 10678 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out; 10679 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out; 10680 struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general; 10681 struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in; 10682 struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out; 10683 struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out; 10684 struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in; 10685 struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in; 10686 struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out; 10687 u8 reserved_0[0x42c0]; 10688}; 10689 10690union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 10691 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10692 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10693 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10694 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10695 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10696 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 10697 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10698 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10699 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 10700 struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs; 10701 u8 reserved_0[0x7c0]; 10702}; 10703 10704struct mlx5_ifc_ppcnt_reg_bits { 10705 u8 swid[0x8]; 10706 u8 local_port[0x8]; 10707 u8 pnat[0x2]; 10708 u8 reserved_0[0x8]; 10709 u8 grp[0x6]; 10710 10711 u8 clr[0x1]; 10712 u8 reserved_1[0x1c]; 10713 u8 prio_tc[0x3]; 10714 10715 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 10716}; 10717 10718struct mlx5_ifc_pcie_lanes_counters_bits { 10719 u8 life_time_counter_high[0x20]; 10720 10721 u8 life_time_counter_low[0x20]; 10722 10723 u8 error_counter_lane0[0x20]; 10724 10725 u8 error_counter_lane1[0x20]; 10726 10727 u8 error_counter_lane2[0x20]; 10728 10729 u8 error_counter_lane3[0x20]; 10730 10731 u8 error_counter_lane4[0x20]; 10732 10733 u8 error_counter_lane5[0x20]; 10734 10735 u8 error_counter_lane6[0x20]; 10736 10737 u8 error_counter_lane7[0x20]; 10738 10739 u8 error_counter_lane8[0x20]; 10740 10741 u8 error_counter_lane9[0x20]; 10742 10743 u8 error_counter_lane10[0x20]; 10744 10745 u8 error_counter_lane11[0x20]; 10746 10747 u8 error_counter_lane12[0x20]; 10748 10749 u8 error_counter_lane13[0x20]; 10750 10751 u8 error_counter_lane14[0x20]; 10752 10753 u8 error_counter_lane15[0x20]; 10754 10755 u8 reserved_at_240[0x580]; 10756}; 10757 10758struct mlx5_ifc_pcie_lanes_counters_ext_bits { 10759 u8 reserved_at_0[0x40]; 10760 10761 u8 error_counter_lane0[0x20]; 10762 10763 u8 error_counter_lane1[0x20]; 10764 10765 u8 error_counter_lane2[0x20]; 10766 10767 u8 error_counter_lane3[0x20]; 10768 10769 u8 error_counter_lane4[0x20]; 10770 10771 u8 error_counter_lane5[0x20]; 10772 10773 u8 error_counter_lane6[0x20]; 10774 10775 u8 error_counter_lane7[0x20]; 10776 10777 u8 error_counter_lane8[0x20]; 10778 10779 u8 error_counter_lane9[0x20]; 10780 10781 u8 error_counter_lane10[0x20]; 10782 10783 u8 error_counter_lane11[0x20]; 10784 10785 u8 error_counter_lane12[0x20]; 10786 10787 u8 error_counter_lane13[0x20]; 10788 10789 u8 error_counter_lane14[0x20]; 10790 10791 u8 error_counter_lane15[0x20]; 10792 10793 u8 reserved_at_240[0x580]; 10794}; 10795 10796struct mlx5_ifc_pcie_perf_counters_bits { 10797 u8 life_time_counter_high[0x20]; 10798 10799 u8 life_time_counter_low[0x20]; 10800 10801 u8 rx_errors[0x20]; 10802 10803 u8 tx_errors[0x20]; 10804 10805 u8 l0_to_recovery_eieos[0x20]; 10806 10807 u8 l0_to_recovery_ts[0x20]; 10808 10809 u8 l0_to_recovery_framing[0x20]; 10810 10811 u8 l0_to_recovery_retrain[0x20]; 10812 10813 u8 crc_error_dllp[0x20]; 10814 10815 u8 crc_error_tlp[0x20]; 10816 10817 u8 tx_overflow_buffer_pkt[0x40]; 10818 10819 u8 outbound_stalled_reads[0x20]; 10820 10821 u8 outbound_stalled_writes[0x20]; 10822 10823 u8 outbound_stalled_reads_events[0x20]; 10824 10825 u8 outbound_stalled_writes_events[0x20]; 10826 10827 u8 tx_overflow_buffer_marked_pkt[0x40]; 10828 10829 u8 reserved_at_240[0x580]; 10830}; 10831 10832struct mlx5_ifc_pcie_perf_counters_ext_bits { 10833 u8 reserved_at_0[0x40]; 10834 10835 u8 rx_errors[0x20]; 10836 10837 u8 tx_errors[0x20]; 10838 10839 u8 reserved_at_80[0xc0]; 10840 10841 u8 tx_overflow_buffer_pkt[0x40]; 10842 10843 u8 outbound_stalled_reads[0x20]; 10844 10845 u8 outbound_stalled_writes[0x20]; 10846 10847 u8 outbound_stalled_reads_events[0x20]; 10848 10849 u8 outbound_stalled_writes_events[0x20]; 10850 10851 u8 tx_overflow_buffer_marked_pkt[0x40]; 10852 10853 u8 reserved_at_240[0x580]; 10854}; 10855 10856struct mlx5_ifc_pcie_timers_states_bits { 10857 u8 life_time_counter_high[0x20]; 10858 10859 u8 life_time_counter_low[0x20]; 10860 10861 u8 time_to_boot_image_start[0x20]; 10862 10863 u8 time_to_link_image[0x20]; 10864 10865 u8 calibration_time[0x20]; 10866 10867 u8 time_to_first_perst[0x20]; 10868 10869 u8 time_to_detect_state[0x20]; 10870 10871 u8 time_to_l0[0x20]; 10872 10873 u8 time_to_crs_en[0x20]; 10874 10875 u8 time_to_plastic_image_start[0x20]; 10876 10877 u8 time_to_iron_image_start[0x20]; 10878 10879 u8 perst_handler[0x20]; 10880 10881 u8 times_in_l1[0x20]; 10882 10883 u8 times_in_l23[0x20]; 10884 10885 u8 dl_down[0x20]; 10886 10887 u8 config_cycle1usec[0x20]; 10888 10889 u8 config_cycle2to7usec[0x20]; 10890 10891 u8 config_cycle8to15usec[0x20]; 10892 10893 u8 config_cycle16to63usec[0x20]; 10894 10895 u8 config_cycle64usec[0x20]; 10896 10897 u8 correctable_err_msg_sent[0x20]; 10898 10899 u8 non_fatal_err_msg_sent[0x20]; 10900 10901 u8 fatal_err_msg_sent[0x20]; 10902 10903 u8 reserved_at_2e0[0x4e0]; 10904}; 10905 10906struct mlx5_ifc_pcie_timers_states_ext_bits { 10907 u8 reserved_at_0[0x40]; 10908 10909 u8 time_to_boot_image_start[0x20]; 10910 10911 u8 time_to_link_image[0x20]; 10912 10913 u8 calibration_time[0x20]; 10914 10915 u8 time_to_first_perst[0x20]; 10916 10917 u8 time_to_detect_state[0x20]; 10918 10919 u8 time_to_l0[0x20]; 10920 10921 u8 time_to_crs_en[0x20]; 10922 10923 u8 time_to_plastic_image_start[0x20]; 10924 10925 u8 time_to_iron_image_start[0x20]; 10926 10927 u8 perst_handler[0x20]; 10928 10929 u8 times_in_l1[0x20]; 10930 10931 u8 times_in_l23[0x20]; 10932 10933 u8 dl_down[0x20]; 10934 10935 u8 config_cycle1usec[0x20]; 10936 10937 u8 config_cycle2to7usec[0x20]; 10938 10939 u8 config_cycle8to15usec[0x20]; 10940 10941 u8 config_cycle16to63usec[0x20]; 10942 10943 u8 config_cycle64usec[0x20]; 10944 10945 u8 correctable_err_msg_sent[0x20]; 10946 10947 u8 non_fatal_err_msg_sent[0x20]; 10948 10949 u8 fatal_err_msg_sent[0x20]; 10950 10951 u8 reserved_at_2e0[0x4e0]; 10952}; 10953 10954union mlx5_ifc_mpcnt_reg_counter_set_auto_bits { 10955 struct mlx5_ifc_pcie_perf_counters_bits pcie_perf_counters; 10956 struct mlx5_ifc_pcie_lanes_counters_bits pcie_lanes_counters; 10957 struct mlx5_ifc_pcie_timers_states_bits pcie_timers_states; 10958 u8 reserved_at_0[0x7c0]; 10959}; 10960 10961union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits { 10962 struct mlx5_ifc_pcie_perf_counters_ext_bits pcie_perf_counters_ext; 10963 struct mlx5_ifc_pcie_lanes_counters_ext_bits pcie_lanes_counters_ext; 10964 struct mlx5_ifc_pcie_timers_states_ext_bits pcie_timers_states_ext; 10965 u8 reserved_at_0[0x7c0]; 10966}; 10967 10968struct mlx5_ifc_mpcnt_reg_bits { 10969 u8 reserved_at_0[0x2]; 10970 u8 depth[0x6]; 10971 u8 pcie_index[0x8]; 10972 u8 node[0x8]; 10973 u8 reserved_at_18[0x2]; 10974 u8 grp[0x6]; 10975 10976 u8 clr[0x1]; 10977 u8 reserved_at_21[0x1f]; 10978 10979 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits counter_set; 10980}; 10981 10982struct mlx5_ifc_mpcnt_reg_ext_bits { 10983 u8 reserved_at_0[0x2]; 10984 u8 depth[0x6]; 10985 u8 pcie_index[0x8]; 10986 u8 node[0x8]; 10987 u8 reserved_at_18[0x2]; 10988 u8 grp[0x6]; 10989 10990 u8 clr[0x1]; 10991 u8 reserved_at_21[0x1f]; 10992 10993 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits counter_set; 10994}; 10995 10996struct mlx5_ifc_monitor_opcodes_layout_bits { 10997 u8 reserved_at_0[0x10]; 10998 u8 monitor_opcode[0x10]; 10999}; 11000 11001union mlx5_ifc_pddr_status_opcode_bits { 11002 struct mlx5_ifc_monitor_opcodes_layout_bits monitor_opcodes; 11003 u8 reserved_at_0[0x20]; 11004}; 11005 11006struct mlx5_ifc_troubleshooting_info_page_layout_bits { 11007 u8 reserved_at_0[0x10]; 11008 u8 group_opcode[0x10]; 11009 11010 union mlx5_ifc_pddr_status_opcode_bits status_opcode; 11011 11012 u8 user_feedback_data[0x10]; 11013 u8 user_feedback_index[0x10]; 11014 11015 u8 status_message[0x760]; 11016}; 11017 11018union mlx5_ifc_pddr_page_data_bits { 11019 struct mlx5_ifc_troubleshooting_info_page_layout_bits troubleshooting_info_page; 11020 struct mlx5_ifc_pddr_module_info_bits pddr_module_info; 11021 u8 reserved_at_0[0x7c0]; 11022}; 11023 11024struct mlx5_ifc_pddr_reg_bits { 11025 u8 reserved_at_0[0x8]; 11026 u8 local_port[0x8]; 11027 u8 pnat[0x2]; 11028 u8 reserved_at_12[0xe]; 11029 11030 u8 reserved_at_20[0x18]; 11031 u8 page_select[0x8]; 11032 11033 union mlx5_ifc_pddr_page_data_bits page_data; 11034}; 11035 11036enum { 11037 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN = 0x9050, 11038 MLX5_MPEIN_PWR_STATUS_INVALID = 0, 11039 MLX5_MPEIN_PWR_STATUS_SUFFICIENT = 1, 11040 MLX5_MPEIN_PWR_STATUS_INSUFFICIENT = 2, 11041}; 11042 11043struct mlx5_ifc_mpein_reg_bits { 11044 u8 reserved_at_0[0x2]; 11045 u8 depth[0x6]; 11046 u8 pcie_index[0x8]; 11047 u8 node[0x8]; 11048 u8 reserved_at_18[0x8]; 11049 11050 u8 capability_mask[0x20]; 11051 11052 u8 reserved_at_40[0x8]; 11053 u8 link_width_enabled[0x8]; 11054 u8 link_speed_enabled[0x10]; 11055 11056 u8 lane0_physical_position[0x8]; 11057 u8 link_width_active[0x8]; 11058 u8 link_speed_active[0x10]; 11059 11060 u8 num_of_pfs[0x10]; 11061 u8 num_of_vfs[0x10]; 11062 11063 u8 bdf0[0x10]; 11064 u8 reserved_at_b0[0x10]; 11065 11066 u8 max_read_request_size[0x4]; 11067 u8 max_payload_size[0x4]; 11068 u8 reserved_at_c8[0x5]; 11069 u8 pwr_status[0x3]; 11070 u8 port_type[0x4]; 11071 u8 reserved_at_d4[0xb]; 11072 u8 lane_reversal[0x1]; 11073 11074 u8 reserved_at_e0[0x14]; 11075 u8 pci_power[0xc]; 11076 11077 u8 reserved_at_100[0x20]; 11078 11079 u8 device_status[0x10]; 11080 u8 port_state[0x8]; 11081 u8 reserved_at_138[0x8]; 11082 11083 u8 reserved_at_140[0x10]; 11084 u8 receiver_detect_result[0x10]; 11085 11086 u8 reserved_at_160[0x20]; 11087}; 11088 11089struct mlx5_ifc_mpein_reg_ext_bits { 11090 u8 reserved_at_0[0x2]; 11091 u8 depth[0x6]; 11092 u8 pcie_index[0x8]; 11093 u8 node[0x8]; 11094 u8 reserved_at_18[0x8]; 11095 11096 u8 reserved_at_20[0x20]; 11097 11098 u8 reserved_at_40[0x8]; 11099 u8 link_width_enabled[0x8]; 11100 u8 link_speed_enabled[0x10]; 11101 11102 u8 lane0_physical_position[0x8]; 11103 u8 link_width_active[0x8]; 11104 u8 link_speed_active[0x10]; 11105 11106 u8 num_of_pfs[0x10]; 11107 u8 num_of_vfs[0x10]; 11108 11109 u8 bdf0[0x10]; 11110 u8 reserved_at_b0[0x10]; 11111 11112 u8 max_read_request_size[0x4]; 11113 u8 max_payload_size[0x4]; 11114 u8 reserved_at_c8[0x5]; 11115 u8 pwr_status[0x3]; 11116 u8 port_type[0x4]; 11117 u8 reserved_at_d4[0xb]; 11118 u8 lane_reversal[0x1]; 11119}; 11120 11121struct mlx5_ifc_mcqi_cap_bits { 11122 u8 supported_info_bitmask[0x20]; 11123 11124 u8 component_size[0x20]; 11125 11126 u8 max_component_size[0x20]; 11127 11128 u8 log_mcda_word_size[0x4]; 11129 u8 reserved_at_64[0xc]; 11130 u8 mcda_max_write_size[0x10]; 11131 11132 u8 rd_en[0x1]; 11133 u8 reserved_at_81[0x1]; 11134 u8 match_chip_id[0x1]; 11135 u8 match_psid[0x1]; 11136 u8 check_user_timestamp[0x1]; 11137 u8 match_base_guid_mac[0x1]; 11138 u8 reserved_at_86[0x1a]; 11139}; 11140 11141struct mlx5_ifc_mcqi_reg_bits { 11142 u8 read_pending_component[0x1]; 11143 u8 reserved_at_1[0xf]; 11144 u8 component_index[0x10]; 11145 11146 u8 reserved_at_20[0x20]; 11147 11148 u8 reserved_at_40[0x1b]; 11149 u8 info_type[0x5]; 11150 11151 u8 info_size[0x20]; 11152 11153 u8 offset[0x20]; 11154 11155 u8 reserved_at_a0[0x10]; 11156 u8 data_size[0x10]; 11157 11158 u8 data[0][0x20]; 11159}; 11160 11161struct mlx5_ifc_mcc_reg_bits { 11162 u8 reserved_at_0[0x4]; 11163 u8 time_elapsed_since_last_cmd[0xc]; 11164 u8 reserved_at_10[0x8]; 11165 u8 instruction[0x8]; 11166 11167 u8 reserved_at_20[0x10]; 11168 u8 component_index[0x10]; 11169 11170 u8 reserved_at_40[0x8]; 11171 u8 update_handle[0x18]; 11172 11173 u8 handle_owner_type[0x4]; 11174 u8 handle_owner_host_id[0x4]; 11175 u8 reserved_at_68[0x1]; 11176 u8 control_progress[0x7]; 11177 u8 error_code[0x8]; 11178 u8 reserved_at_78[0x4]; 11179 u8 control_state[0x4]; 11180 11181 u8 component_size[0x20]; 11182 11183 u8 reserved_at_a0[0x60]; 11184}; 11185 11186struct mlx5_ifc_mcda_reg_bits { 11187 u8 reserved_at_0[0x8]; 11188 u8 update_handle[0x18]; 11189 11190 u8 offset[0x20]; 11191 11192 u8 reserved_at_40[0x10]; 11193 u8 size[0x10]; 11194 11195 u8 reserved_at_60[0x20]; 11196 11197 u8 data[0][0x20]; 11198}; 11199 11200union mlx5_ifc_ports_control_registers_document_bits { 11201 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data; 11202 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11203 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11204 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11205 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11206 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11207 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 11208 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11209 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11210 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout; 11211 struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout; 11212 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11213 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date; 11214 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11215 struct mlx5_ifc_paos_reg_bits paos_reg; 11216 struct mlx5_ifc_pbmc_reg_bits pbmc_reg; 11217 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11218 struct mlx5_ifc_peir_reg_bits peir_reg; 11219 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11220 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11221 struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg; 11222 struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg; 11223 struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg; 11224 struct mlx5_ifc_phrr_reg_bits phrr_reg; 11225 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11226 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11227 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11228 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11229 struct mlx5_ifc_plib_reg_bits plib_reg; 11230 struct mlx5_ifc_pll_status_data_bits pll_status_data; 11231 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11232 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11233 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11234 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11235 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11236 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11237 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11238 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11239 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11240 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11241 struct mlx5_ifc_ppll_reg_bits ppll_reg; 11242 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11243 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11244 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11245 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11246 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11247 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11248 struct mlx5_ifc_pude_reg_bits pude_reg; 11249 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11250 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11251 struct mlx5_ifc_slrp_reg_bits slrp_reg; 11252 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11253 u8 reserved_0[0x7880]; 11254}; 11255 11256union mlx5_ifc_debug_enhancements_document_bits { 11257 struct mlx5_ifc_health_buffer_bits health_buffer; 11258 u8 reserved_0[0x200]; 11259}; 11260 11261union mlx5_ifc_no_dram_nic_document_bits { 11262 struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg; 11263 struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word; 11264 struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word; 11265 struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters; 11266 struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters; 11267 struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg; 11268 struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg; 11269 struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell; 11270 u8 reserved_0[0x3160]; 11271}; 11272 11273union mlx5_ifc_uplink_pci_interface_document_bits { 11274 struct mlx5_ifc_initial_seg_bits initial_seg; 11275 struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap; 11276 u8 reserved_0[0x20120]; 11277}; 11278 11279struct mlx5_ifc_qpdpm_dscp_reg_bits { 11280 u8 e[0x1]; 11281 u8 reserved_at_01[0x0b]; 11282 u8 prio[0x04]; 11283}; 11284 11285struct mlx5_ifc_qpdpm_reg_bits { 11286 u8 reserved_at_0[0x8]; 11287 u8 local_port[0x8]; 11288 u8 reserved_at_10[0x10]; 11289 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11290}; 11291 11292struct mlx5_ifc_qpts_reg_bits { 11293 u8 reserved_at_0[0x8]; 11294 u8 local_port[0x8]; 11295 u8 reserved_at_10[0x2d]; 11296 u8 trust_state[0x3]; 11297}; 11298 11299struct mlx5_ifc_mfrl_reg_bits { 11300 u8 reserved_at_0[0x38]; 11301 u8 reset_level[0x8]; 11302}; 11303 11304enum { 11305 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTCAP = 0x9009, 11306 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTECR = 0x9109, 11307 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTMP = 0x900a, 11308 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTWE = 0x900b, 11309 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTBR = 0x900f, 11310 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTEWE = 0x910b, 11311 MLX5_MAX_TEMPERATURE = 16, 11312}; 11313 11314struct mlx5_ifc_mtbr_temp_record_bits { 11315 u8 max_temperature[0x10]; 11316 u8 temperature[0x10]; 11317}; 11318 11319struct mlx5_ifc_mtbr_reg_bits { 11320 u8 reserved_at_0[0x14]; 11321 u8 base_sensor_index[0xc]; 11322 11323 u8 reserved_at_20[0x18]; 11324 u8 num_rec[0x8]; 11325 11326 u8 reserved_at_40[0x40]; 11327 11328 struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE]; 11329}; 11330 11331struct mlx5_ifc_mtbr_reg_ext_bits { 11332 u8 reserved_at_0[0x14]; 11333 u8 base_sensor_index[0xc]; 11334 11335 u8 reserved_at_20[0x18]; 11336 u8 num_rec[0x8]; 11337 11338 u8 reserved_at_40[0x40]; 11339 11340 struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE]; 11341}; 11342 11343struct mlx5_ifc_mtcap_bits { 11344 u8 reserved_at_0[0x19]; 11345 u8 sensor_count[0x7]; 11346 11347 u8 reserved_at_20[0x19]; 11348 u8 internal_sensor_count[0x7]; 11349 11350 u8 sensor_map[0x40]; 11351}; 11352 11353struct mlx5_ifc_mtcap_ext_bits { 11354 u8 reserved_at_0[0x19]; 11355 u8 sensor_count[0x7]; 11356 11357 u8 reserved_at_20[0x20]; 11358 11359 u8 sensor_map[0x40]; 11360}; 11361 11362struct mlx5_ifc_mtecr_bits { 11363 u8 reserved_at_0[0x4]; 11364 u8 last_sensor[0xc]; 11365 u8 reserved_at_10[0x4]; 11366 u8 sensor_count[0xc]; 11367 11368 u8 reserved_at_20[0x19]; 11369 u8 internal_sensor_count[0x7]; 11370 11371 u8 sensor_map_0[0x20]; 11372 11373 u8 reserved_at_60[0x2a0]; 11374}; 11375 11376struct mlx5_ifc_mtecr_ext_bits { 11377 u8 reserved_at_0[0x4]; 11378 u8 last_sensor[0xc]; 11379 u8 reserved_at_10[0x4]; 11380 u8 sensor_count[0xc]; 11381 11382 u8 reserved_at_20[0x20]; 11383 11384 u8 sensor_map_0[0x20]; 11385 11386 u8 reserved_at_60[0x2a0]; 11387}; 11388 11389struct mlx5_ifc_mtewe_bits { 11390 u8 reserved_at_0[0x4]; 11391 u8 last_sensor[0xc]; 11392 u8 reserved_at_10[0x4]; 11393 u8 sensor_count[0xc]; 11394 11395 u8 sensor_warning_0[0x20]; 11396 11397 u8 reserved_at_40[0x2a0]; 11398}; 11399 11400struct mlx5_ifc_mtewe_ext_bits { 11401 u8 reserved_at_0[0x4]; 11402 u8 last_sensor[0xc]; 11403 u8 reserved_at_10[0x4]; 11404 u8 sensor_count[0xc]; 11405 11406 u8 sensor_warning_0[0x20]; 11407 11408 u8 reserved_at_40[0x2a0]; 11409}; 11410 11411struct mlx5_ifc_mtmp_bits { 11412 u8 reserved_at_0[0x14]; 11413 u8 sensor_index[0xc]; 11414 11415 u8 reserved_at_20[0x10]; 11416 u8 temperature[0x10]; 11417 11418 u8 mte[0x1]; 11419 u8 mtr[0x1]; 11420 u8 reserved_at_42[0xe]; 11421 u8 max_temperature[0x10]; 11422 11423 u8 tee[0x2]; 11424 u8 reserved_at_62[0xe]; 11425 u8 temperature_threshold_hi[0x10]; 11426 11427 u8 reserved_at_80[0x10]; 11428 u8 temperature_threshold_lo[0x10]; 11429 11430 u8 reserved_at_a0[0x20]; 11431 11432 u8 sensor_name_hi[0x20]; 11433 11434 u8 sensor_name_lo[0x20]; 11435}; 11436 11437struct mlx5_ifc_mtmp_ext_bits { 11438 u8 reserved_at_0[0x14]; 11439 u8 sensor_index[0xc]; 11440 11441 u8 reserved_at_20[0x10]; 11442 u8 temperature[0x10]; 11443 11444 u8 mte[0x1]; 11445 u8 mtr[0x1]; 11446 u8 reserved_at_42[0xe]; 11447 u8 max_temperature[0x10]; 11448 11449 u8 tee[0x2]; 11450 u8 reserved_at_62[0xe]; 11451 u8 temperature_threshold_hi[0x10]; 11452 11453 u8 reserved_at_80[0x10]; 11454 u8 temperature_threshold_lo[0x10]; 11455 11456 u8 reserved_at_a0[0x20]; 11457 11458 u8 sensor_name_hi[0x20]; 11459 11460 u8 sensor_name_lo[0x20]; 11461}; 11462 11463struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 11464 u8 opcode[0x10]; 11465 u8 uid[0x10]; 11466 11467 u8 vhca_tunnel_id[0x10]; 11468 u8 obj_type[0x10]; 11469 11470 u8 obj_id[0x20]; 11471 11472 u8 reserved_at_60[0x20]; 11473}; 11474 11475struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 11476 u8 status[0x8]; 11477 u8 reserved_at_8[0x18]; 11478 11479 u8 syndrome[0x20]; 11480 11481 u8 obj_id[0x20]; 11482 11483 u8 reserved_at_60[0x20]; 11484}; 11485 11486struct mlx5_ifc_umem_bits { 11487 u8 reserved_at_0[0x80]; 11488 11489 u8 reserved_at_80[0x1b]; 11490 u8 log_page_size[0x5]; 11491 11492 u8 page_offset[0x20]; 11493 11494 u8 num_of_mtt[0x40]; 11495 11496 struct mlx5_ifc_mtt_bits mtt[0]; 11497}; 11498 11499struct mlx5_ifc_uctx_bits { 11500 u8 cap[0x20]; 11501 11502 u8 reserved_at_20[0x160]; 11503}; 11504 11505struct mlx5_ifc_create_umem_in_bits { 11506 u8 opcode[0x10]; 11507 u8 uid[0x10]; 11508 11509 u8 reserved_at_20[0x10]; 11510 u8 op_mod[0x10]; 11511 11512 u8 reserved_at_40[0x40]; 11513 11514 struct mlx5_ifc_umem_bits umem; 11515}; 11516 11517struct mlx5_ifc_create_uctx_in_bits { 11518 u8 opcode[0x10]; 11519 u8 reserved_at_10[0x10]; 11520 11521 u8 reserved_at_20[0x10]; 11522 u8 op_mod[0x10]; 11523 11524 u8 reserved_at_40[0x40]; 11525 11526 struct mlx5_ifc_uctx_bits uctx; 11527}; 11528 11529struct mlx5_ifc_destroy_uctx_in_bits { 11530 u8 opcode[0x10]; 11531 u8 reserved_at_10[0x10]; 11532 11533 u8 reserved_at_20[0x10]; 11534 u8 op_mod[0x10]; 11535 11536 u8 reserved_at_40[0x10]; 11537 u8 uid[0x10]; 11538 11539 u8 reserved_at_60[0x20]; 11540}; 11541 11542struct mlx5_ifc_mtrc_string_db_param_bits { 11543 u8 string_db_base_address[0x20]; 11544 11545 u8 reserved_at_20[0x8]; 11546 u8 string_db_size[0x18]; 11547}; 11548 11549struct mlx5_ifc_mtrc_cap_bits { 11550 u8 trace_owner[0x1]; 11551 u8 trace_to_memory[0x1]; 11552 u8 reserved_at_2[0x4]; 11553 u8 trc_ver[0x2]; 11554 u8 reserved_at_8[0x14]; 11555 u8 num_string_db[0x4]; 11556 11557 u8 first_string_trace[0x8]; 11558 u8 num_string_trace[0x8]; 11559 u8 reserved_at_30[0x28]; 11560 11561 u8 log_max_trace_buffer_size[0x8]; 11562 11563 u8 reserved_at_60[0x20]; 11564 11565 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11566 11567 u8 reserved_at_280[0x180]; 11568}; 11569 11570struct mlx5_ifc_mtrc_conf_bits { 11571 u8 reserved_at_0[0x1c]; 11572 u8 trace_mode[0x4]; 11573 u8 reserved_at_20[0x18]; 11574 u8 log_trace_buffer_size[0x8]; 11575 u8 trace_mkey[0x20]; 11576 u8 reserved_at_60[0x3a0]; 11577}; 11578 11579struct mlx5_ifc_mtrc_stdb_bits { 11580 u8 string_db_index[0x4]; 11581 u8 reserved_at_4[0x4]; 11582 u8 read_size[0x18]; 11583 u8 start_offset[0x20]; 11584 u8 string_db_data[0]; 11585}; 11586 11587struct mlx5_ifc_mtrc_ctrl_bits { 11588 u8 trace_status[0x2]; 11589 u8 reserved_at_2[0x2]; 11590 u8 arm_event[0x1]; 11591 u8 reserved_at_5[0xb]; 11592 u8 modify_field_select[0x10]; 11593 u8 reserved_at_20[0x2b]; 11594 u8 current_timestamp52_32[0x15]; 11595 u8 current_timestamp31_0[0x20]; 11596 u8 reserved_at_80[0x180]; 11597}; 11598 11599struct mlx5_ifc_affiliated_event_header_bits { 11600 u8 reserved_at_0[0x10]; 11601 u8 obj_type[0x10]; 11602 11603 u8 obj_id[0x20]; 11604}; 11605 11606#define MLX5_FC_BULK_SIZE_FACTOR 128 11607 11608enum mlx5_fc_bulk_alloc_bitmask { 11609 MLX5_FC_BULK_128 = (1 << 0), 11610 MLX5_FC_BULK_256 = (1 << 1), 11611 MLX5_FC_BULK_512 = (1 << 2), 11612 MLX5_FC_BULK_1024 = (1 << 3), 11613 MLX5_FC_BULK_2048 = (1 << 4), 11614 MLX5_FC_BULK_4096 = (1 << 5), 11615 MLX5_FC_BULK_8192 = (1 << 6), 11616 MLX5_FC_BULK_16384 = (1 << 7), 11617}; 11618 11619#define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 11620 11621 11622#endif /* MLX5_IFC_H */ 11623