1/*-
2 * Copyright (c) 2017 Ian Lepore <ian@freebsd.org>
3 * All rights reserved.
4 *
5 * Development sponsored by Microsemi, Inc.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30/*
31 * Microsemi / Vitesse VSC8501 (and similar).
32 */
33
34#include "opt_platform.h"
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/kernel.h>
39#include <sys/socket.h>
40#include <sys/errno.h>
41#include <sys/module.h>
42#include <sys/bus.h>
43#include <sys/malloc.h>
44#include <sys/resource.h>
45#include <sys/rman.h>
46
47#include <net/if.h>
48#include <net/if_media.h>
49
50#include <dev/mii/mii.h>
51#include <dev/mii/miivar.h>
52#include "miidevs.h"
53#include "miibus_if.h"
54
55#ifdef FDT
56#include <dev/ofw/openfirm.h>
57#include <dev/ofw/ofw_bus.h>
58#include <dev/ofw/ofw_bus_subr.h>
59#include <dev/mii/mii_fdt.h>
60#endif
61
62#define	BIT(x)	(1 << (x))
63
64/* Vitesse VSC8501 */
65#define	VSC8501_EXTPAGE_REG		0x001f
66
67#define	VSC8501_EXTCTL1_REG		0x0017
68#define	  VSC8501_EXTCTL1_RGMII_MODE	  (1u << 12)
69
70#define	VSC8501_INT_MASK		0x19
71#define	VSC8501_INT_MDINT		BIT(15)
72#define	VSC8501_INT_SPD_CHG		BIT(14)
73#define	VSC8501_INT_LINK_CHG		BIT(13)
74#define	VSC8501_INT_FD_CHG		BIT(12)
75#define	VSC8501_INT_AN_CMPL		BIT(10)
76
77#define	VSC8501_INT_STS			0x1a
78
79#define	VSC8501_RGMII_CTRL_PAGE		0x02
80#define	VSC8501_RGMII_CTRL_REG		0x14
81#define	  VSC8501_RGMII_DELAY_MASK	  0x07
82#define	  VSC8501_RGMII_DELAY_TXSHIFT	  0
83#define	  VSC8501_RGMII_DELAY_RXSHIFT	  4
84#define	  VSC8501_RGMII_RXCLOCK_DISABLE	  (1u << 11)
85#define	  VSC8501_RGMII_RXSWAP		  (1u <<  7)
86#define	  VSC8501_RGMII_TXSWAP		  (1u <<  3)
87#define	  VSC8501_RGMII_LANESWAP	  (VSC8501_RGMII_RXSWAP | \
88					   VSC8501_RGMII_TXSWAP)
89
90struct vscphy_softc {
91	mii_softc_t	mii_sc;
92	device_t	dev;
93	mii_contype_t	contype;
94	int		rxdelay;
95	int		txdelay;
96	bool		laneswap;
97	struct resource *irq_res;
98	void 		*irq_cookie;
99};
100
101static void vscphy_reset(struct mii_softc *);
102static int  vscphy_service(struct mii_softc *, struct mii_data *, int);
103
104static const struct mii_phydesc vscphys[] = {
105	MII_PHY_DESC(xxVITESSE, VSC8501),
106	MII_PHY_DESC(xxVITESSE, VSC8504),
107	MII_PHY_DESC(xxVITESSE, VSC8514),
108	MII_PHY_END
109};
110
111static const struct mii_phy_funcs vscphy_funcs = {
112	vscphy_service,
113	ukphy_status,
114	vscphy_reset
115};
116
117#ifdef FDT
118static void
119vscphy_fdt_get_config(struct vscphy_softc *vsc)
120{
121	mii_fdt_phy_config_t *cfg;
122	pcell_t val;
123
124	cfg = mii_fdt_get_config(vsc->dev);
125	vsc->contype = cfg->con_type;
126	vsc->laneswap = (cfg->flags & MIIF_FDT_LANE_SWAP) &&
127	    !(cfg->flags & MIIF_FDT_NO_LANE_SWAP);
128	if (OF_getencprop(cfg->phynode, "rx-delay", &val, sizeof(val)) > 0)
129		vsc->rxdelay = val;
130	if (OF_getencprop(cfg->phynode, "tx-delay", &val, sizeof(val)) > 0)
131		vsc->txdelay = val;
132	vsc->mii_sc.mii_maxspeed = cfg->max_speed;
133	mii_fdt_free_config(cfg);
134}
135#endif
136
137static inline int
138vscphy_read(struct vscphy_softc *sc, u_int reg)
139{
140	u_int val;
141
142	val = PHY_READ(&sc->mii_sc, reg);
143	return (val);
144}
145
146static inline void
147vscphy_write(struct vscphy_softc *sc, u_int reg, u_int val)
148{
149
150	PHY_WRITE(&sc->mii_sc, reg, val);
151}
152
153static void
154vsc8501_setup_rgmii(struct vscphy_softc *vsc)
155{
156	int reg;
157
158	vscphy_write(vsc, VSC8501_EXTPAGE_REG, VSC8501_RGMII_CTRL_PAGE);
159
160	reg = vscphy_read(vsc, VSC8501_RGMII_CTRL_REG);
161	reg &= ~VSC8501_RGMII_RXCLOCK_DISABLE;
162	reg &= ~VSC8501_RGMII_LANESWAP;
163	reg &= ~(VSC8501_RGMII_DELAY_MASK << VSC8501_RGMII_DELAY_TXSHIFT);
164	reg &= ~(VSC8501_RGMII_DELAY_MASK << VSC8501_RGMII_DELAY_RXSHIFT);
165	if (vsc->laneswap)
166		reg |= VSC8501_RGMII_LANESWAP;
167	if (vsc->contype == MII_CONTYPE_RGMII_ID ||
168	    vsc->contype == MII_CONTYPE_RGMII_TXID) {
169		reg |= vsc->txdelay << VSC8501_RGMII_DELAY_TXSHIFT;
170	}
171	if (vsc->contype == MII_CONTYPE_RGMII_ID ||
172	    vsc->contype == MII_CONTYPE_RGMII_RXID) {
173		reg |= vsc->rxdelay << VSC8501_RGMII_DELAY_RXSHIFT;
174	}
175	vscphy_write(vsc, VSC8501_RGMII_CTRL_REG, reg);
176
177	vscphy_write(vsc, VSC8501_EXTPAGE_REG, 0);
178}
179
180static void
181vsc8501_reset(struct vscphy_softc *vsc)
182{
183	int reg;
184
185	/*
186	 * Must set whether the mac<->phy connection is RGMII first; changes to
187	 * that bit take effect only after a softreset.
188	 */
189	reg = vscphy_read(vsc, VSC8501_EXTCTL1_REG);
190	if (mii_contype_is_rgmii(vsc->contype))
191		reg |= VSC8501_EXTCTL1_RGMII_MODE;
192	else
193		reg &= ~VSC8501_EXTCTL1_RGMII_MODE;
194	vscphy_write(vsc, VSC8501_EXTCTL1_REG, reg);
195
196	mii_phy_reset(&vsc->mii_sc);
197
198	/*
199	 * Setup rgmii control register if necessary, after softreset.
200	 */
201	if (mii_contype_is_rgmii(vsc->contype))
202	    vsc8501_setup_rgmii(vsc);
203}
204
205static void
206vscphy_reset(struct mii_softc *sc)
207{
208	struct vscphy_softc *vsc = (struct vscphy_softc *)sc;
209
210	switch (sc->mii_mpd_model) {
211	case MII_MODEL_xxVITESSE_VSC8501:
212		vsc8501_reset(vsc);
213		break;
214	default:
215		mii_phy_reset(sc);
216		break;
217	}
218}
219
220static int
221vscphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
222{
223
224	switch (cmd) {
225	case MII_POLLSTAT:
226		break;
227
228	case MII_MEDIACHG:
229		mii_phy_setmedia(sc);
230		break;
231
232	case MII_TICK:
233		if (mii_phy_tick(sc) == EJUSTRETURN)
234			return (0);
235		break;
236	}
237
238	/* Update the media status. */
239	PHY_STATUS(sc);
240
241	/* Callback if something changed. */
242	mii_phy_update(sc, cmd);
243	return (0);
244}
245
246static int
247vscphy_probe(device_t dev)
248{
249
250	return (mii_phy_dev_probe(dev, vscphys, BUS_PROBE_DEFAULT));
251}
252
253static void
254vscphy_intr(void *arg)
255{
256	struct vscphy_softc *vsc;
257	uint32_t status;
258
259	vsc = (struct vscphy_softc *)arg;
260
261	status = vscphy_read(vsc, VSC8501_INT_STS);
262	status &= vscphy_read(vsc, VSC8501_INT_MASK);
263
264	if (!status)
265		return;
266
267	PHY_STATUS(&vsc->mii_sc);
268	mii_phy_update(&vsc->mii_sc, MII_MEDIACHG);
269}
270
271static int
272vscphy_attach(device_t dev)
273{
274	struct vscphy_softc *vsc;
275	uint32_t value;
276	int rid, error;
277
278	vsc = device_get_softc(dev);
279	vsc->dev = dev;
280
281#ifdef FDT
282	vscphy_fdt_get_config(vsc);
283#endif
284
285	mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &vscphy_funcs, 1);
286	mii_phy_setmedia(&vsc->mii_sc);
287
288	rid = 0;
289	vsc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
290	    RF_ACTIVE | RF_SHAREABLE);
291	if (vsc->irq_res == NULL)
292		goto no_irq;
293
294	error = bus_setup_intr(dev, vsc->irq_res, INTR_TYPE_NET | INTR_MPSAFE,
295	    NULL, vscphy_intr, vsc, &vsc->irq_cookie);
296	if (error != 0) {
297		bus_release_resource(dev, SYS_RES_IRQ, 0, vsc->irq_res);
298		vsc->irq_res = NULL;
299		goto no_irq;
300	}
301
302	/* Ack and unmask all relevant interrupts. */
303	(void)vscphy_read(vsc, VSC8501_INT_STS);
304	value = VSC8501_INT_MDINT    |
305		VSC8501_INT_SPD_CHG  |
306		VSC8501_INT_LINK_CHG |
307		VSC8501_INT_FD_CHG   |
308		VSC8501_INT_AN_CMPL;
309	vscphy_write(vsc, VSC8501_INT_MASK, value);
310
311no_irq:
312	return (0);
313}
314
315static int
316vscphy_detach(device_t dev)
317{
318	struct vscphy_softc *vsc;
319
320	vsc = device_get_softc(dev);
321
322	bus_teardown_intr(dev, vsc->irq_res, vsc->irq_cookie);
323	bus_release_resource(dev, SYS_RES_IRQ, 0, vsc->irq_res);
324
325	return (mii_phy_detach(dev));
326}
327
328static device_method_t vscphy_methods[] = {
329	/* device interface */
330	DEVMETHOD(device_probe,		vscphy_probe),
331	DEVMETHOD(device_attach,	vscphy_attach),
332	DEVMETHOD(device_detach,	vscphy_detach),
333	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
334	DEVMETHOD_END
335};
336
337static driver_t vscphy_driver = {
338	"vscphy",
339	vscphy_methods,
340	sizeof(struct vscphy_softc)
341};
342
343DRIVER_MODULE(vscphy, miibus, vscphy_driver, 0, 0);
344