1/*
2 * Copyright (c) 2022 Jared McNeill <jmcneill@invisible.ca>
3 * Copyright (c) 2022 Soren Schmidt <sos@deepcore.dk>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
16 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
17 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
18 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
19 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28/*
29 * Motorcomm YT8511C / YT8511H Integrated 10/100/1000 Gigabit Ethernet phy
30 */
31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/kernel.h>
35#include <sys/socket.h>
36#include <sys/errno.h>
37#include <sys/module.h>
38#include <sys/bus.h>
39
40#include <net/if.h>
41#include <net/if_media.h>
42
43#include <dev/mii/mii.h>
44#include <dev/mii/miivar.h>
45
46#include "miibus_if.h"
47
48#define	MCOMMPHY_OUI			0x000000
49#define	MCOMMPHY_MODEL			0x10
50#define	MCOMMPHY_REV			0x0a
51
52#define	EXT_REG_ADDR			0x1e
53#define	EXT_REG_DATA			0x1f
54
55/* Extended registers */
56#define	PHY_CLOCK_GATING_REG		0x0c
57#define	 RX_CLK_DELAY_EN		0x0001
58#define	 CLK_25M_SEL			0x0006
59#define	 CLK_25M_SEL_125M		3
60#define	 TX_CLK_DELAY_SEL		0x00f0
61#define	PHY_SLEEP_CONTROL1_REG		0x27
62#define	 PLLON_IN_SLP			0x4000
63
64#define	LOWEST_SET_BIT(mask)		((((mask) - 1) & (mask)) ^ (mask))
65#define	SHIFTIN(x, mask)		((x) * LOWEST_SET_BIT(mask))
66
67static int
68mcommphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
69{
70	switch (cmd) {
71	case MII_POLLSTAT:
72		break;
73
74	case MII_MEDIACHG:
75		mii_phy_setmedia(sc);
76		break;
77
78	case MII_TICK:
79		if (mii_phy_tick(sc) == EJUSTRETURN)
80			return (0);
81		break;
82	}
83
84	/* Update the media status. */
85	PHY_STATUS(sc);
86
87	/* Callback if something changed. */
88	mii_phy_update(sc, cmd);
89
90	return (0);
91}
92
93static const struct mii_phy_funcs mcommphy_funcs = {
94	mcommphy_service,
95	ukphy_status,
96	mii_phy_reset
97};
98
99static int
100mcommphy_probe(device_t dev)
101{
102	struct mii_attach_args *ma = device_get_ivars(dev);
103
104	/*
105	 * The YT8511C reports an OUI of 0. Best we can do here is to match
106	 * exactly the contents of the PHY identification registers.
107	 */
108	if (MII_OUI(ma->mii_id1, ma->mii_id2) == MCOMMPHY_OUI &&
109	    MII_MODEL(ma->mii_id2) == MCOMMPHY_MODEL &&
110	    MII_REV(ma->mii_id2) == MCOMMPHY_REV) {
111		device_set_desc(dev, "Motorcomm YT8511 media interface");
112		return BUS_PROBE_DEFAULT;
113	}
114	return (ENXIO);
115}
116
117static int
118mcommphy_attach(device_t dev)
119{
120	struct mii_softc *sc = device_get_softc(dev);
121	uint16_t oldaddr, data;
122
123	mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &mcommphy_funcs, 0);
124
125	PHY_RESET(sc);
126
127	/* begin chip stuff */
128	oldaddr = PHY_READ(sc, EXT_REG_ADDR);
129
130	PHY_WRITE(sc, EXT_REG_ADDR, PHY_CLOCK_GATING_REG);
131	data = PHY_READ(sc, EXT_REG_DATA);
132	data &= ~CLK_25M_SEL;
133	data |= SHIFTIN(CLK_25M_SEL_125M, CLK_25M_SEL);
134	if (sc->mii_flags & MIIF_RX_DELAY) {
135		data |= RX_CLK_DELAY_EN;
136	} else {
137		data &= ~RX_CLK_DELAY_EN;
138	}
139	data &= ~TX_CLK_DELAY_SEL;
140	if (sc->mii_flags & MIIF_TX_DELAY) {
141		data |= SHIFTIN(0xf, TX_CLK_DELAY_SEL);
142	} else {
143		data |= SHIFTIN(0x2, TX_CLK_DELAY_SEL);
144	}
145	PHY_WRITE(sc, EXT_REG_DATA, data);
146
147	PHY_WRITE(sc, EXT_REG_ADDR, PHY_SLEEP_CONTROL1_REG);
148	data = PHY_READ(sc, EXT_REG_DATA);
149	data |= PLLON_IN_SLP;
150	PHY_WRITE(sc, EXT_REG_DATA, data);
151
152	PHY_WRITE(sc, EXT_REG_ADDR, oldaddr);
153	/* end chip stuff */
154
155	sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask;
156	if (sc->mii_capabilities & BMSR_EXTSTAT)
157		sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
158	device_printf(dev, " ");
159	mii_phy_add_media(sc);
160	printf("\n");
161
162	MIIBUS_MEDIAINIT(sc->mii_dev);
163
164	return (0);
165}
166
167
168static device_method_t mcommphy_methods[] = {
169	/* device interface */
170	DEVMETHOD(device_probe,		mcommphy_probe),
171	DEVMETHOD(device_attach,	mcommphy_attach),
172	DEVMETHOD(device_detach,	mii_phy_detach),
173	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
174	DEVMETHOD_END
175};
176
177static driver_t mcommphy_driver = {
178	"mcommphy",
179	mcommphy_methods,
180	sizeof(struct mii_softc)
181};
182
183DRIVER_MODULE(mcommphy, miibus, mcommphy_driver, 0, 0);
184