1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2017 Ian Lepore.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28/*
29 * Driver for ISL12xx family i2c realtime clocks:
30 *  - ISL1209 = 2B sram, tamper/event timestamp
31 *  - ISL1218 = 8B sram, DS13xx pin compatible (but not software compatible)
32 *  - ISL1219 = 2B sram, tamper/event timestamp
33 *  - ISL1220 = 8B sram, separate Fout
34 *  - ISL1221 = 2B sram, separate Fout, tamper/event timestamp
35 *
36 * This driver supports only the basic RTC functionality in all these chips.
37 */
38
39#include "opt_platform.h"
40
41#include <sys/param.h>
42#include <sys/systm.h>
43#include <sys/bus.h>
44#include <sys/clock.h>
45#include <sys/kernel.h>
46#include <sys/lock.h>
47#include <sys/module.h>
48#include <sys/sx.h>
49
50#ifdef FDT
51#include <dev/ofw/ofw_bus.h>
52#include <dev/ofw/ofw_bus_subr.h>
53#endif
54
55#include <dev/iicbus/iiconf.h>
56#include <dev/iicbus/iicbus.h>
57
58#include "clock_if.h"
59#include "iicbus_if.h"
60
61/*
62 * All register and bit names as found in the datasheet.  When a bit name ends
63 * in 'B' that stands for "bar" and it is an active-low signal; something named
64 * "EVENB" implies 1=event-disable, 0=event-enable.
65 */
66
67#define	ISL12XX_SC_REG		0x00		/* RTC Seconds */
68
69#define	ISL12XX_SR_REG		0x07		/* Status */
70#define	  ISL12XX_SR_ARST	  (1u << 7)	/*   Auto-reset on status read */
71#define	  ISL12XX_SR_XTOSCB	  (1u << 5)	/*   Osc disable (use ext osc) */
72#define	  ISL12XX_SR_WRTC	  (1u << 4)	/*   Write RTC enable */
73#define	  ISL12XX_SR_EVT	  (1u << 3)	/*   Event occurred (w0c) */
74#define	  ISL12XX_SR_ALM	  (1u << 2)	/*   Alarm occurred (w0c) */
75#define	  ISL12XX_SR_BAT	  (1u << 1)	/*   Running on battery (w0c) */
76#define	  ISL12XX_SR_RTCF	  (1u << 0)	/*   RTC fail (power loss) */
77#define	  ISL12XX_SR_W0C_BITS (ISL12XX_SR_BAT | ISL12XX_SR_ALM | ISL12XX_SR_EVT)
78
79#define	ISL12XX_INT_REG		0x08		/* Interrupts */
80#define	  ISL12XX_INT_IM	  (1u << 7)	/*   Alarm interrupt mode */
81#define	  ISL12XX_INT_ALME	  (1u << 6)	/*   Alarm enable */
82#define	  ISL12XX_INT_LPMODE	  (1u << 5)	/*   Low Power mode */
83#define	  ISL12XX_INT_FOBATB	  (1u << 4)	/*   Fout/IRQ disabled on bat */
84#define	  ISL12XX_INT_FO_SHIFT	  0		/*   Frequency output select */
85#define	  ISL12XX_INT_FO_MASK	  0x0f		/*   shift and mask. */
86
87#define	ISL12XX_EV_REG		0x09		/* Event */
88#define	  ISL12XX_EV_EVIENB	  (1u << 7)	/*   Disable internal pullup */
89#define	  ISL12XX_EV_EVBATB	  (1u << 6)	/*   Disable ev detect on bat */
90#define	  ISL12XX_EV_RTCHLT	  (1u << 5)	/*   Halt RTC on event */
91#define	  ISL12XX_EV_EVEN	  (1u << 4)	/*   Event detect enable */
92#define	  ISL12XX_EV_EHYS_SHIFT	  2		/*   Event input hysteresis */
93#define	  ISL12XX_EV_EHYS_MASK	  0x03		/*   selection; see datasheet */
94#define	  ISL12XX_EV_ESMP_SHIFT	  0		/*   Event input sample rate */
95#define	  ISL12XX_EV_ESMP_MASK	  0x03		/*   selection; see datasheet */
96
97#define	ISL12XX_ATR_REG		0x0a		/* Analog trim (osc adjust) */
98
99#define	ISL12XX_DTR_REG		0x0b		/* Digital trim (osc adjust) */
100
101#define	ISL12XX_SCA_REG		0x0c		/* Alarm seconds */
102
103#define	ISL12XX_USR1_REG	0x12		/* User byte 1 */
104
105#define	ISL12XX_USR2_REG	0x13		/* User byte 2 */
106
107#define	ISL12XX_SCT_REG		0x14		/* Timestamp (event) seconds */
108
109#define	ISL12XX_24HR_FLAG	(1u << 7)	/* Hours register 24-hr mode */
110#define	ISL12XX_PM_FLAG		(1u << 5)	/* Hours register PM flag */
111#define	ISL12xx_12HR_MASK	0x1f		/* Hours mask in AM/PM mode */
112#define	ISL12xx_24HR_MASK	0x3f		/* Hours mask in 24-hr mode */
113
114/*
115 * A struct laid out in the same order as the time registers in the chip.
116 */
117struct time_regs {
118	uint8_t sec, min, hour, day, month, year;
119};
120
121struct isl12xx_softc {
122	device_t	dev;
123	device_t	busdev;
124	struct intr_config_hook
125			init_hook;
126	bool		use_ampm;
127};
128
129#ifdef FDT
130static struct ofw_compat_data compat_data[] = {
131	{"isil,isl1209", 1},
132	{"isil,isl1218", 1},
133	{"isil,isl1219", 1},
134	{"isil,isl1220", 1},
135	{"isil,isl1221", 1},
136	{NULL,           0},
137};
138#endif
139
140/*
141 * When doing i2c IO, indicate that we need to wait for exclusive bus ownership,
142 * but that we should not wait if we already own the bus.  This lets us put
143 * iicbus_acquire_bus() calls with a non-recursive wait at the entry of our API
144 * functions to ensure that only one client at a time accesses the hardware for
145 * the entire series of operations it takes to read or write the clock.
146 */
147#define	WAITFLAGS	(IIC_WAIT | IIC_RECURSIVE)
148
149static inline int
150isl12xx_read1(struct isl12xx_softc *sc, uint8_t reg, uint8_t *data)
151{
152
153	return (iicdev_readfrom(sc->dev, reg, data, 1, WAITFLAGS));
154}
155
156static inline int
157isl12xx_write1(struct isl12xx_softc *sc, uint8_t reg, uint8_t val)
158{
159
160	return (iicdev_writeto(sc->dev, reg, &val, 1, WAITFLAGS));
161}
162
163static void
164isl12xx_init(void *arg)
165{
166	struct isl12xx_softc *sc = arg;
167	uint8_t sreg;
168
169	config_intrhook_disestablish(&sc->init_hook);
170
171	/*
172	 * Check the clock-stopped/power-fail bit, just so we can report it to
173	 * the user at boot time.
174	 */
175	isl12xx_read1(sc, ISL12XX_SR_REG, &sreg);
176	if (sreg & ISL12XX_SR_RTCF) {
177		device_printf(sc->dev,
178		    "RTC clock stopped; check battery\n");
179	}
180
181	/*
182	 * Register as a system realtime clock.
183	 */
184	clock_register_flags(sc->dev, 1000000, CLOCKF_SETTIME_NO_ADJ);
185	clock_schedule(sc->dev, 1);
186}
187
188static int
189isl12xx_probe(device_t dev)
190{
191
192#ifdef FDT
193	if (!ofw_bus_status_okay(dev))
194		return (ENXIO);
195
196	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
197		device_set_desc(dev, "Intersil ISL12xx RTC");
198		return (BUS_PROBE_DEFAULT);
199	}
200#endif
201	return (ENXIO);
202}
203
204static int
205isl12xx_attach(device_t dev)
206{
207	struct isl12xx_softc *sc = device_get_softc(dev);
208
209	sc->dev = dev;
210	sc->busdev = device_get_parent(sc->dev);
211
212	/*
213	 * Chip init must wait until interrupts are enabled.  Often i2c access
214	 * works only when the interrupts are available.
215	 */
216	sc->init_hook.ich_func = isl12xx_init;
217	sc->init_hook.ich_arg = sc;
218	if (config_intrhook_establish(&sc->init_hook) != 0)
219		return (ENOMEM);
220
221	return (0);
222}
223
224static int
225isl12xx_detach(device_t dev)
226{
227
228	clock_unregister(dev);
229	return (0);
230}
231
232static int
233isl12xx_gettime(device_t dev, struct timespec *ts)
234{
235	struct isl12xx_softc *sc = device_get_softc(dev);
236	struct bcd_clocktime bct;
237	struct time_regs tregs;
238	int err;
239	uint8_t hourmask, sreg;
240
241	/*
242	 * Read the status and time registers.
243	 */
244	if ((err = iicbus_request_bus(sc->busdev, sc->dev, IIC_WAIT)) == 0) {
245		if ((err = isl12xx_read1(sc, ISL12XX_SR_REG, &sreg)) == 0) {
246			err = iicdev_readfrom(sc->dev, ISL12XX_SC_REG, &tregs,
247			    sizeof(tregs), WAITFLAGS);
248		}
249		iicbus_release_bus(sc->busdev, sc->dev);
250	}
251	if (err != 0)
252		return (err);
253
254	/* If power failed, we can't provide valid time. */
255	if (sreg & ISL12XX_SR_RTCF)
256		return (EINVAL);
257
258	/* If chip is in AM/PM mode remember that for when we set time. */
259	if (tregs.hour & ISL12XX_24HR_FLAG) {
260		hourmask = ISL12xx_24HR_MASK;
261	} else {
262		sc->use_ampm = true;
263		hourmask = ISL12xx_12HR_MASK;
264	}
265
266	bct.nsec = 0;
267	bct.sec  = tregs.sec;
268	bct.min  = tregs.min;
269	bct.hour = tregs.hour & hourmask;
270	bct.day  = tregs.day;
271	bct.mon  = tregs.month;
272	bct.year = tregs.year;
273	bct.ispm = tregs.hour & ISL12XX_PM_FLAG;
274
275	clock_dbgprint_bcd(sc->dev, CLOCK_DBG_READ, &bct);
276	return (clock_bcd_to_ts(&bct, ts, sc->use_ampm));
277}
278
279static int
280isl12xx_settime(device_t dev, struct timespec *ts)
281{
282	struct isl12xx_softc *sc = device_get_softc(dev);
283	struct bcd_clocktime bct;
284	struct time_regs tregs;
285	int err;
286	uint8_t ampmflags, sreg;
287
288	/*
289	 * We request a timespec with no resolution-adjustment.  That also
290	 * disables utc adjustment, so apply that ourselves.
291	 */
292	ts->tv_sec -= utc_offset();
293	ts->tv_nsec = 0;
294	clock_ts_to_bcd(ts, &bct, sc->use_ampm);
295	clock_dbgprint_bcd(sc->dev, CLOCK_DBG_WRITE, &bct);
296
297	/* If the chip is in AM/PM mode, set flags as needed. */
298	if (!sc->use_ampm)
299		ampmflags = ISL12XX_24HR_FLAG;
300	else
301		ampmflags = bct.ispm ? ISL12XX_PM_FLAG : 0;
302
303	tregs.sec   = bct.sec;
304	tregs.min   = bct.min;
305	tregs.hour  = bct.hour | ampmflags;
306	tregs.day   = bct.day;
307	tregs.month = bct.mon;
308	tregs.year  = bct.year % 100;
309
310	/*
311	 * To set the time we have to set the WRTC enable bit in the control
312	 * register, then write the time regs, then clear the WRTC bit.  While
313	 * doing so we have to be careful to not write a 0 to any sreg bit which
314	 * is "write 0 to clear". One of those bits could get set between
315	 * reading and writing the register.  All those bits ignore attempts to
316	 * write a 1, so just always OR-in all the W0C bits to be sure we never
317	 * accidentally clear one.  We hold ownership of the i2c bus for the
318	 * whole read-modify-write sequence.
319	 */
320	if ((err = iicbus_request_bus(sc->busdev, sc->dev, IIC_WAIT)) != 0)
321		return (err);
322	if ((err = isl12xx_read1(sc, ISL12XX_SR_REG, &sreg)) == 0) {
323		sreg |= ISL12XX_SR_WRTC | ISL12XX_SR_W0C_BITS;
324		if ((err = isl12xx_write1(sc, ISL12XX_SR_REG, sreg)) == 0) {
325			err = iicdev_writeto(sc->dev, ISL12XX_SC_REG, &tregs,
326			    sizeof(tregs), WAITFLAGS);
327			sreg &= ~ISL12XX_SR_WRTC;
328			isl12xx_write1(sc, ISL12XX_SR_REG, sreg);
329		}
330	}
331	iicbus_release_bus(sc->busdev, sc->dev);
332
333	return (err);
334}
335
336static device_method_t isl12xx_methods[] = {
337        /* device_if methods */
338	DEVMETHOD(device_probe,		isl12xx_probe),
339	DEVMETHOD(device_attach,	isl12xx_attach),
340	DEVMETHOD(device_detach,	isl12xx_detach),
341
342        /* clock_if methods */
343	DEVMETHOD(clock_gettime,	isl12xx_gettime),
344	DEVMETHOD(clock_settime,	isl12xx_settime),
345
346	DEVMETHOD_END,
347};
348
349static driver_t isl12xx_driver = {
350	"isl12xx",
351	isl12xx_methods,
352	sizeof(struct isl12xx_softc),
353};
354
355DRIVER_MODULE(isl12xx, iicbus, isl12xx_driver, NULL, NULL);
356MODULE_VERSION(isl12xx, 1);
357MODULE_DEPEND(isl12xx, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER);
358IICBUS_FDT_PNP_INFO(compat_data);
359