1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2004-2005 MARVELL SEMICONDUCTOR ISRAEL, LTD. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28#ifndef __INCmvStorageDevh 29#define __INCmvStorageDevh 30 31/* Definitions */ 32 33/* ATA register on the ATA drive*/ 34 35#define MV_EDMA_ATA_FEATURES_ADDR 0x11 36#define MV_EDMA_ATA_SECTOR_COUNT_ADDR 0x12 37#define MV_EDMA_ATA_LBA_LOW_ADDR 0x13 38#define MV_EDMA_ATA_LBA_MID_ADDR 0x14 39#define MV_EDMA_ATA_LBA_HIGH_ADDR 0x15 40#define MV_EDMA_ATA_DEVICE_ADDR 0x16 41#define MV_EDMA_ATA_COMMAND_ADDR 0x17 42 43#define MV_ATA_ERROR_STATUS 0x00000001 /* MV_BIT0 */ 44#define MV_ATA_DATA_REQUEST_STATUS 0x00000008 /* MV_BIT3 */ 45#define MV_ATA_SERVICE_STATUS 0x00000010 /* MV_BIT4 */ 46#define MV_ATA_DEVICE_FAULT_STATUS 0x00000020 /* MV_BIT5 */ 47#define MV_ATA_READY_STATUS 0x00000040 /* MV_BIT6 */ 48#define MV_ATA_BUSY_STATUS 0x00000080 /* MV_BIT7 */ 49 50 51#define MV_ATA_COMMAND_READ_SECTORS 0x20 52#define MV_ATA_COMMAND_READ_SECTORS_EXT 0x24 53#define MV_ATA_COMMAND_READ_VERIFY_SECTORS 0x40 54#define MV_ATA_COMMAND_READ_VERIFY_SECTORS_EXT 0x42 55#define MV_ATA_COMMAND_READ_BUFFER 0xE4 56#define MV_ATA_COMMAND_WRITE_BUFFER 0xE8 57#define MV_ATA_COMMAND_WRITE_SECTORS 0x30 58#define MV_ATA_COMMAND_WRITE_SECTORS_EXT 0x34 59#define MV_ATA_COMMAND_DIAGNOSTIC 0x90 60#define MV_ATA_COMMAND_SMART 0xb0 61#define MV_ATA_COMMAND_READ_MULTIPLE 0xc4 62#define MV_ATA_COMMAND_WRITE_MULTIPLE 0xc5 63#define MV_ATA_COMMAND_STANDBY_IMMEDIATE 0xe0 64#define MV_ATA_COMMAND_IDLE_IMMEDIATE 0xe1 65#define MV_ATA_COMMAND_STANDBY 0xe2 66#define MV_ATA_COMMAND_IDLE 0xe3 67#define MV_ATA_COMMAND_SLEEP 0xe6 68#define MV_ATA_COMMAND_IDENTIFY 0xec 69#define MV_ATA_COMMAND_DEVICE_CONFIG 0xb1 70#define MV_ATA_COMMAND_SET_FEATURES 0xef 71#define MV_ATA_COMMAND_WRITE_DMA 0xca 72#define MV_ATA_COMMAND_WRITE_DMA_EXT 0x35 73#define MV_ATA_COMMAND_WRITE_DMA_QUEUED 0xcc 74#define MV_ATA_COMMAND_WRITE_DMA_QUEUED_EXT 0x36 75#define MV_ATA_COMMAND_WRITE_FPDMA_QUEUED_EXT 0x61 76#define MV_ATA_COMMAND_READ_DMA 0xc8 77#define MV_ATA_COMMAND_READ_DMA_EXT 0x25 78#define MV_ATA_COMMAND_READ_DMA_QUEUED 0xc7 79#define MV_ATA_COMMAND_READ_DMA_QUEUED_EXT 0x26 80#define MV_ATA_COMMAND_READ_FPDMA_QUEUED_EXT 0x60 81#define MV_ATA_COMMAND_FLUSH_CACHE 0xe7 82#define MV_ATA_COMMAND_FLUSH_CACHE_EXT 0xea 83 84 85#define MV_ATA_SET_FEATURES_DISABLE_8_BIT_PIO 0x01 86#define MV_ATA_SET_FEATURES_ENABLE_WCACHE 0x02 /* Enable write cache */ 87#define MV_ATA_SET_FEATURES_TRANSFER 0x03 /* Set transfer mode */ 88#define MV_ATA_TRANSFER_UDMA_0 0x40 89#define MV_ATA_TRANSFER_UDMA_1 0x41 90#define MV_ATA_TRANSFER_UDMA_2 0x42 91#define MV_ATA_TRANSFER_UDMA_3 0x43 92#define MV_ATA_TRANSFER_UDMA_4 0x44 93#define MV_ATA_TRANSFER_UDMA_5 0x45 94#define MV_ATA_TRANSFER_UDMA_6 0x46 95#define MV_ATA_TRANSFER_UDMA_7 0x47 96#define MV_ATA_TRANSFER_PIO_SLOW 0x00 97#define MV_ATA_TRANSFER_PIO_0 0x08 98#define MV_ATA_TRANSFER_PIO_1 0x09 99#define MV_ATA_TRANSFER_PIO_2 0x0A 100#define MV_ATA_TRANSFER_PIO_3 0x0B 101#define MV_ATA_TRANSFER_PIO_4 0x0C 102/* Enable advanced power management */ 103#define MV_ATA_SET_FEATURES_ENABLE_APM 0x05 104/* Disable media status notification*/ 105#define MV_ATA_SET_FEATURES_DISABLE_MSN 0x31 106/* Disable read look-ahead */ 107#define MV_ATA_SET_FEATURES_DISABLE_RLA 0x55 108/* Enable release interrupt */ 109#define MV_ATA_SET_FEATURES_ENABLE_RI 0x5D 110/* Enable SERVICE interrupt */ 111#define MV_ATA_SET_FEATURES_ENABLE_SI 0x5E 112/* Disable revert power-on defaults */ 113#define MV_ATA_SET_FEATURES_DISABLE_RPOD 0x66 114/* Disable write cache */ 115#define MV_ATA_SET_FEATURES_DISABLE_WCACHE 0x82 116/* Disable advanced power management*/ 117#define MV_ATA_SET_FEATURES_DISABLE_APM 0x85 118/* Enable media status notification */ 119#define MV_ATA_SET_FEATURES_ENABLE_MSN 0x95 120/* Enable read look-ahead */ 121#define MV_ATA_SET_FEATURES_ENABLE_RLA 0xAA 122/* Enable revert power-on defaults */ 123#define MV_ATA_SET_FEATURES_ENABLE_RPOD 0xCC 124/* Disable release interrupt */ 125#define MV_ATA_SET_FEATURES_DISABLE_RI 0xDD 126/* Disable SERVICE interrupt */ 127#define MV_ATA_SET_FEATURES_DISABLE_SI 0xDE 128 129/* Defines for parsing the IDENTIFY command results*/ 130#define IDEN_SERIAL_NUM_OFFSET 10 131#define IDEN_SERIAL_NUM_SIZE 19-10 132#define IDEN_FIRMWARE_OFFSET 23 133#define IDEN_FIRMWARE_SIZE 26-23 134#define IDEN_MODEL_OFFSET 27 135#define IDEN_MODEL_SIZE 46-27 136#define IDEN_CAPACITY_1_OFFSET 49 137#define IDEN_VALID 53 138#define IDEN_NUM_OF_ADDRESSABLE_SECTORS 60 139#define IDEN_PIO_MODE_SPPORTED 64 140#define IDEN_QUEUE_DEPTH 75 141#define IDEN_SATA_CAPABILITIES 76 142#define IDEN_SATA_FEATURES_SUPPORTED 78 143#define IDEN_SATA_FEATURES_ENABLED 79 144#define IDEN_ATA_VERSION 80 145#define IDEN_SUPPORTED_COMMANDS1 82 146#define IDEN_SUPPORTED_COMMANDS2 83 147#define IDEN_ENABLED_COMMANDS1 85 148#define IDEN_ENABLED_COMMANDS2 86 149#define IDEN_UDMA_MODE 88 150#define IDEN_SATA_CAPABILITY 76 151 152 153/* Typedefs */ 154 155/* Structures */ 156typedef struct mvStorageDevRegisters 157{ 158 /* Fields set by CORE driver */ 159 MV_U8 errorRegister; 160 MV_U16 sectorCountRegister; 161 MV_U16 lbaLowRegister; 162 MV_U16 lbaMidRegister; 163 MV_U16 lbaHighRegister; 164 MV_U8 deviceRegister; 165 MV_U8 statusRegister; 166} MV_STORAGE_DEVICE_REGISTERS; 167 168/* Bits for HD_ERROR */ 169#define NM_ERR 0x02 /* media present */ 170#define ABRT_ERR 0x04 /* Command aborted */ 171#define MCR_ERR 0x08 /* media change request */ 172#define IDNF_ERR 0x10 /* ID field not found */ 173#define MC_ERR 0x20 /* media changed */ 174#define UNC_ERR 0x40 /* Uncorrect data */ 175#define WP_ERR 0x40 /* write protect */ 176#define ICRC_ERR 0x80 /* new meaning: CRC error during transfer */ 177 178/* Function */ 179 180MV_BOOLEAN HPTLIBAPI mvStorageDevATAExecuteNonUDMACommand(MV_SATA_ADAPTER *pAdapter, 181 MV_U8 channelIndex, 182 MV_NON_UDMA_PROTOCOL protocolType, 183 MV_BOOLEAN isEXT, 184 MV_U16 FAR *bufPtr, MV_U32 count, 185 MV_U16 features, 186 MV_U16 sectorCount, 187 MV_U16 lbaLow, MV_U16 lbaMid, 188 MV_U16 lbaHigh, MV_U8 device, 189 MV_U8 command); 190 191MV_BOOLEAN HPTLIBAPI mvStorageDevATAIdentifyDevice(MV_SATA_ADAPTER *pAdapter, 192 MV_U8 channelIndex); 193 194MV_BOOLEAN HPTLIBAPI mvStorageDevATASetFeatures(MV_SATA_ADAPTER *pAdapter, 195 MV_U8 channelIndex, MV_U8 subCommand, 196 MV_U8 subCommandSpecific1, 197 MV_U8 subCommandSpecific2, 198 MV_U8 subCommandSpecific3, 199 MV_U8 subCommandSpecific4); 200 201MV_BOOLEAN HPTLIBAPI mvStorageDevATAIdleImmediate(MV_SATA_ADAPTER *pAdapter, 202 MV_U8 channelIndex); 203 204MV_BOOLEAN HPTLIBAPI mvStorageDevATAFlushWriteCache(MV_SATA_ADAPTER *pAdapter, 205 MV_U8 channelIndex); 206 207MV_BOOLEAN HPTLIBAPI mvStorageDevATASoftResetDevice(MV_SATA_ADAPTER *pAdapter, 208 MV_U8 channelIndex); 209 210MV_BOOLEAN HPTLIBAPI mvStorageDevWaitStat(MV_SATA_CHANNEL *pSataChannel, 211 MV_U8 good, MV_U8 bad, MV_U32 loops, MV_U32 delay); 212 213MV_BOOLEAN HPTLIBAPI mvReadWrite(MV_SATA_CHANNEL *pSataChannel, LBA_T Lba, UCHAR Cmd, void *tmpBuffer); 214 215#endif 216