1/*- 2SPDX-License-Identifier: BSD-3-Clause 3 4Copyright (c) 1999-2001, Intel Corporation 5 6All rights reserved. 7 8Redistribution and use in source and binary forms, with or without 9modification, are permitted provided that the following conditions are met: 10 11 1. Redistributions of source code must retain the above copyright notice, 12 this list of conditions and the following disclaimer. 13 14 2. Redistributions in binary form must reproduce the above copyright notice, 15 this list of conditions and the following disclaimer in the documentation 16 and/or other materials provided with the distribution. 17 18 3. Neither the name of Intel Corporation nor the names of its contributors 19 may be used to endorse or promote products derived from this software 20 without specific prior written permission. 21 22THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' 23AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 28PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 29LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 31EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32*/ 33/* 34 */ 35/* 36rcvbundl.h 37 38Author: Patrick J Luhmann (PJL) 39Date: 05/30/2000 40Version: 3.28 41 42This file contains the loadable micro code arrays to implement receive bundling on the 43D101 A-step, D101 B-step, D101M (B-step only), D101S, D102 B-step, 44D102 B-step with TCO work around, D102 C-step and D102 E-step. 45 46Each controller has its own specific micro code array. The array for one controller 47is totally incompatible with any other controller, and if used will most likely 48cause the controller to lock up and stop responding to the driver. Each micro 49code array has its own parameter offsets (described below), and they each have 50their own version number (which should not be confused with the version of the 51rcvbundl.h file given above). 52 53*/ 54 55 56 57/************************************************************************* 58* CPUSaver parameters 59* 60* All CPUSaver parameters are 16-bit literals that are part of a 61* "move immediate value" instruction. By changing the value of 62* the literal in the instruction before the code is loaded, the 63* driver can change algorithm. 64* 65* CPUSAVER_DWORD - This is the location of the instruction that loads 66* the dead-man timer with its initial value. By writing a 16-bit 67* value to the low word of this instruction, the driver can change 68* the timer value. The current default is either x600 or x800; 69* experiments show that the value probably should stay within the 70* range of x200 - x1000. 71* 72* CPUSAVER_BUNDLE_MAX_DWORD - This is the location of the instruction 73* that sets the maximum number of frames that will be bundled. In 74* some situations, such as the TCP windowing algorithm, it may be 75* better to limit the growth of the bundle size than let it go as 76* high as it can, because that could cause too much added latency. 77* The default is six, because this is the number of packets in the 78* default TCP window size. A value of 1 would make CPUSaver indicate 79* an interrupt for every frame received. If you do not want to put 80* a limit on the bundle size, set this value to xFFFF. 81* 82* CPUSAVER_MIN_SIZE_DWORD - This is the location of the instruction 83* that contains a bit-mask describing the minimum size frame that 84* will be bundled. The default masks the lower 7 bits, which means 85* that any frame less than 128 bytes in length will not be bundled, 86* but will instead immediately generate an interrupt. This does 87* not affect the current bundle in any way. Any frame that is 128 88* bytes or large will be bundled normally. This feature is meant 89* to provide immediate indication of ACK frames in a TCP environment. 90* Customers were seeing poor performance when a machine with CPUSaver 91* enabled was sending but not receiving. The delay introduced when 92* the ACKs were received was enough to reduce total throughput, because 93* the sender would sit idle until the ACK was finally seen. 94* 95* The current default is 0xFF80, which masks out the lower 7 bits. 96* This means that any frame which is x7F (127) bytes or smaller 97* will cause an immediate interrupt. Because this value must be a 98* bit mask, there are only a few valid values that can be used. To 99* turn this feature off, the driver can write the value xFFFF to the 100* lower word of this instruction (in the same way that the other 101* parameters are used). Likewise, a value of 0xF800 (2047) would 102* cause an interrupt to be generated for every frame, because all 103* standard Ethernet frames are <= 2047 bytes in length. 104*************************************************************************/ 105 106 107 108/********************************************************/ 109/* CPUSaver micro code for the D101A */ 110/********************************************************/ 111 112/* Version 2.0 */ 113 114/* This value is the same for both A and B step of 558. */ 115#define D101_CPUSAVER_DWORD 72 116 117 118#define D101_A_RCVBUNDLE_UCODE \ 119{\ 1200x03B301BB, \ 1210x0046FFFF, \ 1220xFFFFFFFF, \ 1230x051DFFFF, \ 1240xFFFFFFFF, \ 1250xFFFFFFFF, \ 1260x000C0001, \ 1270x00101212, \ 1280x000C0008, \ 1290x003801BC, \ 1300x00000000, \ 1310x00124818, \ 1320x000C1000, \ 1330x00220809, \ 1340x00010200, \ 1350x00124818, \ 1360x000CFFFC, \ 1370x003803B5, \ 1380x00000000, \ 1390x00000000, \ 1400x00000000, \ 1410x00000000, \ 1420x0010009C, \ 1430x0024B81D, \ 1440x00130836, \ 1450x000C0001, \ 1460x0026081C, \ 1470x0020C81B, \ 1480x00130824, \ 1490x00222819, \ 1500x00101213, \ 1510x00041000, \ 1520x003A03B3, \ 1530x00010200, \ 1540x00101B13, \ 1550x00238081, \ 1560x00213049, \ 1570x0038003B, \ 1580x00000000, \ 1590x00000000, \ 1600x00000000, \ 1610x00000000, \ 1620x00000000, \ 1630x00000000, \ 1640x00000000, \ 1650x00000000, \ 1660x00000000, \ 1670x00000000, \ 1680x00000000, \ 1690x00000000, \ 1700x00000000, \ 1710x00000000, \ 1720x00000000, \ 1730x00000000, \ 1740x0010009C, \ 1750x0024B83E, \ 1760x00130826, \ 1770x000C0001, \ 1780x0026083B, \ 1790x00010200, \ 1800x00134824, \ 1810x000C0001, \ 1820x00101213, \ 1830x00041000, \ 1840x0038051E, \ 1850x00101313, \ 1860x00010400, \ 1870x00380521, \ 1880x00050600, \ 1890x00100824, \ 1900x00101310, \ 1910x00041000, \ 1920x00080600, \ 1930x00101B10, \ 1940x0038051E, \ 1950x00000000, \ 1960x00000000, \ 1970x00000000, \ 1980x00000000, \ 1990x00000000, \ 2000x00000000, \ 2010x00000000, \ 2020x00000000, \ 2030x00000000, \ 2040x00000000, \ 2050x00000000, \ 2060x00000000, \ 2070x00000000, \ 2080x00000000, \ 2090x00000000, \ 2100x00000000, \ 2110x00000000, \ 2120x00000000, \ 2130x00000000, \ 2140x00000000, \ 2150x00000000, \ 2160x00000000, \ 2170x00000000, \ 2180x00000000, \ 2190x00000000, \ 2200x00000000, \ 2210x00000000, \ 222} 223 224 225/********************************************************/ 226/* CPUSaver micro code for the D101B */ 227/********************************************************/ 228 229/* Version 2.0 */ 230 231#define D101_B0_RCVBUNDLE_UCODE \ 232{\ 2330x03B401BC, \ 2340x0047FFFF, \ 2350xFFFFFFFF, \ 2360x051EFFFF, \ 2370xFFFFFFFF, \ 2380xFFFFFFFF, \ 2390x000C0001, \ 2400x00101B92, \ 2410x000C0008, \ 2420x003801BD, \ 2430x00000000, \ 2440x00124818, \ 2450x000C1000, \ 2460x00220809, \ 2470x00010200, \ 2480x00124818, \ 2490x000CFFFC, \ 2500x003803B6, \ 2510x00000000, \ 2520x00000000, \ 2530x00000000, \ 2540x00000000, \ 2550x0010009C, \ 2560x0024B81D, \ 2570x0013082F, \ 2580x000C0001, \ 2590x0026081C, \ 2600x0020C81B, \ 2610x00130837, \ 2620x00222819, \ 2630x00101B93, \ 2640x00041000, \ 2650x003A03B4, \ 2660x00010200, \ 2670x00101793, \ 2680x00238082, \ 2690x0021304A, \ 2700x0038003C, \ 2710x00000000, \ 2720x00000000, \ 2730x00000000, \ 2740x00000000, \ 2750x00000000, \ 2760x00000000, \ 2770x00000000, \ 2780x00000000, \ 2790x00000000, \ 2800x00000000, \ 2810x00000000, \ 2820x00000000, \ 2830x00000000, \ 2840x00000000, \ 2850x00000000, \ 2860x00000000, \ 2870x0010009C, \ 2880x0024B83E, \ 2890x00130826, \ 2900x000C0001, \ 2910x0026083B, \ 2920x00010200, \ 2930x00134837, \ 2940x000C0001, \ 2950x00101B93, \ 2960x00041000, \ 2970x0038051F, \ 2980x00101313, \ 2990x00010400, \ 3000x00380522, \ 3010x00050600, \ 3020x00100837, \ 3030x00101310, \ 3040x00041000, \ 3050x00080600, \ 3060x00101790, \ 3070x0038051F, \ 3080x00000000, \ 3090x00000000, \ 3100x00000000, \ 3110x00000000, \ 3120x00000000, \ 3130x00000000, \ 3140x00000000, \ 3150x00000000, \ 3160x00000000, \ 3170x00000000, \ 3180x00000000, \ 3190x00000000, \ 3200x00000000, \ 3210x00000000, \ 3220x00000000, \ 3230x00000000, \ 3240x00000000, \ 3250x00000000, \ 3260x00000000, \ 3270x00000000, \ 3280x00000000, \ 3290x00000000, \ 3300x00000000, \ 3310x00000000, \ 3320x00000000, \ 3330x00000000, \ 3340x00000000, \ 335} 336 337 338/********************************************************/ 339/* CPUSaver micro code for the D101M (B-step only) */ 340/********************************************************/ 341 342/* Version 2.10 */ 343 344/* Parameter values for the D101M B-step */ 345#define D101M_CPUSAVER_DWORD 78 346#define D101M_CPUSAVER_BUNDLE_MAX_DWORD 65 347#define D101M_CPUSAVER_MIN_SIZE_DWORD 126 348 349 350#define D101M_B_RCVBUNDLE_UCODE \ 351{\ 3520x00550215, \ 3530xFFFF0437, \ 3540xFFFFFFFF, \ 3550x06A70789, \ 3560xFFFFFFFF, \ 3570x0558FFFF, \ 3580x000C0001, \ 3590x00101312, \ 3600x000C0008, \ 3610x00380216, \ 3620x0010009C, \ 3630x00204056, \ 3640x002380CC, \ 3650x00380056, \ 3660x0010009C, \ 3670x00244C0B, \ 3680x00000800, \ 3690x00124818, \ 3700x00380438, \ 3710x00000000, \ 3720x00140000, \ 3730x00380555, \ 3740x00308000, \ 3750x00100662, \ 3760x00100561, \ 3770x000E0408, \ 3780x00134861, \ 3790x000C0002, \ 3800x00103093, \ 3810x00308000, \ 3820x00100624, \ 3830x00100561, \ 3840x000E0408, \ 3850x00100861, \ 3860x000C007E, \ 3870x00222C21, \ 3880x000C0002, \ 3890x00103093, \ 3900x00380C7A, \ 3910x00080000, \ 3920x00103090, \ 3930x00380C7A, \ 3940x00000000, \ 3950x00000000, \ 3960x00000000, \ 3970x00000000, \ 3980x0010009C, \ 3990x00244C2D, \ 4000x00010004, \ 4010x00041000, \ 4020x003A0437, \ 4030x00044010, \ 4040x0038078A, \ 4050x00000000, \ 4060x00100099, \ 4070x00206C7A, \ 4080x0010009C, \ 4090x00244C48, \ 4100x00130824, \ 4110x000C0001, \ 4120x00101213, \ 4130x00260C75, \ 4140x00041000, \ 4150x00010004, \ 4160x00130826, \ 4170x000C0006, \ 4180x002206A8, \ 4190x0013C926, \ 4200x00101313, \ 4210x003806A8, \ 4220x00000000, \ 4230x00000000, \ 4240x00000000, \ 4250x00000000, \ 4260x00000000, \ 4270x00000000, \ 4280x00000000, \ 4290x00000000, \ 4300x00080600, \ 4310x00101B10, \ 4320x00050004, \ 4330x00100826, \ 4340x00101210, \ 4350x00380C34, \ 4360x00000000, \ 4370x00000000, \ 4380x0021155B, \ 4390x00100099, \ 4400x00206559, \ 4410x0010009C, \ 4420x00244559, \ 4430x00130836, \ 4440x000C0000, \ 4450x00220C62, \ 4460x000C0001, \ 4470x00101B13, \ 4480x00229C0E, \ 4490x00210C0E, \ 4500x00226C0E, \ 4510x00216C0E, \ 4520x0022FC0E, \ 4530x00215C0E, \ 4540x00214C0E, \ 4550x00380555, \ 4560x00010004, \ 4570x00041000, \ 4580x00278C67, \ 4590x00040800, \ 4600x00018100, \ 4610x003A0437, \ 4620x00130826, \ 4630x000C0001, \ 4640x00220559, \ 4650x00101313, \ 4660x00380559, \ 4670x00000000, \ 4680x00000000, \ 4690x00000000, \ 4700x00000000, \ 4710x00000000, \ 4720x00000000, \ 4730x00000000, \ 4740x00000000, \ 4750x00130831, \ 4760x0010090B, \ 4770x00124813, \ 4780x000CFF80, \ 4790x002606AB, \ 4800x00041000, \ 4810x003806A8, \ 4820x00000000, \ 4830x00000000, \ 4840x00000000, \ 4850x00000000, \ 486} 487 488 489/********************************************************/ 490/* CPUSaver micro code for the D101S */ 491/********************************************************/ 492 493/* Version 1.20 */ 494 495/* Parameter values for the D101S */ 496#define D101S_CPUSAVER_DWORD 78 497#define D101S_CPUSAVER_BUNDLE_MAX_DWORD 67 498#define D101S_CPUSAVER_MIN_SIZE_DWORD 129 499 500 501#define D101S_RCVBUNDLE_UCODE \ 502{\ 5030x00550242, \ 5040xFFFF047E, \ 5050xFFFFFFFF, \ 5060x06FF0818, \ 5070xFFFFFFFF, \ 5080x05A6FFFF, \ 5090x000C0001, \ 5100x00101312, \ 5110x000C0008, \ 5120x00380243, \ 5130x0010009C, \ 5140x00204056, \ 5150x002380D0, \ 5160x00380056, \ 5170x0010009C, \ 5180x00244F8B, \ 5190x00000800, \ 5200x00124818, \ 5210x0038047F, \ 5220x00000000, \ 5230x00140000, \ 5240x003805A3, \ 5250x00308000, \ 5260x00100610, \ 5270x00100561, \ 5280x000E0408, \ 5290x00134861, \ 5300x000C0002, \ 5310x00103093, \ 5320x00308000, \ 5330x00100624, \ 5340x00100561, \ 5350x000E0408, \ 5360x00100861, \ 5370x000C007E, \ 5380x00222FA1, \ 5390x000C0002, \ 5400x00103093, \ 5410x00380F90, \ 5420x00080000, \ 5430x00103090, \ 5440x00380F90, \ 5450x00000000, \ 5460x00000000, \ 5470x00000000, \ 5480x00000000, \ 5490x0010009C, \ 5500x00244FAD, \ 5510x00010004, \ 5520x00041000, \ 5530x003A047E, \ 5540x00044010, \ 5550x00380819, \ 5560x00000000, \ 5570x00100099, \ 5580x00206FFD, \ 5590x0010009A, \ 5600x0020AFFD, \ 5610x0010009C, \ 5620x00244FC8, \ 5630x00130824, \ 5640x000C0001, \ 5650x00101213, \ 5660x00260FF8, \ 5670x00041000, \ 5680x00010004, \ 5690x00130826, \ 5700x000C0006, \ 5710x00220700, \ 5720x0013C926, \ 5730x00101313, \ 5740x00380700, \ 5750x00000000, \ 5760x00000000, \ 5770x00000000, \ 5780x00000000, \ 5790x00000000, \ 5800x00000000, \ 5810x00080600, \ 5820x00101B10, \ 5830x00050004, \ 5840x00100826, \ 5850x00101210, \ 5860x00380FB6, \ 5870x00000000, \ 5880x00000000, \ 5890x002115A9, \ 5900x00100099, \ 5910x002065A7, \ 5920x0010009A, \ 5930x0020A5A7, \ 5940x0010009C, \ 5950x002445A7, \ 5960x00130836, \ 5970x000C0000, \ 5980x00220FE4, \ 5990x000C0001, \ 6000x00101B13, \ 6010x00229F8E, \ 6020x00210F8E, \ 6030x00226F8E, \ 6040x00216F8E, \ 6050x0022FF8E, \ 6060x00215F8E, \ 6070x00214F8E, \ 6080x003805A3, \ 6090x00010004, \ 6100x00041000, \ 6110x00278FE9, \ 6120x00040800, \ 6130x00018100, \ 6140x003A047E, \ 6150x00130826, \ 6160x000C0001, \ 6170x002205A7, \ 6180x00101313, \ 6190x003805A7, \ 6200x00000000, \ 6210x00000000, \ 6220x00000000, \ 6230x00000000, \ 6240x00000000, \ 6250x00000000, \ 6260x00000000, \ 6270x00000000, \ 6280x00000000, \ 6290x00130831, \ 6300x0010090B, \ 6310x00124813, \ 6320x000CFF80, \ 6330x00260703, \ 6340x00041000, \ 6350x00380700, \ 6360x00000000, \ 637} 638 639 640/********************************************************/ 641/* CPUSaver micro code for the D102 B-step */ 642/********************************************************/ 643 644/* Version 2.0 */ 645 646/* 647 This version of CPUSaver is different from all others in 648 a different way. It combines the CPUSaver algorithm with 649 fixes for bugs in the B-step hardware (specifically, bugs 650 with Inline Receive). 651 Thus, when CPUSaver is disabled, this micro code image will 652 still need to be loaded. Before this happens, the hit addresses 653 for the CPUSaver algorithm must be set to 0x1FFFF. The hit 654 addresses for CPUSaver are (starting with 0, and remember that 655 656*/ 657 658/* Parameter values for the D102 B-step */ 659#define D102_B_CPUSAVER_DWORD 91 660#define D102_B_CPUSAVER_BUNDLE_MAX_DWORD 115 661#define D102_B_CPUSAVER_MIN_SIZE_DWORD 70 662 663 664#define D102_B_RCVBUNDLE_UCODE \ 665{\ 6660x006F0276, \ 6670x02BF0E93, \ 6680x1FFF0ED9, \ 6690x0D2508FA, \ 6700x04D21FFF, \ 6710x0EA10892, \ 6720x00300001, \ 6730x0140D871, \ 6740x00300008, \ 6750x00E00277, \ 6760x01406C57, \ 6770x00816073, \ 6780x008700FA, \ 6790x00E00070, \ 6800x00E00E94, \ 6810x00200004, \ 6820x01410000, \ 6830x014B6F6F, \ 6840x0030FFFF, \ 6850x01486F72, \ 6860x00E81F9B, \ 6870x00E00EA3, \ 6880x003C0040, \ 6890x00380920, \ 6900x00C02000, \ 6910x0150ED38, \ 6920x0150EE39, \ 6930x0150EF3A, \ 6940x003C0040, \ 6950x01506F0D, \ 6960x01600E72, \ 6970x00380AE0, \ 6980x00E002C0, \ 6990x00300001, \ 7000x014C0000, \ 7010x008404DC, \ 7020x014C6F72, \ 7030x00E01F9D, \ 7040x01406C51, \ 7050x0080DFC2, \ 7060x01406C52, \ 7070x00815FC2, \ 7080x01406C57, \ 7090x00917FD5, \ 7100x00E01FE6, \ 7110x00000000, \ 7120x01406C57, \ 7130x00919FAD, \ 7140x00038800, \ 7150x00300000, \ 7160x00E81FF2, \ 7170x014D6FC4, \ 7180x00E008FB, \ 7190x00000000, \ 7200x00822D30, \ 7210x01406C51, \ 7220x0080CD26, \ 7230x01406C52, \ 7240x00814D26, \ 7250x01406C57, \ 7260x00916D26, \ 7270x014C6FD7, \ 7280x00300000, \ 7290x00841FDB, \ 7300x00300001, \ 7310x0140D772, \ 7320x00E012B3, \ 7330x014C6F91, \ 7340x0150710B, \ 7350x01496F72, \ 7360x0030FF80, \ 7370x00940EDD, \ 7380x00102000, \ 7390x00E00EDA, \ 7400x01406C57, \ 7410x00917FFD, \ 7420x00001000, \ 7430x00E01FFD, \ 7440x00138800, \ 7450x00300001, \ 7460x00E81FF2, \ 7470x00202500, \ 7480x00E81F9B, \ 7490x01600EC5, \ 7500x00E00893, \ 7510x00000000, \ 7520x01406CD5, \ 7530x0091EEA3, \ 7540x00904EA3, \ 7550x00901F89, \ 7560x00E00EA3, \ 7570x00200600, \ 7580x0140D76F, \ 7590x00138400, \ 7600x01406FD8, \ 7610x0140D96F, \ 7620x00E01FE6, \ 7630x00038400, \ 7640x00102000, \ 7650x00971FE0, \ 7660x00101000, \ 7670x00050200, \ 7680x00E804D2, \ 7690x014C6FD8, \ 7700x00300001, \ 7710x00840D26, \ 7720x0140D872, \ 7730x00E00D26, \ 7740x014C6FD9, \ 7750x00300001, \ 7760x0140D972, \ 7770x00941FBD, \ 7780x00102000, \ 7790x00038400, \ 7800x014C6FD8, \ 7810x00300006, \ 7820x00840EDA, \ 7830x014F71D8, \ 7840x0140D872, \ 7850x00E00EDA, \ 7860x00340020, \ 7870x014C6FED, \ 7880x01603472, \ 7890x016035EE, \ 7900x016036EF, \ 7910x00300004, \ 7920x01611C71, \ 7930x00300014, \ 7940x00200A00, \ 7950x00E810B9, \ 7960x00600000, \ 7970x01496F50, \ 7980x00E004D3, \ 7990x00000000, \ 800} 801 802 803 804 805/********************************************************/ 806/* TCO micro code for the D102 B-step */ 807/********************************************************/ 808 809/* Version 2.0 */ 810 811/* 812 This version is a fix to TCO bug. This version can be loaded instead 813 the CPUSaver version by modifing the registry key "LoadTcoUCodeInsteadOfCpuSaver" 814 815*/ 816 817 818#define D102_B_TCO_UCODE \ 819{\ 8200x1FFF0ED3, \ 8210x02BF0E93, \ 8220x1FFF1FFF, \ 8230x1FFF08FA, \ 8240x1FFF1FFF, \ 8250x0EA10892, \ 8260x00906ED8, \ 8270x01406C55, \ 8280x00E00ED4, \ 8290x00000000, \ 8300x00000000, \ 8310x00000000, \ 8320x00000000, \ 8330x00000000, \ 8340x00E00E94, \ 8350x00200004, \ 8360x01410000, \ 8370x014B6F6F, \ 8380x0030FFFF, \ 8390x01486F72, \ 8400x00E81F9B, \ 8410x00E00EA3, \ 8420x003C0040, \ 8430x00380920, \ 8440x00C02000, \ 8450x0150ED38, \ 8460x0150EE39, \ 8470x0150EF3A, \ 8480x003C0040, \ 8490x01506F0D, \ 8500x01600E72, \ 8510x00380AE0, \ 8520x00E002C0, \ 8530x00300001, \ 8540x014C0000, \ 8550x008404DC, \ 8560x014C6F72, \ 8570x00E01F9D, \ 8580x00000000, \ 8590x00000000, \ 8600x00000000, \ 8610x00000000, \ 8620x00000000, \ 8630x00000000, \ 8640x00000000, \ 8650x00000000, \ 8660x01406C57, \ 8670x00919FAD, \ 8680x00038800, \ 8690x00300000, \ 8700x00E81FD5, \ 8710x014D6FC4, \ 8720x00E008FB, \ 8730x00000000, \ 8740x00000000, \ 8750x00000000, \ 8760x00000000, \ 8770x00000000, \ 8780x00000000, \ 8790x00000000, \ 8800x00000000, \ 8810x00000000, \ 8820x00000000, \ 8830x00000000, \ 8840x00000000, \ 8850x00000000, \ 8860x00000000, \ 8870x00000000, \ 8880x00000000, \ 8890x00000000, \ 8900x00000000, \ 8910x00000000, \ 8920x00000000, \ 8930x00000000, \ 8940x00000000, \ 8950x00000000, \ 8960x00000000, \ 8970x00000000, \ 8980x00138800, \ 8990x00300001, \ 9000x00E81FD5, \ 9010x00202500, \ 9020x00E81F9B, \ 9030x01600EC5, \ 9040x00E00893, \ 9050x00000000, \ 9060x01406CD5, \ 9070x0091EEA3, \ 9080x00904EA3, \ 9090x00901F89, \ 9100x00E00EA3, \ 9110x00340020, \ 9120x014C6FED, \ 9130x01603472, \ 9140x016035EE, \ 9150x016036EF, \ 9160x00300004, \ 9170x01611C71, \ 9180x00300014, \ 9190x00200A00, \ 9200x00E810B9, \ 9210x00600000, \ 9220x00000000, \ 9230x00000000, \ 9240x00000000, \ 9250x00000000, \ 9260x00000000, \ 9270x00000000, \ 9280x00000000, \ 9290x00000000, \ 9300x00000000, \ 9310x00000000, \ 9320x00000000, \ 9330x00000000, \ 9340x00000000, \ 9350x00000000, \ 9360x00000000, \ 9370x00000000, \ 9380x00000000, \ 9390x00000000, \ 9400x00000000, \ 9410x00000000, \ 9420x00000000, \ 9430x00000000, \ 9440x00000000, \ 9450x00000000, \ 9460x00000000, \ 9470x00000000, \ 9480x00000000, \ 9490x00000000, \ 9500x00000000, \ 9510x00000000, \ 9520x00000000, \ 9530x00000000, \ 954} 955 956 957 958/********************************************************/ 959/* Micro code for the D102 C-step */ 960/********************************************************/ 961 962/* Parameter values for the D102 C-step */ 963#define D102_C_CPUSAVER_DWORD 46 964#define D102_C_CPUSAVER_BUNDLE_MAX_DWORD 54 965#define D102_C_CPUSAVER_MIN_SIZE_DWORD 133 /* not implemented */ 966 967 968 969 970 971#if 0 972// this uCode include the CPU Saver and the TCO work around 973//for IP fregments. 974#endif 975#define D102_C_RCVBUNDLE_UCODE \ 976{ \ 9770x00700279, \ 9780x0E6104E2, \ 9790x02BF0CAE, \ 9800x1519150C, \ 9810x1FFF0E5B, \ 9820x1FFF1FFF, \ 9830x00E014D8, \ 9840x00000000, \ 9850x00000000, \ 9860x00000000, \ 9870x00E014DC, \ 9880x00000000, \ 9890x00000000, \ 9900x00000000, \ 9910x00E014F4, \ 9920x00000000, \ 9930x00000000, \ 9940x00000000, \ 9950x00000000, \ 9960x00000000, \ 9970x00000000, \ 9980x00000000, \ 9990x00E014E0, \ 10000x00000000, \ 10010x00000000, \ 10020x00000000, \ 10030x00000000, \ 10040x00000000, \ 10050x00000000, \ 10060x00000000, \ 10070x00000000, \ 10080x00000000, \ 10090x00000000, \ 10100x00000000, \ 10110x00000000, \ 10120x00000000, \ 10130x00000000, \ 10140x00000000, \ 10150x00E014E7, \ 10160x00000000, \ 10170x00000000, \ 10180x00000000, \ 10190x00141000, \ 10200x015D6F0D, \ 10210x00E002C0, \ 10220x00000000, \ 10230x00200600, \ 10240x00E0150D, \ 10250x00000000, \ 10260x00000000, \ 10270x00000000, \ 10280x00000000, \ 10290x00000000, \ 10300x00000000, \ 10310x00300006, \ 10320x00E0151A, \ 10330x00000000, \ 10340x00000000, \ 10350x00000000, \ 10360x00000000, \ 10370x00000000, \ 10380x00000000, \ 10390x00000000, \ 10400x00000000, \ 10410x00000000, \ 10420x00000000, \ 10430x00000000, \ 10440x00000000, \ 10450x00000000, \ 10460x00000000, \ 10470x00906E65, \ 10480x00800E60, \ 10490x00E00E5D, \ 10500x00000000, \ 10510x00000000, \ 10520x00000000, \ 10530x00000000, \ 10540x00000000, \ 10550x00000000, \ 10560x00000000, \ 10570x00000000, \ 10580x00000000, \ 10590x00000000, \ 10600x00000000, \ 10610x00000000, \ 10620x00000000, \ 10630x00000000, \ 10640x00000000, \ 10650x00000000, \ 10660x00000000, \ 10670x00000000, \ 10680x00000000, \ 10690x00000000, \ 10700x00000000, \ 10710x00000000, \ 10720x00000000, \ 10730x00000000, \ 10740x00000000, \ 10750x00000000, \ 10760x00000000, \ 10770x00000000, \ 10780x00000000, \ 10790x00000000, \ 10800x00000000, \ 10810x00000000, \ 10820x00000000, \ 10830x00000000, \ 10840x00000000, \ 10850x00000000, \ 10860x00000000, \ 10870x00000000, \ 10880x00000000, \ 10890x00000000, \ 10900x00000000, \ 10910x00000000, \ 10920x00000000, \ 10930x00000000, \ 10940x00000000, \ 10950x00000000, \ 10960x00000000, \ 10970x00000000, \ 10980x00000000, \ 10990x00000000, \ 11000x00000000, \ 11010x00000000, \ 11020x00000000, \ 11030x00000000, \ 11040x00000000, \ 11050x00000000, \ 11060x00000000, \ 11070x00000000, \ 11080x00000000, \ 11090x00000000, \ 11100x00000000, \ 1111} 1112 1113/********************************************************/ 1114/* Micro code for the D102 E-step */ 1115/********************************************************/ 1116 1117/* Parameter values for the D102 E-step */ 1118#define D102_E_CPUSAVER_DWORD 42 1119#define D102_E_CPUSAVER_BUNDLE_MAX_DWORD 54 1120#define D102_E_CPUSAVER_MIN_SIZE_DWORD 46 1121 1122#define D102_E_RCVBUNDLE_UCODE \ 1123{\ 11240x007D028F, \ 11250x0E4204F9, \ 11260x14ED0C85, \ 11270x14FA14E9, \ 11280x0EF70E36, \ 11290x1FFF1FFF, \ 11300x00E014B9, \ 11310x00000000, \ 11320x00000000, \ 11330x00000000, \ 11340x00E014BD, \ 11350x00000000, \ 11360x00000000, \ 11370x00000000, \ 11380x00E014D5, \ 11390x00000000, \ 11400x00000000, \ 11410x00000000, \ 11420x00000000, \ 11430x00000000, \ 11440x00000000, \ 11450x00000000, \ 11460x00E014C1, \ 11470x00000000, \ 11480x00000000, \ 11490x00000000, \ 11500x00000000, \ 11510x00000000, \ 11520x00000000, \ 11530x00000000, \ 11540x00000000, \ 11550x00000000, \ 11560x00000000, \ 11570x00000000, \ 11580x00000000, \ 11590x00000000, \ 11600x00000000, \ 11610x00000000, \ 11620x00E014C8, \ 11630x00000000, \ 11640x00000000, \ 11650x00000000, \ 11660x00200600, \ 11670x00E014EE, \ 11680x00000000, \ 11690x00000000, \ 11700x0030FF80, \ 11710x00940E46, \ 11720x00038200, \ 11730x00102000, \ 11740x00E00E43, \ 11750x00000000, \ 11760x00000000, \ 11770x00000000, \ 11780x00300006, \ 11790x00E014FB, \ 11800x00000000, \ 11810x00000000, \ 11820x00000000, \ 11830x00000000, \ 11840x00000000, \ 11850x00000000, \ 11860x00000000, \ 11870x00000000, \ 11880x00000000, \ 11890x00000000, \ 11900x00000000, \ 11910x00000000, \ 11920x00000000, \ 11930x00000000, \ 11940x00906E41, \ 11950x00800E3C, \ 11960x00E00E39, \ 11970x00000000, \ 11980x00906EFD, \ 11990x00900EFD, \ 12000x00E00EF8, \ 12010x00000000, \ 12020x00000000, \ 12030x00000000, \ 12040x00000000, \ 12050x00000000, \ 12060x00000000, \ 12070x00000000, \ 12080x00000000, \ 12090x00000000, \ 12100x00000000, \ 12110x00000000, \ 12120x00000000, \ 12130x00000000, \ 12140x00000000, \ 12150x00000000, \ 12160x00000000, \ 12170x00000000, \ 12180x00000000, \ 12190x00000000, \ 12200x00000000, \ 12210x00000000, \ 12220x00000000, \ 12230x00000000, \ 12240x00000000, \ 12250x00000000, \ 12260x00000000, \ 12270x00000000, \ 12280x00000000, \ 12290x00000000, \ 12300x00000000, \ 12310x00000000, \ 12320x00000000, \ 12330x00000000, \ 12340x00000000, \ 12350x00000000, \ 12360x00000000, \ 12370x00000000, \ 12380x00000000, \ 12390x00000000, \ 12400x00000000, \ 12410x00000000, \ 12420x00000000, \ 12430x00000000, \ 12440x00000000, \ 12450x00000000, \ 12460x00000000, \ 12470x00000000, \ 12480x00000000, \ 12490x00000000, \ 12500x00000000, \ 12510x00000000, \ 12520x00000000, \ 12530x00000000, \ 12540x00000000, \ 12550x00000000, \ 12560x00000000, \ 12570x00000000, \ 1258} 1259