1/*- 2 * Copyright (c) 2015 Semihalf 3 * Copyright (c) 2015 Stormshield 4 * Copyright (c) 2018-2019, Rubicon Communications, LLC (Netgate) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30#include "opt_platform.h" 31 32#include <sys/param.h> 33#include <sys/bus.h> 34#include <sys/errno.h> 35#include <sys/kernel.h> 36#include <sys/kthread.h> 37#include <sys/module.h> 38#include <sys/taskqueue.h> 39#include <sys/socket.h> 40#include <sys/sockio.h> 41 42#include <net/if.h> 43#include <net/if_media.h> 44#include <net/if_types.h> 45 46#include <dev/etherswitch/etherswitch.h> 47#include <dev/mii/mii.h> 48#include <dev/mii/miivar.h> 49 50#ifdef FDT 51#include <dev/ofw/ofw_bus.h> 52#include <dev/ofw/ofw_bus_subr.h> 53#else 54#include <machine/stdarg.h> 55#endif 56 57#include "e6000swreg.h" 58#include "etherswitch_if.h" 59#include "miibus_if.h" 60#include "mdio_if.h" 61 62MALLOC_DECLARE(M_E6000SW); 63MALLOC_DEFINE(M_E6000SW, "e6000sw", "e6000sw switch"); 64 65#define E6000SW_LOCK(_sc) sx_xlock(&(_sc)->sx) 66#define E6000SW_UNLOCK(_sc) sx_unlock(&(_sc)->sx) 67#define E6000SW_LOCK_ASSERT(_sc, _what) sx_assert(&(_sc)->sx, (_what)) 68#define E6000SW_TRYLOCK(_sc) sx_tryxlock(&(_sc)->sx) 69#define E6000SW_LOCKED(_sc) sx_xlocked(&(_sc)->sx) 70#define E6000SW_WAITREADY(_sc, _reg, _bit) \ 71 e6000sw_waitready((_sc), REG_GLOBAL, (_reg), (_bit)) 72#define E6000SW_WAITREADY2(_sc, _reg, _bit) \ 73 e6000sw_waitready((_sc), REG_GLOBAL2, (_reg), (_bit)) 74#define MDIO_READ(dev, addr, reg) \ 75 MDIO_READREG(device_get_parent(dev), (addr), (reg)) 76#define MDIO_WRITE(dev, addr, reg, val) \ 77 MDIO_WRITEREG(device_get_parent(dev), (addr), (reg), (val)) 78 79 80typedef struct e6000sw_softc { 81 device_t dev; 82#ifdef FDT 83 phandle_t node; 84#endif 85 86 struct sx sx; 87 if_t ifp[E6000SW_MAX_PORTS]; 88 char *ifname[E6000SW_MAX_PORTS]; 89 device_t miibus[E6000SW_MAX_PORTS]; 90 struct taskqueue *sc_tq; 91 struct timeout_task sc_tt; 92 93 int vlans[E6000SW_NUM_VLANS]; 94 uint32_t swid; 95 uint32_t vlan_mode; 96 uint32_t cpuports_mask; 97 uint32_t fixed_mask; 98 uint32_t fixed25_mask; 99 uint32_t ports_mask; 100 int phy_base; 101 int sw_addr; 102 int num_ports; 103} e6000sw_softc_t; 104 105static etherswitch_info_t etherswitch_info = { 106 .es_nports = 0, 107 .es_nvlangroups = 0, 108 .es_vlan_caps = ETHERSWITCH_VLAN_PORT | ETHERSWITCH_VLAN_DOT1Q, 109 .es_name = "Marvell 6000 series switch" 110}; 111 112static void e6000sw_identify(driver_t *, device_t); 113static int e6000sw_probe(device_t); 114#ifdef FDT 115static int e6000sw_parse_fixed_link(e6000sw_softc_t *, phandle_t, uint32_t); 116static int e6000sw_parse_ethernet(e6000sw_softc_t *, phandle_t, uint32_t); 117#endif 118static int e6000sw_attach(device_t); 119static int e6000sw_detach(device_t); 120static int e6000sw_read_xmdio(device_t, int, int, int); 121static int e6000sw_write_xmdio(device_t, int, int, int, int); 122static int e6000sw_readphy(device_t, int, int); 123static int e6000sw_writephy(device_t, int, int, int); 124static int e6000sw_readphy_locked(device_t, int, int); 125static int e6000sw_writephy_locked(device_t, int, int, int); 126static etherswitch_info_t* e6000sw_getinfo(device_t); 127static int e6000sw_getconf(device_t, etherswitch_conf_t *); 128static int e6000sw_setconf(device_t, etherswitch_conf_t *); 129static void e6000sw_lock(device_t); 130static void e6000sw_unlock(device_t); 131static int e6000sw_getport(device_t, etherswitch_port_t *); 132static int e6000sw_setport(device_t, etherswitch_port_t *); 133static int e6000sw_set_vlan_mode(e6000sw_softc_t *, uint32_t); 134static int e6000sw_readreg_wrapper(device_t, int); 135static int e6000sw_writereg_wrapper(device_t, int, int); 136static int e6000sw_getvgroup_wrapper(device_t, etherswitch_vlangroup_t *); 137static int e6000sw_setvgroup_wrapper(device_t, etherswitch_vlangroup_t *); 138static int e6000sw_setvgroup(device_t, etherswitch_vlangroup_t *); 139static int e6000sw_getvgroup(device_t, etherswitch_vlangroup_t *); 140static void e6000sw_setup(device_t, e6000sw_softc_t *); 141static void e6000sw_tick(void *, int); 142static void e6000sw_set_atustat(device_t, e6000sw_softc_t *, int, int); 143static int e6000sw_atu_flush(device_t, e6000sw_softc_t *, int); 144static int e6000sw_vtu_flush(e6000sw_softc_t *); 145static int e6000sw_vtu_update(e6000sw_softc_t *, int, int, int, int, int); 146static __inline void e6000sw_writereg(e6000sw_softc_t *, int, int, int); 147static __inline uint32_t e6000sw_readreg(e6000sw_softc_t *, int, int); 148static int e6000sw_ifmedia_upd(if_t); 149static void e6000sw_ifmedia_sts(if_t, struct ifmediareq *); 150static int e6000sw_atu_mac_table(device_t, e6000sw_softc_t *, struct atu_opt *, 151 int); 152static int e6000sw_get_pvid(e6000sw_softc_t *, int, int *); 153static void e6000sw_set_pvid(e6000sw_softc_t *, int, int); 154static __inline bool e6000sw_is_cpuport(e6000sw_softc_t *, int); 155static __inline bool e6000sw_is_fixedport(e6000sw_softc_t *, int); 156static __inline bool e6000sw_is_fixed25port(e6000sw_softc_t *, int); 157static __inline bool e6000sw_is_phyport(e6000sw_softc_t *, int); 158static __inline bool e6000sw_is_portenabled(e6000sw_softc_t *, int); 159static __inline struct mii_data *e6000sw_miiforphy(e6000sw_softc_t *, 160 unsigned int); 161 162static device_method_t e6000sw_methods[] = { 163 /* device interface */ 164 DEVMETHOD(device_identify, e6000sw_identify), 165 DEVMETHOD(device_probe, e6000sw_probe), 166 DEVMETHOD(device_attach, e6000sw_attach), 167 DEVMETHOD(device_detach, e6000sw_detach), 168 169 /* bus interface */ 170 DEVMETHOD(bus_add_child, device_add_child_ordered), 171 172 /* mii interface */ 173 DEVMETHOD(miibus_readreg, e6000sw_readphy), 174 DEVMETHOD(miibus_writereg, e6000sw_writephy), 175 176 /* etherswitch interface */ 177 DEVMETHOD(etherswitch_getinfo, e6000sw_getinfo), 178 DEVMETHOD(etherswitch_getconf, e6000sw_getconf), 179 DEVMETHOD(etherswitch_setconf, e6000sw_setconf), 180 DEVMETHOD(etherswitch_lock, e6000sw_lock), 181 DEVMETHOD(etherswitch_unlock, e6000sw_unlock), 182 DEVMETHOD(etherswitch_getport, e6000sw_getport), 183 DEVMETHOD(etherswitch_setport, e6000sw_setport), 184 DEVMETHOD(etherswitch_readreg, e6000sw_readreg_wrapper), 185 DEVMETHOD(etherswitch_writereg, e6000sw_writereg_wrapper), 186 DEVMETHOD(etherswitch_readphyreg, e6000sw_readphy), 187 DEVMETHOD(etherswitch_writephyreg, e6000sw_writephy), 188 DEVMETHOD(etherswitch_setvgroup, e6000sw_setvgroup_wrapper), 189 DEVMETHOD(etherswitch_getvgroup, e6000sw_getvgroup_wrapper), 190 191 DEVMETHOD_END 192}; 193 194DEFINE_CLASS_0(e6000sw, e6000sw_driver, e6000sw_methods, 195 sizeof(e6000sw_softc_t)); 196 197DRIVER_MODULE(e6000sw, mdio, e6000sw_driver, 0, 0); 198DRIVER_MODULE(etherswitch, e6000sw, etherswitch_driver, 0, 0); 199DRIVER_MODULE(miibus, e6000sw, miibus_driver, 0, 0); 200MODULE_DEPEND(e6000sw, mdio, 1, 1, 1); 201 202 203static void 204e6000sw_identify(driver_t *driver, device_t parent) 205{ 206 207 if (device_find_child(parent, "e6000sw", -1) == NULL) 208 BUS_ADD_CHILD(parent, 0, "e6000sw", -1); 209} 210 211static int 212e6000sw_probe(device_t dev) 213{ 214 e6000sw_softc_t *sc; 215 const char *description; 216#ifdef FDT 217 phandle_t switch_node; 218#else 219 int is_6190; 220#endif 221 222 sc = device_get_softc(dev); 223 sc->dev = dev; 224 225#ifdef FDT 226 switch_node = ofw_bus_find_compatible(OF_finddevice("/"), 227 "marvell,mv88e6085"); 228 if (switch_node == 0) { 229 switch_node = ofw_bus_find_compatible(OF_finddevice("/"), 230 "marvell,mv88e6190"); 231 232 if (switch_node == 0) 233 return (ENXIO); 234 235 /* 236 * Trust DTS and fix the port register offset for the MV88E6190 237 * detection bellow. 238 */ 239 sc->swid = MV88E6190; 240 } 241 242 if (bootverbose) 243 device_printf(dev, "Found switch_node: 0x%x\n", switch_node); 244 245 sc->node = switch_node; 246 247 if (OF_getencprop(sc->node, "reg", &sc->sw_addr, 248 sizeof(sc->sw_addr)) < 0) 249 return (ENXIO); 250#else 251 if (resource_int_value(device_get_name(sc->dev), 252 device_get_unit(sc->dev), "addr", &sc->sw_addr) != 0) 253 return (ENXIO); 254 if (resource_int_value(device_get_name(sc->dev), 255 device_get_unit(sc->dev), "is6190", &is_6190) != 0) 256 /* 257 * Check "is8190" to keep backward compatibility with 258 * older setups. 259 */ 260 resource_int_value(device_get_name(sc->dev), 261 device_get_unit(sc->dev), "is8190", &is_6190); 262 if (is_6190 != 0) 263 sc->swid = MV88E6190; 264#endif 265 if (sc->sw_addr < 0 || sc->sw_addr > 32) 266 return (ENXIO); 267 268 /* 269 * Create temporary lock, just to satisfy assertions, 270 * when obtaining the switch ID. Destroy immediately afterwards. 271 */ 272 sx_init(&sc->sx, "e6000sw_tmp"); 273 E6000SW_LOCK(sc); 274 sc->swid = e6000sw_readreg(sc, REG_PORT(sc, 0), SWITCH_ID) & 0xfff0; 275 E6000SW_UNLOCK(sc); 276 sx_destroy(&sc->sx); 277 278 switch (sc->swid) { 279 case MV88E6141: 280 description = "Marvell 88E6141"; 281 sc->phy_base = 0x10; 282 sc->num_ports = 6; 283 break; 284 case MV88E6341: 285 description = "Marvell 88E6341"; 286 sc->phy_base = 0x10; 287 sc->num_ports = 6; 288 break; 289 case MV88E6352: 290 description = "Marvell 88E6352"; 291 sc->num_ports = 7; 292 break; 293 case MV88E6172: 294 description = "Marvell 88E6172"; 295 sc->num_ports = 7; 296 break; 297 case MV88E6176: 298 description = "Marvell 88E6176"; 299 sc->num_ports = 7; 300 break; 301 case MV88E6190: 302 description = "Marvell 88E6190"; 303 sc->num_ports = 11; 304 break; 305 default: 306 device_printf(dev, "Unrecognized device, id 0x%x.\n", sc->swid); 307 return (ENXIO); 308 } 309 310 device_set_desc(dev, description); 311 312 return (BUS_PROBE_DEFAULT); 313} 314 315#ifdef FDT 316static int 317e6000sw_parse_fixed_link(e6000sw_softc_t *sc, phandle_t node, uint32_t port) 318{ 319 int speed; 320 phandle_t fixed_link; 321 322 fixed_link = ofw_bus_find_child(node, "fixed-link"); 323 324 if (fixed_link != 0) { 325 sc->fixed_mask |= (1 << port); 326 327 if (OF_getencprop(fixed_link, 328 "speed", &speed, sizeof(speed)) < 0) { 329 device_printf(sc->dev, 330 "Port %d has a fixed-link node without a speed " 331 "property\n", port); 332 return (ENXIO); 333 } 334 if (speed == 2500 && (MVSWITCH(sc, MV88E6141) || 335 MVSWITCH(sc, MV88E6341) || MVSWITCH(sc, MV88E6190))) 336 sc->fixed25_mask |= (1 << port); 337 } 338 339 return (0); 340} 341 342static int 343e6000sw_parse_ethernet(e6000sw_softc_t *sc, phandle_t port_handle, uint32_t port) { 344 phandle_t switch_eth, switch_eth_handle; 345 346 if (OF_getencprop(port_handle, "ethernet", (void*)&switch_eth_handle, 347 sizeof(switch_eth_handle)) > 0) { 348 if (switch_eth_handle > 0) { 349 switch_eth = OF_node_from_xref(switch_eth_handle); 350 351 device_printf(sc->dev, "CPU port at %d\n", port); 352 sc->cpuports_mask |= (1 << port); 353 354 return (e6000sw_parse_fixed_link(sc, switch_eth, port)); 355 } else 356 device_printf(sc->dev, 357 "Port %d has ethernet property but it points " 358 "to an invalid location\n", port); 359 } 360 361 return (0); 362} 363 364static int 365e6000sw_parse_child_fdt(e6000sw_softc_t *sc, phandle_t child, int *pport) 366{ 367 uint32_t port; 368 369 if (pport == NULL) 370 return (ENXIO); 371 372 if (OF_getencprop(child, "reg", (void *)&port, sizeof(port)) < 0) 373 return (ENXIO); 374 if (port >= sc->num_ports) 375 return (ENXIO); 376 *pport = port; 377 378 if (e6000sw_parse_fixed_link(sc, child, port) != 0) 379 return (ENXIO); 380 381 if (e6000sw_parse_ethernet(sc, child, port) != 0) 382 return (ENXIO); 383 384 if ((sc->fixed_mask & (1 << port)) != 0) 385 device_printf(sc->dev, "fixed port at %d\n", port); 386 else 387 device_printf(sc->dev, "PHY at port %d\n", port); 388 389 return (0); 390} 391#else 392 393static int 394e6000sw_check_hint_val(device_t dev, int *val, char *fmt, ...) 395{ 396 char *resname; 397 int err, len; 398 va_list ap; 399 400 len = min(strlen(fmt) * 2, 128); 401 if (len == 0) 402 return (-1); 403 resname = malloc(len, M_E6000SW, M_WAITOK); 404 memset(resname, 0, len); 405 va_start(ap, fmt); 406 vsnprintf(resname, len - 1, fmt, ap); 407 va_end(ap); 408 err = resource_int_value(device_get_name(dev), device_get_unit(dev), 409 resname, val); 410 free(resname, M_E6000SW); 411 412 return (err); 413} 414 415static int 416e6000sw_parse_hinted_port(e6000sw_softc_t *sc, int port) 417{ 418 int err, val; 419 420 err = e6000sw_check_hint_val(sc->dev, &val, "port%ddisabled", port); 421 if (err == 0 && val != 0) 422 return (1); 423 424 err = e6000sw_check_hint_val(sc->dev, &val, "port%dcpu", port); 425 if (err == 0 && val != 0) { 426 sc->cpuports_mask |= (1 << port); 427 sc->fixed_mask |= (1 << port); 428 if (bootverbose) 429 device_printf(sc->dev, "CPU port at %d\n", port); 430 } 431 err = e6000sw_check_hint_val(sc->dev, &val, "port%dspeed", port); 432 if (err == 0 && val != 0) { 433 sc->fixed_mask |= (1 << port); 434 if (val == 2500) 435 sc->fixed25_mask |= (1 << port); 436 } 437 438 if (bootverbose) { 439 if ((sc->fixed_mask & (1 << port)) != 0) 440 device_printf(sc->dev, "fixed port at %d\n", port); 441 else 442 device_printf(sc->dev, "PHY at port %d\n", port); 443 } 444 445 return (0); 446} 447#endif 448 449static int 450e6000sw_init_interface(e6000sw_softc_t *sc, int port) 451{ 452 char name[IFNAMSIZ]; 453 454 snprintf(name, IFNAMSIZ, "%sport", device_get_nameunit(sc->dev)); 455 456 sc->ifp[port] = if_alloc(IFT_ETHER); 457 if (sc->ifp[port] == NULL) 458 return (ENOMEM); 459 if_setsoftc(sc->ifp[port], sc); 460 if_setflagbits(sc->ifp[port], IFF_UP | IFF_BROADCAST | 461 IFF_DRV_RUNNING | IFF_SIMPLEX, 0); 462 sc->ifname[port] = malloc(strlen(name) + 1, M_E6000SW, M_NOWAIT); 463 if (sc->ifname[port] == NULL) { 464 if_free(sc->ifp[port]); 465 return (ENOMEM); 466 } 467 memcpy(sc->ifname[port], name, strlen(name) + 1); 468 if_initname(sc->ifp[port], sc->ifname[port], port); 469 470 return (0); 471} 472 473static int 474e6000sw_attach_miibus(e6000sw_softc_t *sc, int port) 475{ 476 int err; 477 478 err = mii_attach(sc->dev, &sc->miibus[port], sc->ifp[port], 479 e6000sw_ifmedia_upd, e6000sw_ifmedia_sts, BMSR_DEFCAPMASK, 480 port + sc->phy_base, MII_OFFSET_ANY, 0); 481 if (err != 0) 482 return (err); 483 484 return (0); 485} 486 487static void 488e6000sw_serdes_power(device_t dev, int port, bool sgmii) 489{ 490 uint32_t reg; 491 492 /* SGMII */ 493 reg = e6000sw_read_xmdio(dev, port, E6000SW_SERDES_DEV, 494 E6000SW_SERDES_SGMII_CTL); 495 if (sgmii) 496 reg &= ~E6000SW_SERDES_PDOWN; 497 else 498 reg |= E6000SW_SERDES_PDOWN; 499 e6000sw_write_xmdio(dev, port, E6000SW_SERDES_DEV, 500 E6000SW_SERDES_SGMII_CTL, reg); 501 502 /* 10GBASE-R/10GBASE-X4/X2 */ 503 reg = e6000sw_read_xmdio(dev, port, E6000SW_SERDES_DEV, 504 E6000SW_SERDES_PCS_CTL1); 505 if (sgmii) 506 reg |= E6000SW_SERDES_PDOWN; 507 else 508 reg &= ~E6000SW_SERDES_PDOWN; 509 e6000sw_write_xmdio(dev, port, E6000SW_SERDES_DEV, 510 E6000SW_SERDES_PCS_CTL1, reg); 511} 512 513static int 514e6000sw_attach(device_t dev) 515{ 516 bool sgmii; 517 e6000sw_softc_t *sc; 518#ifdef FDT 519 phandle_t child, ports; 520#endif 521 int err, port; 522 uint32_t reg; 523 524 err = 0; 525 sc = device_get_softc(dev); 526 527 /* 528 * According to the Linux source code, all of the Switch IDs we support 529 * are multi_chip capable, and should go into multi-chip mode if the 530 * sw_addr != 0. 531 */ 532 if (MVSWITCH_MULTICHIP(sc)) 533 device_printf(dev, "multi-chip addressing mode (%#x)\n", 534 sc->sw_addr); 535 else 536 device_printf(dev, "single-chip addressing mode\n"); 537 538 sx_init(&sc->sx, "e6000sw"); 539 540 E6000SW_LOCK(sc); 541 e6000sw_setup(dev, sc); 542 543 sc->sc_tq = taskqueue_create("e6000sw_taskq", M_NOWAIT, 544 taskqueue_thread_enqueue, &sc->sc_tq); 545 546 TIMEOUT_TASK_INIT(sc->sc_tq, &sc->sc_tt, 0, e6000sw_tick, sc); 547 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 548 device_get_nameunit(dev)); 549 550#ifdef FDT 551 ports = ofw_bus_find_child(sc->node, "ports"); 552 if (ports == 0) { 553 device_printf(dev, "failed to parse DTS: no ports found for " 554 "switch\n"); 555 E6000SW_UNLOCK(sc); 556 return (ENXIO); 557 } 558 559 for (child = OF_child(ports); child != 0; child = OF_peer(child)) { 560 err = e6000sw_parse_child_fdt(sc, child, &port); 561 if (err != 0) { 562 device_printf(sc->dev, "failed to parse DTS\n"); 563 goto out_fail; 564 } 565#else 566 for (port = 0; port < sc->num_ports; port++) { 567 err = e6000sw_parse_hinted_port(sc, port); 568 if (err != 0) 569 continue; 570#endif 571 572 /* Port is in use. */ 573 sc->ports_mask |= (1 << port); 574 575 err = e6000sw_init_interface(sc, port); 576 if (err != 0) { 577 device_printf(sc->dev, "failed to init interface\n"); 578 goto out_fail; 579 } 580 581 if (e6000sw_is_fixedport(sc, port)) { 582 /* Link must be down to change speed force value. */ 583 reg = e6000sw_readreg(sc, REG_PORT(sc, port), 584 PSC_CONTROL); 585 reg &= ~PSC_CONTROL_LINK_UP; 586 reg |= PSC_CONTROL_FORCED_LINK; 587 e6000sw_writereg(sc, REG_PORT(sc, port), PSC_CONTROL, 588 reg); 589 590 /* 591 * Force speed, full-duplex, EEE off and flow-control 592 * on. 593 */ 594 reg &= ~(PSC_CONTROL_SPD2500 | PSC_CONTROL_ALT_SPD | 595 PSC_CONTROL_FORCED_FC | PSC_CONTROL_FC_ON | 596 PSC_CONTROL_FORCED_EEE); 597 if (e6000sw_is_fixed25port(sc, port)) 598 reg |= PSC_CONTROL_SPD2500; 599 else 600 reg |= PSC_CONTROL_SPD1000; 601 if (MVSWITCH(sc, MV88E6190) && 602 e6000sw_is_fixed25port(sc, port)) 603 reg |= PSC_CONTROL_ALT_SPD; 604 reg |= PSC_CONTROL_FORCED_DPX | PSC_CONTROL_FULLDPX | 605 PSC_CONTROL_FORCED_LINK | PSC_CONTROL_LINK_UP | 606 PSC_CONTROL_FORCED_SPD; 607 if (!MVSWITCH(sc, MV88E6190)) 608 reg |= PSC_CONTROL_FORCED_FC | PSC_CONTROL_FC_ON; 609 if (MVSWITCH(sc, MV88E6141) || 610 MVSWITCH(sc, MV88E6341) || 611 MVSWITCH(sc, MV88E6190)) 612 reg |= PSC_CONTROL_FORCED_EEE; 613 e6000sw_writereg(sc, REG_PORT(sc, port), PSC_CONTROL, 614 reg); 615 /* Power on the SERDES interfaces. */ 616 if (MVSWITCH(sc, MV88E6190) && 617 (port == 9 || port == 10)) { 618 if (e6000sw_is_fixed25port(sc, port)) 619 sgmii = false; 620 else 621 sgmii = true; 622 e6000sw_serdes_power(sc->dev, port, sgmii); 623 } 624 } 625 626 /* Don't attach miibus at CPU/fixed ports */ 627 if (!e6000sw_is_phyport(sc, port)) 628 continue; 629 630 err = e6000sw_attach_miibus(sc, port); 631 if (err != 0) { 632 device_printf(sc->dev, "failed to attach miibus\n"); 633 goto out_fail; 634 } 635 } 636 637 etherswitch_info.es_nports = sc->num_ports; 638 639 /* Default to port vlan. */ 640 e6000sw_set_vlan_mode(sc, ETHERSWITCH_VLAN_PORT); 641 642 reg = e6000sw_readreg(sc, REG_GLOBAL, SWITCH_GLOBAL_STATUS); 643 if (reg & SWITCH_GLOBAL_STATUS_IR) 644 device_printf(dev, "switch is ready.\n"); 645 E6000SW_UNLOCK(sc); 646 647 bus_generic_probe(dev); 648 bus_generic_attach(dev); 649 650 taskqueue_enqueue_timeout(sc->sc_tq, &sc->sc_tt, hz); 651 652 return (0); 653 654out_fail: 655 e6000sw_detach(dev); 656 657 return (err); 658} 659 660static int 661e6000sw_waitready(e6000sw_softc_t *sc, uint32_t phy, uint32_t reg, 662 uint32_t busybit) 663{ 664 int i; 665 666 for (i = 0; i < E6000SW_RETRIES; i++) { 667 if ((e6000sw_readreg(sc, phy, reg) & busybit) == 0) 668 return (0); 669 DELAY(1); 670 } 671 672 return (1); 673} 674 675/* XMDIO/Clause 45 access. */ 676static int 677e6000sw_read_xmdio(device_t dev, int phy, int devaddr, int devreg) 678{ 679 e6000sw_softc_t *sc; 680 uint32_t reg; 681 682 sc = device_get_softc(dev); 683 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 684 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 685 device_printf(dev, "Timeout while waiting for switch\n"); 686 return (ETIMEDOUT); 687 } 688 689 reg = devaddr & SMI_CMD_REG_ADDR_MASK; 690 reg |= (phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK; 691 692 /* Load C45 register address. */ 693 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, devreg); 694 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 695 reg | SMI_CMD_OP_C45_ADDR); 696 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 697 device_printf(dev, "Timeout while waiting for switch\n"); 698 return (ETIMEDOUT); 699 } 700 701 /* Start C45 read operation. */ 702 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 703 reg | SMI_CMD_OP_C45_READ); 704 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 705 device_printf(dev, "Timeout while waiting for switch\n"); 706 return (ETIMEDOUT); 707 } 708 709 /* Read C45 data. */ 710 reg = e6000sw_readreg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG); 711 712 return (reg & PHY_DATA_MASK); 713} 714 715static int 716e6000sw_write_xmdio(device_t dev, int phy, int devaddr, int devreg, int val) 717{ 718 e6000sw_softc_t *sc; 719 uint32_t reg; 720 721 sc = device_get_softc(dev); 722 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 723 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 724 device_printf(dev, "Timeout while waiting for switch\n"); 725 return (ETIMEDOUT); 726 } 727 728 reg = devaddr & SMI_CMD_REG_ADDR_MASK; 729 reg |= (phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK; 730 731 /* Load C45 register address. */ 732 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, devreg); 733 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 734 reg | SMI_CMD_OP_C45_ADDR); 735 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 736 device_printf(dev, "Timeout while waiting for switch\n"); 737 return (ETIMEDOUT); 738 } 739 740 /* Load data and start the C45 write operation. */ 741 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, devreg); 742 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 743 reg | SMI_CMD_OP_C45_WRITE); 744 745 return (0); 746} 747 748static int 749e6000sw_readphy(device_t dev, int phy, int reg) 750{ 751 e6000sw_softc_t *sc; 752 int locked, ret; 753 754 sc = device_get_softc(dev); 755 756 locked = E6000SW_LOCKED(sc); 757 if (!locked) 758 E6000SW_LOCK(sc); 759 ret = e6000sw_readphy_locked(dev, phy, reg); 760 if (!locked) 761 E6000SW_UNLOCK(sc); 762 763 return (ret); 764} 765 766/* 767 * PHY registers are paged. Put page index in reg 22 (accessible from every 768 * page), then access specific register. 769 */ 770static int 771e6000sw_readphy_locked(device_t dev, int phy, int reg) 772{ 773 e6000sw_softc_t *sc; 774 uint32_t val; 775 776 sc = device_get_softc(dev); 777 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 778 779 if (!e6000sw_is_phyport(sc, phy) || reg >= E6000SW_NUM_PHY_REGS) { 780 device_printf(dev, "Wrong register address.\n"); 781 return (EINVAL); 782 } 783 784 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 785 device_printf(dev, "Timeout while waiting for switch\n"); 786 return (ETIMEDOUT); 787 } 788 789 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 790 SMI_CMD_OP_C22_READ | (reg & SMI_CMD_REG_ADDR_MASK) | 791 ((phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK)); 792 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 793 device_printf(dev, "Timeout while waiting for switch\n"); 794 return (ETIMEDOUT); 795 } 796 797 val = e6000sw_readreg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG); 798 799 return (val & PHY_DATA_MASK); 800} 801 802static int 803e6000sw_writephy(device_t dev, int phy, int reg, int data) 804{ 805 e6000sw_softc_t *sc; 806 int locked, ret; 807 808 sc = device_get_softc(dev); 809 810 locked = E6000SW_LOCKED(sc); 811 if (!locked) 812 E6000SW_LOCK(sc); 813 ret = e6000sw_writephy_locked(dev, phy, reg, data); 814 if (!locked) 815 E6000SW_UNLOCK(sc); 816 817 return (ret); 818} 819 820static int 821e6000sw_writephy_locked(device_t dev, int phy, int reg, int data) 822{ 823 e6000sw_softc_t *sc; 824 825 sc = device_get_softc(dev); 826 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 827 828 if (!e6000sw_is_phyport(sc, phy) || reg >= E6000SW_NUM_PHY_REGS) { 829 device_printf(dev, "Wrong register address.\n"); 830 return (EINVAL); 831 } 832 833 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 834 device_printf(dev, "Timeout while waiting for switch\n"); 835 return (ETIMEDOUT); 836 } 837 838 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, 839 data & PHY_DATA_MASK); 840 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 841 SMI_CMD_OP_C22_WRITE | (reg & SMI_CMD_REG_ADDR_MASK) | 842 ((phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK)); 843 844 return (0); 845} 846 847static int 848e6000sw_detach(device_t dev) 849{ 850 int phy; 851 e6000sw_softc_t *sc; 852 853 sc = device_get_softc(dev); 854 855 if (device_is_attached(dev)) 856 taskqueue_drain_timeout(sc->sc_tq, &sc->sc_tt); 857 858 if (sc->sc_tq != NULL) 859 taskqueue_free(sc->sc_tq); 860 861 device_delete_children(dev); 862 863 sx_destroy(&sc->sx); 864 for (phy = 0; phy < sc->num_ports; phy++) { 865 if (sc->ifp[phy] != NULL) 866 if_free(sc->ifp[phy]); 867 if (sc->ifname[phy] != NULL) 868 free(sc->ifname[phy], M_E6000SW); 869 } 870 871 return (0); 872} 873 874static etherswitch_info_t* 875e6000sw_getinfo(device_t dev) 876{ 877 878 return (ðerswitch_info); 879} 880 881static int 882e6000sw_getconf(device_t dev, etherswitch_conf_t *conf) 883{ 884 struct e6000sw_softc *sc; 885 886 /* Return the VLAN mode. */ 887 sc = device_get_softc(dev); 888 conf->cmd = ETHERSWITCH_CONF_VLAN_MODE; 889 conf->vlan_mode = sc->vlan_mode; 890 891 return (0); 892} 893 894static int 895e6000sw_setconf(device_t dev, etherswitch_conf_t *conf) 896{ 897 struct e6000sw_softc *sc; 898 899 /* Set the VLAN mode. */ 900 sc = device_get_softc(dev); 901 if (conf->cmd & ETHERSWITCH_CONF_VLAN_MODE) { 902 E6000SW_LOCK(sc); 903 e6000sw_set_vlan_mode(sc, conf->vlan_mode); 904 E6000SW_UNLOCK(sc); 905 } 906 907 return (0); 908} 909 910static void 911e6000sw_lock(device_t dev) 912{ 913 struct e6000sw_softc *sc; 914 915 sc = device_get_softc(dev); 916 917 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 918 E6000SW_LOCK(sc); 919} 920 921static void 922e6000sw_unlock(device_t dev) 923{ 924 struct e6000sw_softc *sc; 925 926 sc = device_get_softc(dev); 927 928 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 929 E6000SW_UNLOCK(sc); 930} 931 932static int 933e6000sw_getport(device_t dev, etherswitch_port_t *p) 934{ 935 struct mii_data *mii; 936 int err; 937 struct ifmediareq *ifmr; 938 uint32_t reg; 939 940 e6000sw_softc_t *sc = device_get_softc(dev); 941 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 942 943 if (p->es_port >= sc->num_ports || p->es_port < 0) 944 return (EINVAL); 945 if (!e6000sw_is_portenabled(sc, p->es_port)) 946 return (0); 947 948 E6000SW_LOCK(sc); 949 e6000sw_get_pvid(sc, p->es_port, &p->es_pvid); 950 951 /* Port flags. */ 952 reg = e6000sw_readreg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2); 953 if (reg & PORT_CONTROL2_DISC_TAGGED) 954 p->es_flags |= ETHERSWITCH_PORT_DROPTAGGED; 955 if (reg & PORT_CONTROL2_DISC_UNTAGGED) 956 p->es_flags |= ETHERSWITCH_PORT_DROPUNTAGGED; 957 958 err = 0; 959 if (e6000sw_is_fixedport(sc, p->es_port)) { 960 if (e6000sw_is_cpuport(sc, p->es_port)) 961 p->es_flags |= ETHERSWITCH_PORT_CPU; 962 ifmr = &p->es_ifmr; 963 ifmr->ifm_status = IFM_ACTIVE | IFM_AVALID; 964 ifmr->ifm_count = 0; 965 if (e6000sw_is_fixed25port(sc, p->es_port)) 966 ifmr->ifm_active = IFM_2500_T; 967 else 968 ifmr->ifm_active = IFM_1000_T; 969 ifmr->ifm_active |= IFM_ETHER | IFM_FDX; 970 ifmr->ifm_current = ifmr->ifm_active; 971 ifmr->ifm_mask = 0; 972 } else { 973 mii = e6000sw_miiforphy(sc, p->es_port); 974 err = ifmedia_ioctl(mii->mii_ifp, &p->es_ifr, 975 &mii->mii_media, SIOCGIFMEDIA); 976 } 977 E6000SW_UNLOCK(sc); 978 979 return (err); 980} 981 982static int 983e6000sw_setport(device_t dev, etherswitch_port_t *p) 984{ 985 e6000sw_softc_t *sc; 986 int err; 987 struct mii_data *mii; 988 uint32_t reg; 989 990 sc = device_get_softc(dev); 991 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 992 993 if (p->es_port >= sc->num_ports || p->es_port < 0) 994 return (EINVAL); 995 if (!e6000sw_is_portenabled(sc, p->es_port)) 996 return (0); 997 998 E6000SW_LOCK(sc); 999 1000 /* Port flags. */ 1001 reg = e6000sw_readreg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2); 1002 if (p->es_flags & ETHERSWITCH_PORT_DROPTAGGED) 1003 reg |= PORT_CONTROL2_DISC_TAGGED; 1004 else 1005 reg &= ~PORT_CONTROL2_DISC_TAGGED; 1006 if (p->es_flags & ETHERSWITCH_PORT_DROPUNTAGGED) 1007 reg |= PORT_CONTROL2_DISC_UNTAGGED; 1008 else 1009 reg &= ~PORT_CONTROL2_DISC_UNTAGGED; 1010 e6000sw_writereg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2, reg); 1011 1012 err = 0; 1013 if (p->es_pvid != 0) 1014 e6000sw_set_pvid(sc, p->es_port, p->es_pvid); 1015 if (e6000sw_is_phyport(sc, p->es_port)) { 1016 mii = e6000sw_miiforphy(sc, p->es_port); 1017 err = ifmedia_ioctl(mii->mii_ifp, &p->es_ifr, &mii->mii_media, 1018 SIOCSIFMEDIA); 1019 } 1020 E6000SW_UNLOCK(sc); 1021 1022 return (err); 1023} 1024 1025static __inline void 1026e6000sw_port_vlan_assign(e6000sw_softc_t *sc, int port, uint32_t fid, 1027 uint32_t members) 1028{ 1029 uint32_t reg; 1030 1031 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VLAN_MAP); 1032 reg &= ~(PORT_MASK(sc) | PORT_VLAN_MAP_FID_MASK); 1033 reg |= members & PORT_MASK(sc) & ~(1 << port); 1034 reg |= (fid << PORT_VLAN_MAP_FID) & PORT_VLAN_MAP_FID_MASK; 1035 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_VLAN_MAP, reg); 1036 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL1); 1037 reg &= ~PORT_CONTROL1_FID_MASK; 1038 reg |= (fid >> 4) & PORT_CONTROL1_FID_MASK; 1039 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL1, reg); 1040} 1041 1042static int 1043e6000sw_init_vlan(struct e6000sw_softc *sc) 1044{ 1045 int i, port, ret; 1046 uint32_t members; 1047 1048 /* Disable all ports */ 1049 for (port = 0; port < sc->num_ports; port++) { 1050 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL); 1051 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL, 1052 (ret & ~PORT_CONTROL_ENABLE)); 1053 } 1054 1055 /* Flush VTU. */ 1056 e6000sw_vtu_flush(sc); 1057 1058 for (port = 0; port < sc->num_ports; port++) { 1059 /* Reset the egress and frame mode. */ 1060 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL); 1061 ret &= ~(PORT_CONTROL_EGRESS | PORT_CONTROL_FRAME); 1062 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL, ret); 1063 1064 /* Set the 802.1q mode. */ 1065 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL2); 1066 ret &= ~PORT_CONTROL2_DOT1Q; 1067 if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) 1068 ret |= PORT_CONTROL2_DOT1Q; 1069 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL2, ret); 1070 } 1071 1072 for (port = 0; port < sc->num_ports; port++) { 1073 if (!e6000sw_is_portenabled(sc, port)) 1074 continue; 1075 1076 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VID); 1077 1078 /* Set port priority */ 1079 ret &= ~PORT_VID_PRIORITY_MASK; 1080 1081 /* Set VID map */ 1082 ret &= ~PORT_VID_DEF_VID_MASK; 1083 if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) 1084 ret |= 1; 1085 else 1086 ret |= (port + 1); 1087 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_VID, ret); 1088 } 1089 1090 /* Assign the member ports to each origin port. */ 1091 for (port = 0; port < sc->num_ports; port++) { 1092 members = 0; 1093 if (e6000sw_is_portenabled(sc, port)) { 1094 for (i = 0; i < sc->num_ports; i++) { 1095 if (i == port || !e6000sw_is_portenabled(sc, i)) 1096 continue; 1097 members |= (1 << i); 1098 } 1099 } 1100 /* Default to FID 0. */ 1101 e6000sw_port_vlan_assign(sc, port, 0, members); 1102 } 1103 1104 /* Reset internal VLAN table. */ 1105 for (i = 0; i < nitems(sc->vlans); i++) 1106 sc->vlans[i] = 0; 1107 1108 /* Create default VLAN (1). */ 1109 if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) { 1110 sc->vlans[0] = 1; 1111 e6000sw_vtu_update(sc, 0, sc->vlans[0], 1, 0, sc->ports_mask); 1112 } 1113 1114 /* Enable all ports */ 1115 for (port = 0; port < sc->num_ports; port++) { 1116 if (!e6000sw_is_portenabled(sc, port)) 1117 continue; 1118 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL); 1119 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL, 1120 (ret | PORT_CONTROL_ENABLE)); 1121 } 1122 1123 return (0); 1124} 1125 1126static int 1127e6000sw_set_vlan_mode(struct e6000sw_softc *sc, uint32_t mode) 1128{ 1129 1130 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1131 switch (mode) { 1132 case ETHERSWITCH_VLAN_PORT: 1133 sc->vlan_mode = ETHERSWITCH_VLAN_PORT; 1134 etherswitch_info.es_nvlangroups = sc->num_ports; 1135 return (e6000sw_init_vlan(sc)); 1136 break; 1137 case ETHERSWITCH_VLAN_DOT1Q: 1138 sc->vlan_mode = ETHERSWITCH_VLAN_DOT1Q; 1139 etherswitch_info.es_nvlangroups = E6000SW_NUM_VLANS; 1140 return (e6000sw_init_vlan(sc)); 1141 break; 1142 default: 1143 return (EINVAL); 1144 } 1145} 1146 1147/* 1148 * Registers in this switch are divided into sections, specified in 1149 * documentation. So as to access any of them, section index and reg index 1150 * is necessary. etherswitchcfg uses only one variable, so indexes were 1151 * compressed into addr_reg: 32 * section_index + reg_index. 1152 */ 1153static int 1154e6000sw_readreg_wrapper(device_t dev, int addr_reg) 1155{ 1156 e6000sw_softc_t *sc; 1157 1158 sc = device_get_softc(dev); 1159 if ((addr_reg > (REG_GLOBAL2 * 32 + REG_NUM_MAX)) || 1160 (addr_reg < (REG_PORT(sc, 0) * 32))) { 1161 device_printf(dev, "Wrong register address.\n"); 1162 return (EINVAL); 1163 } 1164 1165 return (e6000sw_readreg(device_get_softc(dev), addr_reg / 32, 1166 addr_reg % 32)); 1167} 1168 1169static int 1170e6000sw_writereg_wrapper(device_t dev, int addr_reg, int val) 1171{ 1172 e6000sw_softc_t *sc; 1173 1174 sc = device_get_softc(dev); 1175 if ((addr_reg > (REG_GLOBAL2 * 32 + REG_NUM_MAX)) || 1176 (addr_reg < (REG_PORT(sc, 0) * 32))) { 1177 device_printf(dev, "Wrong register address.\n"); 1178 return (EINVAL); 1179 } 1180 e6000sw_writereg(device_get_softc(dev), addr_reg / 32, 1181 addr_reg % 32, val); 1182 1183 return (0); 1184} 1185 1186/* 1187 * setvgroup/getvgroup called from etherswitchfcg need to be locked, 1188 * while internal calls do not. 1189 */ 1190static int 1191e6000sw_setvgroup_wrapper(device_t dev, etherswitch_vlangroup_t *vg) 1192{ 1193 e6000sw_softc_t *sc; 1194 int ret; 1195 1196 sc = device_get_softc(dev); 1197 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 1198 1199 E6000SW_LOCK(sc); 1200 ret = e6000sw_setvgroup(dev, vg); 1201 E6000SW_UNLOCK(sc); 1202 1203 return (ret); 1204} 1205 1206static int 1207e6000sw_getvgroup_wrapper(device_t dev, etherswitch_vlangroup_t *vg) 1208{ 1209 e6000sw_softc_t *sc; 1210 int ret; 1211 1212 sc = device_get_softc(dev); 1213 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 1214 1215 E6000SW_LOCK(sc); 1216 ret = e6000sw_getvgroup(dev, vg); 1217 E6000SW_UNLOCK(sc); 1218 1219 return (ret); 1220} 1221 1222static int 1223e6000sw_set_port_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg) 1224{ 1225 uint32_t port; 1226 1227 port = vg->es_vlangroup; 1228 if (port > sc->num_ports) 1229 return (EINVAL); 1230 1231 if (vg->es_member_ports != vg->es_untagged_ports) { 1232 device_printf(sc->dev, "Tagged ports not supported.\n"); 1233 return (EINVAL); 1234 } 1235 1236 e6000sw_port_vlan_assign(sc, port, 0, vg->es_untagged_ports); 1237 vg->es_vid = port | ETHERSWITCH_VID_VALID; 1238 1239 return (0); 1240} 1241 1242static int 1243e6000sw_set_dot1q_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg) 1244{ 1245 int i, vlan; 1246 1247 vlan = vg->es_vid & ETHERSWITCH_VID_MASK; 1248 1249 /* Set VLAN to '0' removes it from table. */ 1250 if (vlan == 0) { 1251 e6000sw_vtu_update(sc, VTU_PURGE, 1252 sc->vlans[vg->es_vlangroup], 0, 0, 0); 1253 sc->vlans[vg->es_vlangroup] = 0; 1254 return (0); 1255 } 1256 1257 /* Is this VLAN already in table ? */ 1258 for (i = 0; i < etherswitch_info.es_nvlangroups; i++) 1259 if (i != vg->es_vlangroup && vlan == sc->vlans[i]) 1260 return (EINVAL); 1261 1262 sc->vlans[vg->es_vlangroup] = vlan; 1263 e6000sw_vtu_update(sc, 0, vlan, vg->es_vlangroup + 1, 1264 vg->es_member_ports & sc->ports_mask, 1265 vg->es_untagged_ports & sc->ports_mask); 1266 1267 return (0); 1268} 1269 1270static int 1271e6000sw_setvgroup(device_t dev, etherswitch_vlangroup_t *vg) 1272{ 1273 e6000sw_softc_t *sc; 1274 1275 sc = device_get_softc(dev); 1276 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1277 1278 if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT) 1279 return (e6000sw_set_port_vlan(sc, vg)); 1280 else if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) 1281 return (e6000sw_set_dot1q_vlan(sc, vg)); 1282 1283 return (EINVAL); 1284} 1285 1286static int 1287e6000sw_get_port_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg) 1288{ 1289 uint32_t port, reg; 1290 1291 port = vg->es_vlangroup; 1292 if (port > sc->num_ports) 1293 return (EINVAL); 1294 1295 if (!e6000sw_is_portenabled(sc, port)) { 1296 vg->es_vid = port; 1297 return (0); 1298 } 1299 1300 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VLAN_MAP); 1301 vg->es_untagged_ports = vg->es_member_ports = reg & PORT_MASK(sc); 1302 vg->es_vid = port | ETHERSWITCH_VID_VALID; 1303 vg->es_fid = (reg & PORT_VLAN_MAP_FID_MASK) >> PORT_VLAN_MAP_FID; 1304 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL1); 1305 vg->es_fid |= (reg & PORT_CONTROL1_FID_MASK) << 4; 1306 1307 return (0); 1308} 1309 1310static int 1311e6000sw_get_dot1q_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg) 1312{ 1313 int i, port; 1314 uint32_t reg; 1315 1316 vg->es_fid = 0; 1317 vg->es_vid = sc->vlans[vg->es_vlangroup]; 1318 vg->es_untagged_ports = vg->es_member_ports = 0; 1319 if (vg->es_vid == 0) 1320 return (0); 1321 1322 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1323 device_printf(sc->dev, "VTU unit is busy, cannot access\n"); 1324 return (EBUSY); 1325 } 1326 1327 e6000sw_writereg(sc, REG_GLOBAL, VTU_VID, vg->es_vid - 1); 1328 1329 reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_OPERATION); 1330 reg &= ~VTU_OP_MASK; 1331 reg |= VTU_GET_NEXT | VTU_BUSY; 1332 e6000sw_writereg(sc, REG_GLOBAL, VTU_OPERATION, reg); 1333 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1334 device_printf(sc->dev, "Timeout while reading\n"); 1335 return (EBUSY); 1336 } 1337 1338 reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_VID); 1339 if (reg == VTU_VID_MASK || (reg & VTU_VID_VALID) == 0) 1340 return (EINVAL); 1341 if ((reg & VTU_VID_MASK) != vg->es_vid) 1342 return (EINVAL); 1343 1344 vg->es_vid |= ETHERSWITCH_VID_VALID; 1345 reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_DATA); 1346 for (i = 0; i < sc->num_ports; i++) { 1347 if (i == VTU_PPREG(sc)) 1348 reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_DATA2); 1349 port = (reg >> VTU_PORT(sc, i)) & VTU_PORT_MASK; 1350 if (port == VTU_PORT_UNTAGGED) { 1351 vg->es_untagged_ports |= (1 << i); 1352 vg->es_member_ports |= (1 << i); 1353 } else if (port == VTU_PORT_TAGGED) 1354 vg->es_member_ports |= (1 << i); 1355 } 1356 1357 return (0); 1358} 1359 1360static int 1361e6000sw_getvgroup(device_t dev, etherswitch_vlangroup_t *vg) 1362{ 1363 e6000sw_softc_t *sc; 1364 1365 sc = device_get_softc(dev); 1366 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1367 1368 if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT) 1369 return (e6000sw_get_port_vlan(sc, vg)); 1370 else if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) 1371 return (e6000sw_get_dot1q_vlan(sc, vg)); 1372 1373 return (EINVAL); 1374} 1375 1376static __inline struct mii_data* 1377e6000sw_miiforphy(e6000sw_softc_t *sc, unsigned int phy) 1378{ 1379 1380 if (!e6000sw_is_phyport(sc, phy)) 1381 return (NULL); 1382 1383 return (device_get_softc(sc->miibus[phy])); 1384} 1385 1386static int 1387e6000sw_ifmedia_upd(if_t ifp) 1388{ 1389 e6000sw_softc_t *sc; 1390 struct mii_data *mii; 1391 1392 sc = if_getsoftc(ifp); 1393 mii = e6000sw_miiforphy(sc, if_getdunit(ifp)); 1394 if (mii == NULL) 1395 return (ENXIO); 1396 mii_mediachg(mii); 1397 1398 return (0); 1399} 1400 1401static void 1402e6000sw_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 1403{ 1404 e6000sw_softc_t *sc; 1405 struct mii_data *mii; 1406 1407 sc = if_getsoftc(ifp); 1408 mii = e6000sw_miiforphy(sc, if_getdunit(ifp)); 1409 1410 if (mii == NULL) 1411 return; 1412 1413 mii_pollstat(mii); 1414 ifmr->ifm_active = mii->mii_media_active; 1415 ifmr->ifm_status = mii->mii_media_status; 1416} 1417 1418static int 1419e6000sw_smi_waitready(e6000sw_softc_t *sc, int phy) 1420{ 1421 int i; 1422 1423 for (i = 0; i < E6000SW_SMI_TIMEOUT; i++) { 1424 if ((MDIO_READ(sc->dev, phy, SMI_CMD) & SMI_CMD_BUSY) == 0) 1425 return (0); 1426 DELAY(1); 1427 } 1428 1429 return (1); 1430} 1431 1432static __inline uint32_t 1433e6000sw_readreg(e6000sw_softc_t *sc, int addr, int reg) 1434{ 1435 1436 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1437 1438 if (!MVSWITCH_MULTICHIP(sc)) 1439 return (MDIO_READ(sc->dev, addr, reg) & 0xffff); 1440 1441 if (e6000sw_smi_waitready(sc, sc->sw_addr)) { 1442 printf("e6000sw: readreg timeout\n"); 1443 return (0xffff); 1444 } 1445 MDIO_WRITE(sc->dev, sc->sw_addr, SMI_CMD, 1446 SMI_CMD_OP_C22_READ | (reg & SMI_CMD_REG_ADDR_MASK) | 1447 ((addr << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK)); 1448 if (e6000sw_smi_waitready(sc, sc->sw_addr)) { 1449 printf("e6000sw: readreg timeout\n"); 1450 return (0xffff); 1451 } 1452 1453 return (MDIO_READ(sc->dev, sc->sw_addr, SMI_DATA) & 0xffff); 1454} 1455 1456static __inline void 1457e6000sw_writereg(e6000sw_softc_t *sc, int addr, int reg, int val) 1458{ 1459 1460 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1461 1462 if (!MVSWITCH_MULTICHIP(sc)) { 1463 MDIO_WRITE(sc->dev, addr, reg, val); 1464 return; 1465 } 1466 1467 if (e6000sw_smi_waitready(sc, sc->sw_addr)) { 1468 printf("e6000sw: readreg timeout\n"); 1469 return; 1470 } 1471 MDIO_WRITE(sc->dev, sc->sw_addr, SMI_DATA, val); 1472 MDIO_WRITE(sc->dev, sc->sw_addr, SMI_CMD, 1473 SMI_CMD_OP_C22_WRITE | (reg & SMI_CMD_REG_ADDR_MASK) | 1474 ((addr << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK)); 1475} 1476 1477static __inline bool 1478e6000sw_is_cpuport(e6000sw_softc_t *sc, int port) 1479{ 1480 1481 return ((sc->cpuports_mask & (1 << port)) ? true : false); 1482} 1483 1484static __inline bool 1485e6000sw_is_fixedport(e6000sw_softc_t *sc, int port) 1486{ 1487 1488 return ((sc->fixed_mask & (1 << port)) ? true : false); 1489} 1490 1491static __inline bool 1492e6000sw_is_fixed25port(e6000sw_softc_t *sc, int port) 1493{ 1494 1495 return ((sc->fixed25_mask & (1 << port)) ? true : false); 1496} 1497 1498static __inline bool 1499e6000sw_is_phyport(e6000sw_softc_t *sc, int port) 1500{ 1501 uint32_t phy_mask; 1502 phy_mask = ~(sc->fixed_mask | sc->cpuports_mask); 1503 1504 return ((phy_mask & (1 << port)) ? true : false); 1505} 1506 1507static __inline bool 1508e6000sw_is_portenabled(e6000sw_softc_t *sc, int port) 1509{ 1510 1511 return ((sc->ports_mask & (1 << port)) ? true : false); 1512} 1513 1514static __inline void 1515e6000sw_set_pvid(e6000sw_softc_t *sc, int port, int pvid) 1516{ 1517 uint32_t reg; 1518 1519 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VID); 1520 reg &= ~PORT_VID_DEF_VID_MASK; 1521 reg |= (pvid & PORT_VID_DEF_VID_MASK); 1522 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_VID, reg); 1523} 1524 1525static __inline int 1526e6000sw_get_pvid(e6000sw_softc_t *sc, int port, int *pvid) 1527{ 1528 1529 if (pvid == NULL) 1530 return (ENXIO); 1531 1532 *pvid = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VID) & 1533 PORT_VID_DEF_VID_MASK; 1534 1535 return (0); 1536} 1537 1538/* 1539 * Convert port status to ifmedia. 1540 */ 1541static void 1542e6000sw_update_ifmedia(uint16_t portstatus, u_int *media_status, u_int *media_active) 1543{ 1544 *media_active = IFM_ETHER; 1545 *media_status = IFM_AVALID; 1546 1547 if ((portstatus & PORT_STATUS_LINK_MASK) != 0) 1548 *media_status |= IFM_ACTIVE; 1549 else { 1550 *media_active |= IFM_NONE; 1551 return; 1552 } 1553 1554 switch (portstatus & PORT_STATUS_SPEED_MASK) { 1555 case PORT_STATUS_SPEED_10: 1556 *media_active |= IFM_10_T; 1557 break; 1558 case PORT_STATUS_SPEED_100: 1559 *media_active |= IFM_100_TX; 1560 break; 1561 case PORT_STATUS_SPEED_1000: 1562 *media_active |= IFM_1000_T; 1563 break; 1564 } 1565 1566 if ((portstatus & PORT_STATUS_DUPLEX_MASK) == 0) 1567 *media_active |= IFM_FDX; 1568 else 1569 *media_active |= IFM_HDX; 1570} 1571 1572static void 1573e6000sw_tick(void *arg, int p __unused) 1574{ 1575 e6000sw_softc_t *sc; 1576 struct mii_data *mii; 1577 struct mii_softc *miisc; 1578 uint16_t portstatus; 1579 int port; 1580 1581 sc = arg; 1582 1583 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 1584 1585 E6000SW_LOCK(sc); 1586 for (port = 0; port < sc->num_ports; port++) { 1587 /* Tick only on PHY ports */ 1588 if (!e6000sw_is_portenabled(sc, port) || 1589 !e6000sw_is_phyport(sc, port)) 1590 continue; 1591 1592 mii = e6000sw_miiforphy(sc, port); 1593 if (mii == NULL) 1594 continue; 1595 1596 portstatus = e6000sw_readreg(sc, REG_PORT(sc, port), 1597 PORT_STATUS); 1598 1599 e6000sw_update_ifmedia(portstatus, 1600 &mii->mii_media_status, &mii->mii_media_active); 1601 1602 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 1603 if (IFM_INST(mii->mii_media.ifm_cur->ifm_media) 1604 != miisc->mii_inst) 1605 continue; 1606 mii_phy_update(miisc, MII_POLLSTAT); 1607 } 1608 } 1609 E6000SW_UNLOCK(sc); 1610} 1611 1612static void 1613e6000sw_setup(device_t dev, e6000sw_softc_t *sc) 1614{ 1615 uint32_t atu_ctrl; 1616 1617 /* Set aging time. */ 1618 atu_ctrl = e6000sw_readreg(sc, REG_GLOBAL, ATU_CONTROL); 1619 atu_ctrl &= ~ATU_CONTROL_AGETIME_MASK; 1620 atu_ctrl |= E6000SW_DEFAULT_AGETIME << ATU_CONTROL_AGETIME; 1621 e6000sw_writereg(sc, REG_GLOBAL, ATU_CONTROL, atu_ctrl); 1622 1623 /* Send all with specific mac address to cpu port */ 1624 e6000sw_writereg(sc, REG_GLOBAL2, MGMT_EN_2x, MGMT_EN_ALL); 1625 e6000sw_writereg(sc, REG_GLOBAL2, MGMT_EN_0x, MGMT_EN_ALL); 1626 1627 /* Disable Remote Management */ 1628 e6000sw_writereg(sc, REG_GLOBAL, SWITCH_GLOBAL_CONTROL2, 0); 1629 1630 /* Disable loopback filter and flow control messages */ 1631 e6000sw_writereg(sc, REG_GLOBAL2, SWITCH_MGMT, 1632 SWITCH_MGMT_PRI_MASK | 1633 (1 << SWITCH_MGMT_RSVD2CPU) | 1634 SWITCH_MGMT_FC_PRI_MASK | 1635 (1 << SWITCH_MGMT_FORCEFLOW)); 1636 1637 e6000sw_atu_flush(dev, sc, NO_OPERATION); 1638 e6000sw_atu_mac_table(dev, sc, NULL, NO_OPERATION); 1639 e6000sw_set_atustat(dev, sc, 0, COUNT_ALL); 1640} 1641 1642static void 1643e6000sw_set_atustat(device_t dev, e6000sw_softc_t *sc, int bin, int flag) 1644{ 1645 1646 e6000sw_readreg(sc, REG_GLOBAL2, ATU_STATS); 1647 e6000sw_writereg(sc, REG_GLOBAL2, ATU_STATS, (bin << ATU_STATS_BIN ) | 1648 (flag << ATU_STATS_FLAG)); 1649} 1650 1651static int 1652e6000sw_atu_mac_table(device_t dev, e6000sw_softc_t *sc, struct atu_opt *atu, 1653 int flag) 1654{ 1655 uint16_t ret_opt; 1656 uint16_t ret_data; 1657 1658 if (flag == NO_OPERATION) 1659 return (0); 1660 else if ((flag & (LOAD_FROM_FIB | PURGE_FROM_FIB | GET_NEXT_IN_FIB | 1661 GET_VIOLATION_DATA | CLEAR_VIOLATION_DATA)) == 0) { 1662 device_printf(dev, "Wrong Opcode for ATU operation\n"); 1663 return (EINVAL); 1664 } 1665 1666 if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY)) { 1667 device_printf(dev, "ATU unit is busy, cannot access\n"); 1668 return (EBUSY); 1669 } 1670 1671 ret_opt = e6000sw_readreg(sc, REG_GLOBAL, ATU_OPERATION); 1672 if (flag & LOAD_FROM_FIB) { 1673 ret_data = e6000sw_readreg(sc, REG_GLOBAL, ATU_DATA); 1674 e6000sw_writereg(sc, REG_GLOBAL2, ATU_DATA, (ret_data & 1675 ~ENTRY_STATE)); 1676 } 1677 e6000sw_writereg(sc, REG_GLOBAL, ATU_MAC_ADDR01, atu->mac_01); 1678 e6000sw_writereg(sc, REG_GLOBAL, ATU_MAC_ADDR23, atu->mac_23); 1679 e6000sw_writereg(sc, REG_GLOBAL, ATU_MAC_ADDR45, atu->mac_45); 1680 e6000sw_writereg(sc, REG_GLOBAL, ATU_FID, atu->fid); 1681 1682 e6000sw_writereg(sc, REG_GLOBAL, ATU_OPERATION, 1683 (ret_opt | ATU_UNIT_BUSY | flag)); 1684 1685 if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY)) 1686 device_printf(dev, "Timeout while waiting ATU\n"); 1687 else if (flag & GET_NEXT_IN_FIB) { 1688 atu->mac_01 = e6000sw_readreg(sc, REG_GLOBAL, 1689 ATU_MAC_ADDR01); 1690 atu->mac_23 = e6000sw_readreg(sc, REG_GLOBAL, 1691 ATU_MAC_ADDR23); 1692 atu->mac_45 = e6000sw_readreg(sc, REG_GLOBAL, 1693 ATU_MAC_ADDR45); 1694 } 1695 1696 return (0); 1697} 1698 1699static int 1700e6000sw_atu_flush(device_t dev, e6000sw_softc_t *sc, int flag) 1701{ 1702 uint32_t reg; 1703 1704 if (flag == NO_OPERATION) 1705 return (0); 1706 1707 if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY)) { 1708 device_printf(dev, "ATU unit is busy, cannot access\n"); 1709 return (EBUSY); 1710 } 1711 reg = e6000sw_readreg(sc, REG_GLOBAL, ATU_OPERATION); 1712 e6000sw_writereg(sc, REG_GLOBAL, ATU_OPERATION, 1713 (reg | ATU_UNIT_BUSY | flag)); 1714 if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY)) 1715 device_printf(dev, "Timeout while flushing ATU\n"); 1716 1717 return (0); 1718} 1719 1720static int 1721e6000sw_vtu_flush(e6000sw_softc_t *sc) 1722{ 1723 1724 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1725 device_printf(sc->dev, "VTU unit is busy, cannot access\n"); 1726 return (EBUSY); 1727 } 1728 1729 e6000sw_writereg(sc, REG_GLOBAL, VTU_OPERATION, VTU_FLUSH | VTU_BUSY); 1730 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1731 device_printf(sc->dev, "Timeout while flushing VTU\n"); 1732 return (ETIMEDOUT); 1733 } 1734 1735 return (0); 1736} 1737 1738static int 1739e6000sw_vtu_update(e6000sw_softc_t *sc, int purge, int vid, int fid, 1740 int members, int untagged) 1741{ 1742 int i, op; 1743 uint32_t data[2]; 1744 1745 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1746 device_printf(sc->dev, "VTU unit is busy, cannot access\n"); 1747 return (EBUSY); 1748 } 1749 1750 *data = (vid & VTU_VID_MASK); 1751 if (purge == 0) 1752 *data |= VTU_VID_VALID; 1753 e6000sw_writereg(sc, REG_GLOBAL, VTU_VID, *data); 1754 1755 if (purge == 0) { 1756 data[0] = 0; 1757 data[1] = 0; 1758 for (i = 0; i < sc->num_ports; i++) { 1759 if ((untagged & (1 << i)) != 0) 1760 data[i / VTU_PPREG(sc)] |= 1761 VTU_PORT_UNTAGGED << VTU_PORT(sc, i); 1762 else if ((members & (1 << i)) != 0) 1763 data[i / VTU_PPREG(sc)] |= 1764 VTU_PORT_TAGGED << VTU_PORT(sc, i); 1765 else 1766 data[i / VTU_PPREG(sc)] |= 1767 VTU_PORT_DISCARD << VTU_PORT(sc, i); 1768 } 1769 e6000sw_writereg(sc, REG_GLOBAL, VTU_DATA, data[0]); 1770 e6000sw_writereg(sc, REG_GLOBAL, VTU_DATA2, data[1]); 1771 e6000sw_writereg(sc, REG_GLOBAL, VTU_FID, 1772 fid & VTU_FID_MASK(sc)); 1773 op = VTU_LOAD; 1774 } else 1775 op = VTU_PURGE; 1776 1777 e6000sw_writereg(sc, REG_GLOBAL, VTU_OPERATION, op | VTU_BUSY); 1778 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1779 device_printf(sc->dev, "Timeout while flushing VTU\n"); 1780 return (ETIMEDOUT); 1781 } 1782 1783 return (0); 1784} 1785