1/* 2 * Copyright �� 2007-2008 Intel Corporation 3 * Jesse Barnes <jesse.barnes@intel.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#ifndef __DRM_EDID_H__ 24#define __DRM_EDID_H__ 25 26#define EDID_LENGTH 128 27#define DDC_ADDR 0x50 28 29#define CEA_EXT 0x02 30#define VTB_EXT 0x10 31#define DI_EXT 0x40 32#define LS_EXT 0x50 33#define MI_EXT 0x60 34 35struct est_timings { 36 u8 t1; 37 u8 t2; 38 u8 mfg_rsvd; 39} __attribute__((packed)); 40 41/* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */ 42#define EDID_TIMING_ASPECT_SHIFT 6 43#define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT) 44 45/* need to add 60 */ 46#define EDID_TIMING_VFREQ_SHIFT 0 47#define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT) 48 49struct std_timing { 50 u8 hsize; /* need to multiply by 8 then add 248 */ 51 u8 vfreq_aspect; 52} __attribute__((packed)); 53 54#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) 55#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) 56#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) 57#define DRM_EDID_PT_STEREO (1 << 5) 58#define DRM_EDID_PT_INTERLACED (1 << 7) 59 60/* If detailed data is pixel timing */ 61struct detailed_pixel_timing { 62 u8 hactive_lo; 63 u8 hblank_lo; 64 u8 hactive_hblank_hi; 65 u8 vactive_lo; 66 u8 vblank_lo; 67 u8 vactive_vblank_hi; 68 u8 hsync_offset_lo; 69 u8 hsync_pulse_width_lo; 70 u8 vsync_offset_pulse_width_lo; 71 u8 hsync_vsync_offset_pulse_width_hi; 72 u8 width_mm_lo; 73 u8 height_mm_lo; 74 u8 width_height_mm_hi; 75 u8 hborder; 76 u8 vborder; 77 u8 misc; 78} __attribute__((packed)); 79 80/* If it's not pixel timing, it'll be one of the below */ 81struct detailed_data_string { 82 u8 str[13]; 83} __attribute__((packed)); 84 85struct detailed_data_monitor_range { 86 u8 min_vfreq; 87 u8 max_vfreq; 88 u8 min_hfreq_khz; 89 u8 max_hfreq_khz; 90 u8 pixel_clock_mhz; /* need to multiply by 10 */ 91 u8 flags; 92 union { 93 struct { 94 u8 reserved; 95 u8 hfreq_start_khz; /* need to multiply by 2 */ 96 u8 c; /* need to divide by 2 */ 97 __le16 m; 98 u8 k; 99 u8 j; /* need to divide by 2 */ 100 } __attribute__((packed)) gtf2; 101 struct { 102 u8 version; 103 u8 data1; /* high 6 bits: extra clock resolution */ 104 u8 data2; /* plus low 2 of above: max hactive */ 105 u8 supported_aspects; 106 u8 flags; /* preferred aspect and blanking support */ 107 u8 supported_scalings; 108 u8 preferred_refresh; 109 } __attribute__((packed)) cvt; 110 } formula; 111} __attribute__((packed)); 112 113struct detailed_data_wpindex { 114 u8 white_yx_lo; /* Lower 2 bits each */ 115 u8 white_x_hi; 116 u8 white_y_hi; 117 u8 gamma; /* need to divide by 100 then add 1 */ 118} __attribute__((packed)); 119 120struct detailed_data_color_point { 121 u8 windex1; 122 u8 wpindex1[3]; 123 u8 windex2; 124 u8 wpindex2[3]; 125} __attribute__((packed)); 126 127struct cvt_timing { 128 u8 code[3]; 129} __attribute__((packed)); 130 131struct detailed_non_pixel { 132 u8 pad1; 133 u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name 134 fb=color point data, fa=standard timing data, 135 f9=undefined, f8=mfg. reserved */ 136 u8 pad2; 137 union { 138 struct detailed_data_string str; 139 struct detailed_data_monitor_range range; 140 struct detailed_data_wpindex color; 141 struct std_timing timings[6]; 142 struct cvt_timing cvt[4]; 143 } data; 144} __attribute__((packed)); 145 146#define EDID_DETAIL_EST_TIMINGS 0xf7 147#define EDID_DETAIL_CVT_3BYTE 0xf8 148#define EDID_DETAIL_COLOR_MGMT_DATA 0xf9 149#define EDID_DETAIL_STD_MODES 0xfa 150#define EDID_DETAIL_MONITOR_CPDATA 0xfb 151#define EDID_DETAIL_MONITOR_NAME 0xfc 152#define EDID_DETAIL_MONITOR_RANGE 0xfd 153#define EDID_DETAIL_MONITOR_STRING 0xfe 154#define EDID_DETAIL_MONITOR_SERIAL 0xff 155 156struct detailed_timing { 157 __le16 pixel_clock; /* need to multiply by 10 KHz */ 158 union { 159 struct detailed_pixel_timing pixel_data; 160 struct detailed_non_pixel other_data; 161 } data; 162} __attribute__((packed)); 163 164#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0) 165#define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1) 166#define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2) 167#define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3) 168#define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4) 169#define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5) 170#define DRM_EDID_INPUT_DIGITAL (1 << 7) 171#define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) 172#define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) 173#define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) 174#define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) 175#define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) 176#define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) 177#define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) 178#define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) 179#define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) 180#define DRM_EDID_DIGITAL_TYPE_UNDEF (0) 181#define DRM_EDID_DIGITAL_TYPE_DVI (1) 182#define DRM_EDID_DIGITAL_TYPE_HDMI_A (2) 183#define DRM_EDID_DIGITAL_TYPE_HDMI_B (3) 184#define DRM_EDID_DIGITAL_TYPE_MDDI (4) 185#define DRM_EDID_DIGITAL_TYPE_DP (5) 186 187#define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0) 188#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1) 189#define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2) 190/* If analog */ 191#define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */ 192/* If digital */ 193#define DRM_EDID_FEATURE_COLOR_MASK (3 << 3) 194#define DRM_EDID_FEATURE_RGB (0 << 3) 195#define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3) 196#define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3) 197#define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */ 198 199#define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5) 200#define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6) 201#define DRM_EDID_FEATURE_PM_STANDBY (1 << 7) 202 203struct edid { 204 u8 header[8]; 205 /* Vendor & product info */ 206 u8 mfg_id[2]; 207 u8 prod_code[2]; 208 u32 serial; /* FIXME: byte order */ 209 u8 mfg_week; 210 u8 mfg_year; 211 /* EDID version */ 212 u8 version; 213 u8 revision; 214 /* Display info: */ 215 u8 input; 216 u8 width_cm; 217 u8 height_cm; 218 u8 gamma; 219 u8 features; 220 /* Color characteristics */ 221 u8 red_green_lo; 222 u8 black_white_lo; 223 u8 red_x; 224 u8 red_y; 225 u8 green_x; 226 u8 green_y; 227 u8 blue_x; 228 u8 blue_y; 229 u8 white_x; 230 u8 white_y; 231 /* Est. timings and mfg rsvd timings*/ 232 struct est_timings established_timings; 233 /* Standard timings 1-8*/ 234 struct std_timing standard_timings[8]; 235 /* Detailing timings 1-4 */ 236 struct detailed_timing detailed_timings[4]; 237 /* Number of 128 byte ext. blocks */ 238 u8 extensions; 239 /* Checksum */ 240 u8 checksum; 241} __attribute__((packed)); 242 243#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 244 245struct drm_encoder; 246struct drm_connector; 247struct drm_display_mode; 248void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid); 249int drm_av_sync_delay(struct drm_connector *connector, 250 struct drm_display_mode *mode); 251struct drm_connector *drm_select_eld(struct drm_encoder *encoder, 252 struct drm_display_mode *mode); 253int drm_load_edid_firmware(struct drm_connector *connector); 254 255#endif /* __DRM_EDID_H__ */ 256