1/*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org> 5 * Copyright (C) 2010, Broadcom Corporation. 6 * All rights reserved. 7 * 8 * This file is derived from the hndpmu.h header contributed by Broadcom 9 * to to the Linux staging repository, as well as later revisions of hndpmu.h 10 * distributed with the Asus RT-N16 firmware source code release. 11 * 12 * Permission to use, copy, modify, and/or distribute this software for any 13 * purpose with or without fee is hereby granted, provided that the above 14 * copyright notice and this permission notice appear in all copies. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 17 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 19 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 20 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 21 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 22 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 23 * 24 */ 25 26#ifndef _BHND_CORES_PMU_BHND_PMU_PRIVATE_H_ 27#define _BHND_CORES_PMU_BHND_PMU_PRIVATE_H_ 28 29#include <sys/types.h> 30 31#include "bhnd_pmuvar.h" 32 33/* Register I/O */ 34#define BHND_PMU_READ_4(_sc, _reg) (_sc)->io->rd4((_reg), (_sc)->io_ctx) 35#define BHND_PMU_WRITE_4(_sc, _reg, _val) \ 36 (_sc)->io->wr4((_reg), (_val), (_sc)->io_ctx) 37 38#define BHND_PMU_AND_4(_sc, _reg, _val) \ 39 BHND_PMU_WRITE_4((_sc), (_reg), \ 40 BHND_PMU_READ_4((_sc), (_reg)) & (_val)) 41#define BHND_PMU_OR_4(_sc, _reg, _val) \ 42 BHND_PMU_WRITE_4((_sc), (_reg), \ 43 BHND_PMU_READ_4((_sc), (_reg)) | (_val)) 44 45/* Indirect register support */ 46#define BHND_PMU_IND_READ(_sc, _src, _reg) \ 47 bhnd_pmu_ind_read((_sc)->io, (_sc)->io_ctx, \ 48 BHND_PMU_ ## _src ## _ADDR, BHND_PMU_ ## _src ## _DATA, (_reg)) 49#define BHND_PMU_IND_WRITE(_sc, _src, _reg, _val, _mask) \ 50 bhnd_pmu_ind_write((_sc)->io, (_sc)->io_ctx, \ 51 BHND_PMU_ ## _src ## _ADDR, \ 52 BHND_PMU_ ## _src ## _DATA, (_reg), (_val), (_mask)) 53 54/* Chip Control indirect registers */ 55#define BHND_PMU_CCTRL_READ(_sc, _reg) \ 56 BHND_PMU_IND_READ((_sc), CHIP_CONTROL, (_reg)) 57#define BHND_PMU_CCTRL_WRITE(_sc, _reg, _val, _mask) \ 58 BHND_PMU_IND_WRITE((_sc), CHIP_CONTROL, (_reg), (_val), (_mask)) 59 60/* Regulator Control indirect registers */ 61#define BHND_PMU_REGCTRL_READ(_sc, _reg) \ 62 BHND_PMU_IND_READ((_sc), REG_CONTROL, (_reg)) 63#define BHND_PMU_REGCTRL_WRITE(_sc, _reg, _val, _mask) \ 64 BHND_PMU_IND_WRITE((_sc), REG_CONTROL, (_reg), (_val), (_mask)) 65 66/* PLL Control indirect registers */ 67#define BHND_PMU_PLL_READ(_sc, _reg) \ 68 BHND_PMU_IND_READ((_sc), PLL_CONTROL, (_reg)) 69#define BHND_PMU_PLL_WRITE(_sc, _reg, _val, _mask) \ 70 BHND_PMU_IND_WRITE((_sc), PLL_CONTROL, (_reg), (_val), (_mask)) 71 72/** FVCO frequencies, in Hz */ 73enum { 74 FVCO_880 = 880 * 1000, /**< 880MHz */ 75 FVCO_1760 = 1760 * 1000, /**< 1760MHz */ 76 FVCO_1440 = 1440 * 1000, /**< 1440MHz */ 77 FVCO_960 = 960 * 1000, /**< 960MHz */ 78}; 79 80/** LDO voltage tunables */ 81enum { 82 SET_LDO_VOLTAGE_LDO1 = 1, 83 SET_LDO_VOLTAGE_LDO2 = 2, 84 SET_LDO_VOLTAGE_LDO3 = 3, 85 SET_LDO_VOLTAGE_PAREF = 4, 86 SET_LDO_VOLTAGE_CLDO_PWM = 5, 87 SET_LDO_VOLTAGE_CLDO_BURST = 6, 88 SET_LDO_VOLTAGE_CBUCK_PWM = 7, 89 SET_LDO_VOLTAGE_CBUCK_BURST = 8, 90 SET_LDO_VOLTAGE_LNLDO1 = 9, 91 SET_LDO_VOLTAGE_LNLDO2_SEL = 10, 92}; 93 94uint32_t bhnd_pmu_ind_read(const struct bhnd_pmu_io *io, void *io_ctx, 95 bus_size_t addr, bus_size_t data, uint32_t reg); 96void bhnd_pmu_ind_write(const struct bhnd_pmu_io *io, void *io_ctx, 97 bus_size_t addr, bus_size_t data, uint32_t reg, 98 uint32_t val, uint32_t mask); 99 100int bhnd_pmu_init(struct bhnd_pmu_softc *sc); 101void bhnd_pmu_pll_init(struct bhnd_pmu_softc *sc, uint32_t xtalfreq); 102int bhnd_pmu_res_init(struct bhnd_pmu_softc *sc); 103void bhnd_pmu_swreg_init(struct bhnd_pmu_softc *sc); 104 105uint32_t bhnd_pmu_force_ilp(struct bhnd_pmu_softc *sc, bool force); 106 107void bhnd_pmu_set_switcher_voltage(struct bhnd_pmu_softc *sc, 108 uint8_t bb_voltage, uint8_t rf_voltage); 109int bhnd_pmu_set_ldo_voltage(struct bhnd_pmu_softc *sc, 110 uint8_t ldo, uint8_t voltage); 111int bhnd_pmu_fast_pwrup_delay(struct bhnd_pmu_softc *sc, 112 u_int *pwrup_delay); 113void bhnd_pmu_rcal(struct bhnd_pmu_softc *sc); 114int bhnd_pmu_set_spuravoid(struct bhnd_pmu_softc *sc, 115 bhnd_pmu_spuravoid spuravoid); 116 117bool bhnd_pmu_is_otp_powered(struct bhnd_pmu_softc *sc); 118uint32_t bhnd_pmu_measure_alpclk(struct bhnd_pmu_softc *sc); 119 120int bhnd_pmu_radio_enable(struct bhnd_pmu_softc *sc, 121 device_t d11core, bool enable); 122 123uint32_t bhnd_pmu_waitforclk_on_backplane(struct bhnd_pmu_softc *sc, 124 uint32_t clk, uint32_t delay); 125 126int bhnd_pmu_otp_power(struct bhnd_pmu_softc *sc, bool on); 127void bhnd_pmu_sdiod_drive_strength_init(struct bhnd_pmu_softc *sc, 128 uint32_t drivestrength); 129 130int bhnd_pmu_paref_ldo_enable(struct bhnd_pmu_softc *sc, 131 bool enable); 132 133#endif /* _BHND_CORES_PMU_BHND_PMU_PRIVATE_H_ */ 134