1#-
2# Copyright (c) 2016 Landon Fuller <landon@landonf.org>
3# Copyright (c) 2017 The FreeBSD Foundation
4# All rights reserved.
5#
6# Portions of this software were developed by Landon Fuller
7# under sponsorship from the FreeBSD Foundation.
8#
9# Redistribution and use in source and binary forms, with or without
10# modification, are permitted provided that the following conditions
11# are met:
12# 1. Redistributions of source code must retain the above copyright
13#    notice, this list of conditions and the following disclaimer.
14# 2. Redistributions in binary form must reproduce the above copyright
15#    notice, this list of conditions and the following disclaimer in the
16#    documentation and/or other materials provided with the distribution.
17#
18# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21# IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
22# INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
23# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
25# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
27# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29
30#include <sys/types.h>
31#include <sys/bus.h>
32
33#include <dev/bhnd/bhnd.h>
34
35INTERFACE bhnd_pwrctl_hostb;
36
37#
38# bhnd(4) PWRCTL host bridge interface.
39#
40# Provides a common interface to the clock hardware managed by a parent host
41# bridge (e.g. bhndb_pci(4)).
42#
43# Early PWRCTL chipsets[1] expose clock management via their host bridge
44# interface, requiring that a host bridge driver (e.g. bhndb(4)) work in
45# tandem with the ChipCommon-attached PWRCTL driver.
46#
47# [1] Currently, this is known to include PCI (not PCIe) devices, with
48# ChipCommon core revisions 0-9.
49#
50
51HEADER {
52	#include <dev/bhnd/bhnd.h>
53};
54
55CODE {
56	static bhnd_clksrc
57	bhnd_pwrctl_hostb_get_clksrc(device_t dev, device_t child,
58	    bhnd_clock clock)
59	{
60		return (BHND_CLKSRC_UNKNOWN);
61	}
62
63	static int
64	bhnd_pwrctl_hostb_gate_clock(device_t dev, device_t child,
65	    bhnd_clock clock)
66	{
67		return (ENODEV);
68	}
69
70	static int
71	bhnd_pwrctl_hostb_ungate_clock(device_t dev, device_t child,
72	    bhnd_clock clock)
73	{
74		return (ENODEV);
75	}
76
77};
78
79/**
80 * If supported by the chipset, return the clock source for the given clock.
81 *
82 * @param dev	The parent of @p child.
83 * @param child	The bhnd device requesting a clock source.
84 * @param clock	The clock for which a clock source will be returned.
85 *
86 * @retval	bhnd_clksrc		The clock source for @p clock.
87 * @retval	BHND_CLKSRC_UNKNOWN	If @p clock is unsupported, or its
88 *					clock source is not known to the bus.
89 */
90METHOD bhnd_clksrc get_clksrc {
91	device_t	dev;
92	device_t	child;
93	bhnd_clock	clock;
94} DEFAULT bhnd_pwrctl_hostb_get_clksrc;
95
96/**
97 * If supported by the chipset, gate the clock source for @p clock.
98 *
99 * @param dev	The parent of @p child.
100 * @param child	The bhnd device requesting clock gating.
101 * @param clock	The clock to be disabled.
102 *
103 * @retval 0		success
104 * @retval ENODEV	If bus-level clock source management is not supported.
105 * @retval ENXIO	If bus-level management of @p clock is not supported.
106 */
107METHOD int gate_clock {
108	device_t	dev;
109	device_t	child;
110	bhnd_clock	clock;
111} DEFAULT bhnd_pwrctl_hostb_gate_clock;
112
113/**
114 * If supported by the chipset, ungate the clock source for @p clock.
115 *
116 * @param dev	The parent of @p child.
117 * @param child	The bhnd device requesting clock gating.
118 * @param clock	The clock to be enabled.
119 *
120 * @retval 0		success
121 * @retval ENODEV	If bus-level clock source management is not supported.
122 * @retval ENXIO	If bus-level management of @p clock is not supported.
123 */
124METHOD int ungate_clock {
125	device_t	dev;
126	device_t	child;
127	bhnd_clock	clock;
128} DEFAULT bhnd_pwrctl_hostb_ungate_clock;