1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 18 * NO WARRANTY 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGES. 30 */ 31 32/* 33 * Defintions for the Atheros Wireless LAN controller driver. 34 */ 35#ifndef _DEV_ATH_ATHVAR_H 36#define _DEV_ATH_ATHVAR_H 37 38#include <machine/atomic.h> 39 40#include <dev/ath/ath_hal/ah.h> 41#include <dev/ath/ath_hal/ah_desc.h> 42#include <net80211/ieee80211_radiotap.h> 43#include <dev/ath/if_athioctl.h> 44#include <dev/ath/if_athrate.h> 45#ifdef ATH_DEBUG_ALQ 46#include <dev/ath/if_ath_alq.h> 47#endif 48 49#define ATH_TIMEOUT 1000 50 51/* 52 * There is a separate TX ath_buf pool for management frames. 53 * This ensures that management frames such as probe responses 54 * and BAR frames can be transmitted during periods of high 55 * TX activity. 56 */ 57#define ATH_MGMT_TXBUF 32 58 59/* 60 * 802.11n requires more TX and RX buffers to do AMPDU. 61 */ 62#define ATH_ENABLE_11N /* 802.11n support for AR5416 and later */ 63#ifdef ATH_ENABLE_11N 64#define ATH_TXBUF 512 65#define ATH_RXBUF 512 66#endif 67 68#ifndef ATH_RXBUF 69#define ATH_RXBUF 40 /* number of RX buffers */ 70#endif 71#ifndef ATH_TXBUF 72#define ATH_TXBUF 200 /* number of TX buffers */ 73#endif 74#define ATH_BCBUF 4 /* number of beacon buffers */ 75 76#define ATH_TXDESC 10 /* number of descriptors per buffer */ 77#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 78#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 79#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 80 81#define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 82#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 83#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 84 85/* 86 * The following bits can be set during the PCI (and perhaps non-PCI 87 * later) device probe path. 88 * 89 * It controls some of the driver and HAL behaviour. 90 */ 91 92#define ATH_PCI_CUS198 0x0001 93#define ATH_PCI_CUS230 0x0002 94#define ATH_PCI_CUS217 0x0004 95#define ATH_PCI_CUS252 0x0008 96#define ATH_PCI_WOW 0x0010 97#define ATH_PCI_BT_ANT_DIV 0x0020 98#define ATH_PCI_D3_L1_WAR 0x0040 99#define ATH_PCI_AR9565_1ANT 0x0080 100#define ATH_PCI_AR9565_2ANT 0x0100 101#define ATH_PCI_NO_PLL_PWRSAVE 0x0200 102#define ATH_PCI_KILLER 0x0400 103 104/* 105 * The key cache is used for h/w cipher state and also for 106 * tracking station state such as the current tx antenna. 107 * We also setup a mapping table between key cache slot indices 108 * and station state to short-circuit node lookups on rx. 109 * Different parts have different size key caches. We handle 110 * up to ATH_KEYMAX entries (could dynamically allocate state). 111 */ 112#define ATH_KEYMAX 128 /* max key cache size we handle */ 113#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 114 115struct taskqueue; 116struct kthread; 117struct ath_buf; 118 119#define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 120 121/* 122 * Per-TID state 123 * 124 * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 125 */ 126struct ath_tid { 127 TAILQ_HEAD(,ath_buf) tid_q; /* pending buffers */ 128 struct ath_node *an; /* pointer to parent */ 129 int tid; /* tid */ 130 int ac; /* which AC gets this traffic */ 131 int hwq_depth; /* how many buffers are on HW */ 132 u_int axq_depth; /* SW queue depth */ 133 134 struct { 135 TAILQ_HEAD(,ath_buf) tid_q; /* filtered queue */ 136 u_int axq_depth; /* SW queue depth */ 137 } filtq; 138 139 /* 140 * Entry on the ath_txq; when there's traffic 141 * to send 142 */ 143 TAILQ_ENTRY(ath_tid) axq_qelem; 144 int sched; 145 int paused; /* >0 if the TID has been paused */ 146 147 /* 148 * These are flags - perhaps later collapse 149 * down to a single uint32_t ? 150 */ 151 int addba_tx_pending; /* TX ADDBA pending */ 152 int bar_wait; /* waiting for BAR */ 153 int bar_tx; /* BAR TXed */ 154 int isfiltered; /* is this node currently filtered */ 155 156 /* 157 * Is the TID being cleaned up after a transition 158 * from aggregation to non-aggregation? 159 * When this is set to 1, this TID will be paused 160 * and no further traffic will be queued until all 161 * the hardware packets pending for this TID have been 162 * TXed/completed; at which point (non-aggregation) 163 * traffic will resume being TXed. 164 */ 165 int cleanup_inprogress; 166 /* 167 * How many hardware-queued packets are 168 * waiting to be cleaned up. 169 * This is only valid if cleanup_inprogress is 1. 170 */ 171 int incomp; 172 173 /* 174 * The following implements a ring representing 175 * the frames in the current BAW. 176 * To avoid copying the array content each time 177 * the BAW is moved, the baw_head/baw_tail point 178 * to the current BAW begin/end; when the BAW is 179 * shifted the head/tail of the array are also 180 * appropriately shifted. 181 */ 182 /* active tx buffers, beginning at current BAW */ 183 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 184 /* where the baw head is in the array */ 185 int baw_head; 186 /* where the BAW tail is in the array */ 187 int baw_tail; 188}; 189 190/* driver-specific node state */ 191struct ath_node { 192 struct ieee80211_node an_node; /* base class */ 193 u_int8_t an_mgmtrix; /* min h/w rate index */ 194 u_int8_t an_mcastrix; /* mcast h/w rate index */ 195 uint32_t an_is_powersave; /* node is sleeping */ 196 uint32_t an_stack_psq; /* net80211 psq isn't empty */ 197 uint32_t an_tim_set; /* TIM has been set */ 198 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 199 struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 200 char an_name[32]; /* eg "wlan0_a1" */ 201 struct mtx an_mtx; /* protecting the rate control state */ 202 uint32_t an_swq_depth; /* how many SWQ packets for this 203 node */ 204 int clrdmask; /* has clrdmask been set */ 205 uint32_t an_leak_count; /* How many frames to leak during pause */ 206 HAL_NODE_STATS an_node_stats; /* HAL node stats for this node */ 207 /* variable-length rate control state follows */ 208}; 209#define ATH_NODE(ni) ((struct ath_node *)(ni)) 210#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 211 212#define ATH_RSSI_LPF_LEN 10 213#define ATH_RSSI_DUMMY_MARKER 0x127 214#define ATH_EP_MUL(x, mul) ((x) * (mul)) 215#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 216#define ATH_LPF_RSSI(x, y, len) \ 217 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 218#define ATH_RSSI_LPF(x, y) do { \ 219 if ((y) >= -20) \ 220 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 221} while (0) 222#define ATH_EP_RND(x,mul) \ 223 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 224#define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 225 226typedef enum { 227 ATH_BUFTYPE_NORMAL = 0, 228 ATH_BUFTYPE_MGMT = 1, 229} ath_buf_type_t; 230 231struct ath_buf { 232 TAILQ_ENTRY(ath_buf) bf_list; 233 struct ath_buf * bf_next; /* next buffer in the aggregate */ 234 int bf_nseg; 235 HAL_STATUS bf_rxstatus; 236 uint16_t bf_flags; /* status flags (below) */ 237 uint16_t bf_descid; /* 16 bit descriptor ID */ 238 struct ath_desc *bf_desc; /* virtual addr of desc */ 239 struct ath_desc_status bf_status; /* tx/rx status */ 240 bus_addr_t bf_daddr; /* physical addr of desc */ 241 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 242 struct mbuf *bf_m; /* mbuf for buf */ 243 struct ieee80211_node *bf_node; /* pointer to the node */ 244 struct ath_desc *bf_lastds; /* last descriptor for comp status */ 245 struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 246 bus_size_t bf_mapsize; 247#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 248 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 249 uint32_t bf_nextfraglen; /* length of next fragment */ 250 251 /* Completion function to call on TX complete (fail or not) */ 252 /* 253 * "fail" here is set to 1 if the queue entries were removed 254 * through a call to ath_tx_draintxq(). 255 */ 256 void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 257 258 /* This state is kept to support software retries and aggregation */ 259 struct { 260 uint16_t bfs_seqno; /* sequence number of this packet */ 261 uint16_t bfs_ndelim; /* number of delims for padding */ 262 263 uint8_t bfs_retries; /* retry count */ 264 uint8_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 265 uint8_t bfs_nframes; /* number of frames in aggregate */ 266 uint8_t bfs_pri; /* packet AC priority */ 267 uint8_t bfs_tx_queue; /* destination hardware TX queue */ 268 269 u_int32_t bfs_aggr:1, /* part of aggregate? */ 270 bfs_aggrburst:1, /* part of aggregate burst? */ 271 bfs_isretried:1, /* retried frame? */ 272 bfs_dobaw:1, /* actually check against BAW? */ 273 bfs_addedbaw:1, /* has been added to the BAW */ 274 bfs_shpream:1, /* use short preamble */ 275 bfs_istxfrag:1, /* is fragmented */ 276 bfs_ismrr:1, /* do multi-rate TX retry */ 277 bfs_doprot:1, /* do RTS/CTS based protection */ 278 bfs_doratelookup:1; /* do rate lookup before each TX */ 279 280 /* 281 * These fields are passed into the 282 * descriptor setup functions. 283 */ 284 285 /* Make this an 8 bit value? */ 286 HAL_PKT_TYPE bfs_atype; /* packet type */ 287 288 uint32_t bfs_pktlen; /* length of this packet */ 289 290 uint16_t bfs_hdrlen; /* length of this packet header */ 291 uint16_t bfs_al; /* length of aggregate */ 292 293 uint16_t bfs_txflags; /* HAL (tx) descriptor flags */ 294 uint8_t bfs_txrate0; /* first TX rate */ 295 uint8_t bfs_try0; /* first try count */ 296 297 uint16_t bfs_txpower; /* tx power */ 298 uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 299 uint8_t bfs_ctsrate; /* CTS rate */ 300 301 /* 16 bit? */ 302 int32_t bfs_keyix; /* crypto key index */ 303 int32_t bfs_txantenna; /* TX antenna config */ 304 305 /* Make this an 8 bit value? */ 306 enum ieee80211_protmode bfs_protmode; 307 308 /* 16 bit? */ 309 uint32_t bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 310 int32_t bfs_rc_maxpktlen; /* max packet length/bucket from ratectrl or -1 */ 311 struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 312 } bf_state; 313}; 314typedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 315 316#define ATH_BUF_MGMT 0x00000001 /* (tx) desc is a mgmt desc */ 317#define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 318#define ATH_BUF_FIFOEND 0x00000004 319#define ATH_BUF_FIFOPTR 0x00000008 320#define ATH_BUF_TOA_PROBE 0x00000010 /* ToD/ToA exchange probe */ 321 322#define ATH_BUF_FLAGS_CLONE (ATH_BUF_MGMT | ATH_BUF_TOA_PROBE) 323 324/* 325 * DMA state for tx/rx descriptors. 326 */ 327struct ath_descdma { 328 const char* dd_name; 329 struct ath_desc *dd_desc; /* descriptors */ 330 int dd_descsize; /* size of single descriptor */ 331 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 332 bus_size_t dd_desc_len; /* size of dd_desc */ 333 bus_dma_segment_t dd_dseg; 334 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 335 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 336 struct ath_buf *dd_bufptr; /* associated buffers */ 337}; 338 339/* 340 * Data transmit queue state. One of these exists for each 341 * hardware transmit queue. Packets sent to us from above 342 * are assigned to queues based on their priority. Not all 343 * devices support a complete set of hardware transmit queues. 344 * For those devices the array sc_ac2q will map multiple 345 * priorities to fewer hardware queues (typically all to one 346 * hardware queue). 347 */ 348struct ath_txq { 349 struct ath_softc *axq_softc; /* Needed for scheduling */ 350 u_int axq_qnum; /* hardware q number */ 351#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 352 u_int axq_ac; /* WME AC */ 353 u_int axq_flags; 354//#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 355#define ATH_TXQ_PUTRUNNING 0x0002 /* ath_hal_puttxbuf has been called */ 356 u_int axq_depth; /* queue depth (stat only) */ 357 u_int axq_aggr_depth; /* how many aggregates are queued */ 358 u_int axq_intrcnt; /* interrupt count */ 359 u_int32_t *axq_link; /* link ptr in last TX desc */ 360 TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 361 struct mtx axq_lock; /* lock on q and link */ 362 363 /* 364 * This is the FIFO staging buffer when doing EDMA. 365 * 366 * For legacy chips, we just push the head pointer to 367 * the hardware and we ignore this list. 368 * 369 * For EDMA, the staging buffer is treated as normal; 370 * when it's time to push a list of frames to the hardware 371 * we move that list here and we stamp buffers with 372 * flags to identify the beginning/end of that particular 373 * FIFO entry. 374 */ 375 struct { 376 TAILQ_HEAD(axq_q_f_s, ath_buf) axq_q; 377 u_int axq_depth; /* how many frames (1 per legacy, 1 per A-MPDU list) are in the FIFO queue */ 378 } fifo; 379 u_int axq_fifo_depth; /* how many FIFO slots are active */ 380 381 /* 382 * XXX the holdingbf field is protected by the TXBUF lock 383 * for now, NOT the TXQ lock. 384 * 385 * Architecturally, it would likely be better to move 386 * the holdingbf field to a separate array in ath_softc 387 * just to highlight that it's not protected by the normal 388 * TX path lock. 389 */ 390 struct ath_buf *axq_holdingbf; /* holding TX buffer */ 391 char axq_name[12]; /* e.g. "ath0_txq4" */ 392 393 /* Per-TID traffic queue for software -> hardware TX */ 394 /* 395 * This is protected by the general TX path lock, not (for now) 396 * by the TXQ lock. 397 */ 398 TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 399}; 400 401#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 402 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 403 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 404 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 405 } while (0) 406#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 407#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 408#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 409#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 410#define ATH_TXQ_UNLOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, \ 411 MA_NOTOWNED) 412 413#define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx) 414#define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx) 415#define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED) 416#define ATH_NODE_UNLOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, \ 417 MA_NOTOWNED) 418 419/* 420 * These are for the hardware queue. 421 */ 422#define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 423 TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 424 (_tq)->axq_depth++; \ 425} while (0) 426#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 427 TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 428 (_tq)->axq_depth++; \ 429} while (0) 430#define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 431 TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 432 (_tq)->axq_depth--; \ 433} while (0) 434#define ATH_TXQ_FIRST(_tq) TAILQ_FIRST(&(_tq)->axq_q) 435#define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 436 437/* 438 * These are for the TID software queue. 439 */ 440#define ATH_TID_INSERT_HEAD(_tq, _elm, _field) do { \ 441 TAILQ_INSERT_HEAD(&(_tq)->tid_q, (_elm), _field); \ 442 (_tq)->axq_depth++; \ 443 (_tq)->an->an_swq_depth++; \ 444} while (0) 445#define ATH_TID_INSERT_TAIL(_tq, _elm, _field) do { \ 446 TAILQ_INSERT_TAIL(&(_tq)->tid_q, (_elm), _field); \ 447 (_tq)->axq_depth++; \ 448 (_tq)->an->an_swq_depth++; \ 449} while (0) 450#define ATH_TID_REMOVE(_tq, _elm, _field) do { \ 451 TAILQ_REMOVE(&(_tq)->tid_q, _elm, _field); \ 452 (_tq)->axq_depth--; \ 453 (_tq)->an->an_swq_depth--; \ 454} while (0) 455#define ATH_TID_FIRST(_tq) TAILQ_FIRST(&(_tq)->tid_q) 456#define ATH_TID_LAST(_tq, _field) TAILQ_LAST(&(_tq)->tid_q, _field) 457 458/* 459 * These are for the TID filtered frame queue 460 */ 461#define ATH_TID_FILT_INSERT_HEAD(_tq, _elm, _field) do { \ 462 TAILQ_INSERT_HEAD(&(_tq)->filtq.tid_q, (_elm), _field); \ 463 (_tq)->axq_depth++; \ 464 (_tq)->an->an_swq_depth++; \ 465} while (0) 466#define ATH_TID_FILT_INSERT_TAIL(_tq, _elm, _field) do { \ 467 TAILQ_INSERT_TAIL(&(_tq)->filtq.tid_q, (_elm), _field); \ 468 (_tq)->axq_depth++; \ 469 (_tq)->an->an_swq_depth++; \ 470} while (0) 471#define ATH_TID_FILT_REMOVE(_tq, _elm, _field) do { \ 472 TAILQ_REMOVE(&(_tq)->filtq.tid_q, _elm, _field); \ 473 (_tq)->axq_depth--; \ 474 (_tq)->an->an_swq_depth--; \ 475} while (0) 476#define ATH_TID_FILT_FIRST(_tq) TAILQ_FIRST(&(_tq)->filtq.tid_q) 477#define ATH_TID_FILT_LAST(_tq, _field) TAILQ_LAST(&(_tq)->filtq.tid_q,_field) 478 479struct ath_vap { 480 struct ieee80211vap av_vap; /* base class */ 481 int av_bslot; /* beacon slot index */ 482 struct ath_buf *av_bcbuf; /* beacon buffer */ 483 struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 484 485 void (*av_recv_mgmt)(struct ieee80211_node *, 486 struct mbuf *, int, 487 const struct ieee80211_rx_stats *, int, int); 488 int (*av_newstate)(struct ieee80211vap *, 489 enum ieee80211_state, int); 490 void (*av_bmiss)(struct ieee80211vap *); 491 void (*av_node_ps)(struct ieee80211_node *, int); 492 int (*av_set_tim)(struct ieee80211_node *, int); 493 void (*av_recv_pspoll)(struct ieee80211_node *, 494 struct mbuf *); 495 struct ieee80211_quiet_ie quiet_ie; 496}; 497#define ATH_VAP(vap) ((struct ath_vap *)(vap)) 498 499struct taskqueue; 500struct ath_tx99; 501 502/* 503 * Whether to reset the TX/RX queue with or without 504 * a queue flush. 505 */ 506typedef enum { 507 ATH_RESET_DEFAULT = 0, 508 ATH_RESET_NOLOSS = 1, 509 ATH_RESET_FULL = 2, 510} ATH_RESET_TYPE; 511 512struct ath_rx_methods { 513 void (*recv_sched_queue)(struct ath_softc *sc, 514 HAL_RX_QUEUE q, int dosched); 515 void (*recv_sched)(struct ath_softc *sc, int dosched); 516 void (*recv_stop)(struct ath_softc *sc, int dodelay); 517 int (*recv_start)(struct ath_softc *sc); 518 void (*recv_flush)(struct ath_softc *sc); 519 void (*recv_tasklet)(void *arg, int npending); 520 int (*recv_rxbuf_init)(struct ath_softc *sc, 521 struct ath_buf *bf); 522 int (*recv_setup)(struct ath_softc *sc); 523 int (*recv_teardown)(struct ath_softc *sc); 524}; 525 526/* 527 * Represent the current state of the RX FIFO. 528 */ 529struct ath_rx_edma { 530 struct ath_buf **m_fifo; 531 int m_fifolen; 532 int m_fifo_head; 533 int m_fifo_tail; 534 int m_fifo_depth; 535 struct mbuf *m_rxpending; 536 struct ath_buf *m_holdbf; 537}; 538 539struct ath_tx_edma_fifo { 540 struct ath_buf **m_fifo; 541 int m_fifolen; 542 int m_fifo_head; 543 int m_fifo_tail; 544 int m_fifo_depth; 545}; 546 547struct ath_tx_methods { 548 int (*xmit_setup)(struct ath_softc *sc); 549 int (*xmit_teardown)(struct ath_softc *sc); 550 void (*xmit_attach_comp_func)(struct ath_softc *sc); 551 552 void (*xmit_dma_restart)(struct ath_softc *sc, 553 struct ath_txq *txq); 554 void (*xmit_handoff)(struct ath_softc *sc, 555 struct ath_txq *txq, struct ath_buf *bf); 556 void (*xmit_drain)(struct ath_softc *sc, 557 ATH_RESET_TYPE reset_type); 558}; 559 560struct ath_softc { 561 struct ieee80211com sc_ic; 562 struct ath_stats sc_stats; /* device statistics */ 563 struct ath_tx_aggr_stats sc_aggr_stats; 564 struct ath_intr_stats sc_intr_stats; 565 uint64_t sc_debug; 566 uint64_t sc_ktrdebug; 567 int sc_nvaps; /* # vaps */ 568 int sc_nstavaps; /* # station vaps */ 569 int sc_nmeshvaps; /* # mbss vaps */ 570 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 571 u_int8_t sc_nbssid0; /* # vap's using base mac */ 572 uint32_t sc_bssidmask; /* bssid mask */ 573 574 struct ath_rx_methods sc_rx; 575 struct ath_rx_edma sc_rxedma[HAL_NUM_RX_QUEUES]; /* HP/LP queues */ 576 ath_bufhead sc_rx_rxlist[HAL_NUM_RX_QUEUES]; /* deferred RX completion */ 577 struct ath_tx_methods sc_tx; 578 struct ath_tx_edma_fifo sc_txedma[HAL_NUM_TX_QUEUES]; 579 580 /* 581 * This is (currently) protected by the TX queue lock; 582 * it should migrate to a separate lock later 583 * so as to minimise contention. 584 */ 585 ath_bufhead sc_txbuf_list; 586 587 int sc_rx_statuslen; 588 int sc_tx_desclen; 589 int sc_tx_statuslen; 590 int sc_tx_nmaps; /* Number of TX maps */ 591 int sc_edma_bufsize; 592 int sc_rx_stopped; /* XXX only for EDMA */ 593 int sc_rx_resetted; /* XXX only for EDMA */ 594 595 void (*sc_node_cleanup)(struct ieee80211_node *); 596 void (*sc_node_free)(struct ieee80211_node *); 597 device_t sc_dev; 598 HAL_BUS_TAG sc_st; /* bus space tag */ 599 HAL_BUS_HANDLE sc_sh; /* bus space handle */ 600 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 601 struct mtx sc_mtx; /* master lock (recursive) */ 602 struct mtx sc_pcu_mtx; /* PCU access mutex */ 603 char sc_pcu_mtx_name[32]; 604 struct mtx sc_rx_mtx; /* RX access mutex */ 605 char sc_rx_mtx_name[32]; 606 struct mtx sc_tx_mtx; /* TX handling/comp mutex */ 607 char sc_tx_mtx_name[32]; 608 struct mtx sc_tx_ic_mtx; /* TX queue mutex */ 609 char sc_tx_ic_mtx_name[32]; 610 struct taskqueue *sc_tq; /* private task queue */ 611 struct ath_hal *sc_ah; /* Atheros HAL */ 612 struct ath_ratectrl *sc_rc; /* tx rate control support */ 613 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 614 void (*sc_setdefantenna)(struct ath_softc *, u_int); 615 616 /* 617 * First set of flags. 618 */ 619 uint32_t sc_invalid : 1,/* disable hardware accesses */ 620 sc_mrretry : 1,/* multi-rate retry support */ 621 sc_mrrprot : 1,/* MRR + protection support */ 622 sc_softled : 1,/* enable LED gpio status */ 623 sc_hardled : 1,/* enable MAC LED status */ 624 sc_splitmic : 1,/* split TKIP MIC keys */ 625 sc_needmib : 1,/* enable MIB stats intr */ 626 sc_diversity: 1,/* enable rx diversity */ 627 sc_hasveol : 1,/* tx VEOL support */ 628 sc_ledstate : 1,/* LED on/off state */ 629 sc_blinking : 1,/* LED blink operation active */ 630 sc_mcastkey : 1,/* mcast key cache search */ 631 sc_scanning : 1,/* scanning active */ 632 sc_syncbeacon:1,/* sync/resync beacon timers */ 633 sc_hasclrkey: 1,/* CLR key supported */ 634 sc_xchanmode: 1,/* extended channel mode */ 635 sc_outdoor : 1,/* outdoor operation */ 636 sc_dturbo : 1,/* dynamic turbo in use */ 637 sc_hasbmask : 1,/* bssid mask support */ 638 sc_hasbmatch: 1,/* bssid match disable support*/ 639 sc_hastsfadd: 1,/* tsf adjust support */ 640 sc_beacons : 1,/* beacons running */ 641 sc_swbmiss : 1,/* sta mode using sw bmiss */ 642 sc_stagbeacons:1,/* use staggered beacons */ 643 sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 644 sc_resume_up: 1,/* on resume, start all vaps */ 645 sc_tdma : 1,/* TDMA in use */ 646 sc_setcca : 1,/* set/clr CCA with TDMA */ 647 sc_resetcal : 1,/* reset cal state next trip */ 648 sc_rxslink : 1,/* do self-linked final descriptor */ 649 sc_rxtsf32 : 1,/* RX dec TSF is 32 bits */ 650 sc_isedma : 1,/* supports EDMA */ 651 sc_do_mybeacon : 1; /* supports mybeacon */ 652 653 /* 654 * Second set of flags. 655 */ 656 u_int32_t sc_running : 1, /* initialized */ 657 sc_use_ent : 1, 658 sc_rx_stbc : 1, 659 sc_tx_stbc : 1, 660 sc_has_ldpc : 1, 661 sc_hasenforcetxop : 1, /* support enforce TxOP */ 662 sc_hasdivcomb : 1, /* RX diversity combining */ 663 sc_rx_lnamixer : 1, /* RX using LNA mixing */ 664 sc_btcoex_mci : 1; /* MCI bluetooth coex */ 665 666 int sc_cabq_enable; /* Enable cabq transmission */ 667 668 /* 669 * Enterprise mode configuration for AR9380 and later chipsets. 670 */ 671 uint32_t sc_ent_cfg; 672 673 uint32_t sc_eerd; /* regdomain from EEPROM */ 674 uint32_t sc_eecc; /* country code from EEPROM */ 675 /* rate tables */ 676 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 677 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 678 enum ieee80211_phymode sc_curmode; /* current phy mode */ 679 HAL_OPMODE sc_opmode; /* current operating mode */ 680 u_int16_t sc_curtxpow; /* current tx power limit */ 681 u_int16_t sc_curaid; /* current association id */ 682 struct ieee80211_channel *sc_curchan; /* current installed channel */ 683 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 684 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 685 struct { 686 u_int8_t ieeerate; /* IEEE rate */ 687 u_int8_t rxflags; /* radiotap rx flags */ 688 u_int8_t txflags; /* radiotap tx flags */ 689 u_int16_t ledon; /* softled on time */ 690 u_int16_t ledoff; /* softled off time */ 691 } sc_hwmap[32]; /* h/w rate ix mappings */ 692 u_int8_t sc_protrix; /* protection rate index */ 693 u_int8_t sc_lastdatarix; /* last data frame rate index */ 694 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 695 u_int sc_fftxqmin; /* min frames before staging */ 696 u_int sc_fftxqmax; /* max frames before drop */ 697 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 698 699 HAL_INT sc_imask; /* interrupt mask copy */ 700 701 /* 702 * These are modified in the interrupt handler as well as 703 * the task queues and other contexts. Thus these must be 704 * protected by a mutex, or they could clash. 705 * 706 * For now, access to these is behind the ATH_LOCK, 707 * just to save time. 708 */ 709 uint32_t sc_txq_active; /* bitmap of active TXQs */ 710 uint32_t sc_kickpcu; /* whether to kick the PCU */ 711 uint32_t sc_rxproc_cnt; /* In RX processing */ 712 uint32_t sc_txproc_cnt; /* In TX processing */ 713 uint32_t sc_txstart_cnt; /* In TX output (raw/start) */ 714 uint32_t sc_inreset_cnt; /* In active reset/chanchange */ 715 uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */ 716 uint32_t sc_intr_cnt; /* refcount on interrupt handling */ 717 718 u_int sc_keymax; /* size of key cache */ 719 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 720 721 /* 722 * Software based LED blinking 723 */ 724 u_int sc_ledpin; /* GPIO pin for driving LED */ 725 u_int sc_ledon; /* pin setting for LED on */ 726 u_int sc_ledidle; /* idle polling interval */ 727 int sc_ledevent; /* time of last LED event */ 728 u_int8_t sc_txrix; /* current tx rate for LED */ 729 u_int16_t sc_ledoff; /* off time for current blink */ 730 struct callout sc_ledtimer; /* led off timer */ 731 732 /* 733 * Hardware based LED blinking 734 */ 735 int sc_led_pwr_pin; /* MAC power LED GPIO pin */ 736 int sc_led_net_pin; /* MAC network LED GPIO pin */ 737 738 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 739 u_int sc_rfsilentpol; /* pin setting for rfkill on */ 740 741 struct ath_descdma sc_rxdma; /* RX descriptors */ 742 ath_bufhead sc_rxbuf; /* receive buffer */ 743 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 744 struct task sc_rxtask; /* rx int processing */ 745 u_int8_t sc_defant; /* current default antenna */ 746 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 747 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 748 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 749 struct ath_rx_radiotap_header sc_rx_th; 750 int sc_rx_th_len; 751 u_int sc_monpass; /* frames to pass in mon.mode */ 752 753 struct ath_descdma sc_txdma; /* TX descriptors */ 754 uint16_t sc_txbuf_descid; 755 ath_bufhead sc_txbuf; /* transmit buffer */ 756 int sc_txbuf_cnt; /* how many buffers avail */ 757 struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */ 758 ath_bufhead sc_txbuf_mgmt; /* mgmt transmit buffer */ 759 struct ath_descdma sc_txsdma; /* EDMA TX status desc's */ 760 struct mtx sc_txbuflock; /* txbuf lock */ 761 char sc_txname[12]; /* e.g. "ath0_buf" */ 762 u_int sc_txqsetup; /* h/w queues setup */ 763 u_int sc_txintrperiod;/* tx interrupt batching */ 764 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 765 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 766 struct task sc_txtask; /* tx int processing */ 767 struct task sc_txqtask; /* tx proc processing */ 768 769 struct ath_descdma sc_txcompdma; /* TX EDMA completion */ 770 struct mtx sc_txcomplock; /* TX EDMA completion lock */ 771 char sc_txcompname[12]; /* eg ath0_txcomp */ 772 773 int sc_wd_timer; /* count down for wd timer */ 774 struct callout sc_wd_ch; /* tx watchdog timer */ 775 struct ath_tx_radiotap_header sc_tx_th; 776 int sc_tx_th_len; 777 778 struct ath_descdma sc_bdma; /* beacon descriptors */ 779 ath_bufhead sc_bbuf; /* beacon buffers */ 780 u_int sc_bhalq; /* HAL q for outgoing beacons */ 781 u_int sc_bmisscount; /* missed beacon transmits */ 782 u_int32_t sc_ant_tx[ATH_IOCTL_STATS_NUM_TX_ANTENNA]; 783 /* recent tx frames/antenna */ 784 struct ath_txq *sc_cabq; /* tx q for cab frames */ 785 struct task sc_bmisstask; /* bmiss int processing */ 786 struct task sc_tsfoortask; /* TSFOOR int processing */ 787 struct task sc_bstucktask; /* stuck beacon processing */ 788 struct task sc_resettask; /* interface reset task */ 789 struct task sc_fataltask; /* fatal task */ 790 enum { 791 OK, /* no change needed */ 792 UPDATE, /* update pending */ 793 COMMIT /* beacon sent, commit change */ 794 } sc_updateslot; /* slot time update fsm */ 795 int sc_slotupdate; /* slot to advance fsm */ 796 struct ieee80211vap *sc_bslot[ATH_BCBUF]; 797 int sc_nbcnvaps; /* # vaps with beacons */ 798 799 struct callout sc_cal_ch; /* callout handle for cals */ 800 int sc_lastlongcal; /* last long cal completed */ 801 int sc_lastcalreset;/* last cal reset done */ 802 int sc_lastani; /* last ANI poll */ 803 int sc_lastshortcal; /* last short calibration */ 804 HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 805 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 806 u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 807 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 808 u_int sc_tdmaswba; /* TDMA SWBA counter */ 809 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 810 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 811 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 812 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 813 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 814 uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 815 uint32_t sc_txchainmask; /* hardware TX chainmask */ 816 uint32_t sc_rxchainmask; /* hardware RX chainmask */ 817 uint32_t sc_cur_txchainmask; /* currently configured TX chainmask */ 818 uint32_t sc_cur_rxchainmask; /* currently configured RX chainmask */ 819 uint32_t sc_rts_aggr_limit; /* TX limit on RTS aggregates */ 820 int sc_aggr_limit; /* TX limit on all aggregates */ 821 int sc_delim_min_pad; /* Minimum delimiter count */ 822 823 /* Queue limits */ 824 825 /* 826 * To avoid queue starvation in congested conditions, 827 * these parameters tune the maximum number of frames 828 * queued to the data/mcastq before they're dropped. 829 * 830 * This is to prevent: 831 * + a single destination overwhelming everything, including 832 * management/multicast frames; 833 * + multicast frames overwhelming everything (when the 834 * air is sufficiently busy that cabq can't drain.) 835 * + A node in powersave shouldn't be allowed to exhaust 836 * all available mbufs; 837 * 838 * These implement: 839 * + data_minfree is the maximum number of free buffers 840 * overall to successfully allow a data frame. 841 * 842 * + mcastq_maxdepth is the maximum depth allowed of the cabq. 843 */ 844 int sc_txq_node_maxdepth; 845 int sc_txq_data_minfree; 846 int sc_txq_mcastq_maxdepth; 847 int sc_txq_node_psq_maxdepth; 848 849 /* 850 * Software queue twiddles 851 * 852 * hwq_limit_nonaggr: 853 * when to begin limiting non-aggregate frames to the 854 * hardware queue, regardless of the TID. 855 * hwq_limit_aggr: 856 * when to begin limiting A-MPDU frames to the 857 * hardware queue, regardless of the TID. 858 * tid_hwq_lo: how low the per-TID hwq count has to be before the 859 * TID will be scheduled again 860 * tid_hwq_hi: how many frames to queue to the HWQ before the TID 861 * stops being scheduled. 862 */ 863 int sc_hwq_limit_nonaggr; 864 int sc_hwq_limit_aggr; 865 int sc_tid_hwq_lo; 866 int sc_tid_hwq_hi; 867 868 /* DFS related state */ 869 void *sc_dfs; /* Used by an optional DFS module */ 870 int sc_dodfs; /* Whether to enable DFS rx filter bits */ 871 struct task sc_dfstask; /* DFS processing task */ 872 873 /* Spectral related state */ 874 void *sc_spectral; 875 int sc_dospectral; 876 877 /* LNA diversity related state */ 878 void *sc_lna_div; 879 int sc_dolnadiv; 880 881 /* ALQ */ 882#ifdef ATH_DEBUG_ALQ 883 struct if_ath_alq sc_alq; 884#endif 885 886 /* TX AMPDU handling */ 887 int (*sc_addba_request)(struct ieee80211_node *, 888 struct ieee80211_tx_ampdu *, int, int, int); 889 int (*sc_addba_response)(struct ieee80211_node *, 890 struct ieee80211_tx_ampdu *, int, int, int); 891 void (*sc_addba_stop)(struct ieee80211_node *, 892 struct ieee80211_tx_ampdu *); 893 void (*sc_addba_response_timeout) 894 (struct ieee80211_node *, 895 struct ieee80211_tx_ampdu *); 896 void (*sc_bar_response)(struct ieee80211_node *ni, 897 struct ieee80211_tx_ampdu *tap, 898 int status); 899 900 /* 901 * Powersave state tracking. 902 * 903 * target/cur powerstate is the chip power state. 904 * target selfgen state is the self-generated frames 905 * state. The chip can be awake but transmitted frames 906 * can have the PWRMGT bit set to 1 so the destination 907 * thinks the node is asleep. 908 */ 909 HAL_POWER_MODE sc_target_powerstate; 910 HAL_POWER_MODE sc_target_selfgen_state; 911 912 HAL_POWER_MODE sc_cur_powerstate; 913 914 int sc_powersave_refcnt; 915 916 /* ATH_PCI_* flags */ 917 uint32_t sc_pci_devinfo; 918 919 /* BT coex */ 920 struct { 921 struct ath_descdma buf; 922 923 /* gpm/sched buffer, saved pointers */ 924 char *sched_buf; 925 bus_addr_t sched_paddr; 926 char *gpm_buf; 927 bus_addr_t gpm_paddr; 928 929 uint32_t wlan_channels[4]; 930 } sc_btcoex; 931}; 932 933#define ATH_LOCK_INIT(_sc) \ 934 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 935 NULL, MTX_DEF | MTX_RECURSE) 936#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 937#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 938#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 939#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 940#define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 941 942/* 943 * The TX lock is non-reentrant and serialises the TX frame send 944 * and completion operations. 945 */ 946#define ATH_TX_LOCK_INIT(_sc) do {\ 947 snprintf((_sc)->sc_tx_mtx_name, \ 948 sizeof((_sc)->sc_tx_mtx_name), \ 949 "%s TX lock", \ 950 device_get_nameunit((_sc)->sc_dev)); \ 951 mtx_init(&(_sc)->sc_tx_mtx, (_sc)->sc_tx_mtx_name, \ 952 NULL, MTX_DEF); \ 953 } while (0) 954#define ATH_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_tx_mtx) 955#define ATH_TX_LOCK(_sc) mtx_lock(&(_sc)->sc_tx_mtx) 956#define ATH_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_tx_mtx) 957#define ATH_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_mtx, \ 958 MA_OWNED) 959#define ATH_TX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_mtx, \ 960 MA_NOTOWNED) 961#define ATH_TX_TRYLOCK(_sc) (mtx_owned(&(_sc)->sc_tx_mtx) != 0 && \ 962 mtx_trylock(&(_sc)->sc_tx_mtx)) 963 964/* 965 * The PCU lock is non-recursive and should be treated as a spinlock. 966 * Although currently the interrupt code is run in netisr context and 967 * doesn't require this, this may change in the future. 968 * Please keep this in mind when protecting certain code paths 969 * with the PCU lock. 970 * 971 * The PCU lock is used to serialise access to the PCU so things such 972 * as TX, RX, state change (eg channel change), channel reset and updates 973 * from interrupt context (eg kickpcu, txqactive bits) do not clash. 974 * 975 * Although the current single-thread taskqueue mechanism protects the 976 * majority of these situations by simply serialising them, there are 977 * a few others which occur at the same time. These include the TX path 978 * (which only acquires ATH_LOCK when recycling buffers to the free list), 979 * ath_set_channel, the channel scanning API and perhaps quite a bit more. 980 */ 981#define ATH_PCU_LOCK_INIT(_sc) do {\ 982 snprintf((_sc)->sc_pcu_mtx_name, \ 983 sizeof((_sc)->sc_pcu_mtx_name), \ 984 "%s PCU lock", \ 985 device_get_nameunit((_sc)->sc_dev)); \ 986 mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \ 987 NULL, MTX_DEF); \ 988 } while (0) 989#define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx) 990#define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx) 991#define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx) 992#define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 993 MA_OWNED) 994#define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 995 MA_NOTOWNED) 996 997/* 998 * The RX lock is primarily a(nother) workaround to ensure that the 999 * RX FIFO/list isn't modified by various execution paths. 1000 * Even though RX occurs in a single context (the ath taskqueue), the 1001 * RX path can be executed via various reset/channel change paths. 1002 */ 1003#define ATH_RX_LOCK_INIT(_sc) do {\ 1004 snprintf((_sc)->sc_rx_mtx_name, \ 1005 sizeof((_sc)->sc_rx_mtx_name), \ 1006 "%s RX lock", \ 1007 device_get_nameunit((_sc)->sc_dev)); \ 1008 mtx_init(&(_sc)->sc_rx_mtx, (_sc)->sc_rx_mtx_name, \ 1009 NULL, MTX_DEF); \ 1010 } while (0) 1011#define ATH_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_rx_mtx) 1012#define ATH_RX_LOCK(_sc) mtx_lock(&(_sc)->sc_rx_mtx) 1013#define ATH_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_rx_mtx) 1014#define ATH_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 1015 MA_OWNED) 1016#define ATH_RX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 1017 MA_NOTOWNED) 1018 1019#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 1020 1021#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 1022 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 1023 device_get_nameunit((_sc)->sc_dev)); \ 1024 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 1025} while (0) 1026#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 1027#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 1028#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 1029#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 1030 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 1031#define ATH_TXBUF_UNLOCK_ASSERT(_sc) \ 1032 mtx_assert(&(_sc)->sc_txbuflock, MA_NOTOWNED) 1033 1034#define ATH_TXSTATUS_LOCK_INIT(_sc) do { \ 1035 snprintf((_sc)->sc_txcompname, sizeof((_sc)->sc_txcompname), \ 1036 "%s_buf", \ 1037 device_get_nameunit((_sc)->sc_dev)); \ 1038 mtx_init(&(_sc)->sc_txcomplock, (_sc)->sc_txcompname, NULL, \ 1039 MTX_DEF); \ 1040} while (0) 1041#define ATH_TXSTATUS_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txcomplock) 1042#define ATH_TXSTATUS_LOCK(_sc) mtx_lock(&(_sc)->sc_txcomplock) 1043#define ATH_TXSTATUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txcomplock) 1044#define ATH_TXSTATUS_LOCK_ASSERT(_sc) \ 1045 mtx_assert(&(_sc)->sc_txcomplock, MA_OWNED) 1046 1047int ath_attach(u_int16_t, struct ath_softc *); 1048int ath_detach(struct ath_softc *); 1049void ath_resume(struct ath_softc *); 1050void ath_suspend(struct ath_softc *); 1051void ath_shutdown(struct ath_softc *); 1052void ath_intr(void *); 1053 1054/* 1055 * HAL definitions to comply with local coding convention. 1056 */ 1057#define ath_hal_detach(_ah) \ 1058 ((*(_ah)->ah_detach)((_ah))) 1059#define ath_hal_reset(_ah, _opmode, _chan, _fullreset, _resettype, _pstatus) \ 1060 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_fullreset), \ 1061 (_resettype), (_pstatus))) 1062#define ath_hal_macversion(_ah) \ 1063 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 1064#define ath_hal_getratetable(_ah, _mode) \ 1065 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 1066#define ath_hal_getmac(_ah, _mac) \ 1067 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 1068#define ath_hal_setmac(_ah, _mac) \ 1069 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 1070#define ath_hal_getbssidmask(_ah, _mask) \ 1071 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 1072#define ath_hal_setbssidmask(_ah, _mask) \ 1073 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 1074#define ath_hal_intrset(_ah, _mask) \ 1075 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 1076#define ath_hal_intrget(_ah) \ 1077 ((*(_ah)->ah_getInterrupts)((_ah))) 1078#define ath_hal_intrpend(_ah) \ 1079 ((*(_ah)->ah_isInterruptPending)((_ah))) 1080#define ath_hal_getisr(_ah, _pmask) \ 1081 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 1082#define ath_hal_updatetxtriglevel(_ah, _inc) \ 1083 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 1084#define ath_hal_setpower(_ah, _mode) \ 1085 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 1086#define ath_hal_setselfgenpower(_ah, _mode) \ 1087 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_FALSE)) 1088#define ath_hal_keycachesize(_ah) \ 1089 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 1090#define ath_hal_keyreset(_ah, _ix) \ 1091 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 1092#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 1093 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 1094#define ath_hal_keyisvalid(_ah, _ix) \ 1095 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 1096#define ath_hal_keysetmac(_ah, _ix, _mac) \ 1097 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 1098#define ath_hal_getrxfilter(_ah) \ 1099 ((*(_ah)->ah_getRxFilter)((_ah))) 1100#define ath_hal_setrxfilter(_ah, _filter) \ 1101 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 1102#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 1103 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 1104#define ath_hal_waitforbeacon(_ah, _bf) \ 1105 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 1106#define ath_hal_putrxbuf(_ah, _bufaddr, _rxq) \ 1107 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr), (_rxq))) 1108/* NB: common across all chips */ 1109#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 1110#define ath_hal_gettsf32(_ah) \ 1111 OS_REG_READ(_ah, AR_TSF_L32) 1112#define ath_hal_gettsf64(_ah) \ 1113 ((*(_ah)->ah_getTsf64)((_ah))) 1114#define ath_hal_settsf64(_ah, _val) \ 1115 ((*(_ah)->ah_setTsf64)((_ah), (_val))) 1116#define ath_hal_resettsf(_ah) \ 1117 ((*(_ah)->ah_resetTsf)((_ah))) 1118#define ath_hal_rxena(_ah) \ 1119 ((*(_ah)->ah_enableReceive)((_ah))) 1120#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 1121 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 1122#define ath_hal_gettxbuf(_ah, _q) \ 1123 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 1124#define ath_hal_numtxpending(_ah, _q) \ 1125 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 1126#define ath_hal_getrxbuf(_ah, _rxq) \ 1127 ((*(_ah)->ah_getRxDP)((_ah), (_rxq))) 1128#define ath_hal_txstart(_ah, _q) \ 1129 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 1130#define ath_hal_setchannel(_ah, _chan) \ 1131 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 1132#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 1133 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 1134#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 1135 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 1136#define ath_hal_calreset(_ah, _chan) \ 1137 ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 1138#define ath_hal_setledstate(_ah, _state) \ 1139 ((*(_ah)->ah_setLedState)((_ah), (_state))) 1140#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 1141 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 1142#define ath_hal_beaconreset(_ah) \ 1143 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 1144#define ath_hal_beaconsettimers(_ah, _bt) \ 1145 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 1146#define ath_hal_beacontimers(_ah, _bs) \ 1147 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 1148#define ath_hal_getnexttbtt(_ah) \ 1149 ((*(_ah)->ah_getNextTBTT)((_ah))) 1150#define ath_hal_setassocid(_ah, _bss, _associd) \ 1151 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 1152#define ath_hal_phydisable(_ah) \ 1153 ((*(_ah)->ah_phyDisable)((_ah))) 1154#define ath_hal_setopmode(_ah) \ 1155 ((*(_ah)->ah_setPCUConfig)((_ah))) 1156#define ath_hal_stoptxdma(_ah, _qnum) \ 1157 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 1158#define ath_hal_stoppcurecv(_ah) \ 1159 ((*(_ah)->ah_stopPcuReceive)((_ah))) 1160#define ath_hal_startpcurecv(_ah, _is_scanning) \ 1161 ((*(_ah)->ah_startPcuReceive)((_ah), (_is_scanning))) 1162#define ath_hal_stopdmarecv(_ah) \ 1163 ((*(_ah)->ah_stopDmaReceive)((_ah))) 1164#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 1165 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 1166 (_indata), (_insize), (_outdata), (_outsize))) 1167#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 1168 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 1169#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 1170 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 1171#define ath_hal_resettxqueue(_ah, _q) \ 1172 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 1173#define ath_hal_releasetxqueue(_ah, _q) \ 1174 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 1175#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 1176 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 1177#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 1178 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 1179/* NB: common across all chips */ 1180#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 1181#define ath_hal_txqenabled(_ah, _qnum) \ 1182 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 1183#define ath_hal_getrfgain(_ah) \ 1184 ((*(_ah)->ah_getRfGain)((_ah))) 1185#define ath_hal_getdefantenna(_ah) \ 1186 ((*(_ah)->ah_getDefAntenna)((_ah))) 1187#define ath_hal_setdefantenna(_ah, _ant) \ 1188 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 1189#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 1190 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 1191#define ath_hal_ani_poll(_ah, _chan) \ 1192 ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 1193#define ath_hal_mibevent(_ah, _stats) \ 1194 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 1195#define ath_hal_setslottime(_ah, _us) \ 1196 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 1197#define ath_hal_getslottime(_ah) \ 1198 ((*(_ah)->ah_getSlotTime)((_ah))) 1199#define ath_hal_setacktimeout(_ah, _us) \ 1200 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 1201#define ath_hal_getacktimeout(_ah) \ 1202 ((*(_ah)->ah_getAckTimeout)((_ah))) 1203#define ath_hal_setctstimeout(_ah, _us) \ 1204 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 1205#define ath_hal_getctstimeout(_ah) \ 1206 ((*(_ah)->ah_getCTSTimeout)((_ah))) 1207#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 1208 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 1209#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 1210 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 1211#define ath_hal_ciphersupported(_ah, _cipher) \ 1212 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 1213#define ath_hal_getregdomain(_ah, _prd) \ 1214 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 1215#define ath_hal_setregdomain(_ah, _rd) \ 1216 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 1217#define ath_hal_getcountrycode(_ah, _pcc) \ 1218 (*(_pcc) = (_ah)->ah_countryCode) 1219#define ath_hal_gettkipmic(_ah) \ 1220 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 1221#define ath_hal_settkipmic(_ah, _v) \ 1222 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 1223#define ath_hal_hastkipsplit(_ah) \ 1224 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 1225#define ath_hal_gettkipsplit(_ah) \ 1226 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 1227#define ath_hal_settkipsplit(_ah, _v) \ 1228 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 1229#define ath_hal_haswmetkipmic(_ah) \ 1230 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 1231#define ath_hal_hwphycounters(_ah) \ 1232 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 1233#define ath_hal_hasdiversity(_ah) \ 1234 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 1235#define ath_hal_getdiversity(_ah) \ 1236 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 1237#define ath_hal_setdiversity(_ah, _v) \ 1238 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 1239#define ath_hal_getantennaswitch(_ah) \ 1240 ((*(_ah)->ah_getAntennaSwitch)((_ah))) 1241#define ath_hal_setantennaswitch(_ah, _v) \ 1242 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 1243#define ath_hal_getdiag(_ah, _pv) \ 1244 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 1245#define ath_hal_setdiag(_ah, _v) \ 1246 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 1247#define ath_hal_getnumtxqueues(_ah, _pv) \ 1248 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 1249#define ath_hal_hasveol(_ah) \ 1250 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 1251#define ath_hal_hastxpowlimit(_ah) \ 1252 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 1253#define ath_hal_settxpowlimit(_ah, _pow) \ 1254 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 1255#define ath_hal_gettxpowlimit(_ah, _ppow) \ 1256 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 1257#define ath_hal_getmaxtxpow(_ah, _ppow) \ 1258 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 1259#define ath_hal_gettpscale(_ah, _scale) \ 1260 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 1261#define ath_hal_settpscale(_ah, _v) \ 1262 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 1263#define ath_hal_hastpc(_ah) \ 1264 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 1265#define ath_hal_gettpc(_ah) \ 1266 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 1267#define ath_hal_settpc(_ah, _v) \ 1268 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 1269#define ath_hal_hasbursting(_ah) \ 1270 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 1271#define ath_hal_setmcastkeysearch(_ah, _v) \ 1272 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 1273#define ath_hal_hasmcastkeysearch(_ah) \ 1274 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 1275#define ath_hal_getmcastkeysearch(_ah) \ 1276 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 1277#define ath_hal_hasfastframes(_ah) \ 1278 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 1279#define ath_hal_hasbssidmask(_ah) \ 1280 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 1281#define ath_hal_hasbssidmatch(_ah) \ 1282 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 1283#define ath_hal_hastsfadjust(_ah) \ 1284 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 1285#define ath_hal_gettsfadjust(_ah) \ 1286 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 1287#define ath_hal_settsfadjust(_ah, _onoff) \ 1288 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 1289#define ath_hal_hasrfsilent(_ah) \ 1290 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 1291#define ath_hal_getrfkill(_ah) \ 1292 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 1293#define ath_hal_setrfkill(_ah, _onoff) \ 1294 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 1295#define ath_hal_getrfsilent(_ah, _prfsilent) \ 1296 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 1297#define ath_hal_setrfsilent(_ah, _rfsilent) \ 1298 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 1299#define ath_hal_gettpack(_ah, _ptpack) \ 1300 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 1301#define ath_hal_settpack(_ah, _tpack) \ 1302 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 1303#define ath_hal_gettpcts(_ah, _ptpcts) \ 1304 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 1305#define ath_hal_settpcts(_ah, _tpcts) \ 1306 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 1307#define ath_hal_hasintmit(_ah) \ 1308 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1309 HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 1310#define ath_hal_getintmit(_ah) \ 1311 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1312 HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 1313#define ath_hal_setintmit(_ah, _v) \ 1314 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ 1315 HAL_CAP_INTMIT_ENABLE, _v, NULL) 1316#define ath_hal_hasmybeacon(_ah) \ 1317 (ath_hal_getcapability(_ah, HAL_CAP_DO_MYBEACON, 1, NULL) == HAL_OK) 1318 1319#define ath_hal_hasenforcetxop(_ah) \ 1320 (ath_hal_getcapability(_ah, HAL_CAP_ENFORCE_TXOP, 0, NULL) == HAL_OK) 1321#define ath_hal_getenforcetxop(_ah) \ 1322 (ath_hal_getcapability(_ah, HAL_CAP_ENFORCE_TXOP, 1, NULL) == HAL_OK) 1323#define ath_hal_setenforcetxop(_ah, _v) \ 1324 ath_hal_setcapability(_ah, HAL_CAP_ENFORCE_TXOP, 1, _v, NULL) 1325 1326#define ath_hal_hasrxlnamixer(_ah) \ 1327 (ath_hal_getcapability(_ah, HAL_CAP_RX_LNA_MIXING, 0, NULL) == HAL_OK) 1328 1329#define ath_hal_hasdivantcomb(_ah) \ 1330 (ath_hal_getcapability(_ah, HAL_CAP_ANT_DIV_COMB, 0, NULL) == HAL_OK) 1331#define ath_hal_hasldpc(_ah) \ 1332 (ath_hal_getcapability(_ah, HAL_CAP_LDPC, 0, NULL) == HAL_OK) 1333#define ath_hal_hasldpcwar(_ah) \ 1334 (ath_hal_getcapability(_ah, HAL_CAP_LDPCWAR, 0, NULL) == HAL_OK) 1335 1336/* EDMA definitions */ 1337#define ath_hal_hasedma(_ah) \ 1338 (ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \ 1339 0, NULL) == HAL_OK) 1340#define ath_hal_getrxfifodepth(_ah, _qtype, _req) \ 1341 (ath_hal_getcapability(_ah, HAL_CAP_RXFIFODEPTH, _qtype, _req) \ 1342 == HAL_OK) 1343#define ath_hal_getntxmaps(_ah, _req) \ 1344 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXMAPS, 0, _req) \ 1345 == HAL_OK) 1346#define ath_hal_gettxdesclen(_ah, _req) \ 1347 (ath_hal_getcapability(_ah, HAL_CAP_TXDESCLEN, 0, _req) \ 1348 == HAL_OK) 1349#define ath_hal_gettxstatuslen(_ah, _req) \ 1350 (ath_hal_getcapability(_ah, HAL_CAP_TXSTATUSLEN, 0, _req) \ 1351 == HAL_OK) 1352#define ath_hal_getrxstatuslen(_ah, _req) \ 1353 (ath_hal_getcapability(_ah, HAL_CAP_RXSTATUSLEN, 0, _req) \ 1354 == HAL_OK) 1355#define ath_hal_setrxbufsize(_ah, _req) \ 1356 (ath_hal_setcapability(_ah, HAL_CAP_RXBUFSIZE, 0, _req, NULL) \ 1357 == AH_TRUE) 1358 1359#define ath_hal_getchannoise(_ah, _c) \ 1360 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 1361 1362/* 802.11n HAL methods */ 1363#define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 1364 (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 1365#define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 1366 (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 1367#define ath_hal_setrxchainmask(_ah, _rx) \ 1368 (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL)) 1369#define ath_hal_settxchainmask(_ah, _tx) \ 1370 (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL)) 1371#define ath_hal_split4ktrans(_ah) \ 1372 (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \ 1373 0, NULL) == HAL_OK) 1374#define ath_hal_self_linked_final_rxdesc(_ah) \ 1375 (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \ 1376 0, NULL) == HAL_OK) 1377#define ath_hal_gtxto_supported(_ah) \ 1378 (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 1379#define ath_hal_get_rx_tsf_prec(_ah, _pr) \ 1380 (ath_hal_getcapability((_ah), HAL_CAP_RXTSTAMP_PREC, 0, (_pr)) \ 1381 == HAL_OK) 1382#define ath_hal_get_tx_tsf_prec(_ah, _pr) \ 1383 (ath_hal_getcapability((_ah), HAL_CAP_TXTSTAMP_PREC, 0, (_pr)) \ 1384 == HAL_OK) 1385#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 1386 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 1387#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 1388 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 1389#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 1390 _txr0, _txtr0, _keyix, _ant, _flags, \ 1391 _rtsrate, _rtsdura) \ 1392 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 1393 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 1394 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 1395#define ath_hal_setupxtxdesc(_ah, _ds, \ 1396 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 1397 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 1398 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 1399#define ath_hal_filltxdesc(_ah, _ds, _b, _l, _did, _qid, _first, _last, _ds0) \ 1400 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_b), (_l), (_did), (_qid), \ 1401 (_first), (_last), (_ds0))) 1402#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 1403 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 1404#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 1405 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 1406#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 1407 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 1408#define ath_hal_settxdesclink(_ah, _ds, _link) \ 1409 ((*(_ah)->ah_setTxDescLink)((_ah), (_ds), (_link))) 1410#define ath_hal_gettxdesclink(_ah, _ds, _link) \ 1411 ((*(_ah)->ah_getTxDescLink)((_ah), (_ds), (_link))) 1412#define ath_hal_gettxdesclinkptr(_ah, _ds, _linkptr) \ 1413 ((*(_ah)->ah_getTxDescLinkPtr)((_ah), (_ds), (_linkptr))) 1414#define ath_hal_setuptxstatusring(_ah, _tsstart, _tspstart, _size) \ 1415 ((*(_ah)->ah_setupTxStatusRing)((_ah), (_tsstart), (_tspstart), \ 1416 (_size))) 1417#define ath_hal_gettxrawtxdesc(_ah, _txstatus) \ 1418 ((*(_ah)->ah_getTxRawTxDesc)((_ah), (_txstatus))) 1419 1420#define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 1421 _txr0, _txtr0, _antm, _rcr, _rcd) \ 1422 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 1423 (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 1424#define ath_hal_chaintxdesc(_ah, _ds, _bl, _sl, _pktlen, _hdrlen, _type, \ 1425 _keyix, _cipher, _delims, _first, _last, _lastaggr) \ 1426 ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_bl), (_sl), \ 1427 (_pktlen), (_hdrlen), (_type), (_keyix), (_cipher), (_delims), \ 1428 (_first), (_last), (_lastaggr))) 1429#define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 1430 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 1431 1432#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 1433 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 1434 (_series), (_ns), (_flags))) 1435 1436#define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 1437 ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len), (_num))) 1438#define ath_hal_set11n_aggr_middle(_ah, _ds, _num) \ 1439 ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 1440#define ath_hal_set11n_aggr_last(_ah, _ds) \ 1441 ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 1442 1443#define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 1444 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 1445#define ath_hal_clr11n_aggr(_ah, _ds) \ 1446 ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 1447#define ath_hal_set11n_virtmorefrag(_ah, _ds, _v) \ 1448 ((*(_ah)->ah_set11nVirtMoreFrag)((_ah), (_ds), (_v))) 1449 1450#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 1451 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 1452#define ath_hal_gpioset(_ah, _gpio, _b) \ 1453 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 1454#define ath_hal_gpioget(_ah, _gpio) \ 1455 ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 1456#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 1457 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 1458 1459/* 1460 * PCIe suspend/resume/poweron/poweroff related macros 1461 */ 1462#define ath_hal_enablepcie(_ah, _restore, _poweroff) \ 1463 ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff))) 1464#define ath_hal_disablepcie(_ah) \ 1465 ((*(_ah)->ah_disablePCIE)((_ah))) 1466 1467/* 1468 * This is badly-named; you need to set the correct parameters 1469 * to begin to receive useful radar events; and even then 1470 * it doesn't "enable" DFS. See the ath_dfs/null/ module for 1471 * more information. 1472 */ 1473#define ath_hal_enabledfs(_ah, _param) \ 1474 ((*(_ah)->ah_enableDfs)((_ah), (_param))) 1475#define ath_hal_getdfsthresh(_ah, _param) \ 1476 ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 1477#define ath_hal_getdfsdefaultthresh(_ah, _param) \ 1478 ((*(_ah)->ah_getDfsDefaultThresh)((_ah), (_param))) 1479#define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 1480 ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \ 1481 (_buf), (_event))) 1482#define ath_hal_is_fast_clock_enabled(_ah) \ 1483 ((*(_ah)->ah_isFastClockEnabled)((_ah))) 1484#define ath_hal_radar_wait(_ah, _chan) \ 1485 ((*(_ah)->ah_radarWait)((_ah), (_chan))) 1486#define ath_hal_get_mib_cycle_counts(_ah, _sample) \ 1487 ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample))) 1488#define ath_hal_get_chan_ext_busy(_ah) \ 1489 ((*(_ah)->ah_get11nExtBusy)((_ah))) 1490#define ath_hal_setchainmasks(_ah, _txchainmask, _rxchainmask) \ 1491 ((*(_ah)->ah_setChainMasks)((_ah), (_txchainmask), (_rxchainmask))) 1492#define ath_hal_set_quiet(_ah, _p, _d, _o, _f) \ 1493 ((*(_ah)->ah_setQuiet)((_ah), (_p), (_d), (_o), (_f))) 1494#define ath_hal_getnav(_ah) \ 1495 ((*(_ah)->ah_getNav)((_ah))) 1496#define ath_hal_setnav(_ah, _val) \ 1497 ((*(_ah)->ah_setNav)((_ah), (_val))) 1498 1499#define ath_hal_spectral_supported(_ah) \ 1500 (ath_hal_getcapability(_ah, HAL_CAP_SPECTRAL_SCAN, 0, NULL) == HAL_OK) 1501#define ath_hal_spectral_get_config(_ah, _p) \ 1502 ((*(_ah)->ah_spectralGetConfig)((_ah), (_p))) 1503#define ath_hal_spectral_configure(_ah, _p) \ 1504 ((*(_ah)->ah_spectralConfigure)((_ah), (_p))) 1505#define ath_hal_spectral_start(_ah) \ 1506 ((*(_ah)->ah_spectralStart)((_ah))) 1507#define ath_hal_spectral_stop(_ah) \ 1508 ((*(_ah)->ah_spectralStop)((_ah))) 1509 1510#define ath_hal_btcoex_supported(_ah) \ 1511 (ath_hal_getcapability(_ah, HAL_CAP_BT_COEX, 0, NULL) == HAL_OK) 1512#define ath_hal_btcoex_set_info(_ah, _info) \ 1513 ((*(_ah)->ah_btCoexSetInfo)((_ah), (_info))) 1514#define ath_hal_btcoex_set_config(_ah, _cfg) \ 1515 ((*(_ah)->ah_btCoexSetConfig)((_ah), (_cfg))) 1516#define ath_hal_btcoex_set_qcu_thresh(_ah, _qcuid) \ 1517 ((*(_ah)->ah_btCoexSetQcuThresh)((_ah), (_qcuid))) 1518#define ath_hal_btcoex_set_weights(_ah, _weight) \ 1519 ((*(_ah)->ah_btCoexSetWeights)((_ah), (_weight))) 1520#define ath_hal_btcoex_set_bmiss_thresh(_ah, _thr) \ 1521 ((*(_ah)->ah_btCoexSetBmissThresh)((_ah), (_thr))) 1522#define ath_hal_btcoex_set_parameter(_ah, _attrib, _val) \ 1523 ((*(_ah)->ah_btCoexSetParameter)((_ah), (_attrib), (_val))) 1524#define ath_hal_btcoex_enable(_ah) \ 1525 ((*(_ah)->ah_btCoexEnable)((_ah))) 1526#define ath_hal_btcoex_disable(_ah) \ 1527 ((*(_ah)->ah_btCoexDisable)((_ah))) 1528 1529#define ath_hal_btcoex_mci_setup(_ah, _gp, _gb, _gl, _sp) \ 1530 ((*(_ah)->ah_btMciSetup)((_ah), (_gp), (_gb), (_gl), (_sp))) 1531#define ath_hal_btcoex_mci_send_message(_ah, _h, _f, _p, _l, _wd, _cbt) \ 1532 ((*(_ah)->ah_btMciSendMessage)((_ah), (_h), (_f), (_p), (_l), (_wd), (_cbt))) 1533#define ath_hal_btcoex_mci_get_interrupt(_ah, _mi, _mm) \ 1534 ((*(_ah)->ah_btMciGetInterrupt)((_ah), (_mi), (_mm))) 1535#define ath_hal_btcoex_mci_state(_ah, _st, _pd) \ 1536 ((*(_ah)->ah_btMciState)((_ah), (_st), (_pd))) 1537#define ath_hal_btcoex_mci_detach(_ah) \ 1538 ((*(_ah)->ah_btMciDetach)((_ah))) 1539 1540#define ath_hal_div_comb_conf_get(_ah, _conf) \ 1541 ((*(_ah)->ah_divLnaConfGet)((_ah), (_conf))) 1542#define ath_hal_div_comb_conf_set(_ah, _conf) \ 1543 ((*(_ah)->ah_divLnaConfSet)((_ah), (_conf))) 1544 1545#endif /* _DEV_ATH_ATHVAR_H */ 1546