1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 18 * NO WARRANTY 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGES. 30 */ 31 32/* 33 * Ioctl-related defintions for the Atheros Wireless LAN controller driver. 34 */ 35#ifndef _DEV_ATH_ATHIOCTL_H 36#define _DEV_ATH_ATHIOCTL_H 37 38struct ath_tx_aggr_stats { 39 u_int32_t aggr_pkts[64]; 40 u_int32_t aggr_single_pkt; 41 u_int32_t aggr_nonbaw_pkt; 42 u_int32_t aggr_aggr_pkt; 43 u_int32_t aggr_baw_closed_single_pkt; 44 u_int32_t aggr_low_hwq_single_pkt; 45 u_int32_t aggr_sched_nopkt; 46 u_int32_t aggr_rts_aggr_limited; 47}; 48 49#define ATH_IOCTL_INTR_NUM_SYNC_INTR 32 50struct ath_intr_stats { 51 u_int32_t sync_intr[ATH_IOCTL_INTR_NUM_SYNC_INTR]; 52}; 53 54#define ATH_IOCTL_STATS_NUM_RX_PHYERR 64 55#define ATH_IOCTL_STATS_NUM_TX_ANTENNA 8 56#define ATH_IOCTL_STATS_NUM_RX_ANTENNA 8 57struct ath_stats { 58 u_int32_t ast_watchdog; /* device reset by watchdog */ 59 u_int32_t ast_hardware; /* fatal hardware error interrupts */ 60 u_int32_t ast_bmiss; /* beacon miss interrupts */ 61 u_int32_t ast_bmiss_phantom;/* beacon miss interrupts */ 62 u_int32_t ast_bstuck; /* beacon stuck interrupts */ 63 u_int32_t ast_rxorn; /* rx overrun interrupts */ 64 u_int32_t ast_rxeol; /* rx eol interrupts */ 65 u_int32_t ast_txurn; /* tx underrun interrupts */ 66 u_int32_t ast_mib; /* mib interrupts */ 67 u_int32_t ast_intrcoal; /* interrupts coalesced */ 68 u_int32_t ast_tx_packets; /* packet sent on the interface */ 69 u_int32_t ast_tx_mgmt; /* management frames transmitted */ 70 u_int32_t ast_tx_discard; /* frames discarded prior to assoc */ 71 u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */ 72 u_int32_t ast_tx_encap; /* tx encapsulation failed */ 73 u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */ 74 u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */ 75 u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */ 76 u_int32_t ast_tx_linear; /* tx linearized to cluster */ 77 u_int32_t ast_tx_nodata; /* tx discarded empty frame */ 78 u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */ 79 u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */ 80 u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */ 81 u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */ 82 u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */ 83 u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */ 84 u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */ 85 u_int32_t ast_tx_noack; /* tx frames with no ack marked */ 86 u_int32_t ast_tx_rts; /* tx frames with rts enabled */ 87 u_int32_t ast_tx_cts; /* tx frames with cts enabled */ 88 u_int32_t ast_tx_shortpre;/* tx frames with short preamble */ 89 u_int32_t ast_tx_altrate; /* tx frames with alternate rate */ 90 u_int32_t ast_tx_protect; /* tx frames with protection */ 91 u_int32_t ast_tx_ctsburst;/* tx frames with cts and bursting */ 92 u_int32_t ast_tx_ctsext; /* tx frames with cts extension */ 93 u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */ 94 u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */ 95 u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */ 96 u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */ 97 u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */ 98 u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */ 99 u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */ 100 u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */ 101 u_int32_t ast_rx_phy[ATH_IOCTL_STATS_NUM_RX_PHYERR]; 102 /* rx PHY error per-code counts */ 103 u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */ 104 u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */ 105 u_int32_t ast_rx_packets; /* packet recv on the interface */ 106 u_int32_t ast_rx_mgt; /* management frames received */ 107 u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */ 108 int8_t ast_tx_rssi; /* tx rssi of last ack */ 109 int8_t ast_rx_rssi; /* rx rssi from histogram */ 110 u_int8_t ast_tx_rate; /* IEEE rate of last unicast tx */ 111 u_int32_t ast_be_xmit; /* beacons transmitted */ 112 u_int32_t ast_be_nombuf; /* beacon setup failed 'cuz no mbuf */ 113 u_int32_t ast_per_cal; /* periodic calibration calls */ 114 u_int32_t ast_per_calfail;/* periodic calibration failed */ 115 u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */ 116 u_int32_t ast_rate_calls; /* rate control checks */ 117 u_int32_t ast_rate_raise; /* rate control raised xmit rate */ 118 u_int32_t ast_rate_drop; /* rate control dropped xmit rate */ 119 u_int32_t ast_ant_defswitch;/* rx/default antenna switches */ 120 u_int32_t ast_ant_txswitch;/* tx antenna switches */ 121 u_int32_t ast_ant_rx[ATH_IOCTL_STATS_NUM_RX_ANTENNA]; 122 /* rx frames with antenna */ 123 u_int32_t ast_ant_tx[ATH_IOCTL_STATS_NUM_TX_ANTENNA]; 124 /* tx frames with antenna */ 125 u_int32_t ast_cabq_xmit; /* cabq frames transmitted */ 126 u_int32_t ast_cabq_busy; /* cabq found busy */ 127 u_int32_t ast_tx_raw; /* tx frames through raw api */ 128 u_int32_t ast_ff_txok; /* fast frames tx'd successfully */ 129 u_int32_t ast_ff_txerr; /* fast frames tx'd w/ error */ 130 u_int32_t ast_ff_rx; /* fast frames rx'd */ 131 u_int32_t ast_ff_flush; /* fast frames flushed from staging q */ 132 u_int32_t ast_tx_qfull; /* tx dropped 'cuz of queue limit */ 133 int8_t ast_rx_noise; /* rx noise floor */ 134 u_int32_t ast_tx_nobuf; /* tx dropped 'cuz no ath buffer */ 135 u_int32_t ast_tdma_update;/* TDMA slot timing updates */ 136 u_int32_t ast_tdma_timers;/* TDMA slot update set beacon timers */ 137 u_int32_t ast_tdma_tsf; /* TDMA slot update set TSF */ 138 u_int16_t ast_tdma_tsfadjp;/* TDMA slot adjust+ (usec, smoothed)*/ 139 u_int16_t ast_tdma_tsfadjm;/* TDMA slot adjust- (usec, smoothed)*/ 140 u_int32_t ast_tdma_ack; /* TDMA tx failed 'cuz ACK required */ 141 u_int32_t ast_tx_raw_fail;/* raw tx failed 'cuz h/w down */ 142 u_int32_t ast_tx_nofrag; /* tx dropped 'cuz no ath frag buffer */ 143 u_int32_t ast_be_missed; /* missed beacons */ 144 u_int32_t ast_ani_cal; /* ANI calibrations performed */ 145 u_int32_t ast_rx_agg; /* number of aggregate frames RX'ed */ 146 u_int32_t ast_rx_halfgi; /* RX half-GI */ 147 u_int32_t ast_rx_2040; /* RX 40mhz frame */ 148 u_int32_t ast_rx_pre_crc_err; /* RX pre-delimiter CRC error */ 149 u_int32_t ast_rx_post_crc_err; /* RX post-delimiter CRC error */ 150 u_int32_t ast_rx_decrypt_busy_err; /* RX decrypt engine busy error */ 151 u_int32_t ast_rx_hi_rx_chain; 152 u_int32_t ast_tx_htprotect; /* HT tx frames with protection */ 153 u_int32_t ast_rx_hitqueueend; /* RX hit descr queue end */ 154 u_int32_t ast_tx_timeout; /* Global TX timeout */ 155 u_int32_t ast_tx_cst; /* Carrier sense timeout */ 156 u_int32_t ast_tx_xtxop; /* tx exceeded TXOP */ 157 u_int32_t ast_tx_timerexpired; /* tx exceeded TX_TIMER */ 158 u_int32_t ast_tx_desccfgerr; /* tx desc cfg error */ 159 u_int32_t ast_tx_swretries; /* software TX retries */ 160 u_int32_t ast_tx_swretrymax; /* software TX retry max limit reach */ 161 u_int32_t ast_tx_data_underrun; 162 u_int32_t ast_tx_delim_underrun; 163 u_int32_t ast_tx_aggr_failall; /* aggregate TX failed in its entirety */ 164 u_int32_t ast_tx_getnobuf; 165 u_int32_t ast_tx_getbusybuf; 166 u_int32_t ast_tx_intr; 167 u_int32_t ast_rx_intr; 168 u_int32_t ast_tx_aggr_ok; /* aggregate TX ok */ 169 u_int32_t ast_tx_aggr_fail; /* aggregate TX failed */ 170 u_int32_t ast_tx_mcastq_overflow; /* multicast queue overflow */ 171 u_int32_t ast_rx_keymiss; 172 u_int32_t ast_tx_swfiltered; 173 u_int32_t ast_tx_node_psq_overflow; 174 u_int32_t ast_rx_stbc; /* RX STBC frame */ 175 u_int32_t ast_tx_nodeq_overflow; /* node sw queue overflow */ 176 u_int32_t ast_tx_ldpc; /* TX LDPC frame */ 177 u_int32_t ast_tx_stbc; /* TX STBC frame */ 178 u_int32_t ast_tsfoor; /* TSFOOR interrupts */ 179 u_int32_t ast_pad[10]; 180}; 181 182#define SIOCGATHSTATS _IOWR('i', 137, struct ifreq) 183#define SIOCZATHSTATS _IOWR('i', 139, struct ifreq) 184#define SIOCGATHAGSTATS _IOWR('i', 141, struct ifreq) 185 186struct ath_diag { 187 char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */ 188 u_int16_t ad_id; 189#define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */ 190#define ATH_DIAG_IN 0x4000 /* copy in parameters */ 191#define ATH_DIAG_OUT 0x0000 /* copy out results (always) */ 192#define ATH_DIAG_ID 0x0fff 193 u_int16_t ad_in_size; /* pack to fit, yech */ 194 caddr_t ad_in_data; 195 caddr_t ad_out_data; 196 u_int ad_out_size; 197 198}; 199#define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag) 200#define SIOCGATHPHYERR _IOWR('i', 140, struct ath_diag) 201 202/* 203 * The rate control ioctl has to support multiple potential rate 204 * control classes. For now, instead of trying to support an 205 * abstraction for this in the API, let's just use a TLV 206 * representation for the payload and let userspace sort it out. 207 */ 208struct ath_rateioctl_tlv { 209 uint16_t tlv_id; 210 uint16_t tlv_len; /* length excluding TLV header */ 211}; 212 213/* 214 * This is purely the six byte MAC address. 215 */ 216#define ATH_RATE_TLV_MACADDR 0xaab0 217 218/* 219 * The rate control modules may decide to push a mapping table 220 * of rix -> net80211 ratecode as part of the update. 221 */ 222#define ATH_RATE_TLV_RATETABLE_NENTRIES 64 223struct ath_rateioctl_rt { 224 uint16_t nentries; 225 uint16_t pad[1]; 226 uint8_t ratecode[ATH_RATE_TLV_RATETABLE_NENTRIES]; 227}; 228#define ATH_RATE_TLV_RATETABLE 0xaab1 229 230/* 231 * This is the sample node statistics structure. 232 * More in ath_rate/sample/sample.h. 233 */ 234#define ATH_RATE_TLV_SAMPLENODE 0xaab2 235 236struct ath_rateioctl { 237 char if_name[IFNAMSIZ]; /* if name */ 238 union { 239 uint8_t macaddr[IEEE80211_ADDR_LEN]; 240 uint64_t pad; 241 } is_u; 242 uint32_t len; 243 caddr_t buf; 244}; 245#define SIOCGATHNODERATESTATS _IOWR('i', 149, struct ath_rateioctl) 246#define SIOCGATHRATESTATS _IOWR('i', 150, struct ath_rateioctl) 247 248/* 249 * Radio capture format. 250 */ 251#define ATH_RX_RADIOTAP_PRESENT_BASE ( \ 252 (1 << IEEE80211_RADIOTAP_TSFT) | \ 253 (1 << IEEE80211_RADIOTAP_FLAGS) | \ 254 (1 << IEEE80211_RADIOTAP_RATE) | \ 255 (1 << IEEE80211_RADIOTAP_ANTENNA) | \ 256 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ 257 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \ 258 (1 << IEEE80211_RADIOTAP_XCHANNEL) | \ 259 0) 260 261#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 262#define ATH_RX_RADIOTAP_PRESENT \ 263 (ATH_RX_RADIOTAP_PRESENT_BASE | \ 264 (1 << IEEE80211_RADIOTAP_VENDOREXT) | \ 265 (1 << IEEE80211_RADIOTAP_EXT) | \ 266 0) 267#else 268#define ATH_RX_RADIOTAP_PRESENT ATH_RX_RADIOTAP_PRESENT_BASE 269#endif /* ATH_ENABLE_RADIOTAP_PRESENT */ 270 271#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 272/* 273 * This is higher than the vendor bitmap used inside 274 * the Atheros reference codebase. 275 */ 276 277/* Bit 8 */ 278#define ATH_RADIOTAP_VENDOR_HEADER 8 279 280/* 281 * Using four chains makes all the fields in the 282 * per-chain info header be 4-byte aligned. 283 */ 284#define ATH_RADIOTAP_MAX_CHAINS 4 285 286/* 287 * AR9380 and later chips are 3x3, which requires 288 * 5 EVM DWORDs in HT40 mode. 289 */ 290#define ATH_RADIOTAP_MAX_EVM 5 291 292/* 293 * The vendor radiotap header data needs to be: 294 * 295 * + Aligned to a 4 byte address 296 * + .. so all internal fields are 4 bytes aligned; 297 * + .. and no 64 bit fields are allowed. 298 * 299 * So padding is required to ensure this is the case. 300 * 301 * Note that because of the lack of alignment with the 302 * vendor header (6 bytes), the first field must be 303 * two bytes so it can be accessed by alignment-strict 304 * platform (eg MIPS.) 305 */ 306struct ath_radiotap_vendor_hdr { /* 30 bytes */ 307 uint8_t vh_version; /* 1 */ 308 uint8_t vh_rx_chainmask; /* 1 */ 309 310 /* At this point it should be 4 byte aligned */ 311 uint32_t evm[ATH_RADIOTAP_MAX_EVM]; /* 5 * 4 = 20 */ 312 313 uint8_t rssi_ctl[ATH_RADIOTAP_MAX_CHAINS]; /* 4 * 4 = 16 */ 314 uint8_t rssi_ext[ATH_RADIOTAP_MAX_CHAINS]; /* 4 * 4 = 16 */ 315 316 uint8_t vh_phyerr_code; /* Phy error code, or 0xff */ 317 uint8_t vh_rs_status; /* RX status */ 318 uint8_t vh_rssi; /* Raw RSSI */ 319 uint8_t vh_flags; /* General flags */ 320#define ATH_VENDOR_PKT_RX 0x01 321#define ATH_VENDOR_PKT_TX 0x02 322#define ATH_VENDOR_PKT_RXPHYERR 0x04 323#define ATH_VENDOR_PKT_ISAGGR 0x08 324#define ATH_VENDOR_PKT_MOREAGGR 0x10 325 326 uint8_t vh_rx_hwrate; /* hardware RX ratecode */ 327 uint8_t vh_rs_flags; /* RX HAL flags */ 328 uint8_t vh_pad[2]; /* pad to DWORD boundary */ 329} __packed; 330#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 331 332struct ath_rx_radiotap_header { 333 struct ieee80211_radiotap_header wr_ihdr; 334 335#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 336 /* Vendor extension header bitmap */ 337 uint32_t wr_ext_bitmap; /* 4 */ 338 339 /* 340 * This padding is needed because: 341 * + the radiotap header is 8 bytes; 342 * + the extension bitmap is 4 bytes; 343 * + the tsf is 8 bytes, so it must start on an 8 byte 344 * boundary. 345 */ 346 uint32_t wr_pad1; 347#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 348 349 /* Normal radiotap fields */ 350 u_int64_t wr_tsf; 351 u_int8_t wr_flags; 352 u_int8_t wr_rate; 353 int8_t wr_antsignal; 354 int8_t wr_antnoise; 355 u_int8_t wr_antenna; 356 u_int8_t wr_pad[3]; 357 u_int32_t wr_chan_flags; 358 u_int16_t wr_chan_freq; 359 u_int8_t wr_chan_ieee; 360 int8_t wr_chan_maxpow; 361 362#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 363 /* 364 * Vendor header section, as required by the 365 * presence of the vendor extension bit and bitmap 366 * entry. 367 * 368 * XXX This must be aligned to a 4 byte address? 369 * XXX or 8 byte address? 370 */ 371 struct ieee80211_radiotap_vendor_header wr_vh; /* 6 bytes */ 372 373 /* 374 * Because of the lack of alignment enforced by the above 375 * header, this vendor section won't be aligned in any 376 * useful way. So, this will include a two-byte version 377 * value which will force the structure to be 4-byte aligned. 378 */ 379 struct ath_radiotap_vendor_hdr wr_v; 380#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 381} __packed __aligned(8); 382 383#define ATH_TX_RADIOTAP_PRESENT ( \ 384 (1 << IEEE80211_RADIOTAP_FLAGS) | \ 385 (1 << IEEE80211_RADIOTAP_RATE) | \ 386 (1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \ 387 (1 << IEEE80211_RADIOTAP_ANTENNA) | \ 388 (1 << IEEE80211_RADIOTAP_XCHANNEL) | \ 389 0) 390 391struct ath_tx_radiotap_header { 392 struct ieee80211_radiotap_header wt_ihdr; 393 u_int8_t wt_flags; 394 u_int8_t wt_rate; 395 u_int8_t wt_txpower; 396 u_int8_t wt_antenna; 397 u_int32_t wt_chan_flags; 398 u_int16_t wt_chan_freq; 399 u_int8_t wt_chan_ieee; 400 int8_t wt_chan_maxpow; 401} __packed; 402 403/* 404 * DFS ioctl commands 405 */ 406 407#define DFS_SET_THRESH 2 408#define DFS_GET_THRESH 3 409#define DFS_RADARDETECTS 6 410 411/* 412 * DFS ioctl parameter types 413 */ 414#define DFS_PARAM_FIRPWR 1 415#define DFS_PARAM_RRSSI 2 416#define DFS_PARAM_HEIGHT 3 417#define DFS_PARAM_PRSSI 4 418#define DFS_PARAM_INBAND 5 419#define DFS_PARAM_NOL 6 /* XXX not used in FreeBSD */ 420#define DFS_PARAM_RELSTEP_EN 7 421#define DFS_PARAM_RELSTEP 8 422#define DFS_PARAM_RELPWR_EN 9 423#define DFS_PARAM_RELPWR 10 424#define DFS_PARAM_MAXLEN 11 425#define DFS_PARAM_USEFIR128 12 426#define DFS_PARAM_BLOCKRADAR 13 427#define DFS_PARAM_MAXRSSI_EN 14 428 429/* FreeBSD-specific start at 32 */ 430#define DFS_PARAM_ENABLE 32 431#define DFS_PARAM_EN_EXTCH 33 432 433/* 434 * Spectral ioctl parameter types 435 */ 436#define SPECTRAL_PARAM_FFT_PERIOD 1 437#define SPECTRAL_PARAM_SS_PERIOD 2 438#define SPECTRAL_PARAM_SS_COUNT 3 439#define SPECTRAL_PARAM_SS_SHORT_RPT 4 440#define SPECTRAL_PARAM_ENABLED 5 441#define SPECTRAL_PARAM_ACTIVE 6 442#define SPECTRAL_PARAM_SS_SPECTRAL_PRI 7 443 444/* 445 * Spectral control parameters 446 */ 447#define SIOCGATHSPECTRAL _IOWR('i', 151, struct ath_diag) 448 449#define SPECTRAL_CONTROL_ENABLE 2 450#define SPECTRAL_CONTROL_DISABLE 3 451#define SPECTRAL_CONTROL_START 4 452#define SPECTRAL_CONTROL_STOP 5 453#define SPECTRAL_CONTROL_GET_PARAMS 6 454#define SPECTRAL_CONTROL_SET_PARAMS 7 455#define SPECTRAL_CONTROL_ENABLE_AT_RESET 8 456#define SPECTRAL_CONTROL_DISABLE_AT_RESET 9 457 458/* 459 * Bluetooth coexistence control parameters 460 */ 461#define SIOCGATHBTCOEX _IOWR('i', 152, struct ath_diag) 462 463#endif /* _DEV_ATH_ATHIOCTL_H */ 464