1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 18 * NO WARRANTY 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGES. 30 */ 31 32#include <sys/cdefs.h> 33/* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40#include "opt_inet.h" 41#include "opt_ath.h" 42/* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49#include "opt_ah.h" 50#include "opt_wlan.h" 51 52#include <sys/param.h> 53#include <sys/systm.h> 54#include <sys/sysctl.h> 55#include <sys/mbuf.h> 56#include <sys/malloc.h> 57#include <sys/lock.h> 58#include <sys/mutex.h> 59#include <sys/kernel.h> 60#include <sys/socket.h> 61#include <sys/sockio.h> 62#include <sys/errno.h> 63#include <sys/callout.h> 64#include <sys/bus.h> 65#include <sys/endian.h> 66#include <sys/kthread.h> 67#include <sys/taskqueue.h> 68#include <sys/priv.h> 69#include <sys/module.h> 70#include <sys/ktr.h> 71#include <sys/smp.h> /* for mp_ncpus */ 72 73#include <machine/bus.h> 74 75#include <net/if.h> 76#include <net/if_var.h> 77#include <net/if_dl.h> 78#include <net/if_media.h> 79#include <net/if_types.h> 80#include <net/if_arp.h> 81#include <net/ethernet.h> 82#include <net/if_llc.h> 83 84#include <net80211/ieee80211_var.h> 85#include <net80211/ieee80211_regdomain.h> 86#ifdef IEEE80211_SUPPORT_SUPERG 87#include <net80211/ieee80211_superg.h> 88#endif 89 90#include <net/bpf.h> 91 92#ifdef INET 93#include <netinet/in.h> 94#include <netinet/if_ether.h> 95#endif 96 97#include <dev/ath/if_athvar.h> 98 99#include <dev/ath/if_ath_debug.h> 100#include <dev/ath/if_ath_misc.h> 101#include <dev/ath/if_ath_tx.h> 102#include <dev/ath/if_ath_beacon.h> 103 104#ifdef ATH_TX99_DIAG 105#include <dev/ath/ath_tx99/ath_tx99.h> 106#endif 107 108/* 109 * Setup a h/w transmit queue for beacons. 110 */ 111int 112ath_beaconq_setup(struct ath_softc *sc) 113{ 114 struct ath_hal *ah = sc->sc_ah; 115 HAL_TXQ_INFO qi; 116 117 memset(&qi, 0, sizeof(qi)); 118 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 119 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 120 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 121 /* NB: for dynamic turbo, don't enable any other interrupts */ 122 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 123 if (sc->sc_isedma) 124 qi.tqi_qflags |= HAL_TXQ_TXOKINT_ENABLE | 125 HAL_TXQ_TXERRINT_ENABLE; 126 127 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 128} 129 130/* 131 * Setup the transmit queue parameters for the beacon queue. 132 */ 133int 134ath_beaconq_config(struct ath_softc *sc) 135{ 136#define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 137 struct ieee80211com *ic = &sc->sc_ic; 138 struct ath_hal *ah = sc->sc_ah; 139 HAL_TXQ_INFO qi; 140 141 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 142 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 143 ic->ic_opmode == IEEE80211_M_MBSS) { 144 /* 145 * Always burst out beacon and CAB traffic. 146 */ 147 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 148 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 149 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 150 } else { 151 struct chanAccParams chp; 152 struct wmeParams *wmep; 153 154 ieee80211_wme_ic_getparams(ic, &chp); 155 wmep = &chp.cap_wmeParams[WME_AC_BE]; 156 157 /* 158 * Adhoc mode; important thing is to use 2x cwmin. 159 */ 160 qi.tqi_aifs = wmep->wmep_aifsn; 161 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 162 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 163 } 164 165 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 166 device_printf(sc->sc_dev, "unable to update parameters for " 167 "beacon hardware queue!\n"); 168 return 0; 169 } else { 170 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 171 return 1; 172 } 173#undef ATH_EXPONENT_TO_VALUE 174} 175 176/* 177 * Allocate and setup an initial beacon frame. 178 */ 179int 180ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 181{ 182 struct ieee80211vap *vap = ni->ni_vap; 183 struct ath_vap *avp = ATH_VAP(vap); 184 struct ath_buf *bf; 185 struct mbuf *m; 186 int error; 187 188 bf = avp->av_bcbuf; 189 DPRINTF(sc, ATH_DEBUG_NODE, "%s: bf_m=%p, bf_node=%p\n", 190 __func__, bf->bf_m, bf->bf_node); 191 if (bf->bf_m != NULL) { 192 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 193 m_freem(bf->bf_m); 194 bf->bf_m = NULL; 195 } 196 if (bf->bf_node != NULL) { 197 ieee80211_free_node(bf->bf_node); 198 bf->bf_node = NULL; 199 } 200 201 /* 202 * NB: the beacon data buffer must be 32-bit aligned; 203 * we assume the mbuf routines will return us something 204 * with this alignment (perhaps should assert). 205 */ 206 m = ieee80211_beacon_alloc(ni); 207 if (m == NULL) { 208 device_printf(sc->sc_dev, "%s: cannot get mbuf\n", __func__); 209 sc->sc_stats.ast_be_nombuf++; 210 return ENOMEM; 211 } 212 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 213 bf->bf_segs, &bf->bf_nseg, 214 BUS_DMA_NOWAIT); 215 if (error != 0) { 216 device_printf(sc->sc_dev, 217 "%s: cannot map mbuf, bus_dmamap_load_mbuf_sg returns %d\n", 218 __func__, error); 219 m_freem(m); 220 return error; 221 } 222 223 /* 224 * Calculate a TSF adjustment factor required for staggered 225 * beacons. Note that we assume the format of the beacon 226 * frame leaves the tstamp field immediately following the 227 * header. 228 */ 229 if (sc->sc_stagbeacons && avp->av_bslot > 0) { 230 uint64_t tsfadjust; 231 struct ieee80211_frame *wh; 232 233 /* 234 * The beacon interval is in TU's; the TSF is in usecs. 235 * We figure out how many TU's to add to align the timestamp 236 * then convert to TSF units and handle byte swapping before 237 * inserting it in the frame. The hardware will then add this 238 * each time a beacon frame is sent. Note that we align vap's 239 * 1..N and leave vap 0 untouched. This means vap 0 has a 240 * timestamp in one beacon interval while the others get a 241 * timstamp aligned to the next interval. 242 */ 243 tsfadjust = ni->ni_intval * 244 (ATH_BCBUF - avp->av_bslot) / ATH_BCBUF; 245 tsfadjust = htole64(tsfadjust << 10); /* TU -> TSF */ 246 247 DPRINTF(sc, ATH_DEBUG_BEACON, 248 "%s: %s beacons bslot %d intval %u tsfadjust %llu\n", 249 __func__, sc->sc_stagbeacons ? "stagger" : "burst", 250 avp->av_bslot, ni->ni_intval, 251 (long long unsigned) le64toh(tsfadjust)); 252 253 wh = mtod(m, struct ieee80211_frame *); 254 memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust)); 255 } 256 bf->bf_m = m; 257 bf->bf_node = ieee80211_ref_node(ni); 258 259 return 0; 260} 261 262/* 263 * Setup the beacon frame for transmit. 264 */ 265static void 266ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 267{ 268#define USE_SHPREAMBLE(_ic) \ 269 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 270 == IEEE80211_F_SHPREAMBLE) 271 struct ieee80211_node *ni = bf->bf_node; 272 struct ieee80211com *ic = ni->ni_ic; 273 struct mbuf *m = bf->bf_m; 274 struct ath_hal *ah = sc->sc_ah; 275 struct ath_desc *ds; 276 int flags, antenna; 277 const HAL_RATE_TABLE *rt; 278 u_int8_t rix, rate; 279 HAL_DMA_ADDR bufAddrList[4]; 280 uint32_t segLenList[4]; 281 HAL_11N_RATE_SERIES rc[4]; 282 283 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n", 284 __func__, m, m->m_len); 285 286 /* setup descriptors */ 287 ds = bf->bf_desc; 288 bf->bf_last = bf; 289 bf->bf_lastds = ds; 290 291 flags = HAL_TXDESC_NOACK; 292 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 293 /* self-linked descriptor */ 294 ath_hal_settxdesclink(sc->sc_ah, ds, bf->bf_daddr); 295 flags |= HAL_TXDESC_VEOL; 296 /* 297 * Let hardware handle antenna switching. 298 */ 299 antenna = sc->sc_txantenna; 300 } else { 301 ath_hal_settxdesclink(sc->sc_ah, ds, 0); 302 /* 303 * Switch antenna every 4 beacons. 304 * XXX assumes two antenna 305 */ 306 if (sc->sc_txantenna != 0) 307 antenna = sc->sc_txantenna; 308 else if (sc->sc_stagbeacons && sc->sc_nbcnvaps != 0) 309 antenna = ((sc->sc_stats.ast_be_xmit / sc->sc_nbcnvaps) & 4 ? 2 : 1); 310 else 311 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 312 } 313 314 KASSERT(bf->bf_nseg == 1, 315 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 316 317 /* 318 * Calculate rate code. 319 * XXX everything at min xmit rate 320 */ 321 rix = 0; 322 rt = sc->sc_currates; 323 rate = rt->info[rix].rateCode; 324 if (USE_SHPREAMBLE(ic)) 325 rate |= rt->info[rix].shortPreamble; 326 ath_hal_setuptxdesc(ah, ds 327 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 328 , sizeof(struct ieee80211_frame)/* header length */ 329 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 330 , ieee80211_get_node_txpower(ni) /* txpower XXX */ 331 , rate, 1 /* series 0 rate/tries */ 332 , HAL_TXKEYIX_INVALID /* no encryption */ 333 , antenna /* antenna mode */ 334 , flags /* no ack, veol for beacons */ 335 , 0 /* rts/cts rate */ 336 , 0 /* rts/cts duration */ 337 ); 338 339 /* 340 * The EDMA HAL currently assumes that _all_ rate control 341 * settings are done in ath_hal_set11nratescenario(), rather 342 * than in ath_hal_setuptxdesc(). 343 */ 344 if (sc->sc_isedma) { 345 memset(&rc, 0, sizeof(rc)); 346 347 rc[0].ChSel = sc->sc_txchainmask; 348 rc[0].Tries = 1; 349 rc[0].Rate = rt->info[rix].rateCode; 350 rc[0].RateIndex = rix; 351 rc[0].tx_power_cap = 0x3f; 352 rc[0].PktDuration = 353 ath_hal_computetxtime(ah, rt, roundup(m->m_len, 4), 354 rix, 0, AH_TRUE); 355 ath_hal_set11nratescenario(ah, ds, 0, 0, rc, 4, flags); 356 } 357 358 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 359 segLenList[0] = roundup(m->m_len, 4); 360 segLenList[1] = segLenList[2] = segLenList[3] = 0; 361 bufAddrList[0] = bf->bf_segs[0].ds_addr; 362 bufAddrList[1] = bufAddrList[2] = bufAddrList[3] = 0; 363 ath_hal_filltxdesc(ah, ds 364 , bufAddrList 365 , segLenList 366 , 0 /* XXX desc id */ 367 , sc->sc_bhalq /* hardware TXQ */ 368 , AH_TRUE /* first segment */ 369 , AH_TRUE /* last segment */ 370 , ds /* first descriptor */ 371 ); 372#if 0 373 ath_desc_swap(ds); 374#endif 375#undef USE_SHPREAMBLE 376} 377 378void 379ath_beacon_update(struct ieee80211vap *vap, int item) 380{ 381 struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off; 382 383 setbit(bo->bo_flags, item); 384} 385 386/* 387 * Handle a beacon miss. 388 */ 389void 390ath_beacon_miss(struct ath_softc *sc) 391{ 392 HAL_SURVEY_SAMPLE hs; 393 HAL_BOOL ret; 394 uint32_t hangs; 395 396 bzero(&hs, sizeof(hs)); 397 398 ret = ath_hal_get_mib_cycle_counts(sc->sc_ah, &hs); 399 400 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) && hangs != 0) { 401 DPRINTF(sc, ATH_DEBUG_BEACON, 402 "%s: hang=0x%08x\n", 403 __func__, 404 hangs); 405 } 406 407#ifdef ATH_DEBUG_ALQ 408 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_MISSED_BEACON)) 409 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_MISSED_BEACON, 0, NULL); 410#endif 411 412 DPRINTF(sc, ATH_DEBUG_BEACON, 413 "%s: valid=%d, txbusy=%u, rxbusy=%u, chanbusy=%u, " 414 "extchanbusy=%u, cyclecount=%u\n", 415 __func__, 416 ret, 417 hs.tx_busy, 418 hs.rx_busy, 419 hs.chan_busy, 420 hs.ext_chan_busy, 421 hs.cycle_count); 422} 423 424/* 425 * Transmit a beacon frame at SWBA. Dynamic updates to the 426 * frame contents are done as needed and the slot time is 427 * also adjusted based on current state. 428 */ 429void 430ath_beacon_proc(void *arg, int pending) 431{ 432 struct ath_softc *sc = arg; 433 struct ath_hal *ah = sc->sc_ah; 434 struct ieee80211vap *vap; 435 struct ath_buf *bf; 436 int slot, otherant; 437 uint32_t bfaddr; 438 439 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 440 __func__, pending); 441 /* 442 * Check if the previous beacon has gone out. If 443 * not don't try to post another, skip this period 444 * and wait for the next. Missed beacons indicate 445 * a problem and should not occur. If we miss too 446 * many consecutive beacons reset the device. 447 */ 448 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 449 450 sc->sc_bmisscount++; 451 sc->sc_stats.ast_be_missed++; 452 ath_beacon_miss(sc); 453 454 DPRINTF(sc, ATH_DEBUG_BEACON, 455 "%s: missed %u consecutive beacons\n", 456 __func__, sc->sc_bmisscount); 457 if (sc->sc_bmisscount >= ath_bstuck_threshold) 458 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 459 return; 460 } 461 if (sc->sc_bmisscount != 0) { 462 DPRINTF(sc, ATH_DEBUG_BEACON, 463 "%s: resume beacon xmit after %u misses\n", 464 __func__, sc->sc_bmisscount); 465 sc->sc_bmisscount = 0; 466#ifdef ATH_DEBUG_ALQ 467 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_RESUME_BEACON)) 468 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_RESUME_BEACON, 0, NULL); 469#endif 470 } 471 472 if (sc->sc_stagbeacons) { /* staggered beacons */ 473 struct ieee80211com *ic = &sc->sc_ic; 474 uint32_t tsftu; 475 476 tsftu = ath_hal_gettsf32(ah) >> 10; 477 /* XXX lintval */ 478 slot = ((tsftu % ic->ic_lintval) * ATH_BCBUF) / ic->ic_lintval; 479 vap = sc->sc_bslot[(slot+1) % ATH_BCBUF]; 480 bfaddr = 0; 481 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 482 bf = ath_beacon_generate(sc, vap); 483 if (bf != NULL) 484 bfaddr = bf->bf_daddr; 485 } 486 } else { /* burst'd beacons */ 487 uint32_t *bflink = &bfaddr; 488 489 for (slot = 0; slot < ATH_BCBUF; slot++) { 490 vap = sc->sc_bslot[slot]; 491 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 492 bf = ath_beacon_generate(sc, vap); 493 /* 494 * XXX TODO: this should use settxdesclinkptr() 495 * otherwise it won't work for EDMA chipsets! 496 */ 497 if (bf != NULL) { 498 /* XXX should do this using the ds */ 499 *bflink = bf->bf_daddr; 500 ath_hal_gettxdesclinkptr(sc->sc_ah, 501 bf->bf_desc, &bflink); 502 } 503 } 504 } 505 /* 506 * XXX TODO: this should use settxdesclinkptr() 507 * otherwise it won't work for EDMA chipsets! 508 */ 509 *bflink = 0; /* terminate list */ 510 } 511 512 /* 513 * Handle slot time change when a non-ERP station joins/leaves 514 * an 11g network. The 802.11 layer notifies us via callback, 515 * we mark updateslot, then wait one beacon before effecting 516 * the change. This gives associated stations at least one 517 * beacon interval to note the state change. 518 */ 519 /* XXX locking */ 520 if (sc->sc_updateslot == UPDATE) { 521 sc->sc_updateslot = COMMIT; /* commit next beacon */ 522 sc->sc_slotupdate = slot; 523 } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot) 524 ath_setslottime(sc); /* commit change to h/w */ 525 526 /* 527 * Check recent per-antenna transmit statistics and flip 528 * the default antenna if noticeably more frames went out 529 * on the non-default antenna. 530 * XXX assumes 2 anntenae 531 */ 532 if (!sc->sc_diversity && (!sc->sc_stagbeacons || slot == 0)) { 533 otherant = sc->sc_defant & 1 ? 2 : 1; 534 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 535 ath_setdefantenna(sc, otherant); 536 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 537 } 538 539 /* Program the CABQ with the contents of the CABQ txq and start it */ 540 ATH_TXQ_LOCK(sc->sc_cabq); 541 ath_beacon_cabq_start(sc); 542 ATH_TXQ_UNLOCK(sc->sc_cabq); 543 544 /* Program the new beacon frame if we have one for this interval */ 545 if (bfaddr != 0) { 546 /* 547 * Stop any current dma and put the new frame on the queue. 548 * This should never fail since we check above that no frames 549 * are still pending on the queue. 550 */ 551 if (! sc->sc_isedma) { 552 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 553 DPRINTF(sc, ATH_DEBUG_ANY, 554 "%s: beacon queue %u did not stop?\n", 555 __func__, sc->sc_bhalq); 556 } 557 } 558 /* NB: cabq traffic should already be queued and primed */ 559 560 ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr); 561 ath_hal_txstart(ah, sc->sc_bhalq); 562 563 sc->sc_stats.ast_be_xmit++; 564 } 565} 566 567static void 568ath_beacon_cabq_start_edma(struct ath_softc *sc) 569{ 570 struct ath_buf *bf, *bf_last; 571 struct ath_txq *cabq = sc->sc_cabq; 572#if 0 573 struct ath_buf *bfi; 574 int i = 0; 575#endif 576 577 ATH_TXQ_LOCK_ASSERT(cabq); 578 579 if (TAILQ_EMPTY(&cabq->axq_q)) 580 return; 581 bf = TAILQ_FIRST(&cabq->axq_q); 582 bf_last = TAILQ_LAST(&cabq->axq_q, axq_q_s); 583 584 /* 585 * This is a dirty, dirty hack to push the contents of 586 * the cabq staging queue into the FIFO. 587 * 588 * This ideally should live in the EDMA code file 589 * and only push things into the CABQ if there's a FIFO 590 * slot. 591 * 592 * We can't treat this like a normal TX queue because 593 * in the case of multi-VAP traffic, we may have to flush 594 * the CABQ each new (staggered) beacon that goes out. 595 * But for non-staggered beacons, we could in theory 596 * handle multicast traffic for all VAPs in one FIFO 597 * push. Just keep all of this in mind if you're wondering 598 * how to correctly/better handle multi-VAP CABQ traffic 599 * with EDMA. 600 */ 601 602 /* 603 * Is the CABQ FIFO free? If not, complain loudly and 604 * don't queue anything. Maybe we'll flush the CABQ 605 * traffic, maybe we won't. But that'll happen next 606 * beacon interval. 607 */ 608 if (cabq->axq_fifo_depth >= HAL_TXFIFO_DEPTH) { 609 device_printf(sc->sc_dev, 610 "%s: Q%d: CAB FIFO queue=%d?\n", 611 __func__, 612 cabq->axq_qnum, 613 cabq->axq_fifo_depth); 614 return; 615 } 616 617 /* 618 * Ok, so here's the gymnastics reqiured to make this 619 * all sensible. 620 */ 621 622 /* 623 * Tag the first/last buffer appropriately. 624 */ 625 bf->bf_flags |= ATH_BUF_FIFOPTR; 626 bf_last->bf_flags |= ATH_BUF_FIFOEND; 627 628#if 0 629 i = 0; 630 TAILQ_FOREACH(bfi, &cabq->axq_q, bf_list) { 631 ath_printtxbuf(sc, bf, cabq->axq_qnum, i, 0); 632 i++; 633 } 634#endif 635 636 /* 637 * We now need to push this set of frames onto the tail 638 * of the FIFO queue. We don't adjust the aggregate 639 * count, only the queue depth counter(s). 640 * We also need to blank the link pointer now. 641 */ 642 TAILQ_CONCAT(&cabq->fifo.axq_q, &cabq->axq_q, bf_list); 643 cabq->axq_link = NULL; 644 cabq->fifo.axq_depth += cabq->axq_depth; 645 cabq->axq_depth = 0; 646 647 /* Bump FIFO queue */ 648 cabq->axq_fifo_depth++; 649 650 /* Push the first entry into the hardware */ 651 ath_hal_puttxbuf(sc->sc_ah, cabq->axq_qnum, bf->bf_daddr); 652 cabq->axq_flags |= ATH_TXQ_PUTRUNNING; 653 654 /* NB: gated by beacon so safe to start here */ 655 ath_hal_txstart(sc->sc_ah, cabq->axq_qnum); 656 657} 658 659static void 660ath_beacon_cabq_start_legacy(struct ath_softc *sc) 661{ 662 struct ath_buf *bf; 663 struct ath_txq *cabq = sc->sc_cabq; 664 665 ATH_TXQ_LOCK_ASSERT(cabq); 666 if (TAILQ_EMPTY(&cabq->axq_q)) 667 return; 668 bf = TAILQ_FIRST(&cabq->axq_q); 669 670 /* Push the first entry into the hardware */ 671 ath_hal_puttxbuf(sc->sc_ah, cabq->axq_qnum, bf->bf_daddr); 672 cabq->axq_flags |= ATH_TXQ_PUTRUNNING; 673 674 /* NB: gated by beacon so safe to start here */ 675 ath_hal_txstart(sc->sc_ah, cabq->axq_qnum); 676} 677 678/* 679 * Start CABQ transmission - this assumes that all frames are prepped 680 * and ready in the CABQ. 681 */ 682void 683ath_beacon_cabq_start(struct ath_softc *sc) 684{ 685 struct ath_txq *cabq = sc->sc_cabq; 686 687 ATH_TXQ_LOCK_ASSERT(cabq); 688 689 if (TAILQ_EMPTY(&cabq->axq_q)) 690 return; 691 692 if (sc->sc_isedma) 693 ath_beacon_cabq_start_edma(sc); 694 else 695 ath_beacon_cabq_start_legacy(sc); 696} 697 698struct ath_buf * 699ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap) 700{ 701 struct ath_vap *avp = ATH_VAP(vap); 702 struct ath_txq *cabq = sc->sc_cabq; 703 struct ath_buf *bf; 704 struct mbuf *m; 705 int nmcastq, error; 706 707 KASSERT(vap->iv_state >= IEEE80211_S_RUN, 708 ("not running, state %d", vap->iv_state)); 709 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 710 711 /* 712 * Update dynamic beacon contents. If this returns 713 * non-zero then we need to remap the memory because 714 * the beacon frame changed size (probably because 715 * of the TIM bitmap). 716 */ 717 bf = avp->av_bcbuf; 718 m = bf->bf_m; 719 /* XXX lock mcastq? */ 720 nmcastq = avp->av_mcastq.axq_depth; 721 722 if (ieee80211_beacon_update(bf->bf_node, m, nmcastq)) { 723 /* XXX too conservative? */ 724 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 725 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 726 bf->bf_segs, &bf->bf_nseg, 727 BUS_DMA_NOWAIT); 728 if (error != 0) { 729 if_printf(vap->iv_ifp, 730 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 731 __func__, error); 732 return NULL; 733 } 734 } 735 if ((vap->iv_bcn_off.bo_tim[4] & 1) && cabq->axq_depth) { 736 DPRINTF(sc, ATH_DEBUG_BEACON, 737 "%s: cabq did not drain, mcastq %u cabq %u\n", 738 __func__, nmcastq, cabq->axq_depth); 739 sc->sc_stats.ast_cabq_busy++; 740 if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) { 741 /* 742 * CABQ traffic from a previous vap is still pending. 743 * We must drain the q before this beacon frame goes 744 * out as otherwise this vap's stations will get cab 745 * frames from a different vap. 746 * XXX could be slow causing us to miss DBA 747 */ 748 /* 749 * XXX TODO: this doesn't stop CABQ DMA - it assumes 750 * that since we're about to transmit a beacon, we've 751 * already stopped transmitting on the CABQ. But this 752 * doesn't at all mean that the CABQ DMA QCU will 753 * accept a new TXDP! So what, should we do a DMA 754 * stop? What if it fails? 755 * 756 * More thought is required here. 757 */ 758 /* 759 * XXX can we even stop TX DMA here? Check what the 760 * reference driver does for cabq for beacons, given 761 * that stopping TX requires RX is paused. 762 */ 763 ath_tx_draintxq(sc, cabq); 764 } 765 } 766 ath_beacon_setup(sc, bf); 767 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 768 769 /* 770 * XXX TODO: tie into net80211 for quiet time IE update and program 771 * local AP timer if we require it. The process of updating the 772 * beacon will also update the IE with the relevant counters. 773 */ 774 775 /* 776 * Enable the CAB queue before the beacon queue to 777 * insure cab frames are triggered by this beacon. 778 */ 779 if (vap->iv_bcn_off.bo_tim[4] & 1) { 780 /* NB: only at DTIM */ 781 ATH_TXQ_LOCK(&avp->av_mcastq); 782 if (nmcastq) { 783 struct ath_buf *bfm, *bfc_last; 784 785 /* 786 * Move frames from the s/w mcast q to the h/w cab q. 787 * 788 * XXX TODO: if we chain together multiple VAPs 789 * worth of CABQ traffic, should we keep the 790 * MORE data bit set on the last frame of each 791 * intermediary VAP (ie, only clear the MORE 792 * bit of the last frame on the last vap?) 793 */ 794 bfm = TAILQ_FIRST(&avp->av_mcastq.axq_q); 795 ATH_TXQ_LOCK(cabq); 796 797 /* 798 * If there's already a frame on the CABQ, we 799 * need to link to the end of the last frame. 800 * We can't use axq_link here because 801 * EDMA descriptors require some recalculation 802 * (checksum) to occur. 803 */ 804 bfc_last = ATH_TXQ_LAST(cabq, axq_q_s); 805 if (bfc_last != NULL) { 806 ath_hal_settxdesclink(sc->sc_ah, 807 bfc_last->bf_lastds, 808 bfm->bf_daddr); 809 } 810 ath_txqmove(cabq, &avp->av_mcastq); 811 ATH_TXQ_UNLOCK(cabq); 812 /* 813 * XXX not entirely accurate, in case a mcast 814 * queue frame arrived before we grabbed the TX 815 * lock. 816 */ 817 sc->sc_stats.ast_cabq_xmit += nmcastq; 818 } 819 ATH_TXQ_UNLOCK(&avp->av_mcastq); 820 } 821 return bf; 822} 823 824void 825ath_beacon_start_adhoc(struct ath_softc *sc, struct ieee80211vap *vap) 826{ 827 struct ath_vap *avp = ATH_VAP(vap); 828 struct ath_hal *ah = sc->sc_ah; 829 struct ath_buf *bf; 830 struct mbuf *m; 831 int error; 832 833 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 834 835 /* 836 * Update dynamic beacon contents. If this returns 837 * non-zero then we need to remap the memory because 838 * the beacon frame changed size (probably because 839 * of the TIM bitmap). 840 */ 841 bf = avp->av_bcbuf; 842 m = bf->bf_m; 843 if (ieee80211_beacon_update(bf->bf_node, m, 0)) { 844 /* XXX too conservative? */ 845 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 846 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 847 bf->bf_segs, &bf->bf_nseg, 848 BUS_DMA_NOWAIT); 849 if (error != 0) { 850 if_printf(vap->iv_ifp, 851 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 852 __func__, error); 853 return; 854 } 855 } 856 ath_beacon_setup(sc, bf); 857 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 858 859 /* NB: caller is known to have already stopped tx dma */ 860 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 861 ath_hal_txstart(ah, sc->sc_bhalq); 862} 863 864/* 865 * Reclaim beacon resources and return buffer to the pool. 866 */ 867void 868ath_beacon_return(struct ath_softc *sc, struct ath_buf *bf) 869{ 870 871 DPRINTF(sc, ATH_DEBUG_NODE, "%s: free bf=%p, bf_m=%p, bf_node=%p\n", 872 __func__, bf, bf->bf_m, bf->bf_node); 873 if (bf->bf_m != NULL) { 874 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 875 m_freem(bf->bf_m); 876 bf->bf_m = NULL; 877 } 878 if (bf->bf_node != NULL) { 879 ieee80211_free_node(bf->bf_node); 880 bf->bf_node = NULL; 881 } 882 TAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list); 883} 884 885/* 886 * Reclaim beacon resources. 887 */ 888void 889ath_beacon_free(struct ath_softc *sc) 890{ 891 struct ath_buf *bf; 892 893 TAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 894 DPRINTF(sc, ATH_DEBUG_NODE, 895 "%s: free bf=%p, bf_m=%p, bf_node=%p\n", 896 __func__, bf, bf->bf_m, bf->bf_node); 897 if (bf->bf_m != NULL) { 898 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 899 m_freem(bf->bf_m); 900 bf->bf_m = NULL; 901 } 902 if (bf->bf_node != NULL) { 903 ieee80211_free_node(bf->bf_node); 904 bf->bf_node = NULL; 905 } 906 } 907} 908 909/* 910 * Configure the beacon and sleep timers. 911 * 912 * When operating as an AP this resets the TSF and sets 913 * up the hardware to notify us when we need to issue beacons. 914 * 915 * When operating in station mode this sets up the beacon 916 * timers according to the timestamp of the last received 917 * beacon and the current TSF, configures PCF and DTIM 918 * handling, programs the sleep registers so the hardware 919 * will wakeup in time to receive beacons, and configures 920 * the beacon miss handling so we'll receive a BMISS 921 * interrupt when we stop seeing beacons from the AP 922 * we've associated with. 923 */ 924void 925ath_beacon_config(struct ath_softc *sc, struct ieee80211vap *vap) 926{ 927#define TSF_TO_TU(_h,_l) \ 928 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 929#define FUDGE 2 930 struct ath_hal *ah = sc->sc_ah; 931 struct ath_vap *avp; 932 struct ieee80211com *ic = &sc->sc_ic; 933 struct ieee80211_node *ni; 934 u_int32_t nexttbtt, intval, tsftu; 935 u_int32_t nexttbtt_u8, intval_u8; 936 u_int64_t tsf, tsf_beacon; 937 938 /* 939 * Find the first VAP that we /can/ use a beacon configuration for. 940 * If it's a STA VAP then if it has SWBMISS set we should ignore it. 941 * 942 * Yes, ideally we'd not have a STA without SWBMISS followed by an 943 * AP STA, and yes this isn't ready for P2P/TSF2 logic on AR9300 and 944 * later chips. 945 */ 946 if (vap == NULL) { 947 IEEE80211_LOCK(ic); 948 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 949 /* A STA VAP w/ SWBMISS set can't be used for beaconing */ 950 if ((vap->iv_opmode == IEEE80211_M_STA) && 951 ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) != 0)) 952 continue; 953 break; 954 } 955 IEEE80211_UNLOCK(ic); 956 } 957 958 if (vap == NULL) { 959 device_printf(sc->sc_dev, "called with no valid vaps?\n"); 960 return; 961 } 962 963 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) != 0) { 964 device_printf(sc->sc_dev, "called on VAP with SWBMISS set?\n"); 965 return; 966 } 967 968 /* Now that we have a vap, we can do this bit */ 969 avp = ATH_VAP(vap); 970 971 ni = ieee80211_ref_node(vap->iv_bss); 972 973 ATH_LOCK(sc); 974 ath_power_set_power_state(sc, HAL_PM_AWAKE); 975 ATH_UNLOCK(sc); 976 977 /* Always clear the quiet IE timers; let the next update program them */ 978 ath_hal_set_quiet(ah, 0, 0, 0, HAL_QUIET_DISABLE); 979 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie)); 980 981 /* extract tstamp from last beacon and convert to TU */ 982 nexttbtt = TSF_TO_TU(le32dec(ni->ni_tstamp.data + 4), 983 le32dec(ni->ni_tstamp.data)); 984 985 tsf_beacon = ((uint64_t) le32dec(ni->ni_tstamp.data + 4)) << 32; 986 tsf_beacon |= le32dec(ni->ni_tstamp.data); 987 988 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 989 ic->ic_opmode == IEEE80211_M_MBSS) { 990 /* 991 * For multi-bss ap/mesh support beacons are either staggered 992 * evenly over N slots or burst together. For the former 993 * arrange for the SWBA to be delivered for each slot. 994 * Slots that are not occupied will generate nothing. 995 */ 996 /* NB: the beacon interval is kept internally in TU's */ 997 intval = ni->ni_intval & HAL_BEACON_PERIOD; 998 if (sc->sc_stagbeacons) 999 intval /= ATH_BCBUF; 1000 } else { 1001 /* NB: the beacon interval is kept internally in TU's */ 1002 intval = ni->ni_intval & HAL_BEACON_PERIOD; 1003 } 1004 1005 /* 1006 * Note: rounding up to the next intval can cause problems with 1007 * bad APs when we're in powersave mode. 1008 * 1009 * In STA mode with powersave enabled, beacons are only received 1010 * whenever the beacon timer fires to wake up the hardware. 1011 * Now, if this is rounded up to the next intval, it assumes 1012 * that the AP has started transmitting beacons at TSF values that 1013 * are multiples of intval, versus say being 25 TU off. 1014 * 1015 * The specification (802.11-2012 10.1.3.2 - Beacon Generation in 1016 * Infrastructure Networks) requires APs be beaconing at a 1017 * multiple of intval. So, if bintval=100, then we shouldn't 1018 * get beacons at intervals other than around multiples of 100. 1019 */ 1020 if (nexttbtt == 0) /* e.g. for ap mode */ 1021 nexttbtt = intval; 1022 else 1023 nexttbtt = roundup(nexttbtt, intval); 1024 1025 1026 if (ic->ic_opmode == IEEE80211_M_STA && !sc->sc_swbmiss) { 1027 HAL_BEACON_STATE bs; 1028 int dtimperiod, dtimcount; 1029 int cfpperiod, cfpcount; 1030 1031 /* 1032 * Setup dtim and cfp parameters according to 1033 * last beacon we received (which may be none). 1034 */ 1035 dtimperiod = ni->ni_dtim_period; 1036 if (dtimperiod <= 0) /* NB: 0 if not known */ 1037 dtimperiod = 1; 1038 dtimcount = ni->ni_dtim_count; 1039 if (dtimcount >= dtimperiod) /* NB: sanity check */ 1040 dtimcount = 0; /* XXX? */ 1041 cfpperiod = 1; /* NB: no PCF support yet */ 1042 cfpcount = 0; 1043 /* 1044 * Pull nexttbtt forward to reflect the current 1045 * TSF and calculate dtim+cfp state for the result. 1046 */ 1047 tsf = ath_hal_gettsf64(ah); 1048 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 1049 1050 DPRINTF(sc, ATH_DEBUG_BEACON, 1051 "%s: beacon tsf=%llu, hw tsf=%llu, nexttbtt=%u, tsftu=%u\n", 1052 __func__, 1053 (unsigned long long) tsf_beacon, 1054 (unsigned long long) tsf, 1055 nexttbtt, 1056 tsftu); 1057 DPRINTF(sc, ATH_DEBUG_BEACON, 1058 "%s: beacon tsf=%llu, hw tsf=%llu, tsf delta=%lld\n", 1059 __func__, 1060 (unsigned long long) tsf_beacon, 1061 (unsigned long long) tsf, 1062 (long long) tsf - 1063 (long long) tsf_beacon); 1064 1065 DPRINTF(sc, ATH_DEBUG_BEACON, 1066 "%s: nexttbtt=%llu, beacon tsf delta=%lld\n", 1067 __func__, 1068 (unsigned long long) nexttbtt, 1069 (long long) ((long long) nexttbtt * 1024LL) - (long long) tsf_beacon); 1070 1071 /* XXX cfpcount? */ 1072 1073 if (nexttbtt > tsftu) { 1074 uint32_t countdiff, oldtbtt, remainder; 1075 1076 oldtbtt = nexttbtt; 1077 remainder = (nexttbtt - tsftu) % intval; 1078 nexttbtt = tsftu + remainder; 1079 1080 countdiff = (oldtbtt - nexttbtt) / intval % dtimperiod; 1081 if (dtimcount > countdiff) { 1082 dtimcount -= countdiff; 1083 } else { 1084 dtimcount += dtimperiod - countdiff; 1085 } 1086 } else { //nexttbtt <= tsftu 1087 uint32_t countdiff, oldtbtt, remainder; 1088 1089 oldtbtt = nexttbtt; 1090 remainder = (tsftu - nexttbtt) % intval; 1091 nexttbtt = tsftu - remainder + intval; 1092 countdiff = (nexttbtt - oldtbtt) / intval % dtimperiod; 1093 if (dtimcount > countdiff) { 1094 dtimcount -= countdiff; 1095 } else { 1096 dtimcount += dtimperiod - countdiff; 1097 } 1098 } 1099 1100 DPRINTF(sc, ATH_DEBUG_BEACON, 1101 "%s: adj nexttbtt=%llu, rx tsf delta=%lld\n", 1102 __func__, 1103 (unsigned long long) nexttbtt, 1104 (long long) ((long long)nexttbtt * 1024LL) - (long long)tsf); 1105 1106 memset(&bs, 0, sizeof(bs)); 1107 bs.bs_intval = intval; 1108 bs.bs_nexttbtt = nexttbtt; 1109 bs.bs_dtimperiod = dtimperiod*intval; 1110 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 1111 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 1112 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 1113 bs.bs_cfpmaxduration = 0; 1114#if 0 1115 /* 1116 * The 802.11 layer records the offset to the DTIM 1117 * bitmap while receiving beacons; use it here to 1118 * enable h/w detection of our AID being marked in 1119 * the bitmap vector (to indicate frames for us are 1120 * pending at the AP). 1121 * XXX do DTIM handling in s/w to WAR old h/w bugs 1122 * XXX enable based on h/w rev for newer chips 1123 */ 1124 bs.bs_timoffset = ni->ni_timoff; 1125#endif 1126 /* 1127 * Calculate the number of consecutive beacons to miss 1128 * before taking a BMISS interrupt. 1129 * Note that we clamp the result to at most 10 beacons. 1130 */ 1131 bs.bs_bmissthreshold = vap->iv_bmissthreshold; 1132 if (bs.bs_bmissthreshold > 10) 1133 bs.bs_bmissthreshold = 10; 1134 else if (bs.bs_bmissthreshold <= 0) 1135 bs.bs_bmissthreshold = 1; 1136 1137 /* 1138 * Calculate sleep duration. The configuration is 1139 * given in ms. We insure a multiple of the beacon 1140 * period is used. Also, if the sleep duration is 1141 * greater than the DTIM period then it makes senses 1142 * to make it a multiple of that. 1143 * 1144 * XXX fixed at 100ms 1145 */ 1146 bs.bs_sleepduration = 1147 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 1148 if (bs.bs_sleepduration > bs.bs_dtimperiod) 1149 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 1150 1151 DPRINTF(sc, ATH_DEBUG_BEACON, 1152 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u " 1153 "nextdtim %u bmiss %u sleep %u cfp:period %u " 1154 "maxdur %u next %u timoffset %u\n" 1155 , __func__ 1156 , tsf 1157 , tsftu 1158 , bs.bs_intval 1159 , bs.bs_nexttbtt 1160 , bs.bs_dtimperiod 1161 , bs.bs_nextdtim 1162 , bs.bs_bmissthreshold 1163 , bs.bs_sleepduration 1164 , bs.bs_cfpperiod 1165 , bs.bs_cfpmaxduration 1166 , bs.bs_cfpnext 1167 , bs.bs_timoffset 1168 ); 1169 ath_hal_intrset(ah, 0); 1170 ath_hal_beacontimers(ah, &bs); 1171 sc->sc_imask |= HAL_INT_BMISS; 1172 ath_hal_intrset(ah, sc->sc_imask); 1173 } else { 1174 ath_hal_intrset(ah, 0); 1175 if (nexttbtt == intval) 1176 intval |= HAL_BEACON_RESET_TSF; 1177 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1178 /* 1179 * In IBSS mode enable the beacon timers but only 1180 * enable SWBA interrupts if we need to manually 1181 * prepare beacon frames. Otherwise we use a 1182 * self-linked tx descriptor and let the hardware 1183 * deal with things. 1184 */ 1185 intval |= HAL_BEACON_ENA; 1186 if (!sc->sc_hasveol) 1187 sc->sc_imask |= HAL_INT_SWBA; 1188 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 1189 /* 1190 * Pull nexttbtt forward to reflect 1191 * the current TSF. 1192 */ 1193 tsf = ath_hal_gettsf64(ah); 1194 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 1195 do { 1196 nexttbtt += intval; 1197 } while (nexttbtt < tsftu); 1198 } 1199 ath_beaconq_config(sc); 1200 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP || 1201 ic->ic_opmode == IEEE80211_M_MBSS) { 1202 /* 1203 * In AP/mesh mode we enable the beacon timers 1204 * and SWBA interrupts to prepare beacon frames. 1205 */ 1206 intval |= HAL_BEACON_ENA; 1207 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 1208 ath_beaconq_config(sc); 1209 } 1210 1211 /* 1212 * Now dirty things because for now, the EDMA HAL has 1213 * nexttbtt and intval is TU/8. 1214 */ 1215 if (sc->sc_isedma) { 1216 nexttbtt_u8 = (nexttbtt << 3) & HAL_BEACON_PERIOD_TU8; 1217 intval_u8 = (intval << 3) & HAL_BEACON_PERIOD_TU8; 1218 if (intval & HAL_BEACON_ENA) 1219 intval_u8 |= HAL_BEACON_ENA; 1220 if (intval & HAL_BEACON_RESET_TSF) 1221 intval_u8 |= HAL_BEACON_RESET_TSF; 1222 ath_hal_beaconinit(ah, nexttbtt_u8, intval_u8); 1223 } else 1224 ath_hal_beaconinit(ah, nexttbtt, intval); 1225 sc->sc_bmisscount = 0; 1226 ath_hal_intrset(ah, sc->sc_imask); 1227 /* 1228 * When using a self-linked beacon descriptor in 1229 * ibss mode load it once here. 1230 */ 1231 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 1232 ath_beacon_start_adhoc(sc, vap); 1233 } 1234 ieee80211_free_node(ni); 1235 1236 tsf = ath_hal_gettsf64(ah); 1237 DPRINTF(sc, ATH_DEBUG_BEACON, 1238 "%s: nexttbtt %u intval %u (%u), tsf64=%llu tsfbeacon=%llu delta=%lld\n", 1239 __func__, nexttbtt, intval, ni->ni_intval, 1240 (unsigned long long) tsf, 1241 (unsigned long long) tsf_beacon, 1242 (long long) tsf - 1243 (long long) tsf_beacon); 1244 1245 ATH_LOCK(sc); 1246 ath_power_restore_power_state(sc); 1247 ATH_UNLOCK(sc); 1248#undef FUDGE 1249#undef TSF_TO_TU 1250} 1251