1139790Simp/*- 24Srgrimes * SPDX-License-Identifier: ISC 34Srgrimes * 44Srgrimes * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 54Srgrimes * Copyright (c) 2002-2008 Atheros Communications, Inc. 64Srgrimes * 74Srgrimes * Permission to use, copy, modify, and/or distribute this software for any 84Srgrimes * purpose with or without fee is hereby granted, provided that the above 94Srgrimes * copyright notice and this permission notice appear in all copies. 104Srgrimes * 114Srgrimes * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 124Srgrimes * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 134Srgrimes * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 144Srgrimes * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 154Srgrimes * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 164Srgrimes * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 174Srgrimes * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 184Srgrimes */ 194Srgrimes#ifndef _ATH_AH_INTERAL_H_ 204Srgrimes#define _ATH_AH_INTERAL_H_ 214Srgrimes/* 224Srgrimes * Atheros Device Hardware Access Layer (HAL). 234Srgrimes * 244Srgrimes * Internal definitions. 254Srgrimes */ 264Srgrimes#define AH_NULL 0 274Srgrimes#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 284Srgrimes#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 294Srgrimes 304Srgrimes#include <net80211/_ieee80211.h> 314Srgrimes#include <sys/queue.h> /* XXX for reasons */ 324Srgrimes 334Srgrimes#ifndef NBBY 344Srgrimes#define NBBY 8 /* number of bits/byte */ 354Srgrimes#endif 364Srgrimes 374Srgrimes#ifndef roundup 384Srgrimes#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 39607Srgrimes#endif 40607Srgrimes#ifndef howmany 4150477Speter#define howmany(x, y) (((x)+((y)-1))/(y)) 424Srgrimes#endif 434Srgrimes 444471Sbde#ifndef offsetof 454471Sbde#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 464Srgrimes#endif 4715565Sphk 48153179Sjhbtypedef struct { 4915565Sphk uint32_t start; /* first register */ 5015565Sphk uint32_t end; /* ending register or zero */ 5115565Sphk} HAL_REGRANGE; 5215565Sphk 5315565Sphktypedef struct { 5415565Sphk uint32_t addr; /* regiser address/offset */ 5515565Sphk uint32_t value; /* value to write */ 5615565Sphk} HAL_REGWRITE; 5715565Sphk 5815565Sphk/* 5915565Sphk * Transmit power scale factor. 60158238Sjhb * 6115565Sphk * NB: This is not public because we want to discourage the use of 6215565Sphk * scaling; folks should use the tx power limit interface. 6315565Sphk */ 6415565Sphktypedef enum { 65158238Sjhb HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 66168439Sru HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 67168439Sru HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 68168439Sru HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 694Srgrimes HAL_TP_SCALE_MIN = 4, /* min, but still on */ 704Srgrimes} HAL_TP_SCALE; 7115565Sphk 7215565Sphktypedef enum { 7315809Sdyson HAL_CAP_RADAR = 0, /* Radar capability */ 74168439Sru HAL_CAP_AR = 1, /* AR capability */ 75168439Sru} HAL_PHYDIAG_CAPS; 76168439Sru 77168439Sru/* 78168439Sru * Enable/disable strong signal fast diversity 79168439Sru */ 80168439Sru#define HAL_CAP_STRONG_DIV 2 8115565Sphk 8215565Sphk/* 8315565Sphk * Each chip or class of chips registers to offer support. 84196705Sjhb * 85196705Sjhb * Compiled-in versions will include a linker set to iterate through the 86196705Sjhb * linked in code. 87196705Sjhb * 884Srgrimes * Modules will have to register HAL backends separately. 89177659Salc */ 90177659Salcstruct ath_hal_chip { 91177659Salc const char *name; 92177659Salc const char *(*probe)(uint16_t vendorid, uint16_t devid); 93177659Salc struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 94177659Salc HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 95177659Salc HAL_OPS_CONFIG *ah, 9615543Sphk HAL_STATUS *error); 9715543Sphk TAILQ_ENTRY(ath_hal_chip) node; 9815543Sphk}; 9915543Sphk#ifndef AH_CHIP 10015543Sphk#define AH_CHIP(_name, _probe, _attach) \ 10115543Sphkstruct ath_hal_chip _name##_chip = { \ 102168668Salc .name = #_name, \ 103168439Sru .probe = _probe, \ 10415543Sphk .attach = _attach, \ 10515543Sphk}; \ 10683757SpeterOS_DATA_SET(ah_chips, _name##_chip) 10783757Speter#endif 10883757Speter 109175329Speter/* 110175329Speter * Each RF backend registers to offer support; this is mostly 11183757Speter * used by multi-chip 5212 solutions. Single-chip solutions 11283757Speter * have a fixed idea about which RF to use. 113112841Sjake * 114112841Sjake * Compiled in versions will include this linker set to iterate through 115112841Sjake * the linked in code. 11683757Speter * 11783757Speter * Modules will have to register RF backends separately. 118112841Sjake */ 11983757Speterstruct ath_hal_rf { 12083757Speter const char *name; 12115543Sphk HAL_BOOL (*probe)(struct ath_hal *ah); 12215543Sphk HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 12315543Sphk TAILQ_ENTRY(ath_hal_rf) node; 12415543Sphk}; 125164262Sru#ifndef AH_RF 126974Sdg#define AH_RF(_name, _probe, _attach) \ 127112841Sjakestruct ath_hal_rf _name##_rf = { \ 128164262Sru .name = __STRING(_name), \ 129164262Sru .probe = _probe, \ 130112841Sjake .attach = _attach, \ 131164262Sru}; \ 132164262SruOS_DATA_SET(ah_rfs, _name##_rf) 133974Sdg#endif 134112841Sjake 135164262Srustruct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 136974Sdg 137113225Sjake/* 138974Sdg * Maximum number of internal channels. Entries are per unique 139974Sdg * frequency so this might be need to be increased to handle all 140974Sdg * usage cases; typically no more than 32 are really needed but 141588Srgrimes * dynamically allocating the data structures is a bit painful 142588Srgrimes * right now. 143588Srgrimes */ 144588Srgrimes#ifndef AH_MAXCHAN 145588Srgrimes#define AH_MAXCHAN 128 146173592Speter#endif 147111363Sjake 1484Srgrimes#define HAL_NF_CAL_HIST_LEN_FULL 5 14915565Sphk#define HAL_NF_CAL_HIST_LEN_SMALL 1 15015565Sphk#define HAL_NUM_NF_READINGS 6 /* 3 chains * (ctl + ext) */ 15115565Sphk#define HAL_NF_LOAD_DELAY 1000 15215565Sphk 15315565Sphk/* 15415565Sphk * PER_CHAN doesn't work for now, as it looks like the device layer 15515543Sphk * has to pre-populate the per-channel list with nominal values. 15618163Sdyson */ 157130755Sbde//#define ATH_NF_PER_CHAN 1 158222813Sattilio 159130573Salctypedef struct { 160130573Salc u_int8_t curr_index; 16118163Sdyson int8_t invalidNFcount; /* TO DO: REMOVE THIS! */ 162248449Sattilio int16_t priv_nf[HAL_NUM_NF_READINGS]; 163248449Sattilio} HAL_NFCAL_BASE; 164112841Sjake 16515543Sphktypedef struct { 166112841Sjake HAL_NFCAL_BASE base; 167112841Sjake int16_t nf_cal_buffer[HAL_NF_CAL_HIST_LEN_FULL][HAL_NUM_NF_READINGS]; 168112841Sjake} HAL_NFCAL_HIST_FULL; 169112841Sjake 170112841Sjaketypedef struct { 171112841Sjake HAL_NFCAL_BASE base; 172112841Sjake int16_t nf_cal_buffer[HAL_NF_CAL_HIST_LEN_SMALL][HAL_NUM_NF_READINGS]; 173112841Sjake} HAL_NFCAL_HIST_SMALL; 174112841Sjake 175112841Sjake#ifdef ATH_NF_PER_CHAN 176112841Sjaketypedef HAL_NFCAL_HIST_FULL HAL_CHAN_NFCAL_HIST; 177112841Sjake#define AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (ichan ? &ichan->nf_cal_hist: NULL) 178111299Sjake#else 179111299Sjaketypedef HAL_NFCAL_HIST_SMALL HAL_CHAN_NFCAL_HIST; 180757Sdg#define AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (&AH_PRIVATE(ah)->nf_cal_hist) 181112841Sjake#endif /* ATH_NF_PER_CHAN */ 182112841Sjake 1834Srgrimes/* 184190272Salc * Internal per-channel state. These are found 1854Srgrimes * using ic_devdata in the ieee80211_channel. 18655205Speter */ 187113040Sjaketypedef struct { 188113040Sjake uint16_t channel; /* h/w frequency, NB: may be mapped */ 189113040Sjake uint8_t privFlags; 1904Srgrimes#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 191112841Sjake#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 192112841Sjake#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 193112841Sjake#define CHANNEL_MIMO_NF_VALID 0x04 /* Mimo NF values are valid */ 19499862Speter uint8_t calValid; /* bitmask of cal types */ 1954Srgrimes int8_t iCoff; 1964Srgrimes int8_t qCoff; 197213455Salc int16_t rawNoiseFloor; 198213455Salc int16_t noiseFloorAdjust; 199213455Salc int16_t noiseFloorCtl[AH_MAX_CHAINS]; 200213455Salc int16_t noiseFloorExt[AH_MAX_CHAINS]; 201213455Salc uint16_t mainSpur; /* cached spur value for this channel */ 202213455Salc 203213455Salc /*XXX TODO: make these part of privFlags */ 2044Srgrimes uint8_t paprd_done:1, /* 1: PAPRD DONE, 0: PAPRD Cal not done */ 2054Srgrimes paprd_table_write_done:1; /* 1: DONE, 0: Cal data write not done */ 206213455Salc int one_time_cals_done; 207213455Salc HAL_CHAN_NFCAL_HIST nf_cal_hist; 208213455Salc} HAL_CHANNEL_INTERNAL; 209213455Salc 210213455Salc/* channel requires noise floor check */ 211213455Salc#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 212153179Sjhb 2134Srgrimes/* all full-width channels */ 214216956Srwatson#define IEEE80211_CHAN_ALLFULL \ 215181775Skmacy (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 216255040Sgibbs#define IEEE80211_CHAN_ALLTURBOFULL \ 217255040Sgibbs (IEEE80211_CHAN_ALLTURBO - \ 218255040Sgibbs (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 219181775Skmacy 220181775Skmacytypedef struct { 221181775Skmacy uint32_t halChanSpreadSupport : 1, 222181775Skmacy halSleepAfterBeaconBroken : 1, 223181775Skmacy halCompressSupport : 1, 224181775Skmacy halBurstSupport : 1, 225181775Skmacy halFastFramesSupport : 1, 226181775Skmacy halChapTuningSupport : 1, 227181775Skmacy halTurboGSupport : 1, 228181775Skmacy halTurboPrimeSupport : 1, 229215587Scperciva halMicAesCcmSupport : 1, 230215587Scperciva halMicCkipSupport : 1, 231181775Skmacy halMicTkipSupport : 1, 232181775Skmacy halTkipMicTxRxKeySupport : 1, 233181775Skmacy halCipherAesCcmSupport : 1, 234181775Skmacy halCipherCkipSupport : 1, 235181775Skmacy halCipherTkipSupport : 1, 236181775Skmacy halPSPollBroken : 1, 237181775Skmacy halVEOLSupport : 1, 238181775Skmacy halBssIdMaskSupport : 1, 239181775Skmacy halMcastKeySrchSupport : 1, 240181775Skmacy halTsfAddSupport : 1, 241181775Skmacy halChanHalfRate : 1, 242181775Skmacy halChanQuarterRate : 1, 243181775Skmacy halHTSupport : 1, 244181775Skmacy halHTSGI20Support : 1, 245181775Skmacy halRfSilentSupport : 1, 246181775Skmacy halHwPhyCounterSupport : 1, 247181775Skmacy halWowSupport : 1, 248181775Skmacy halWowMatchPatternExact : 1, 249181775Skmacy halAutoSleepSupport : 1, 250181775Skmacy halFastCCSupport : 1, 251181775Skmacy halBtCoexSupport : 1; 252181775Skmacy uint32_t halRxStbcSupport : 1, 253181775Skmacy halTxStbcSupport : 1, 254181775Skmacy halGTTSupport : 1, 255181775Skmacy halCSTSupport : 1, 256181775Skmacy halRifsRxSupport : 1, 257181775Skmacy halRifsTxSupport : 1, 258181775Skmacy hal4AddrAggrSupport : 1, 259181775Skmacy halExtChanDfsSupport : 1, 260181775Skmacy halUseCombinedRadarRssi : 1, 261181775Skmacy halForcePpmSupport : 1, 262181775Skmacy halEnhancedPmSupport : 1, 263181775Skmacy halEnhancedDfsSupport : 1, 264181775Skmacy halMbssidAggrSupport : 1, 265181775Skmacy halBssidMatchSupport : 1, 266181775Skmacy hal4kbSplitTransSupport : 1, 267181775Skmacy halHasRxSelfLinkedTail : 1, 268181775Skmacy halSupportsFastClock5GHz : 1, 269181775Skmacy halHasBBReadWar : 1, 270181775Skmacy halSerialiseRegWar : 1, 271181775Skmacy halMciSupport : 1, 272181775Skmacy halRxTxAbortSupport : 1, 273181775Skmacy halPaprdEnabled : 1, 274181775Skmacy halHasUapsdSupport : 1, 275181775Skmacy halWpsPushButtonSupport : 1, 276181775Skmacy halBtCoexApsmWar : 1, 277181775Skmacy halGenTimerSupport : 1, 278181775Skmacy halLDPCSupport : 1, 279181775Skmacy halHwBeaconProcSupport : 1, 280181775Skmacy halEnhancedDmaSupport : 1; 281181775Skmacy uint32_t halIsrRacSupport : 1, 282181775Skmacy halApmEnable : 1, 283202894Salc halIntrMitigation : 1, 2844Srgrimes hal49GhzSupport : 1, 285202894Salc halAntDivCombSupport : 1, 286202894Salc halAntDivCombSupportOrg : 1, 287202894Salc halRadioRetentionSupport : 1, 288202894Salc halSpectralScanSupport : 1, 289202894Salc halRxUsingLnaMixing : 1, 290213455Salc halRxDoMyBeacon : 1, 291213455Salc halHwUapsdTrig : 1; 292213455Salc 293213455Salc uint32_t halWirelessModes; 294202894Salc uint16_t halTotalQueues; 295202894Salc uint16_t halKeyCacheSize; 296202894Salc uint16_t halLow5GhzChan, halHigh5GhzChan; 297202894Salc uint16_t halLow2GhzChan, halHigh2GhzChan; 298213455Salc int halTxTstampPrecision; 299213455Salc int halRxTstampPrecision; 300213455Salc int halRtsAggrLimit; 301213455Salc uint8_t halTxChainMask; 3021307Sdg uint8_t halRxChainMask; 303112569Sjake uint8_t halNumGpioPins; 3044471Sbde uint8_t halNumAntCfg2GHz; 3051307Sdg uint8_t halNumAntCfg5GHz; 306112569Sjake uint32_t halIntrMask; 307112569Sjake uint8_t halTxStreams; 308113266Sjake uint8_t halRxStreams; 309168439Sru HAL_MFP_OPT_T halMfpSupport; 31027464Sdyson 311202894Salc /* AR9300 HAL porting capabilities */ 312202894Salc int hal_paprd_enabled; 313202894Salc int hal_pcie_lcr_offset; 314202894Salc int hal_pcie_lcr_extsync_en; 315202894Salc int halNumTxMaps; 316202894Salc int halTxDescLen; 317202894Salc int halTxStatusLen; 318202894Salc int halRxStatusLen; 31927464Sdyson int halRxHpFifoDepth; 32027464Sdyson int halRxLpFifoDepth; 321202894Salc uint32_t halRegCap; /* XXX needed? */ 3221307Sdg int halNumMRRetries; 323216956Srwatson int hal_ani_poll_interval; 324181854Skmacy int hal_channel_switch_time_usec; 325216956Srwatson} HAL_CAPABILITIES; 326181854Skmacy 327181775Skmacystruct regDomain; 32827464Sdyson 329181775Skmacy/* 330112841Sjake * Definitions for ah_flags in ath_hal_private 331254623Sjkim */ 332254623Sjkim#define AH_USE_EEPROM 0x1 333254623Sjkim#define AH_IS_HB63 0x2 334254623Sjkim 335177659Salc/* 336168439Sru * The ``private area'' follows immediately after the ``public area'' 337168439Sru * in the data structure returned by ath_hal_attach. Private data are 338254623Sjkim * used by device-independent code such as the regulatory domain support. 339114177Sjake * In general, code within the HAL should never depend on data in the 340254623Sjkim * public area. Instead any public data needed internally should be 341254623Sjkim * shadowed here. 342254623Sjkim * 343254623Sjkim * When declaring a device-specific ath_hal data structure this structure 344254623Sjkim * is assumed to at the front; e.g. 345254623Sjkim * 346177659Salc * struct ath_hal_5212 { 347114177Sjake * struct ath_hal_private ah_priv; 3481307Sdg * ... 349254623Sjkim * }; 350112841Sjake * 351254623Sjkim * It might be better to manage the method pointers in this structure 352114177Sjake * using an indirect pointer to a read-only data structure but this would 353114177Sjake * disallow class-style method overriding. 354114177Sjake */ 3551307Sdgstruct ath_hal_private { 3564Srgrimes struct ath_hal h; /* public area */ 3574Srgrimes 35818163Sdyson /* NB: all methods go first to simplify initialization */ 359158060Speter HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 36060755Speter uint16_t channelFlags, 36160755Speter uint16_t *lowChannel, uint16_t *highChannel); 36260938Sjake u_int (*ah_getWirelessModes)(struct ath_hal*); 363195649Salc HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 36460755Speter uint16_t *data); 3654Srgrimes HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 3664Srgrimes uint16_t data); 367130573Salc HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 3684Srgrimes struct ieee80211_channel *); 369158060Speter int16_t (*ah_getNfAdjust)(struct ath_hal *, 370222813Sattilio const HAL_CHANNEL_INTERNAL*); 3714Srgrimes void (*ah_getNoiseFloor)(struct ath_hal *, 37264728Stegge int16_t nfarray[]); 373112841Sjake 374112841Sjake void *ah_eeprom; /* opaque EEPROM state */ 375112841Sjake uint16_t ah_eeversion; /* EEPROM version */ 376112841Sjake void (*ah_eepromDetach)(struct ath_hal *); 377248449Sattilio HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 3784Srgrimes HAL_STATUS (*ah_eepromSet)(struct ath_hal *, int, int); 3794Srgrimes uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 3804Srgrimes HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 3814Srgrimes const void *args, uint32_t argsize, 38255205Speter void **result, uint32_t *resultsize); 38395710Speter 38495710Speter /* 385130573Salc * Device revision information. 386130573Salc */ 387130573Salc uint16_t ah_devid; /* PCI device ID */ 388130573Salc uint16_t ah_subvendorid; /* PCI subvendor ID */ 389130573Salc uint32_t ah_macVersion; /* MAC version id */ 390130573Salc uint16_t ah_macRev; /* MAC revision */ 391135939Salc uint16_t ah_phyRev; /* PHY revision */ 392130573Salc uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 393130573Salc uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 394130573Salc uint32_t ah_flags; /* misc flags */ 395130573Salc uint8_t ah_ispcie; /* PCIE, special treatment */ 3964Srgrimes uint8_t ah_devType; /* card type - CB, PCI, PCIe */ 3974Srgrimes 3984Srgrimes HAL_OPMODE ah_opmode; /* operating mode from reset */ 3994Srgrimes const struct ieee80211_channel *ah_curchan;/* operating channel */ 400164250Sru HAL_CAPABILITIES ah_caps; /* device capabilities */ 4014Srgrimes uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 4024Srgrimes int16_t ah_powerLimit; /* tx power cap */ 4034Srgrimes uint16_t ah_maxPowerLevel; /* calculated max tx power */ 404247622Sattilio u_int ah_tpScale; /* tx power scale factor */ 4054Srgrimes u_int16_t ah_extraTxPow; /* low rates extra-txpower */ 4064Srgrimes uint32_t ah_11nCompat; /* 11n compat controls */ 407158060Speter 408158060Speter /* 409158060Speter * State for regulatory domain handling. 410158060Speter */ 411158060Speter HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 412158060Speter HAL_REG_DOMAIN ah_currentRDext; /* EEPROM extended regdomain flags */ 413158060Speter HAL_DFS_DOMAIN ah_dfsDomain; /* current DFS domain */ 414158060Speter HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 415158060Speter u_int ah_nchan; /* valid items in ah_channels */ 416158060Speter const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 417236045Salc const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 418158060Speter 419158060Speter uint8_t ah_coverageClass; /* coverage class */ 420158060Speter /* 42155205Speter * RF Silent handling; setup according to the EEPROM. 4224Srgrimes */ 423267964Sjhb uint16_t ah_rfsilent; /* GPIO pin + polarity */ 424267964Sjhb HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 425112569Sjake /* 426147671Speter * Diagnostic support for discriminating HIUERR reports. 427120654Speter */ 428120654Speter uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 42931321Sbde int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 4307090Sbde 4317090Sbde /* Only used if ATH_NF_PER_CHAN is defined */ 4324Srgrimes HAL_NFCAL_HIST_FULL nf_cal_hist; 433195649Salc 434237168Salc /* 435161223Sjhb * Channel survey history - current channel only. 436130399Salc */ 437213455Salc HAL_CHANNEL_SURVEY ah_chansurvey; /* channel survey */ 438213455Salc}; 439213455Salc 440213455Salc#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 441213455Salc 442167668Salc#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 443195940Skib AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 444161223Sjhb#define ath_hal_getWirelessModes(_ah) \ 445158238Sjhb AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 446112569Sjake#define ath_hal_eepromRead(_ah, _off, _data) \ 447128098Salc AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 448112312Sjake#define ath_hal_eepromWrite(_ah, _off, _data) \ 449161223Sjhb AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 450112569Sjake#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 451161223Sjhb (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 452177659Salc#define ath_hal_gpioCfgInput(_ah, _gpio) \ 453195649Salc (_ah)->ah_gpioCfgInput(_ah, _gpio) 45492761Salfred#define ath_hal_gpioGet(_ah, _gpio) \ 455122284Salc (_ah)->ah_gpioGet(_ah, _gpio) 45699862Speter#define ath_hal_gpioSet(_ah, _gpio, _val) \ 45799862Speter (_ah)->ah_gpioSet(_ah, _gpio, _val) 45899862Speter#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 459158236Sjhb (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 460220803Skib#define ath_hal_getpowerlimits(_ah, _chan) \ 461220803Skib AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 4624471Sbde#define ath_hal_getNfAdjust(_ah, _c) \ 46355205Speter AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 46418896Sbde#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 46515543Sphk AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 4664Srgrimes#define ath_hal_configPCIE(_ah, _reset, _poweroff) \ 4674471Sbde (_ah)->ah_configPCIE(_ah, _reset, _poweroff) 468#define ath_hal_disablePCIE(_ah) \ 469 (_ah)->ah_disablePCIE(_ah) 470#define ath_hal_setInterrupts(_ah, _mask) \ 471 (_ah)->ah_setInterrupts(_ah, _mask) 472 473#define ath_hal_isrfkillenabled(_ah) \ 474 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, AH_NULL) == HAL_OK) 475#define ath_hal_enable_rfkill(_ah, _v) \ 476 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _v, AH_NULL) 477#define ath_hal_hasrfkill_int(_ah) \ 478 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 3, AH_NULL) == HAL_OK) 479 480#define ath_hal_eepromDetach(_ah) do { \ 481 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 482 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 483} while (0) 484#define ath_hal_eepromGet(_ah, _param, _val) \ 485 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 486#define ath_hal_eepromSet(_ah, _param, _val) \ 487 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 488#define ath_hal_eepromGetFlag(_ah, _param) \ 489 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 490#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 491 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 492#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 493 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 494 495#ifndef _NET_IF_IEEE80211_H_ 496/* 497 * Stuff that would naturally come from _ieee80211.h 498 */ 499#define IEEE80211_ADDR_LEN 6 500 501#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 502#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 503#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 504 505#define IEEE80211_CRC_LEN 4 506 507#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 508 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 509#endif /* _NET_IF_IEEE80211_H_ */ 510 511#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 512 513#define INIT_AIFS 2 514#define INIT_CWMIN 15 515#define INIT_CWMIN_11B 31 516#define INIT_CWMAX 1023 517#define INIT_SH_RETRY 10 518#define INIT_LG_RETRY 10 519#define INIT_SSH_RETRY 32 520#define INIT_SLG_RETRY 32 521 522typedef struct { 523 uint32_t tqi_ver; /* HAL TXQ verson */ 524 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 525 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 526 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 527 uint32_t tqi_priority; 528 uint32_t tqi_aifs; /* aifs */ 529 uint32_t tqi_cwmin; /* cwMin */ 530 uint32_t tqi_cwmax; /* cwMax */ 531 uint16_t tqi_shretry; /* frame short retry limit */ 532 uint16_t tqi_lgretry; /* frame long retry limit */ 533 uint32_t tqi_cbrPeriod; 534 uint32_t tqi_cbrOverflowLimit; 535 uint32_t tqi_burstTime; 536 uint32_t tqi_readyTime; 537 uint32_t tqi_physCompBuf; 538 uint32_t tqi_intFlags; /* flags for internal use */ 539} HAL_TX_QUEUE_INFO; 540 541extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 542 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 543extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 544 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 545 546#define HAL_SPUR_VAL_MASK 0x3FFF 547#define HAL_SPUR_CHAN_WIDTH 87 548#define HAL_BIN_WIDTH_BASE_100HZ 3125 549#define HAL_BIN_WIDTH_TURBO_100HZ 6250 550#define HAL_MAX_BINS_ALLOWED 28 551 552#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 553#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 554 555#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 556 557/* 558 * Deduce if the host cpu has big- or litt-endian byte order. 559 */ 560static __inline__ int 561isBigEndian(void) 562{ 563 union { 564 int32_t i; 565 char c[4]; 566 } u; 567 u.i = 1; 568 return (u.c[0] == 0); 569} 570 571/* unalligned little endian access */ 572#define LE_READ_2(p) \ 573 ((uint16_t) \ 574 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 575#define LE_READ_4(p) \ 576 ((uint32_t) \ 577 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 578 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 579 580/* 581 * Register manipulation macros that expect bit field defines 582 * to follow the convention that an _S suffix is appended for 583 * a shift count, while the field mask has no suffix. 584 */ 585#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 586#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 587#define OS_REG_RMW(_a, _r, _set, _clr) \ 588 OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set)) 589#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 590 OS_REG_WRITE(_a, _r, \ 591 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 592#define OS_REG_SET_BIT(_a, _r, _f) \ 593 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 594#define OS_REG_CLR_BIT(_a, _r, _f) \ 595 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 596#define OS_REG_IS_BIT_SET(_a, _r, _f) \ 597 ((OS_REG_READ(_a, _r) & (_f)) != 0) 598#define OS_REG_RMW_FIELD_ALT(_a, _r, _f, _v) \ 599 OS_REG_WRITE(_a, _r, \ 600 (OS_REG_READ(_a, _r) &~(_f<<_f##_S)) | \ 601 (((_v) << _f##_S) & (_f<<_f##_S))) 602#define OS_REG_READ_FIELD(_a, _r, _f) \ 603 (((OS_REG_READ(_a, _r) & _f) >> _f##_S)) 604#define OS_REG_READ_FIELD_ALT(_a, _r, _f) \ 605 ((OS_REG_READ(_a, _r) >> (_f##_S))&(_f)) 606 607/* Analog register writes may require a delay between each one (eg Merlin?) */ 608#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \ 609 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | \ 610 (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0) 611#define OS_A_REG_WRITE(_a, _r, _v) \ 612 do { OS_REG_WRITE(_a, _r, _v); OS_DELAY(100); } while (0) 613 614/* wait for the register contents to have the specified value */ 615extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 616 uint32_t mask, uint32_t val); 617extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg, 618 uint32_t mask, uint32_t val, uint32_t timeout); 619 620/* return the first n bits in val reversed */ 621extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 622 623/* printf interfaces */ 624extern void ath_hal_printf(struct ath_hal *, const char*, ...) 625 __printflike(2,3); 626extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 627 __printflike(2, 0); 628extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 629 630/* allocate and free memory */ 631extern void *ath_hal_malloc(size_t); 632extern void ath_hal_free(void *); 633 634/* common debugging interfaces */ 635#ifdef AH_DEBUG 636#include "ah_debug.h" 637extern int ath_hal_debug; /* Global debug flags */ 638 639/* 640 * The typecast is purely because some callers will pass in 641 * AH_NULL directly rather than using a NULL ath_hal pointer. 642 */ 643#define HALDEBUG(_ah, __m, ...) \ 644 do { \ 645 if ((__m) == HAL_DEBUG_UNMASKABLE || \ 646 ath_hal_debug & (__m) || \ 647 ((_ah) != NULL && \ 648 ((struct ath_hal *) (_ah))->ah_config.ah_debug & (__m))) { \ 649 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \ 650 } \ 651 } while(0); 652 653extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 654 __printflike(3,4); 655#else 656#define HALDEBUG(_ah, __m, ...) 657#endif /* AH_DEBUG */ 658 659/* 660 * Register logging definitions shared with ardecode. 661 */ 662#include "ah_decode.h" 663 664/* 665 * Common assertion interface. Note: it is a bad idea to generate 666 * an assertion failure for any recoverable event. Instead catch 667 * the violation and, if possible, fix it up or recover from it; either 668 * with an error return value or a diagnostic messages. System software 669 * does not panic unless the situation is hopeless. 670 */ 671#ifdef AH_ASSERT 672extern void ath_hal_assert_failed(const char* filename, 673 int lineno, const char* msg); 674 675#define HALASSERT(_x) do { \ 676 if (!(_x)) { \ 677 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 678 } \ 679} while (0) 680#else 681#define HALASSERT(_x) 682#endif /* AH_ASSERT */ 683 684/* 685 * Regulatory domain support. 686 */ 687 688/* 689 * Return the max allowed antenna gain and apply any regulatory 690 * domain specific changes. 691 */ 692u_int ath_hal_getantennareduction(struct ath_hal *ah, 693 const struct ieee80211_channel *chan, u_int twiceGain); 694 695/* 696 * Return the test group for the specific channel based on 697 * the current regulatory setup. 698 */ 699u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 700 701/* 702 * Map a public channel definition to the corresponding 703 * internal data structure. This implicitly specifies 704 * whether or not the specified channel is ok to use 705 * based on the current regulatory domain constraints. 706 */ 707#ifndef AH_DEBUG 708static OS_INLINE HAL_CHANNEL_INTERNAL * 709ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 710{ 711 HAL_CHANNEL_INTERNAL *cc; 712 713 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 714 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 715 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 716 return cc; 717} 718#else 719/* NB: non-inline version that checks state */ 720HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 721 const struct ieee80211_channel *); 722#endif /* AH_DEBUG */ 723 724/* 725 * Return the h/w frequency for a channel. This may be 726 * different from ic_freq if this is a GSM device that 727 * takes 2.4GHz frequencies and down-converts them. 728 */ 729static OS_INLINE uint16_t 730ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 731{ 732 return ath_hal_checkchannel(ah, c)->channel; 733} 734 735/* 736 * Generic get/set capability support. Each chip overrides 737 * this routine to support chip-specific capabilities. 738 */ 739extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 740 HAL_CAPABILITY_TYPE type, uint32_t capability, 741 uint32_t *result); 742extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 743 HAL_CAPABILITY_TYPE type, uint32_t capability, 744 uint32_t setting, HAL_STATUS *status); 745 746/* The diagnostic codes used to be internally defined here -adrian */ 747#include "ah_diagcodes.h" 748 749/* 750 * The AR5416 and later HALs have MAC and baseband hang checking. 751 */ 752typedef struct { 753 uint32_t hang_reg_offset; 754 uint32_t hang_val; 755 uint32_t hang_mask; 756 uint32_t hang_offset; 757} hal_hw_hang_check_t; 758 759typedef struct { 760 uint32_t dma_dbg_3; 761 uint32_t dma_dbg_4; 762 uint32_t dma_dbg_5; 763 uint32_t dma_dbg_6; 764} mac_dbg_regs_t; 765 766typedef enum { 767 dcu_chain_state = 0x1, 768 dcu_complete_state = 0x2, 769 qcu_state = 0x4, 770 qcu_fsp_ok = 0x8, 771 qcu_fsp_state = 0x10, 772 qcu_stitch_state = 0x20, 773 qcu_fetch_state = 0x40, 774 qcu_complete_state = 0x80 775} hal_mac_hangs_t; 776 777typedef struct { 778 int states; 779 uint8_t dcu_chain_state; 780 uint8_t dcu_complete_state; 781 uint8_t qcu_state; 782 uint8_t qcu_fsp_ok; 783 uint8_t qcu_fsp_state; 784 uint8_t qcu_stitch_state; 785 uint8_t qcu_fetch_state; 786 uint8_t qcu_complete_state; 787} hal_mac_hang_check_t; 788 789enum { 790 HAL_BB_HANG_DFS = 0x0001, 791 HAL_BB_HANG_RIFS = 0x0002, 792 HAL_BB_HANG_RX_CLEAR = 0x0004, 793 HAL_BB_HANG_UNKNOWN = 0x0080, 794 795 HAL_MAC_HANG_SIG1 = 0x0100, 796 HAL_MAC_HANG_SIG2 = 0x0200, 797 HAL_MAC_HANG_UNKNOWN = 0x8000, 798 799 HAL_BB_HANGS = HAL_BB_HANG_DFS 800 | HAL_BB_HANG_RIFS 801 | HAL_BB_HANG_RX_CLEAR 802 | HAL_BB_HANG_UNKNOWN, 803 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 804 | HAL_MAC_HANG_SIG2 805 | HAL_MAC_HANG_UNKNOWN, 806}; 807 808/* Merge these with above */ 809typedef enum hal_hw_hangs { 810 HAL_DFS_BB_HANG_WAR = 0x1, 811 HAL_RIFS_BB_HANG_WAR = 0x2, 812 HAL_RX_STUCK_LOW_BB_HANG_WAR = 0x4, 813 HAL_MAC_HANG_WAR = 0x8, 814 HAL_PHYRESTART_CLR_WAR = 0x10, 815 HAL_MAC_HANG_DETECTED = 0x40000000, 816 HAL_BB_HANG_DETECTED = 0x80000000 817} hal_hw_hangs_t; 818 819/* 820 * Device revision information. 821 */ 822typedef struct { 823 uint16_t ah_devid; /* PCI device ID */ 824 uint16_t ah_subvendorid; /* PCI subvendor ID */ 825 uint32_t ah_macVersion; /* MAC version id */ 826 uint16_t ah_macRev; /* MAC revision */ 827 uint16_t ah_phyRev; /* PHY revision */ 828 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 829 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 830} HAL_REVS; 831 832/* 833 * Argument payload for HAL_DIAG_SETKEY. 834 */ 835typedef struct { 836 HAL_KEYVAL dk_keyval; 837 uint16_t dk_keyix; /* key index */ 838 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 839 int dk_xor; /* XOR key data */ 840} HAL_DIAG_KEYVAL; 841 842/* 843 * Argument payload for HAL_DIAG_EEWRITE. 844 */ 845typedef struct { 846 uint16_t ee_off; /* eeprom offset */ 847 uint16_t ee_data; /* write data */ 848} HAL_DIAG_EEVAL; 849 850typedef struct { 851 u_int offset; /* reg offset */ 852 uint32_t val; /* reg value */ 853} HAL_DIAG_REGVAL; 854 855/* 856 * 11n compatibility tweaks. 857 */ 858#define HAL_DIAG_11N_SERVICES 0x00000003 859#define HAL_DIAG_11N_SERVICES_S 0 860#define HAL_DIAG_11N_TXSTOMP 0x0000000c 861#define HAL_DIAG_11N_TXSTOMP_S 2 862 863typedef struct { 864 int maxNoiseImmunityLevel; /* [0..4] */ 865 int totalSizeDesired[5]; 866 int coarseHigh[5]; 867 int coarseLow[5]; 868 int firpwr[5]; 869 870 int maxSpurImmunityLevel; /* [0..7] */ 871 int cycPwrThr1[8]; 872 873 int maxFirstepLevel; /* [0..2] */ 874 int firstep[3]; 875 876 uint32_t ofdmTrigHigh; 877 uint32_t ofdmTrigLow; 878 int32_t cckTrigHigh; 879 int32_t cckTrigLow; 880 int32_t rssiThrLow; 881 int32_t rssiThrHigh; 882 883 int period; /* update listen period */ 884} HAL_ANI_PARAMS; 885 886extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 887 const void *args, uint32_t argsize, 888 void **result, uint32_t *resultsize); 889 890/* 891 * Setup a h/w rate table for use. 892 */ 893extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 894 895/* 896 * Common routine for implementing getChanNoise api. 897 */ 898int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 899 900/* 901 * Initialization support. 902 */ 903typedef struct { 904 const uint32_t *data; 905 int rows, cols; 906} HAL_INI_ARRAY; 907 908#define HAL_INI_INIT(_ia, _data, _cols) do { \ 909 (_ia)->data = (const uint32_t *)(_data); \ 910 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 911 (_ia)->cols = (_cols); \ 912} while (0) 913#define HAL_INI_VAL(_ia, _r, _c) \ 914 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 915 916/* 917 * OS_DELAY() does a PIO READ on the PCI bus which allows 918 * other cards' DMA reads to complete in the middle of our reset. 919 */ 920#define DMA_YIELD(x) do { \ 921 if ((++(x) % 64) == 0) \ 922 OS_DELAY(1); \ 923} while (0) 924 925#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 926 int r; \ 927 for (r = 0; r < N(regArray); r++) { \ 928 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 929 DMA_YIELD(regWr); \ 930 } \ 931} while (0) 932 933#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 934 int r; \ 935 for (r = 0; r < N(regArray); r++) { \ 936 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 937 DMA_YIELD(regWr); \ 938 } \ 939} while (0) 940 941extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 942 int col, int regWr); 943extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 944 int col); 945extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 946 const uint32_t data[], int regWr); 947 948#define CCK_SIFS_TIME 10 949#define CCK_PREAMBLE_BITS 144 950#define CCK_PLCP_BITS 48 951 952#define OFDM_SIFS_TIME 16 953#define OFDM_PREAMBLE_TIME 20 954#define OFDM_PLCP_BITS 22 955#define OFDM_SYMBOL_TIME 4 956 957#define OFDM_HALF_SIFS_TIME 32 958#define OFDM_HALF_PREAMBLE_TIME 40 959#define OFDM_HALF_PLCP_BITS 22 960#define OFDM_HALF_SYMBOL_TIME 8 961 962#define OFDM_QUARTER_SIFS_TIME 64 963#define OFDM_QUARTER_PREAMBLE_TIME 80 964#define OFDM_QUARTER_PLCP_BITS 22 965#define OFDM_QUARTER_SYMBOL_TIME 16 966 967#define TURBO_SIFS_TIME 8 968#define TURBO_PREAMBLE_TIME 14 969#define TURBO_PLCP_BITS 22 970#define TURBO_SYMBOL_TIME 4 971 972#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 973 974/* Generic EEPROM board value functions */ 975extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList, 976 uint16_t listSize, uint16_t *indexL, uint16_t *indexR); 977extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, 978 uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts, 979 uint8_t *pRetVpdList); 980extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft, 981 uint16_t srcRight, int16_t targetLeft, int16_t targetRight); 982 983/* Whether 5ghz fast clock is needed */ 984/* 985 * The chipset (Merlin, AR9300/later) should set the capability flag below; 986 * this flag simply says that the hardware can do it, not that the EEPROM 987 * says it can. 988 * 989 * Merlin 2.0/2.1 chips with an EEPROM version > 16 do 5ghz fast clock 990 * if the relevant eeprom flag is set. 991 * Merlin 2.0/2.1 chips with an EEPROM version <= 16 do 5ghz fast clock 992 * by default. 993 */ 994#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \ 995 (IEEE80211_IS_CHAN_5GHZ(_c) && \ 996 AH_PRIVATE((_ah))->ah_caps.halSupportsFastClock5GHz && \ 997 ath_hal_eepromGetFlag((_ah), AR_EEP_FSTCLK_5G)) 998 999/* 1000 * Fetch the maximum regulatory domain power for the given channel 1001 * in 1/2dBm steps. 1002 */ 1003static inline int 1004ath_hal_get_twice_max_regpower(struct ath_hal_private *ahp, 1005 const HAL_CHANNEL_INTERNAL *ichan, const struct ieee80211_channel *chan) 1006{ 1007 struct ath_hal *ah = &ahp->h; 1008 1009 if (! chan) { 1010 ath_hal_printf(ah, "%s: called with chan=NULL!\n", __func__); 1011 return (0); 1012 } 1013 return (chan->ic_maxpower); 1014} 1015 1016/* 1017 * Get the maximum antenna gain allowed, in 1/2dBm steps. 1018 */ 1019static inline int 1020ath_hal_getantennaallowed(struct ath_hal *ah, 1021 const struct ieee80211_channel *chan) 1022{ 1023 1024 if (! chan) 1025 return (0); 1026 1027 return (chan->ic_maxantgain); 1028} 1029 1030/* 1031 * Map the given 2GHz channel to an IEEE number. 1032 */ 1033extern int ath_hal_mhz2ieee_2ghz(struct ath_hal *, int freq); 1034 1035/* 1036 * Clear the channel survey data. 1037 */ 1038extern void ath_hal_survey_clear(struct ath_hal *ah); 1039 1040/* 1041 * Add a sample to the channel survey data. 1042 */ 1043extern void ath_hal_survey_add_sample(struct ath_hal *ah, 1044 HAL_SURVEY_SAMPLE *hs); 1045 1046/* 1047 * Chip registration - for modules. 1048 */ 1049extern int ath_hal_add_chip(struct ath_hal_chip *ahc); 1050extern int ath_hal_remove_chip(struct ath_hal_chip *ahc); 1051extern int ath_hal_add_rf(struct ath_hal_rf *arf); 1052extern int ath_hal_remove_rf(struct ath_hal_rf *arf); 1053 1054#endif /* _ATH_AH_INTERAL_H_ */ 1055