1/*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31#include <sys/queue.h> /* XXX for reasons */ 32 33#ifndef NBBY 34#define NBBY 8 /* number of bits/byte */ 35#endif 36 37#ifndef roundup 38#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 39#endif 40#ifndef howmany 41#define howmany(x, y) (((x)+((y)-1))/(y)) 42#endif 43 44#ifndef offsetof 45#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 46#endif 47 48typedef struct { 49 uint32_t start; /* first register */ 50 uint32_t end; /* ending register or zero */ 51} HAL_REGRANGE; 52 53typedef struct { 54 uint32_t addr; /* regiser address/offset */ 55 uint32_t value; /* value to write */ 56} HAL_REGWRITE; 57 58/* 59 * Transmit power scale factor. 60 * 61 * NB: This is not public because we want to discourage the use of 62 * scaling; folks should use the tx power limit interface. 63 */ 64typedef enum { 65 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 66 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 67 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 68 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 69 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 70} HAL_TP_SCALE; 71 72typedef enum { 73 HAL_CAP_RADAR = 0, /* Radar capability */ 74 HAL_CAP_AR = 1, /* AR capability */ 75} HAL_PHYDIAG_CAPS; 76 77/* 78 * Enable/disable strong signal fast diversity 79 */ 80#define HAL_CAP_STRONG_DIV 2 81 82/* 83 * Each chip or class of chips registers to offer support. 84 * 85 * Compiled-in versions will include a linker set to iterate through the 86 * linked in code. 87 * 88 * Modules will have to register HAL backends separately. 89 */ 90struct ath_hal_chip { 91 const char *name; 92 const char *(*probe)(uint16_t vendorid, uint16_t devid); 93 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 94 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 95 HAL_OPS_CONFIG *ah, 96 HAL_STATUS *error); 97 TAILQ_ENTRY(ath_hal_chip) node; 98}; 99#ifndef AH_CHIP 100#define AH_CHIP(_name, _probe, _attach) \ 101struct ath_hal_chip _name##_chip = { \ 102 .name = #_name, \ 103 .probe = _probe, \ 104 .attach = _attach, \ 105}; \ 106OS_DATA_SET(ah_chips, _name##_chip) 107#endif 108 109/* 110 * Each RF backend registers to offer support; this is mostly 111 * used by multi-chip 5212 solutions. Single-chip solutions 112 * have a fixed idea about which RF to use. 113 * 114 * Compiled in versions will include this linker set to iterate through 115 * the linked in code. 116 * 117 * Modules will have to register RF backends separately. 118 */ 119struct ath_hal_rf { 120 const char *name; 121 HAL_BOOL (*probe)(struct ath_hal *ah); 122 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 123 TAILQ_ENTRY(ath_hal_rf) node; 124}; 125#ifndef AH_RF 126#define AH_RF(_name, _probe, _attach) \ 127struct ath_hal_rf _name##_rf = { \ 128 .name = __STRING(_name), \ 129 .probe = _probe, \ 130 .attach = _attach, \ 131}; \ 132OS_DATA_SET(ah_rfs, _name##_rf) 133#endif 134 135struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 136 137/* 138 * Maximum number of internal channels. Entries are per unique 139 * frequency so this might be need to be increased to handle all 140 * usage cases; typically no more than 32 are really needed but 141 * dynamically allocating the data structures is a bit painful 142 * right now. 143 */ 144#ifndef AH_MAXCHAN 145#define AH_MAXCHAN 128 146#endif 147 148#define HAL_NF_CAL_HIST_LEN_FULL 5 149#define HAL_NF_CAL_HIST_LEN_SMALL 1 150#define HAL_NUM_NF_READINGS 6 /* 3 chains * (ctl + ext) */ 151#define HAL_NF_LOAD_DELAY 1000 152 153/* 154 * PER_CHAN doesn't work for now, as it looks like the device layer 155 * has to pre-populate the per-channel list with nominal values. 156 */ 157//#define ATH_NF_PER_CHAN 1 158 159typedef struct { 160 u_int8_t curr_index; 161 int8_t invalidNFcount; /* TO DO: REMOVE THIS! */ 162 int16_t priv_nf[HAL_NUM_NF_READINGS]; 163} HAL_NFCAL_BASE; 164 165typedef struct { 166 HAL_NFCAL_BASE base; 167 int16_t nf_cal_buffer[HAL_NF_CAL_HIST_LEN_FULL][HAL_NUM_NF_READINGS]; 168} HAL_NFCAL_HIST_FULL; 169 170typedef struct { 171 HAL_NFCAL_BASE base; 172 int16_t nf_cal_buffer[HAL_NF_CAL_HIST_LEN_SMALL][HAL_NUM_NF_READINGS]; 173} HAL_NFCAL_HIST_SMALL; 174 175#ifdef ATH_NF_PER_CHAN 176typedef HAL_NFCAL_HIST_FULL HAL_CHAN_NFCAL_HIST; 177#define AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (ichan ? &ichan->nf_cal_hist: NULL) 178#else 179typedef HAL_NFCAL_HIST_SMALL HAL_CHAN_NFCAL_HIST; 180#define AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (&AH_PRIVATE(ah)->nf_cal_hist) 181#endif /* ATH_NF_PER_CHAN */ 182 183/* 184 * Internal per-channel state. These are found 185 * using ic_devdata in the ieee80211_channel. 186 */ 187typedef struct { 188 uint16_t channel; /* h/w frequency, NB: may be mapped */ 189 uint8_t privFlags; 190#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 191#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 192#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 193#define CHANNEL_MIMO_NF_VALID 0x04 /* Mimo NF values are valid */ 194 uint8_t calValid; /* bitmask of cal types */ 195 int8_t iCoff; 196 int8_t qCoff; 197 int16_t rawNoiseFloor; 198 int16_t noiseFloorAdjust; 199 int16_t noiseFloorCtl[AH_MAX_CHAINS]; 200 int16_t noiseFloorExt[AH_MAX_CHAINS]; 201 uint16_t mainSpur; /* cached spur value for this channel */ 202 203 /*XXX TODO: make these part of privFlags */ 204 uint8_t paprd_done:1, /* 1: PAPRD DONE, 0: PAPRD Cal not done */ 205 paprd_table_write_done:1; /* 1: DONE, 0: Cal data write not done */ 206 int one_time_cals_done; 207 HAL_CHAN_NFCAL_HIST nf_cal_hist; 208} HAL_CHANNEL_INTERNAL; 209 210/* channel requires noise floor check */ 211#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 212 213/* all full-width channels */ 214#define IEEE80211_CHAN_ALLFULL \ 215 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 216#define IEEE80211_CHAN_ALLTURBOFULL \ 217 (IEEE80211_CHAN_ALLTURBO - \ 218 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 219 220typedef struct { 221 uint32_t halChanSpreadSupport : 1, 222 halSleepAfterBeaconBroken : 1, 223 halCompressSupport : 1, 224 halBurstSupport : 1, 225 halFastFramesSupport : 1, 226 halChapTuningSupport : 1, 227 halTurboGSupport : 1, 228 halTurboPrimeSupport : 1, 229 halMicAesCcmSupport : 1, 230 halMicCkipSupport : 1, 231 halMicTkipSupport : 1, 232 halTkipMicTxRxKeySupport : 1, 233 halCipherAesCcmSupport : 1, 234 halCipherCkipSupport : 1, 235 halCipherTkipSupport : 1, 236 halPSPollBroken : 1, 237 halVEOLSupport : 1, 238 halBssIdMaskSupport : 1, 239 halMcastKeySrchSupport : 1, 240 halTsfAddSupport : 1, 241 halChanHalfRate : 1, 242 halChanQuarterRate : 1, 243 halHTSupport : 1, 244 halHTSGI20Support : 1, 245 halRfSilentSupport : 1, 246 halHwPhyCounterSupport : 1, 247 halWowSupport : 1, 248 halWowMatchPatternExact : 1, 249 halAutoSleepSupport : 1, 250 halFastCCSupport : 1, 251 halBtCoexSupport : 1; 252 uint32_t halRxStbcSupport : 1, 253 halTxStbcSupport : 1, 254 halGTTSupport : 1, 255 halCSTSupport : 1, 256 halRifsRxSupport : 1, 257 halRifsTxSupport : 1, 258 hal4AddrAggrSupport : 1, 259 halExtChanDfsSupport : 1, 260 halUseCombinedRadarRssi : 1, 261 halForcePpmSupport : 1, 262 halEnhancedPmSupport : 1, 263 halEnhancedDfsSupport : 1, 264 halMbssidAggrSupport : 1, 265 halBssidMatchSupport : 1, 266 hal4kbSplitTransSupport : 1, 267 halHasRxSelfLinkedTail : 1, 268 halSupportsFastClock5GHz : 1, 269 halHasBBReadWar : 1, 270 halSerialiseRegWar : 1, 271 halMciSupport : 1, 272 halRxTxAbortSupport : 1, 273 halPaprdEnabled : 1, 274 halHasUapsdSupport : 1, 275 halWpsPushButtonSupport : 1, 276 halBtCoexApsmWar : 1, 277 halGenTimerSupport : 1, 278 halLDPCSupport : 1, 279 halHwBeaconProcSupport : 1, 280 halEnhancedDmaSupport : 1; 281 uint32_t halIsrRacSupport : 1, 282 halApmEnable : 1, 283 halIntrMitigation : 1, 284 hal49GhzSupport : 1, 285 halAntDivCombSupport : 1, 286 halAntDivCombSupportOrg : 1, 287 halRadioRetentionSupport : 1, 288 halSpectralScanSupport : 1, 289 halRxUsingLnaMixing : 1, 290 halRxDoMyBeacon : 1, 291 halHwUapsdTrig : 1; 292 293 uint32_t halWirelessModes; 294 uint16_t halTotalQueues; 295 uint16_t halKeyCacheSize; 296 uint16_t halLow5GhzChan, halHigh5GhzChan; 297 uint16_t halLow2GhzChan, halHigh2GhzChan; 298 int halTxTstampPrecision; 299 int halRxTstampPrecision; 300 int halRtsAggrLimit; 301 uint8_t halTxChainMask; 302 uint8_t halRxChainMask; 303 uint8_t halNumGpioPins; 304 uint8_t halNumAntCfg2GHz; 305 uint8_t halNumAntCfg5GHz; 306 uint32_t halIntrMask; 307 uint8_t halTxStreams; 308 uint8_t halRxStreams; 309 HAL_MFP_OPT_T halMfpSupport; 310 311 /* AR9300 HAL porting capabilities */ 312 int hal_paprd_enabled; 313 int hal_pcie_lcr_offset; 314 int hal_pcie_lcr_extsync_en; 315 int halNumTxMaps; 316 int halTxDescLen; 317 int halTxStatusLen; 318 int halRxStatusLen; 319 int halRxHpFifoDepth; 320 int halRxLpFifoDepth; 321 uint32_t halRegCap; /* XXX needed? */ 322 int halNumMRRetries; 323 int hal_ani_poll_interval; 324 int hal_channel_switch_time_usec; 325} HAL_CAPABILITIES; 326 327struct regDomain; 328 329/* 330 * Definitions for ah_flags in ath_hal_private 331 */ 332#define AH_USE_EEPROM 0x1 333#define AH_IS_HB63 0x2 334 335/* 336 * The ``private area'' follows immediately after the ``public area'' 337 * in the data structure returned by ath_hal_attach. Private data are 338 * used by device-independent code such as the regulatory domain support. 339 * In general, code within the HAL should never depend on data in the 340 * public area. Instead any public data needed internally should be 341 * shadowed here. 342 * 343 * When declaring a device-specific ath_hal data structure this structure 344 * is assumed to at the front; e.g. 345 * 346 * struct ath_hal_5212 { 347 * struct ath_hal_private ah_priv; 348 * ... 349 * }; 350 * 351 * It might be better to manage the method pointers in this structure 352 * using an indirect pointer to a read-only data structure but this would 353 * disallow class-style method overriding. 354 */ 355struct ath_hal_private { 356 struct ath_hal h; /* public area */ 357 358 /* NB: all methods go first to simplify initialization */ 359 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 360 uint16_t channelFlags, 361 uint16_t *lowChannel, uint16_t *highChannel); 362 u_int (*ah_getWirelessModes)(struct ath_hal*); 363 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 364 uint16_t *data); 365 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 366 uint16_t data); 367 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 368 struct ieee80211_channel *); 369 int16_t (*ah_getNfAdjust)(struct ath_hal *, 370 const HAL_CHANNEL_INTERNAL*); 371 void (*ah_getNoiseFloor)(struct ath_hal *, 372 int16_t nfarray[]); 373 374 void *ah_eeprom; /* opaque EEPROM state */ 375 uint16_t ah_eeversion; /* EEPROM version */ 376 void (*ah_eepromDetach)(struct ath_hal *); 377 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 378 HAL_STATUS (*ah_eepromSet)(struct ath_hal *, int, int); 379 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 380 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 381 const void *args, uint32_t argsize, 382 void **result, uint32_t *resultsize); 383 384 /* 385 * Device revision information. 386 */ 387 uint16_t ah_devid; /* PCI device ID */ 388 uint16_t ah_subvendorid; /* PCI subvendor ID */ 389 uint32_t ah_macVersion; /* MAC version id */ 390 uint16_t ah_macRev; /* MAC revision */ 391 uint16_t ah_phyRev; /* PHY revision */ 392 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 393 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 394 uint32_t ah_flags; /* misc flags */ 395 uint8_t ah_ispcie; /* PCIE, special treatment */ 396 uint8_t ah_devType; /* card type - CB, PCI, PCIe */ 397 398 HAL_OPMODE ah_opmode; /* operating mode from reset */ 399 const struct ieee80211_channel *ah_curchan;/* operating channel */ 400 HAL_CAPABILITIES ah_caps; /* device capabilities */ 401 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 402 int16_t ah_powerLimit; /* tx power cap */ 403 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 404 u_int ah_tpScale; /* tx power scale factor */ 405 u_int16_t ah_extraTxPow; /* low rates extra-txpower */ 406 uint32_t ah_11nCompat; /* 11n compat controls */ 407 408 /* 409 * State for regulatory domain handling. 410 */ 411 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 412 HAL_REG_DOMAIN ah_currentRDext; /* EEPROM extended regdomain flags */ 413 HAL_DFS_DOMAIN ah_dfsDomain; /* current DFS domain */ 414 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 415 u_int ah_nchan; /* valid items in ah_channels */ 416 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 417 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 418 419 uint8_t ah_coverageClass; /* coverage class */ 420 /* 421 * RF Silent handling; setup according to the EEPROM. 422 */ 423 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 424 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 425 /* 426 * Diagnostic support for discriminating HIUERR reports. 427 */ 428 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 429 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 430 431 /* Only used if ATH_NF_PER_CHAN is defined */ 432 HAL_NFCAL_HIST_FULL nf_cal_hist; 433 434 /* 435 * Channel survey history - current channel only. 436 */ 437 HAL_CHANNEL_SURVEY ah_chansurvey; /* channel survey */ 438}; 439 440#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 441 442#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 443 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 444#define ath_hal_getWirelessModes(_ah) \ 445 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 446#define ath_hal_eepromRead(_ah, _off, _data) \ 447 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 448#define ath_hal_eepromWrite(_ah, _off, _data) \ 449 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 450#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 451 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 452#define ath_hal_gpioCfgInput(_ah, _gpio) \ 453 (_ah)->ah_gpioCfgInput(_ah, _gpio) 454#define ath_hal_gpioGet(_ah, _gpio) \ 455 (_ah)->ah_gpioGet(_ah, _gpio) 456#define ath_hal_gpioSet(_ah, _gpio, _val) \ 457 (_ah)->ah_gpioSet(_ah, _gpio, _val) 458#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 459 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 460#define ath_hal_getpowerlimits(_ah, _chan) \ 461 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 462#define ath_hal_getNfAdjust(_ah, _c) \ 463 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 464#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 465 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 466#define ath_hal_configPCIE(_ah, _reset, _poweroff) \ 467 (_ah)->ah_configPCIE(_ah, _reset, _poweroff) 468#define ath_hal_disablePCIE(_ah) \ 469 (_ah)->ah_disablePCIE(_ah) 470#define ath_hal_setInterrupts(_ah, _mask) \ 471 (_ah)->ah_setInterrupts(_ah, _mask) 472 473#define ath_hal_isrfkillenabled(_ah) \ 474 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, AH_NULL) == HAL_OK) 475#define ath_hal_enable_rfkill(_ah, _v) \ 476 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _v, AH_NULL) 477#define ath_hal_hasrfkill_int(_ah) \ 478 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 3, AH_NULL) == HAL_OK) 479 480#define ath_hal_eepromDetach(_ah) do { \ 481 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 482 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 483} while (0) 484#define ath_hal_eepromGet(_ah, _param, _val) \ 485 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 486#define ath_hal_eepromSet(_ah, _param, _val) \ 487 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 488#define ath_hal_eepromGetFlag(_ah, _param) \ 489 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 490#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 491 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 492#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 493 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 494 495#ifndef _NET_IF_IEEE80211_H_ 496/* 497 * Stuff that would naturally come from _ieee80211.h 498 */ 499#define IEEE80211_ADDR_LEN 6 500 501#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 502#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 503#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 504 505#define IEEE80211_CRC_LEN 4 506 507#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 508 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 509#endif /* _NET_IF_IEEE80211_H_ */ 510 511#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 512 513#define INIT_AIFS 2 514#define INIT_CWMIN 15 515#define INIT_CWMIN_11B 31 516#define INIT_CWMAX 1023 517#define INIT_SH_RETRY 10 518#define INIT_LG_RETRY 10 519#define INIT_SSH_RETRY 32 520#define INIT_SLG_RETRY 32 521 522typedef struct { 523 uint32_t tqi_ver; /* HAL TXQ verson */ 524 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 525 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 526 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 527 uint32_t tqi_priority; 528 uint32_t tqi_aifs; /* aifs */ 529 uint32_t tqi_cwmin; /* cwMin */ 530 uint32_t tqi_cwmax; /* cwMax */ 531 uint16_t tqi_shretry; /* frame short retry limit */ 532 uint16_t tqi_lgretry; /* frame long retry limit */ 533 uint32_t tqi_cbrPeriod; 534 uint32_t tqi_cbrOverflowLimit; 535 uint32_t tqi_burstTime; 536 uint32_t tqi_readyTime; 537 uint32_t tqi_physCompBuf; 538 uint32_t tqi_intFlags; /* flags for internal use */ 539} HAL_TX_QUEUE_INFO; 540 541extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 542 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 543extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 544 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 545 546#define HAL_SPUR_VAL_MASK 0x3FFF 547#define HAL_SPUR_CHAN_WIDTH 87 548#define HAL_BIN_WIDTH_BASE_100HZ 3125 549#define HAL_BIN_WIDTH_TURBO_100HZ 6250 550#define HAL_MAX_BINS_ALLOWED 28 551 552#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 553#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 554 555#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 556 557/* 558 * Deduce if the host cpu has big- or litt-endian byte order. 559 */ 560static __inline__ int 561isBigEndian(void) 562{ 563 union { 564 int32_t i; 565 char c[4]; 566 } u; 567 u.i = 1; 568 return (u.c[0] == 0); 569} 570 571/* unalligned little endian access */ 572#define LE_READ_2(p) \ 573 ((uint16_t) \ 574 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 575#define LE_READ_4(p) \ 576 ((uint32_t) \ 577 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 578 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 579 580/* 581 * Register manipulation macros that expect bit field defines 582 * to follow the convention that an _S suffix is appended for 583 * a shift count, while the field mask has no suffix. 584 */ 585#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 586#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 587#define OS_REG_RMW(_a, _r, _set, _clr) \ 588 OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set)) 589#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 590 OS_REG_WRITE(_a, _r, \ 591 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 592#define OS_REG_SET_BIT(_a, _r, _f) \ 593 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 594#define OS_REG_CLR_BIT(_a, _r, _f) \ 595 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 596#define OS_REG_IS_BIT_SET(_a, _r, _f) \ 597 ((OS_REG_READ(_a, _r) & (_f)) != 0) 598#define OS_REG_RMW_FIELD_ALT(_a, _r, _f, _v) \ 599 OS_REG_WRITE(_a, _r, \ 600 (OS_REG_READ(_a, _r) &~(_f<<_f##_S)) | \ 601 (((_v) << _f##_S) & (_f<<_f##_S))) 602#define OS_REG_READ_FIELD(_a, _r, _f) \ 603 (((OS_REG_READ(_a, _r) & _f) >> _f##_S)) 604#define OS_REG_READ_FIELD_ALT(_a, _r, _f) \ 605 ((OS_REG_READ(_a, _r) >> (_f##_S))&(_f)) 606 607/* Analog register writes may require a delay between each one (eg Merlin?) */ 608#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \ 609 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | \ 610 (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0) 611#define OS_A_REG_WRITE(_a, _r, _v) \ 612 do { OS_REG_WRITE(_a, _r, _v); OS_DELAY(100); } while (0) 613 614/* wait for the register contents to have the specified value */ 615extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 616 uint32_t mask, uint32_t val); 617extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg, 618 uint32_t mask, uint32_t val, uint32_t timeout); 619 620/* return the first n bits in val reversed */ 621extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 622 623/* printf interfaces */ 624extern void ath_hal_printf(struct ath_hal *, const char*, ...) 625 __printflike(2,3); 626extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 627 __printflike(2, 0); 628extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 629 630/* allocate and free memory */ 631extern void *ath_hal_malloc(size_t); 632extern void ath_hal_free(void *); 633 634/* common debugging interfaces */ 635#ifdef AH_DEBUG 636#include "ah_debug.h" 637extern int ath_hal_debug; /* Global debug flags */ 638 639/* 640 * The typecast is purely because some callers will pass in 641 * AH_NULL directly rather than using a NULL ath_hal pointer. 642 */ 643#define HALDEBUG(_ah, __m, ...) \ 644 do { \ 645 if ((__m) == HAL_DEBUG_UNMASKABLE || \ 646 ath_hal_debug & (__m) || \ 647 ((_ah) != NULL && \ 648 ((struct ath_hal *) (_ah))->ah_config.ah_debug & (__m))) { \ 649 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \ 650 } \ 651 } while(0); 652 653extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 654 __printflike(3,4); 655#else 656#define HALDEBUG(_ah, __m, ...) 657#endif /* AH_DEBUG */ 658 659/* 660 * Register logging definitions shared with ardecode. 661 */ 662#include "ah_decode.h" 663 664/* 665 * Common assertion interface. Note: it is a bad idea to generate 666 * an assertion failure for any recoverable event. Instead catch 667 * the violation and, if possible, fix it up or recover from it; either 668 * with an error return value or a diagnostic messages. System software 669 * does not panic unless the situation is hopeless. 670 */ 671#ifdef AH_ASSERT 672extern void ath_hal_assert_failed(const char* filename, 673 int lineno, const char* msg); 674 675#define HALASSERT(_x) do { \ 676 if (!(_x)) { \ 677 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 678 } \ 679} while (0) 680#else 681#define HALASSERT(_x) 682#endif /* AH_ASSERT */ 683 684/* 685 * Regulatory domain support. 686 */ 687 688/* 689 * Return the max allowed antenna gain and apply any regulatory 690 * domain specific changes. 691 */ 692u_int ath_hal_getantennareduction(struct ath_hal *ah, 693 const struct ieee80211_channel *chan, u_int twiceGain); 694 695/* 696 * Return the test group for the specific channel based on 697 * the current regulatory setup. 698 */ 699u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 700 701/* 702 * Map a public channel definition to the corresponding 703 * internal data structure. This implicitly specifies 704 * whether or not the specified channel is ok to use 705 * based on the current regulatory domain constraints. 706 */ 707#ifndef AH_DEBUG 708static OS_INLINE HAL_CHANNEL_INTERNAL * 709ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 710{ 711 HAL_CHANNEL_INTERNAL *cc; 712 713 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 714 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 715 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 716 return cc; 717} 718#else 719/* NB: non-inline version that checks state */ 720HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 721 const struct ieee80211_channel *); 722#endif /* AH_DEBUG */ 723 724/* 725 * Return the h/w frequency for a channel. This may be 726 * different from ic_freq if this is a GSM device that 727 * takes 2.4GHz frequencies and down-converts them. 728 */ 729static OS_INLINE uint16_t 730ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 731{ 732 return ath_hal_checkchannel(ah, c)->channel; 733} 734 735/* 736 * Generic get/set capability support. Each chip overrides 737 * this routine to support chip-specific capabilities. 738 */ 739extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 740 HAL_CAPABILITY_TYPE type, uint32_t capability, 741 uint32_t *result); 742extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 743 HAL_CAPABILITY_TYPE type, uint32_t capability, 744 uint32_t setting, HAL_STATUS *status); 745 746/* The diagnostic codes used to be internally defined here -adrian */ 747#include "ah_diagcodes.h" 748 749/* 750 * The AR5416 and later HALs have MAC and baseband hang checking. 751 */ 752typedef struct { 753 uint32_t hang_reg_offset; 754 uint32_t hang_val; 755 uint32_t hang_mask; 756 uint32_t hang_offset; 757} hal_hw_hang_check_t; 758 759typedef struct { 760 uint32_t dma_dbg_3; 761 uint32_t dma_dbg_4; 762 uint32_t dma_dbg_5; 763 uint32_t dma_dbg_6; 764} mac_dbg_regs_t; 765 766typedef enum { 767 dcu_chain_state = 0x1, 768 dcu_complete_state = 0x2, 769 qcu_state = 0x4, 770 qcu_fsp_ok = 0x8, 771 qcu_fsp_state = 0x10, 772 qcu_stitch_state = 0x20, 773 qcu_fetch_state = 0x40, 774 qcu_complete_state = 0x80 775} hal_mac_hangs_t; 776 777typedef struct { 778 int states; 779 uint8_t dcu_chain_state; 780 uint8_t dcu_complete_state; 781 uint8_t qcu_state; 782 uint8_t qcu_fsp_ok; 783 uint8_t qcu_fsp_state; 784 uint8_t qcu_stitch_state; 785 uint8_t qcu_fetch_state; 786 uint8_t qcu_complete_state; 787} hal_mac_hang_check_t; 788 789enum { 790 HAL_BB_HANG_DFS = 0x0001, 791 HAL_BB_HANG_RIFS = 0x0002, 792 HAL_BB_HANG_RX_CLEAR = 0x0004, 793 HAL_BB_HANG_UNKNOWN = 0x0080, 794 795 HAL_MAC_HANG_SIG1 = 0x0100, 796 HAL_MAC_HANG_SIG2 = 0x0200, 797 HAL_MAC_HANG_UNKNOWN = 0x8000, 798 799 HAL_BB_HANGS = HAL_BB_HANG_DFS 800 | HAL_BB_HANG_RIFS 801 | HAL_BB_HANG_RX_CLEAR 802 | HAL_BB_HANG_UNKNOWN, 803 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 804 | HAL_MAC_HANG_SIG2 805 | HAL_MAC_HANG_UNKNOWN, 806}; 807 808/* Merge these with above */ 809typedef enum hal_hw_hangs { 810 HAL_DFS_BB_HANG_WAR = 0x1, 811 HAL_RIFS_BB_HANG_WAR = 0x2, 812 HAL_RX_STUCK_LOW_BB_HANG_WAR = 0x4, 813 HAL_MAC_HANG_WAR = 0x8, 814 HAL_PHYRESTART_CLR_WAR = 0x10, 815 HAL_MAC_HANG_DETECTED = 0x40000000, 816 HAL_BB_HANG_DETECTED = 0x80000000 817} hal_hw_hangs_t; 818 819/* 820 * Device revision information. 821 */ 822typedef struct { 823 uint16_t ah_devid; /* PCI device ID */ 824 uint16_t ah_subvendorid; /* PCI subvendor ID */ 825 uint32_t ah_macVersion; /* MAC version id */ 826 uint16_t ah_macRev; /* MAC revision */ 827 uint16_t ah_phyRev; /* PHY revision */ 828 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 829 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 830} HAL_REVS; 831 832/* 833 * Argument payload for HAL_DIAG_SETKEY. 834 */ 835typedef struct { 836 HAL_KEYVAL dk_keyval; 837 uint16_t dk_keyix; /* key index */ 838 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 839 int dk_xor; /* XOR key data */ 840} HAL_DIAG_KEYVAL; 841 842/* 843 * Argument payload for HAL_DIAG_EEWRITE. 844 */ 845typedef struct { 846 uint16_t ee_off; /* eeprom offset */ 847 uint16_t ee_data; /* write data */ 848} HAL_DIAG_EEVAL; 849 850typedef struct { 851 u_int offset; /* reg offset */ 852 uint32_t val; /* reg value */ 853} HAL_DIAG_REGVAL; 854 855/* 856 * 11n compatibility tweaks. 857 */ 858#define HAL_DIAG_11N_SERVICES 0x00000003 859#define HAL_DIAG_11N_SERVICES_S 0 860#define HAL_DIAG_11N_TXSTOMP 0x0000000c 861#define HAL_DIAG_11N_TXSTOMP_S 2 862 863typedef struct { 864 int maxNoiseImmunityLevel; /* [0..4] */ 865 int totalSizeDesired[5]; 866 int coarseHigh[5]; 867 int coarseLow[5]; 868 int firpwr[5]; 869 870 int maxSpurImmunityLevel; /* [0..7] */ 871 int cycPwrThr1[8]; 872 873 int maxFirstepLevel; /* [0..2] */ 874 int firstep[3]; 875 876 uint32_t ofdmTrigHigh; 877 uint32_t ofdmTrigLow; 878 int32_t cckTrigHigh; 879 int32_t cckTrigLow; 880 int32_t rssiThrLow; 881 int32_t rssiThrHigh; 882 883 int period; /* update listen period */ 884} HAL_ANI_PARAMS; 885 886extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 887 const void *args, uint32_t argsize, 888 void **result, uint32_t *resultsize); 889 890/* 891 * Setup a h/w rate table for use. 892 */ 893extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 894 895/* 896 * Common routine for implementing getChanNoise api. 897 */ 898int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 899 900/* 901 * Initialization support. 902 */ 903typedef struct { 904 const uint32_t *data; 905 int rows, cols; 906} HAL_INI_ARRAY; 907 908#define HAL_INI_INIT(_ia, _data, _cols) do { \ 909 (_ia)->data = (const uint32_t *)(_data); \ 910 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 911 (_ia)->cols = (_cols); \ 912} while (0) 913#define HAL_INI_VAL(_ia, _r, _c) \ 914 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 915 916/* 917 * OS_DELAY() does a PIO READ on the PCI bus which allows 918 * other cards' DMA reads to complete in the middle of our reset. 919 */ 920#define DMA_YIELD(x) do { \ 921 if ((++(x) % 64) == 0) \ 922 OS_DELAY(1); \ 923} while (0) 924 925#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 926 int r; \ 927 for (r = 0; r < N(regArray); r++) { \ 928 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 929 DMA_YIELD(regWr); \ 930 } \ 931} while (0) 932 933#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 934 int r; \ 935 for (r = 0; r < N(regArray); r++) { \ 936 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 937 DMA_YIELD(regWr); \ 938 } \ 939} while (0) 940 941extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 942 int col, int regWr); 943extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 944 int col); 945extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 946 const uint32_t data[], int regWr); 947 948#define CCK_SIFS_TIME 10 949#define CCK_PREAMBLE_BITS 144 950#define CCK_PLCP_BITS 48 951 952#define OFDM_SIFS_TIME 16 953#define OFDM_PREAMBLE_TIME 20 954#define OFDM_PLCP_BITS 22 955#define OFDM_SYMBOL_TIME 4 956 957#define OFDM_HALF_SIFS_TIME 32 958#define OFDM_HALF_PREAMBLE_TIME 40 959#define OFDM_HALF_PLCP_BITS 22 960#define OFDM_HALF_SYMBOL_TIME 8 961 962#define OFDM_QUARTER_SIFS_TIME 64 963#define OFDM_QUARTER_PREAMBLE_TIME 80 964#define OFDM_QUARTER_PLCP_BITS 22 965#define OFDM_QUARTER_SYMBOL_TIME 16 966 967#define TURBO_SIFS_TIME 8 968#define TURBO_PREAMBLE_TIME 14 969#define TURBO_PLCP_BITS 22 970#define TURBO_SYMBOL_TIME 4 971 972#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 973 974/* Generic EEPROM board value functions */ 975extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList, 976 uint16_t listSize, uint16_t *indexL, uint16_t *indexR); 977extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, 978 uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts, 979 uint8_t *pRetVpdList); 980extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft, 981 uint16_t srcRight, int16_t targetLeft, int16_t targetRight); 982 983/* Whether 5ghz fast clock is needed */ 984/* 985 * The chipset (Merlin, AR9300/later) should set the capability flag below; 986 * this flag simply says that the hardware can do it, not that the EEPROM 987 * says it can. 988 * 989 * Merlin 2.0/2.1 chips with an EEPROM version > 16 do 5ghz fast clock 990 * if the relevant eeprom flag is set. 991 * Merlin 2.0/2.1 chips with an EEPROM version <= 16 do 5ghz fast clock 992 * by default. 993 */ 994#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \ 995 (IEEE80211_IS_CHAN_5GHZ(_c) && \ 996 AH_PRIVATE((_ah))->ah_caps.halSupportsFastClock5GHz && \ 997 ath_hal_eepromGetFlag((_ah), AR_EEP_FSTCLK_5G)) 998 999/* 1000 * Fetch the maximum regulatory domain power for the given channel 1001 * in 1/2dBm steps. 1002 */ 1003static inline int 1004ath_hal_get_twice_max_regpower(struct ath_hal_private *ahp, 1005 const HAL_CHANNEL_INTERNAL *ichan, const struct ieee80211_channel *chan) 1006{ 1007 struct ath_hal *ah = &ahp->h; 1008 1009 if (! chan) { 1010 ath_hal_printf(ah, "%s: called with chan=NULL!\n", __func__); 1011 return (0); 1012 } 1013 return (chan->ic_maxpower); 1014} 1015 1016/* 1017 * Get the maximum antenna gain allowed, in 1/2dBm steps. 1018 */ 1019static inline int 1020ath_hal_getantennaallowed(struct ath_hal *ah, 1021 const struct ieee80211_channel *chan) 1022{ 1023 1024 if (! chan) 1025 return (0); 1026 1027 return (chan->ic_maxantgain); 1028} 1029 1030/* 1031 * Map the given 2GHz channel to an IEEE number. 1032 */ 1033extern int ath_hal_mhz2ieee_2ghz(struct ath_hal *, int freq); 1034 1035/* 1036 * Clear the channel survey data. 1037 */ 1038extern void ath_hal_survey_clear(struct ath_hal *ah); 1039 1040/* 1041 * Add a sample to the channel survey data. 1042 */ 1043extern void ath_hal_survey_add_sample(struct ath_hal *ah, 1044 HAL_SURVEY_SAMPLE *hs); 1045 1046/* 1047 * Chip registration - for modules. 1048 */ 1049extern int ath_hal_add_chip(struct ath_hal_chip *ahc); 1050extern int ath_hal_remove_chip(struct ath_hal_chip *ahc); 1051extern int ath_hal_add_rf(struct ath_hal_rf *arf); 1052extern int ath_hal_remove_rf(struct ath_hal_rf *arf); 1053 1054#endif /* _ATH_AH_INTERAL_H_ */ 1055