1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer,
12 *    without modification, immediately at the beginning of the file.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <sys/param.h>
30#include <sys/systm.h>
31#include <sys/kernel.h>
32#include <sys/ata.h>
33#include <sys/bus.h>
34#include <sys/endian.h>
35#include <sys/malloc.h>
36#include <sys/lock.h>
37#include <sys/mutex.h>
38#include <sys/sema.h>
39#include <sys/taskqueue.h>
40#include <vm/uma.h>
41#include <machine/stdarg.h>
42#include <machine/resource.h>
43#include <machine/bus.h>
44#include <sys/rman.h>
45#include <dev/ata/ata-all.h>
46#include <ata_if.h>
47
48void
49ata_sata_phy_check_events(device_t dev, int port)
50{
51    struct ata_channel *ch = device_get_softc(dev);
52    u_int32_t error, status;
53
54    if (ata_sata_scr_read(ch, port, ATA_SERROR, &error))
55	return;
56
57    /* Check that SError value is sane. */
58    if (error == 0xffffffff)
59	return;
60
61    /* Clear set error bits/interrupt. */
62    if (error)
63	ata_sata_scr_write(ch, port, ATA_SERROR, error);
64
65    /* if we have a connection event deal with it */
66    if ((error & ATA_SE_PHY_CHANGED) && (ch->pm_level == 0)) {
67	if (bootverbose) {
68	    if (ata_sata_scr_read(ch, port, ATA_SSTATUS, &status)) {
69		    device_printf(dev, "PHYRDY change\n");
70	    } else if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
71		((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
72		((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) {
73		    device_printf(dev, "CONNECT requested\n");
74	    } else
75		    device_printf(dev, "DISCONNECT requested\n");
76	}
77	taskqueue_enqueue(taskqueue_thread, &ch->conntask);
78    }
79}
80
81int
82ata_sata_scr_read(struct ata_channel *ch, int port, int reg, uint32_t *val)
83{
84
85    if (ch->hw.pm_read != NULL)
86	return (ch->hw.pm_read(ch->dev, port, reg, val));
87    if (ch->r_io[reg].res) {
88	*val = ATA_IDX_INL(ch, reg);
89	return (0);
90    }
91    return (-1);
92}
93
94int
95ata_sata_scr_write(struct ata_channel *ch, int port, int reg, uint32_t val)
96{
97
98    if (ch->hw.pm_write != NULL)
99	return (ch->hw.pm_write(ch->dev, port, reg, val));
100    if (ch->r_io[reg].res) {
101	ATA_IDX_OUTL(ch, reg, val);
102	return (0);
103    }
104    return (-1);
105}
106
107static int
108ata_sata_connect(struct ata_channel *ch, int port, int quick)
109{
110    u_int32_t status;
111    int timeout, t;
112
113    /* wait up to 1 second for "connect well" */
114    timeout = (quick == 2) ? 0 : 100;
115    t = 0;
116    while (1) {
117	if (ata_sata_scr_read(ch, port, ATA_SSTATUS, &status))
118	    return (0);
119	if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
120	    ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
121	    ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE))
122	    break;
123	if (++t > timeout)
124	    break;
125	ata_udelay(10000);
126    }
127    if (bootverbose) {
128	if (t > timeout) {
129	    if (port < 0) {
130		device_printf(ch->dev, "SATA connect timeout status=%08x\n",
131		    status);
132	    } else {
133		device_printf(ch->dev, "p%d: SATA connect timeout status=%08x\n",
134		    port, status);
135	    }
136	} else if (port < 0) {
137	    device_printf(ch->dev, "SATA connect time=%dms status=%08x\n",
138		t * 10, status);
139	} else {
140	    device_printf(ch->dev, "p%d: SATA connect time=%dms status=%08x\n",
141		port, t * 10, status);
142	}
143    }
144
145    /* clear SATA error register */
146    ata_sata_scr_write(ch, port, ATA_SERROR, 0xffffffff);
147
148    return ((t > timeout) ? 0 : 1);
149}
150
151int
152ata_sata_phy_reset(device_t dev, int port, int quick)
153{
154    struct ata_channel *ch = device_get_softc(dev);
155    int loop, retry, sata_rev;
156    uint32_t val, val1;
157
158    sata_rev = ch->user[port < 0 ? 0 : port].revision;
159    if (sata_rev > 0)
160	quick = 0;
161
162    if (quick) {
163	if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val))
164	    return (0);
165	if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) {
166	    ata_sata_scr_write(ch, port, ATA_SCONTROL,
167		ATA_SC_DET_IDLE | ((ch->pm_level > 0) ? 0 :
168		ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER));
169	    return ata_sata_connect(ch, port, quick);
170	}
171    }
172
173    if (bootverbose) {
174	if (port < 0) {
175	    device_printf(dev, "hard reset ...\n");
176	} else {
177	    device_printf(dev, "p%d: hard reset ...\n", port);
178	}
179    }
180    if (sata_rev == 1)
181	val1 = ATA_SC_SPD_SPEED_GEN1;
182    else if (sata_rev == 2)
183	val1 = ATA_SC_SPD_SPEED_GEN2;
184    else if (sata_rev == 3)
185	val1 = ATA_SC_SPD_SPEED_GEN3;
186    else
187	val1 = 0;
188    for (retry = 0; retry < 10; retry++) {
189	for (loop = 0; loop < 10; loop++) {
190	    if (ata_sata_scr_write(ch, port, ATA_SCONTROL, ATA_SC_DET_RESET |
191		    val1 | ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))
192		goto fail;
193	    ata_udelay(100);
194	    if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val))
195		goto fail;
196	    if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_RESET)
197		break;
198	}
199	ata_udelay(5000);
200	for (loop = 0; loop < 10; loop++) {
201	    if (ata_sata_scr_write(ch, port, ATA_SCONTROL,
202		    ATA_SC_DET_IDLE | val1 | ((ch->pm_level > 0) ? 0 :
203		    ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)))
204		goto fail;
205	    ata_udelay(100);
206	    if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val))
207		goto fail;
208	    if ((val & ATA_SC_DET_MASK) == 0)
209		return ata_sata_connect(ch, port, 0);
210	}
211    }
212fail:
213    /* Clear SATA error register. */
214    ata_sata_scr_write(ch, port, ATA_SERROR, 0xffffffff);
215
216    if (bootverbose) {
217	if (port < 0) {
218	    device_printf(dev, "hard reset failed\n");
219	} else {
220	    device_printf(dev, "p%d: hard reset failed\n", port);
221	}
222    }
223    return (0);
224}
225
226int
227ata_sata_setmode(device_t dev, int target, int mode)
228{
229
230	return (min(mode, ATA_UDMA5));
231}
232
233int
234ata_sata_getrev(device_t dev, int target)
235{
236	struct ata_channel *ch = device_get_softc(dev);
237
238	if (ch->r_io[ATA_SSTATUS].res)
239		return ((ATA_IDX_INL(ch, ATA_SSTATUS) & 0x0f0) >> 4);
240	return (0xff);
241}
242
243int
244ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis)
245{
246
247    if (request->flags & ATA_R_ATAPI) {
248	fis[0] = 0x27;  		/* host to device */
249	fis[1] = 0x80 | (request->unit & 0x0f);
250	fis[2] = ATA_PACKET_CMD;
251	if (request->flags & (ATA_R_READ | ATA_R_WRITE))
252	    fis[3] = ATA_F_DMA;
253	else {
254	    fis[5] = request->transfersize;
255	    fis[6] = request->transfersize >> 8;
256	}
257	fis[7] = ATA_D_LBA;
258	fis[15] = ATA_A_4BIT;
259	return 20;
260    }
261    else {
262	fis[0] = 0x27;			/* host to device */
263	fis[1] = 0x80 | (request->unit & 0x0f);
264	fis[2] = request->u.ata.command;
265	fis[3] = request->u.ata.feature;
266	fis[4] = request->u.ata.lba;
267	fis[5] = request->u.ata.lba >> 8;
268	fis[6] = request->u.ata.lba >> 16;
269	fis[7] = ATA_D_LBA;
270	if (!(request->flags & ATA_R_48BIT))
271	    fis[7] |= (ATA_D_IBM | (request->u.ata.lba >> 24 & 0x0f));
272	fis[8] = request->u.ata.lba >> 24;
273	fis[9] = request->u.ata.lba >> 32;
274	fis[10] = request->u.ata.lba >> 40;
275	fis[11] = request->u.ata.feature >> 8;
276	fis[12] = request->u.ata.count;
277	fis[13] = request->u.ata.count >> 8;
278	fis[15] = ATA_A_4BIT;
279	return 20;
280    }
281    return 0;
282}
283
284void
285ata_pm_identify(device_t dev)
286{
287    struct ata_channel *ch = device_get_softc(dev);
288    u_int32_t pm_chipid, pm_revision, pm_ports;
289    int port;
290
291    /* get PM vendor & product data */
292    if (ch->hw.pm_read(dev, ATA_PM, 0, &pm_chipid)) {
293	device_printf(dev, "error getting PM vendor data\n");
294	return;
295    }
296
297    /* get PM revision data */
298    if (ch->hw.pm_read(dev, ATA_PM, 1, &pm_revision)) {
299	device_printf(dev, "error getting PM revision data\n");
300	return;
301    }
302
303    /* get number of HW ports on the PM */
304    if (ch->hw.pm_read(dev, ATA_PM, 2, &pm_ports)) {
305	device_printf(dev, "error getting PM port info\n");
306	return;
307    }
308    pm_ports &= 0x0000000f;
309
310    /* chip specific quirks */
311    switch (pm_chipid) {
312    case 0x37261095:
313	/* This PM declares 6 ports, while only 5 of them are real.
314	 * Port 5 is enclosure management bridge port, which has implementation
315	 * problems, causing probe faults. Hide it for now. */
316	device_printf(dev, "SiI 3726 (rev=%x) Port Multiplier with %d (5) ports\n",
317		      pm_revision, pm_ports);
318	pm_ports = 5;
319	break;
320
321    case 0x47261095:
322	/* This PM declares 7 ports, while only 5 of them are real.
323	 * Port 5 is some fake "Config  Disk" with 640 sectors size,
324	 * port 6 is enclosure management bridge port.
325	 * Both fake ports has implementation problems, causing
326	 * probe faults. Hide them for now. */
327	device_printf(dev, "SiI 4726 (rev=%x) Port Multiplier with %d (5) ports\n",
328		      pm_revision, pm_ports);
329	pm_ports = 5;
330	break;
331
332    default:
333	device_printf(dev, "Port Multiplier (id=%08x rev=%x) with %d ports\n",
334		      pm_chipid, pm_revision, pm_ports);
335    }
336
337    /* reset all ports and register if anything connected */
338    for (port=0; port < pm_ports; port++) {
339	u_int32_t signature;
340
341	if (!ata_sata_phy_reset(dev, port, 1))
342	    continue;
343
344	/*
345	 * XXX: I have no idea how to properly wait for PMP port hardreset
346	 * completion. Without this delay soft reset does not completes
347	 * successfully.
348	 */
349	DELAY(1000000);
350
351	signature = ch->hw.softreset(dev, port);
352
353	if (bootverbose)
354	    device_printf(dev, "p%d: SIGNATURE=%08x\n", port, signature);
355
356	/* figure out whats there */
357	switch (signature >> 16) {
358	case 0x0000:
359	    ch->devices |= (ATA_ATA_MASTER << port);
360	    continue;
361	case 0xeb14:
362	    ch->devices |= (ATA_ATAPI_MASTER << port);
363	    continue;
364	}
365    }
366}
367