1/*- 2 * Copyright (c) 2015,2016 Annapurna Labs Ltd. and affiliates 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29#ifndef __AL_ETH_H__ 30#define __AL_ETH_H__ 31 32#include "al_init_eth_lm.h" 33#include "al_hal_eth.h" 34#include "al_hal_udma_iofic.h" 35#include "al_hal_udma_debug.h" 36#include "al_serdes.h" 37 38enum board_t { 39 ALPINE_INTEGRATED = 0, 40 ALPINE_NIC = 1, 41 ALPINE_FPGA_NIC = 2, 42}; 43 44#define AL_ETH_MAX_HW_QUEUES 4 45#define AL_ETH_NUM_QUEUES 4 46#define AL_ETH_MAX_MSIX_VEC (1 + 2 * AL_ETH_MAX_HW_QUEUES) 47 48#define AL_ETH_DEFAULT_TX_SW_DESCS (512) 49#define AL_ETH_DEFAULT_TX_HW_DESCS (512) 50#define AL_ETH_DEFAULT_RX_DESCS (512) 51 52#if ((AL_ETH_DEFAULT_TX_SW_DESCS / 4) < (AL_ETH_PKT_MAX_BUFS + 2)) 53#define AL_ETH_TX_WAKEUP_THRESH (AL_ETH_DEFAULT_TX_SW_DESCS / 4) 54#else 55#define AL_ETH_TX_WAKEUP_THRESH (AL_ETH_PKT_MAX_BUFS + 2) 56#endif 57 58#define NET_IP_ALIGN 2 59#define AL_ETH_DEFAULT_SMALL_PACKET_LEN (128 - NET_IP_ALIGN) 60#define AL_ETH_HEADER_COPY_SIZE (128 - NET_IP_ALIGN) 61 62#define AL_ETH_DEFAULT_MAX_RX_BUFF_ALLOC_SIZE 9216 63/* 64 * Minimum the buffer size to 600 to avoid situation the mtu will be changed 65 * from too little buffer to very big one and then the number of buffer per 66 * packet could reach the maximum AL_ETH_PKT_MAX_BUFS 67 */ 68#define AL_ETH_DEFAULT_MIN_RX_BUFF_ALLOC_SIZE 600 69#define AL_ETH_DEFAULT_FORCE_1000_BASEX FALSE 70 71#define AL_ETH_DEFAULT_LINK_POLL_INTERVAL 100 72#define AL_ETH_FIRST_LINK_POLL_INTERVAL 1 73 74#define AL_ETH_NAME_MAX_LEN 20 75#define AL_ETH_IRQNAME_SIZE 40 76 77#define AL_ETH_DEFAULT_MDIO_FREQ_KHZ 2500 78#define AL_ETH_MDIO_FREQ_1000_KHZ 1000 79 80struct al_eth_irq { 81 driver_filter_t *handler; 82 void *data; 83 unsigned int vector; 84 uint8_t requested; 85 char name[AL_ETH_IRQNAME_SIZE]; 86 struct resource *res; 87 void *cookie; 88}; 89 90struct al_eth_tx_buffer { 91 struct mbuf *m; 92 struct al_eth_pkt hal_pkt; 93 bus_dmamap_t dma_map; 94 unsigned int tx_descs; 95}; 96 97struct al_eth_rx_buffer { 98 struct mbuf *m; 99 unsigned int data_size; 100 bus_dmamap_t dma_map; 101 struct al_buf al_buf; 102}; 103 104struct al_eth_ring { 105 device_t dev; 106 struct al_eth_adapter *adapter; 107 /* Used to get rx packets from hal */ 108 struct al_eth_pkt hal_pkt; 109 /* Udma queue handler */ 110 struct al_udma_q *dma_q; 111 uint32_t ring_id; 112 uint16_t next_to_use; 113 uint16_t next_to_clean; 114 /* The offset of the interrupt unmask register */ 115 uint32_t *unmask_reg_offset; 116 /* 117 * The value to write to the above register to 118 * unmask the interrupt of this ring 119 */ 120 uint32_t unmask_val; 121 struct al_eth_meta_data hal_meta; 122 /* Contex of tx packet */ 123 struct al_eth_tx_buffer *tx_buffer_info; 124 /* Contex of rx packet */ 125 struct al_eth_rx_buffer *rx_buffer_info; 126 /* Number of tx/rx_buffer_info's entries */ 127 int sw_count; 128 /* Number of hw descriptors */ 129 int hw_count; 130 /* Size (in bytes) of hw descriptors */ 131 size_t descs_size; 132 /* Size (in bytes) of hw completion descriptors, used for rx */ 133 size_t cdescs_size; 134 struct ifnet *netdev; 135 struct al_udma_q_params q_params; 136 struct buf_ring *br; 137 struct mtx br_mtx; 138 struct task enqueue_task; 139 struct taskqueue *enqueue_tq; 140 volatile uint32_t enqueue_is_running; 141 struct task cmpl_task; 142 struct taskqueue *cmpl_tq; 143 volatile uint32_t cmpl_is_running; 144 uint32_t lro_enabled; 145 struct lro_ctrl lro; 146 bus_dma_tag_t dma_buf_tag; 147 volatile uint32_t stall; 148}; 149 150#define AL_ETH_TX_RING_IDX_NEXT(tx_ring, idx) (((idx) + 1) & (AL_ETH_DEFAULT_TX_SW_DESCS - 1)) 151 152#define AL_ETH_RX_RING_IDX_NEXT(rx_ring, idx) (((idx) + 1) & (AL_ETH_DEFAULT_RX_DESCS - 1)) 153#define AL_ETH_RX_RING_IDX_ADD(rx_ring, idx, n) (((idx) + (n)) & (AL_ETH_DEFAULT_RX_DESCS - 1)) 154 155/* flow control configuration */ 156#define AL_ETH_FLOW_CTRL_RX_FIFO_TH_HIGH 0x160 157#define AL_ETH_FLOW_CTRL_RX_FIFO_TH_LOW 0x90 158#define AL_ETH_FLOW_CTRL_QUANTA 0xffff 159#define AL_ETH_FLOW_CTRL_QUANTA_TH 0x8000 160 161#define AL_ETH_FLOW_CTRL_AUTONEG 1 162#define AL_ETH_FLOW_CTRL_RX_PAUSE 2 163#define AL_ETH_FLOW_CTRL_TX_PAUSE 4 164 165/* link configuration for 1G port */ 166struct al_eth_link_config { 167 int old_link; 168 /* Describes what we actually have. */ 169 int active_duplex; 170 int active_speed; 171 172 /* current flow control status */ 173 uint8_t flow_ctrl_active; 174 /* supported configuration (can be changed from ethtool) */ 175 uint8_t flow_ctrl_supported; 176 177 /* the following are not relevant to RGMII */ 178 bool force_1000_base_x; 179 bool autoneg; 180}; 181 182/* SFP detection event */ 183enum al_eth_sfp_detect_evt { 184 /* No change (no connect, disconnect, or new SFP module */ 185 AL_ETH_SFP_DETECT_EVT_NO_CHANGE, 186 /* SFP module connected */ 187 AL_ETH_SFP_DETECT_EVT_CONNECTED, 188 /* SFP module disconnected */ 189 AL_ETH_SFP_DETECT_EVT_DISCONNECTED, 190 /* SFP module replaced */ 191 AL_ETH_SFP_DETECT_EVT_CHANGED, 192}; 193 194/* SFP detection status */ 195struct al_eth_sfp_detect_stat { 196 /* Status is valid (i.e. rest of fields are valid) */ 197 bool valid; 198 bool connected; 199 uint8_t sfp_10g; 200 uint8_t sfp_1g; 201 uint8_t sfp_cable_tech; 202 bool lt_en; 203 bool an_en; 204 enum al_eth_mac_mode mac_mode; 205}; 206 207struct al_eth_retimer_params { 208 bool exist; 209 uint8_t bus_id; 210 uint8_t i2c_addr; 211 enum al_eth_retimer_channel channel; 212}; 213 214struct msix_entry { 215 int entry; 216 int vector; 217}; 218 219/* board specific private data structure */ 220struct al_eth_adapter { 221 enum board_t board_type; 222 device_t miibus; 223 struct mii_data *mii; 224 uint16_t dev_id; 225 uint8_t rev_id; 226 227 device_t dev; 228 struct ifnet *netdev; 229 struct ifmedia media; 230 struct resource *udma_res; 231 struct resource *mac_res; 232 struct resource *ec_res; 233 int if_flags; 234 struct callout wd_callout; 235 struct mtx wd_mtx; 236 struct callout stats_callout; 237 struct mtx stats_mtx; 238 239 /* this is for intx mode */ 240 void *irq_cookie; 241 struct resource *irq_res; 242 243 /* 244 * Some features need tri-state capability, 245 * thus the additional *_CAPABLE flags. 246 */ 247 uint32_t flags; 248#define AL_ETH_FLAG_MSIX_CAPABLE (uint32_t)(1 << 1) 249#define AL_ETH_FLAG_MSIX_ENABLED (uint32_t)(1 << 2) 250#define AL_ETH_FLAG_IN_NETPOLL (uint32_t)(1 << 3) 251#define AL_ETH_FLAG_MQ_CAPABLE (uint32_t)(1 << 4) 252#define AL_ETH_FLAG_SRIOV_CAPABLE (uint32_t)(1 << 5) 253#define AL_ETH_FLAG_SRIOV_ENABLED (uint32_t)(1 << 6) 254#define AL_ETH_FLAG_RESET_REQUESTED (uint32_t)(1 << 7) 255 256 struct al_hal_eth_adapter hal_adapter; 257 258 /* 259 * Rx packets that shorter that this len will be copied to the mbuf 260 */ 261 unsigned int small_copy_len; 262 263 /* Maximum size for rx buffer */ 264 unsigned int max_rx_buff_alloc_size; 265 uint32_t rx_mbuf_sz; 266 267 /* Tx fast path data */ 268 int num_tx_queues; 269 270 /* Rx fast path data */ 271 int num_rx_queues; 272 273 /* TX */ 274 struct al_eth_ring tx_ring[AL_ETH_NUM_QUEUES]; 275 276 /* RX */ 277 struct al_eth_ring rx_ring[AL_ETH_NUM_QUEUES]; 278 279 enum al_iofic_mode int_mode; 280 281#define AL_ETH_MGMT_IRQ_IDX 0 282#define AL_ETH_RXQ_IRQ_IDX(adapter, q) (1 + (q)) 283#define AL_ETH_TXQ_IRQ_IDX(adapter, q) (1 + (adapter)->num_rx_queues + (q)) 284 struct al_eth_irq irq_tbl[AL_ETH_MAX_MSIX_VEC]; 285 struct msix_entry *msix_entries; 286 int msix_vecs; 287 int irq_vecs; 288 289 unsigned int tx_usecs, rx_usecs; /* interrupt coalescing */ 290 291 unsigned int tx_ring_count; 292 unsigned int tx_descs_count; 293 unsigned int rx_ring_count; 294 unsigned int rx_descs_count; 295 296 /* RSS */ 297 uint32_t toeplitz_hash_key[AL_ETH_RX_HASH_KEY_NUM]; 298#define AL_ETH_RX_RSS_TABLE_SIZE AL_ETH_RX_THASH_TABLE_SIZE 299 uint8_t rss_ind_tbl[AL_ETH_RX_RSS_TABLE_SIZE]; 300 301 uint32_t msg_enable; 302 struct al_eth_mac_stats mac_stats; 303 304 enum al_eth_mac_mode mac_mode; 305 bool mac_mode_set; /* Relevant only when 'auto_speed' is set */ 306 uint8_t mac_addr[ETHER_ADDR_LEN]; 307 /* mdio and phy*/ 308 bool phy_exist; 309 struct mii_bus *mdio_bus; 310 struct phy_device *phydev; 311 uint8_t phy_addr; 312 struct al_eth_link_config link_config; 313 314 /* HAL layer data */ 315 int id_number; 316 char name[AL_ETH_NAME_MAX_LEN]; 317 void *internal_pcie_base; /* use for ALPINE_NIC devices */ 318 void *udma_base; 319 void *ec_base; 320 void *mac_base; 321 322 struct al_eth_flow_control_params flow_ctrl_params; 323 324 struct al_eth_adapter_params eth_hal_params; 325 326 struct task link_status_task; 327 uint32_t link_poll_interval; /* task interval in mSec */ 328 329 bool serdes_init; 330 struct al_serdes_grp_obj serdes_obj; 331 uint8_t serdes_grp; 332 uint8_t serdes_lane; 333 334 bool an_en; /* run kr auto-negotiation */ 335 bool lt_en; /* run kr link-training */ 336 337 bool sfp_detection_needed; /* true if need to run sfp detection */ 338 bool auto_speed; /* true if allowed to change SerDes speed configuration */ 339 uint8_t i2c_adapter_id; /* identifier for the i2c adapter to use to access SFP+ module */ 340 enum al_eth_ref_clk_freq ref_clk_freq; /* reference clock frequency */ 341 unsigned int mdio_freq; /* MDIO frequency [Khz] */ 342 343 bool up; 344 345 bool last_link; 346 bool last_establish_failed; 347 struct al_eth_lm_context lm_context; 348 bool use_lm; 349 350 bool dont_override_serdes; /* avoid overriding serdes parameters 351 to preset static values */ 352 struct mtx serdes_config_lock; 353 struct mtx if_rx_lock; 354 355 uint32_t wol; 356 357 struct al_eth_retimer_params retimer; 358 359 bool phy_fixup_needed; 360 361 enum al_eth_lm_max_speed max_speed; 362}; 363 364#endif /* !(AL_ETH_H) */ 365