1/* 2 * Copyright 2008-2012 Freescale Semiconductor Inc. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * * Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 8 * * Redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the 10 * documentation and/or other materials provided with the distribution. 11 * * Neither the name of Freescale Semiconductor nor the 12 * names of its contributors may be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * 16 * ALTERNATIVELY, this software may be distributed under the terms of the 17 * GNU General Public License ("GPL") as published by the Free Software 18 * Foundation, either version 2 of that License or (at your option) any 19 * later version. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#ifndef __FSL_FMAN_TGEC_H 34#define __FSL_FMAN_TGEC_H 35 36#include "common/general.h" 37#include "fsl_enet.h" 38 39 40/* Transmit Inter-Packet Gap Length Register (TX_IPG_LENGTH) */ 41#define TGEC_TX_IPG_LENGTH_MASK 0x000003ff 42 43enum tgec_counters { 44 E_TGEC_COUNTER_R64, 45 E_TGEC_COUNTER_R127, 46 E_TGEC_COUNTER_R255, 47 E_TGEC_COUNTER_R511, 48 E_TGEC_COUNTER_R1023, 49 E_TGEC_COUNTER_R1518, 50 E_TGEC_COUNTER_R1519X, 51 E_TGEC_COUNTER_TRFRG, 52 E_TGEC_COUNTER_TRJBR, 53 E_TGEC_COUNTER_RDRP, 54 E_TGEC_COUNTER_RALN, 55 E_TGEC_COUNTER_TRUND, 56 E_TGEC_COUNTER_TROVR, 57 E_TGEC_COUNTER_RXPF, 58 E_TGEC_COUNTER_TXPF, 59 E_TGEC_COUNTER_ROCT, 60 E_TGEC_COUNTER_RMCA, 61 E_TGEC_COUNTER_RBCA, 62 E_TGEC_COUNTER_RPKT, 63 E_TGEC_COUNTER_RUCA, 64 E_TGEC_COUNTER_RERR, 65 E_TGEC_COUNTER_TOCT, 66 E_TGEC_COUNTER_TMCA, 67 E_TGEC_COUNTER_TBCA, 68 E_TGEC_COUNTER_TUCA, 69 E_TGEC_COUNTER_TERR 70}; 71 72/* Command and Configuration Register (COMMAND_CONFIG) */ 73#define CMD_CFG_EN_TIMESTAMP 0x00100000 74#define CMD_CFG_TX_ADDR_INS_SEL 0x00080000 75#define CMD_CFG_NO_LEN_CHK 0x00020000 76#define CMD_CFG_SEND_IDLE 0x00010000 77#define CMD_CFG_RX_ER_DISC 0x00004000 78#define CMD_CFG_CMD_FRM_EN 0x00002000 79#define CMD_CFG_STAT_CLR 0x00001000 80#define CMD_CFG_LOOPBACK_EN 0x00000400 81#define CMD_CFG_TX_ADDR_INS 0x00000200 82#define CMD_CFG_PAUSE_IGNORE 0x00000100 83#define CMD_CFG_PAUSE_FWD 0x00000080 84#define CMD_CFG_PROMIS_EN 0x00000010 85#define CMD_CFG_WAN_MODE 0x00000008 86#define CMD_CFG_RX_EN 0x00000002 87#define CMD_CFG_TX_EN 0x00000001 88 89/* Interrupt Mask Register (IMASK) */ 90#define TGEC_IMASK_MDIO_SCAN_EVENT 0x00010000 91#define TGEC_IMASK_MDIO_CMD_CMPL 0x00008000 92#define TGEC_IMASK_REM_FAULT 0x00004000 93#define TGEC_IMASK_LOC_FAULT 0x00002000 94#define TGEC_IMASK_TX_ECC_ER 0x00001000 95#define TGEC_IMASK_TX_FIFO_UNFL 0x00000800 96#define TGEC_IMASK_TX_FIFO_OVFL 0x00000400 97#define TGEC_IMASK_TX_ER 0x00000200 98#define TGEC_IMASK_RX_FIFO_OVFL 0x00000100 99#define TGEC_IMASK_RX_ECC_ER 0x00000080 100#define TGEC_IMASK_RX_JAB_FRM 0x00000040 101#define TGEC_IMASK_RX_OVRSZ_FRM 0x00000020 102#define TGEC_IMASK_RX_RUNT_FRM 0x00000010 103#define TGEC_IMASK_RX_FRAG_FRM 0x00000008 104#define TGEC_IMASK_RX_LEN_ER 0x00000004 105#define TGEC_IMASK_RX_CRC_ER 0x00000002 106#define TGEC_IMASK_RX_ALIGN_ER 0x00000001 107 108#define TGEC_EVENTS_MASK \ 109 ((uint32_t)(TGEC_IMASK_MDIO_SCAN_EVENT | \ 110 TGEC_IMASK_MDIO_CMD_CMPL | \ 111 TGEC_IMASK_REM_FAULT | \ 112 TGEC_IMASK_LOC_FAULT | \ 113 TGEC_IMASK_TX_ECC_ER | \ 114 TGEC_IMASK_TX_FIFO_UNFL | \ 115 TGEC_IMASK_TX_FIFO_OVFL | \ 116 TGEC_IMASK_TX_ER | \ 117 TGEC_IMASK_RX_FIFO_OVFL | \ 118 TGEC_IMASK_RX_ECC_ER | \ 119 TGEC_IMASK_RX_JAB_FRM | \ 120 TGEC_IMASK_RX_OVRSZ_FRM | \ 121 TGEC_IMASK_RX_RUNT_FRM | \ 122 TGEC_IMASK_RX_FRAG_FRM | \ 123 TGEC_IMASK_RX_LEN_ER | \ 124 TGEC_IMASK_RX_CRC_ER | \ 125 TGEC_IMASK_RX_ALIGN_ER)) 126 127/* Hashtable Control Register (HASHTABLE_CTRL) */ 128#define TGEC_HASH_MCAST_SHIFT 23 129#define TGEC_HASH_MCAST_EN 0x00000200 130#define TGEC_HASH_ADR_MSK 0x000001ff 131 132#define DEFAULT_WAN_MODE_ENABLE FALSE 133#define DEFAULT_PROMISCUOUS_MODE_ENABLE FALSE 134#define DEFAULT_PAUSE_FORWARD_ENABLE FALSE 135#define DEFAULT_PAUSE_IGNORE FALSE 136#define DEFAULT_TX_ADDR_INS_ENABLE FALSE 137#define DEFAULT_LOOPBACK_ENABLE FALSE 138#define DEFAULT_CMD_FRAME_ENABLE FALSE 139#define DEFAULT_RX_ERROR_DISCARD FALSE 140#define DEFAULT_SEND_IDLE_ENABLE FALSE 141#define DEFAULT_NO_LENGTH_CHECK_ENABLE TRUE 142#define DEFAULT_LGTH_CHECK_NOSTDR FALSE 143#define DEFAULT_TIME_STAMP_ENABLE FALSE 144#define DEFAULT_TX_IPG_LENGTH 12 145#define DEFAULT_MAX_FRAME_LENGTH 0x600 146#define DEFAULT_PAUSE_QUANT 0xf000 147 148/* 149 * 10G memory map 150 */ 151struct tgec_regs { 152 uint32_t tgec_id; /* 0x000 Controller ID */ 153 uint32_t reserved001[1]; /* 0x004 */ 154 uint32_t command_config; /* 0x008 Control and configuration */ 155 uint32_t mac_addr_0; /* 0x00c Lower 32 bits of the MAC adr */ 156 uint32_t mac_addr_1; /* 0x010 Upper 16 bits of the MAC adr */ 157 uint32_t maxfrm; /* 0x014 Maximum frame length */ 158 uint32_t pause_quant; /* 0x018 Pause quanta */ 159 uint32_t rx_fifo_sections; /* 0x01c */ 160 uint32_t tx_fifo_sections; /* 0x020 */ 161 uint32_t rx_fifo_almost_f_e; /* 0x024 */ 162 uint32_t tx_fifo_almost_f_e; /* 0x028 */ 163 uint32_t hashtable_ctrl; /* 0x02c Hash table control*/ 164 uint32_t mdio_cfg_status; /* 0x030 */ 165 uint32_t mdio_command; /* 0x034 */ 166 uint32_t mdio_data; /* 0x038 */ 167 uint32_t mdio_regaddr; /* 0x03c */ 168 uint32_t status; /* 0x040 */ 169 uint32_t tx_ipg_len; /* 0x044 Transmitter inter-packet-gap */ 170 uint32_t mac_addr_2; /* 0x048 Lower 32 bits of 2nd MAC adr */ 171 uint32_t mac_addr_3; /* 0x04c Upper 16 bits of 2nd MAC adr */ 172 uint32_t rx_fifo_ptr_rd; /* 0x050 */ 173 uint32_t rx_fifo_ptr_wr; /* 0x054 */ 174 uint32_t tx_fifo_ptr_rd; /* 0x058 */ 175 uint32_t tx_fifo_ptr_wr; /* 0x05c */ 176 uint32_t imask; /* 0x060 Interrupt mask */ 177 uint32_t ievent; /* 0x064 Interrupt event */ 178 uint32_t udp_port; /* 0x068 Defines a UDP Port number */ 179 uint32_t type_1588v2; /* 0x06c Type field for 1588v2 */ 180 uint32_t reserved070[4]; /* 0x070 */ 181 /*10Ge Statistics Counter */ 182 uint32_t tfrm_u; /* 80 aFramesTransmittedOK */ 183 uint32_t tfrm_l; /* 84 aFramesTransmittedOK */ 184 uint32_t rfrm_u; /* 88 aFramesReceivedOK */ 185 uint32_t rfrm_l; /* 8c aFramesReceivedOK */ 186 uint32_t rfcs_u; /* 90 aFrameCheckSequenceErrors */ 187 uint32_t rfcs_l; /* 94 aFrameCheckSequenceErrors */ 188 uint32_t raln_u; /* 98 aAlignmentErrors */ 189 uint32_t raln_l; /* 9c aAlignmentErrors */ 190 uint32_t txpf_u; /* A0 aPAUSEMACCtrlFramesTransmitted */ 191 uint32_t txpf_l; /* A4 aPAUSEMACCtrlFramesTransmitted */ 192 uint32_t rxpf_u; /* A8 aPAUSEMACCtrlFramesReceived */ 193 uint32_t rxpf_l; /* Ac aPAUSEMACCtrlFramesReceived */ 194 uint32_t rlong_u; /* B0 aFrameTooLongErrors */ 195 uint32_t rlong_l; /* B4 aFrameTooLongErrors */ 196 uint32_t rflr_u; /* B8 aInRangeLengthErrors */ 197 uint32_t rflr_l; /* Bc aInRangeLengthErrors */ 198 uint32_t tvlan_u; /* C0 VLANTransmittedOK */ 199 uint32_t tvlan_l; /* C4 VLANTransmittedOK */ 200 uint32_t rvlan_u; /* C8 VLANReceivedOK */ 201 uint32_t rvlan_l; /* Cc VLANReceivedOK */ 202 uint32_t toct_u; /* D0 ifOutOctets */ 203 uint32_t toct_l; /* D4 ifOutOctets */ 204 uint32_t roct_u; /* D8 ifInOctets */ 205 uint32_t roct_l; /* Dc ifInOctets */ 206 uint32_t ruca_u; /* E0 ifInUcastPkts */ 207 uint32_t ruca_l; /* E4 ifInUcastPkts */ 208 uint32_t rmca_u; /* E8 ifInMulticastPkts */ 209 uint32_t rmca_l; /* Ec ifInMulticastPkts */ 210 uint32_t rbca_u; /* F0 ifInBroadcastPkts */ 211 uint32_t rbca_l; /* F4 ifInBroadcastPkts */ 212 uint32_t terr_u; /* F8 ifOutErrors */ 213 uint32_t terr_l; /* Fc ifOutErrors */ 214 uint32_t reserved100[2]; /* 100-108*/ 215 uint32_t tuca_u; /* 108 ifOutUcastPkts */ 216 uint32_t tuca_l; /* 10c ifOutUcastPkts */ 217 uint32_t tmca_u; /* 110 ifOutMulticastPkts */ 218 uint32_t tmca_l; /* 114 ifOutMulticastPkts */ 219 uint32_t tbca_u; /* 118 ifOutBroadcastPkts */ 220 uint32_t tbca_l; /* 11c ifOutBroadcastPkts */ 221 uint32_t rdrp_u; /* 120 etherStatsDropEvents */ 222 uint32_t rdrp_l; /* 124 etherStatsDropEvents */ 223 uint32_t reoct_u; /* 128 etherStatsOctets */ 224 uint32_t reoct_l; /* 12c etherStatsOctets */ 225 uint32_t rpkt_u; /* 130 etherStatsPkts */ 226 uint32_t rpkt_l; /* 134 etherStatsPkts */ 227 uint32_t trund_u; /* 138 etherStatsUndersizePkts */ 228 uint32_t trund_l; /* 13c etherStatsUndersizePkts */ 229 uint32_t r64_u; /* 140 etherStatsPkts64Octets */ 230 uint32_t r64_l; /* 144 etherStatsPkts64Octets */ 231 uint32_t r127_u; /* 148 etherStatsPkts65to127Octets */ 232 uint32_t r127_l; /* 14c etherStatsPkts65to127Octets */ 233 uint32_t r255_u; /* 150 etherStatsPkts128to255Octets */ 234 uint32_t r255_l; /* 154 etherStatsPkts128to255Octets */ 235 uint32_t r511_u; /* 158 etherStatsPkts256to511Octets */ 236 uint32_t r511_l; /* 15c etherStatsPkts256to511Octets */ 237 uint32_t r1023_u; /* 160 etherStatsPkts512to1023Octets */ 238 uint32_t r1023_l; /* 164 etherStatsPkts512to1023Octets */ 239 uint32_t r1518_u; /* 168 etherStatsPkts1024to1518Octets */ 240 uint32_t r1518_l; /* 16c etherStatsPkts1024to1518Octets */ 241 uint32_t r1519x_u; /* 170 etherStatsPkts1519toX */ 242 uint32_t r1519x_l; /* 174 etherStatsPkts1519toX */ 243 uint32_t trovr_u; /* 178 etherStatsOversizePkts */ 244 uint32_t trovr_l; /* 17c etherStatsOversizePkts */ 245 uint32_t trjbr_u; /* 180 etherStatsJabbers */ 246 uint32_t trjbr_l; /* 184 etherStatsJabbers */ 247 uint32_t trfrg_u; /* 188 etherStatsFragments */ 248 uint32_t trfrg_l; /* 18C etherStatsFragments */ 249 uint32_t rerr_u; /* 190 ifInErrors */ 250 uint32_t rerr_l; /* 194 ifInErrors */ 251}; 252 253/** 254 * struct tgec_cfg - TGEC configuration 255 * 256 * @rx_error_discard: Receive Erroneous Frame Discard Enable. When set to 1 257 * any frame received with an error is discarded in the 258 * Core and not forwarded to the Client interface. 259 * When set to 0 (Reset value), erroneous Frames are 260 * forwarded to the Client interface with ff_rx_err 261 * asserted. 262 * @pause_ignore: Ignore Pause Frame Quanta. If set to 1 received pause 263 * frames are ignored by the MAC. When set to 0 264 * (Reset value) the transmit process is stopped for the 265 * amount of time specified in the pause quanta received 266 * within a pause frame. 267 * @pause_forward_enable: 268 * Terminate / Forward Pause Frames. If set to 1 pause 269 * frames are forwarded to the user application. When set 270 * to 0 (Reset value) pause frames are terminated and 271 * discarded within the MAC. 272 * @no_length_check_enable: 273 * Payload Length Check Disable. When set to 0 274 * (Reset value), the Core checks the frame's payload 275 * length with the Frame Length/Type field, when set to 1 276 * the payload length check is disabled. 277 * @cmd_frame_enable: Enables reception of all command frames. When set to 1 278 * all Command Frames are accepted, when set to 0 279 * (Reset Value) only Pause Frames are accepted and all 280 * other Command Frames are rejected. 281 * @send_idle_enable: Force Idle Generation. When set to 1, the MAC 282 * permanently sends XGMII Idle sequences even when faults 283 * are received. 284 * @wan_mode_enable: WAN Mode Enable. Sets WAN mode (1) or LAN mode 285 * (0, default) of operation. 286 * @promiscuous_mode_enable: 287 * Enables MAC promiscuous operation. When set to 1, all 288 * frames are received without any MAC address filtering, 289 * when set to 0 (Reset value) Unicast Frames with a 290 * destination address not matching the Core MAC Address 291 * (MAC Address programmed in Registers MAC_ADDR_0 and 292 * MAC_ADDR_1 or the MAC address programmed in Registers 293 * MAC_ADDR_2 and MAC_ADDR_3) are rejected. 294 * @tx_addr_ins_enable: Set Source MAC Address on Transmit. If set to 1 the 295 * MAC overwrites the source MAC address received from the 296 * Client Interface with one of the MAC addresses. If set 297 * to 0 (Reset value), the source MAC address from the 298 * Client Interface is transmitted unmodified to the line. 299 * @loopback_enable: PHY Interface Loopback. When set to 1, the signal 300 * loop_ena is set to '1', when set to 0 (Reset value) 301 * the signal loop_ena is set to 0. 302 * @lgth_check_nostdr: The Core interprets the Length/Type field differently 303 * depending on the value of this Bit 304 * @time_stamp_enable: This bit selects between enabling and disabling the 305 * IEEE 1588 functionality. 1: IEEE 1588 is enabled 306 * 0: IEEE 1588 is disabled 307 * @max_frame_length: Maximum supported received frame length. 308 * The 10GEC MAC supports reception of any frame size up 309 * to 16,352 bytes (0x3FE0). Typical settings are 310 * 0x05EE (1,518 bytes) for standard frames. 311 * Default setting is 0x0600 (1,536 bytes). 312 * Received frames that exceed this stated maximum 313 * are truncated. 314 * @pause_quant: Pause quanta value used with transmitted pause frames. 315 * Each quanta represents a 512 bit-times. 316 * @tx_ipg_length: Transmit Inter-Packet-Gap (IPG) value. A 6-bit value: 317 * Depending on LAN or WAN mode of operation the value has 318 * the following meaning: - LAN Mode: Number of octets in 319 * steps of 4. Valid values are 8, 12, 16, ... 100. DIC is 320 * fully supported (see 10.6.1 page 49) for any setting. A 321 * default of 12 (reset value) must be set to conform to 322 * IEEE802.3ae. Warning: When set to 8, PCS layers may not 323 * be able to perform clock rate compensation. - WAN Mode: 324 * Stretch factor. Valid values are 4..15. The stretch 325 * factor is calculated as (value+1)*8. A default of 12 326 * (reset value) must be set to conform to IEEE 802.3ae 327 * (i.e. 13*8=104). A larger value shrinks the IPG 328 * (increasing bandwidth). 329 * 330 * This structure contains basic TGEC configuration and must be passed to 331 * fman_tgec_init() function. A default set of configuration values can be 332 * obtained by calling fman_tgec_defconfig(). 333 */ 334struct tgec_cfg { 335 bool rx_error_discard; 336 bool pause_ignore; 337 bool pause_forward_enable; 338 bool no_length_check_enable; 339 bool cmd_frame_enable; 340 bool send_idle_enable; 341 bool wan_mode_enable; 342 bool promiscuous_mode_enable; 343 bool tx_addr_ins_enable; 344 bool loopback_enable; 345 bool lgth_check_nostdr; 346 bool time_stamp_enable; 347 uint16_t max_frame_length; 348 uint16_t pause_quant; 349 uint32_t tx_ipg_length; 350 bool skip_fman11_workaround; 351}; 352 353 354void fman_tgec_defconfig(struct tgec_cfg *cfg); 355 356/** 357 * fman_tgec_init() - Init tgec hardware block 358 * @regs: Pointer to tgec register block 359 * @cfg: tgec configuration data 360 * @exceptions_mask: initial exceptions mask 361 * 362 * This function initializes the tgec controller and applies its 363 * basic configuration. 364 * 365 * Returns: 0 if successful, an error code otherwise. 366 */ 367 368int fman_tgec_init(struct tgec_regs *regs, struct tgec_cfg *cfg, 369 uint32_t exception_mask); 370 371void fman_tgec_enable(struct tgec_regs *regs, bool apply_rx, bool apply_tx); 372 373void fman_tgec_disable(struct tgec_regs *regs, bool apply_rx, bool apply_tx); 374 375uint32_t fman_tgec_get_revision(struct tgec_regs *regs); 376 377void fman_tgec_set_mac_address(struct tgec_regs *regs, uint8_t *macaddr); 378 379void fman_tgec_set_promiscuous(struct tgec_regs *regs, bool val); 380 381/** 382 * fman_tgec_reset_stat() - Completely resets all TGEC HW counters 383 * @regs: Pointer to TGEC register block 384 */ 385void fman_tgec_reset_stat(struct tgec_regs *regs); 386 387/** 388 * fman_tgec_get_counter() - Reads TGEC HW counters 389 * @regs: Pointer to TGEC register block 390 * @reg_name: Counter name according to the appropriate enum 391 * 392 * Returns: Required counter value 393 */ 394uint64_t fman_tgec_get_counter(struct tgec_regs *regs, 395 enum tgec_counters reg_name); 396 397/** 398 * fman_tgec_set_hash_table() - Sets the Hashtable Control Register 399 * @regs: Pointer to TGEC register block 400 * @value: Value to be written in Hashtable Control Register 401 */ 402void fman_tgec_set_hash_table(struct tgec_regs *regs, uint32_t value); 403 404/** 405 * fman_tgec_set_tx_pause_frames() - Sets the Pause Quanta Register 406 * @regs: Pointer to TGEC register block 407 * @pause_time: Pause quanta value used with transmitted pause frames. 408 * Each quanta represents a 512 bit-times 409 */ 410void fman_tgec_set_tx_pause_frames(struct tgec_regs *regs, uint16_t pause_time); 411 412/** 413 * fman_tgec_set_rx_ignore_pause_frames() - Changes the policy WRT pause frames 414 * @regs: Pointer to TGEC register block 415 * @en: Ignore/Respond to pause frame quanta 416 * 417 * Sets the value of PAUSE_IGNORE field in the COMMAND_CONFIG Register 418 * 0 - MAC stops transmit process for the duration specified 419 * in the Pause frame quanta of a received Pause frame. 420 * 1 - MAC ignores received Pause frames. 421 */ 422void fman_tgec_set_rx_ignore_pause_frames(struct tgec_regs *regs, bool en); 423 424/** 425 * fman_tgec_enable_1588_time_stamp() - change timestamp functionality 426 * @regs: Pointer to TGEC register block 427 * @en: enable/disable timestamp functionality 428 * 429 * Sets the value of EN_TIMESTAMP field in the COMMAND_CONFIG Register 430 * IEEE 1588 timestamp functionality control: 431 * 0 disabled, 1 enabled 432 */ 433 434void fman_tgec_enable_1588_time_stamp(struct tgec_regs *regs, bool en); 435 436uint32_t fman_tgec_get_event(struct tgec_regs *regs, uint32_t ev_mask); 437 438void fman_tgec_ack_event(struct tgec_regs *regs, uint32_t ev_mask); 439 440uint32_t fman_tgec_get_interrupt_mask(struct tgec_regs *regs); 441 442/** 443 * fman_tgec_add_addr_in_paddr() - Sets additional exact match MAC address 444 * @regs: Pointer to TGEC register block 445 * @addr_ptr: Pointer to 6-byte array containing the MAC address 446 * 447 * Sets the additional station MAC address 448 */ 449void fman_tgec_add_addr_in_paddr(struct tgec_regs *regs, uint8_t *addr_ptr); 450 451void fman_tgec_clear_addr_in_paddr(struct tgec_regs *regs); 452 453void fman_tgec_enable_interrupt(struct tgec_regs *regs, uint32_t ev_mask); 454 455void fman_tgec_disable_interrupt(struct tgec_regs *regs, uint32_t ev_mask); 456 457void fman_tgec_reset_filter_table(struct tgec_regs *regs); 458 459void fman_tgec_set_hash_table_entry(struct tgec_regs *regs, uint32_t crc); 460 461 462/** 463 * fman_tgec_get_max_frame_len() - Returns the maximum frame length value 464 * @regs: Pointer to TGEC register block 465 */ 466uint16_t fman_tgec_get_max_frame_len(struct tgec_regs *regs); 467 468/** 469 * fman_tgec_set_erratum_tx_fifo_corruption_10gmac_a007() - Initialize the 470 * main tgec configuration parameters 471 * @regs: Pointer to TGEC register block 472 * 473 * TODO 474 */ 475void fman_tgec_set_erratum_tx_fifo_corruption_10gmac_a007(struct tgec_regs 476 *regs); 477 478 479#endif /* __FSL_FMAN_TGEC_H */ 480