1/* 2 * Copyright 2008-2012 Freescale Semiconductor Inc. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * * Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 8 * * Redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the 10 * documentation and/or other materials provided with the distribution. 11 * * Neither the name of Freescale Semiconductor nor the 12 * names of its contributors may be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * 16 * ALTERNATIVELY, this software may be distributed under the terms of the 17 * GNU General Public License ("GPL") as published by the Free Software 18 * Foundation, either version 2 of that License or (at your option) any 19 * later version. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#ifndef __FSL_FMAN_DTSEC_H 34#define __FSL_FMAN_DTSEC_H 35 36#include "common/general.h" 37#include "fsl_enet.h" 38 39/** 40 * DOC: dTSEC Init sequence 41 * 42 * To prepare dTSEC block for transfer use the following call sequence: 43 * 44 * - fman_dtsec_defconfig() - This step is optional and yet recommended. Its 45 * use is to obtain the default dTSEC configuration parameters. 46 * 47 * - Change dtsec configuration in &dtsec_cfg. This structure will be used 48 * to customize the dTSEC behavior. 49 * 50 * - fman_dtsec_init() - Applies the configuration on dTSEC hardware. Note that 51 * dTSEC is initialized while both Tx and Rx are disabled. 52 * 53 * - fman_dtsec_set_mac_address() - Set the station address (mac address). 54 * This is used by dTSEC to match against received packets. 55 * 56 * - fman_dtsec_adjust_link() - Set the link speed and duplex parameters 57 * after the PHY establishes the link. 58 * 59 * - dtsec_enable_tx() and dtsec_enable_rx() to enable transmission and 60 * reception. 61 */ 62 63/** 64 * DOC: dTSEC Graceful stop 65 * 66 * To temporary stop dTSEC activity use fman_dtsec_stop_tx() and 67 * fman_dtsec_stop_rx(). Note that these functions request dTSEC graceful stop 68 * but return before this stop is complete. To query for graceful stop 69 * completion use fman_dtsec_get_event() and check DTSEC_IEVENT_GTSC and 70 * DTSEC_IEVENT_GRSC bits. Alternatively the dTSEC interrupt mask can be set to 71 * enable graceful stop interrupts. 72 * 73 * To resume operation after graceful stop use fman_dtsec_start_tx() and 74 * fman_dtsec_start_rx(). 75 */ 76 77/** 78 * DOC: dTSEC interrupt handling 79 * 80 * This code does not provide an interrupt handler for dTSEC. Instead this 81 * handler should be implemented and registered to the operating system by the 82 * caller. Some primitives for accessing the event status and mask registers 83 * are provided. 84 * 85 * See "dTSEC Events" section for a list of events that dTSEC can generate. 86 */ 87 88/** 89 * DOC: dTSEC Events 90 * 91 * Interrupt events cause dTSEC event bits to be set. Software may poll the 92 * event register at any time to check for pending interrupts. If an event 93 * occurs and its corresponding enable bit is set in the interrupt mask 94 * register, the event also causes a hardware interrupt at the PIC. 95 * 96 * To poll for event status use the fman_dtsec_get_event() function. 97 * To configure the interrupt mask use fman_dtsec_enable_interrupt() and 98 * fman_dtsec_disable_interrupt() functions. 99 * After servicing a dTSEC interrupt use fman_dtsec_ack_event to reset the 100 * serviced event bit. 101 * 102 * The following events may be signaled by dTSEC hardware: 103 * 104 * %DTSEC_IEVENT_BABR - Babbling receive error. This bit indicates that 105 * a frame was received with length in excess of the MAC's maximum frame length 106 * register. 107 * 108 * %DTSEC_IEVENT_RXC - Receive control (pause frame) interrupt. A pause 109 * control frame was received while Rx pause frame handling is enabled. 110 * Also see fman_dtsec_handle_rx_pause(). 111 * 112 * %DTSEC_IEVENT_MSRO - MIB counter overflow. The count for one of the MIB 113 * counters has exceeded the size of its register. 114 * 115 * %DTSEC_IEVENT_GTSC - Graceful transmit stop complete. Graceful stop is now 116 * complete. The transmitter is in a stopped state, in which only pause frames 117 * can be transmitted. 118 * Also see fman_dtsec_stop_tx(). 119 * 120 * %DTSEC_IEVENT_BABT - Babbling transmit error. The transmitted frame length 121 * has exceeded the value in the MAC's Maximum Frame Length register. 122 * 123 * %DTSEC_IEVENT_TXC - Transmit control (pause frame) interrupt. his bit 124 * indicates that a control frame was transmitted. 125 * 126 * %DTSEC_IEVENT_TXE - Transmit error. This bit indicates that an error 127 * occurred on the transmitted channel. This bit is set whenever any transmit 128 * error occurs which causes the dTSEC to discard all or part of a frame 129 * (LC, CRL, XFUN). 130 * 131 * %DTSEC_IEVENT_LC - Late collision. This bit indicates that a collision 132 * occurred beyond the collision window (slot time) in half-duplex mode. 133 * The frame is truncated with a bad CRC and the remainder of the frame 134 * is discarded. 135 * 136 * %DTSEC_IEVENT_CRL - Collision retry limit. is bit indicates that the number 137 * of successive transmission collisions has exceeded the MAC's half-duplex 138 * register's retransmission maximum count. The frame is discarded without 139 * being transmitted and transmission of the next frame commences. This only 140 * occurs while in half-duplex mode. 141 * The number of retransmit attempts can be set in 142 * &dtsec_halfdup_cfg.@retransmit before calling fman_dtsec_init(). 143 * 144 * %DTSEC_IEVENT_XFUN - Transmit FIFO underrun. This bit indicates that the 145 * transmit FIFO became empty before the complete frame was transmitted. 146 * The frame is truncated with a bad CRC and the remainder of the frame is 147 * discarded. 148 * 149 * %DTSEC_IEVENT_MAG - TBD 150 * 151 * %DTSEC_IEVENT_MMRD - MII management read completion. 152 * 153 * %DTSEC_IEVENT_MMWR - MII management write completion. 154 * 155 * %DTSEC_IEVENT_GRSC - Graceful receive stop complete. It allows the user to 156 * know if the system has completed the stop and it is safe to write to receive 157 * registers (status, control or configuration registers) that are used by the 158 * system during normal operation. 159 * 160 * %DTSEC_IEVENT_TDPE - Internal data error on transmit. This bit indicates 161 * that the dTSEC has detected a parity error on its stored transmit data, which 162 * is likely to compromise the validity of recently transferred frames. 163 * 164 * %DTSEC_IEVENT_RDPE - Internal data error on receive. This bit indicates that 165 * the dTSEC has detected a parity error on its stored receive data, which is 166 * likely to compromise the validity of recently transferred frames. 167 */ 168/* Interrupt Mask Register (IMASK) */ 169#define DTSEC_IMASK_BREN 0x80000000 170#define DTSEC_IMASK_RXCEN 0x40000000 171#define DTSEC_IMASK_MSROEN 0x04000000 172#define DTSEC_IMASK_GTSCEN 0x02000000 173#define DTSEC_IMASK_BTEN 0x01000000 174#define DTSEC_IMASK_TXCEN 0x00800000 175#define DTSEC_IMASK_TXEEN 0x00400000 176#define DTSEC_IMASK_LCEN 0x00040000 177#define DTSEC_IMASK_CRLEN 0x00020000 178#define DTSEC_IMASK_XFUNEN 0x00010000 179#define DTSEC_IMASK_ABRTEN 0x00008000 180#define DTSEC_IMASK_IFERREN 0x00004000 181#define DTSEC_IMASK_MAGEN 0x00000800 182#define DTSEC_IMASK_MMRDEN 0x00000400 183#define DTSEC_IMASK_MMWREN 0x00000200 184#define DTSEC_IMASK_GRSCEN 0x00000100 185#define DTSEC_IMASK_TDPEEN 0x00000002 186#define DTSEC_IMASK_RDPEEN 0x00000001 187 188#define DTSEC_EVENTS_MASK \ 189 ((uint32_t)(DTSEC_IMASK_BREN | \ 190 DTSEC_IMASK_RXCEN | \ 191 DTSEC_IMASK_BTEN | \ 192 DTSEC_IMASK_TXCEN | \ 193 DTSEC_IMASK_TXEEN | \ 194 DTSEC_IMASK_ABRTEN | \ 195 DTSEC_IMASK_LCEN | \ 196 DTSEC_IMASK_CRLEN | \ 197 DTSEC_IMASK_XFUNEN | \ 198 DTSEC_IMASK_IFERREN | \ 199 DTSEC_IMASK_MAGEN | \ 200 DTSEC_IMASK_TDPEEN | \ 201 DTSEC_IMASK_RDPEEN)) 202 203/* dtsec timestamp event bits */ 204#define TMR_PEMASK_TSREEN 0x00010000 205#define TMR_PEVENT_TSRE 0x00010000 206 207/* Group address bit indication */ 208#define MAC_GROUP_ADDRESS 0x0000010000000000ULL 209/* size in bytes of L2 address */ 210#define MAC_ADDRLEN 6 211 212#define DEFAULT_HALFDUP_ON FALSE 213#define DEFAULT_HALFDUP_RETRANSMIT 0xf 214#define DEFAULT_HALFDUP_COLL_WINDOW 0x37 215#define DEFAULT_HALFDUP_EXCESS_DEFER TRUE 216#define DEFAULT_HALFDUP_NO_BACKOFF FALSE 217#define DEFAULT_HALFDUP_BP_NO_BACKOFF FALSE 218#define DEFAULT_HALFDUP_ALT_BACKOFF_VAL 0x0A 219#define DEFAULT_HALFDUP_ALT_BACKOFF_EN FALSE 220#define DEFAULT_RX_DROP_BCAST FALSE 221#define DEFAULT_RX_SHORT_FRM TRUE 222#define DEFAULT_RX_LEN_CHECK FALSE 223#define DEFAULT_TX_PAD_CRC TRUE 224#define DEFAULT_TX_CRC FALSE 225#define DEFAULT_RX_CTRL_ACC FALSE 226#define DEFAULT_TX_PAUSE_TIME 0xf000 227#define DEFAULT_TBIPA 5 228#define DEFAULT_RX_PREPEND 0 229#define DEFAULT_PTP_TSU_EN TRUE 230#define DEFAULT_PTP_EXCEPTION_EN TRUE 231#define DEFAULT_PREAMBLE_LEN 7 232#define DEFAULT_RX_PREAMBLE FALSE 233#define DEFAULT_TX_PREAMBLE FALSE 234#define DEFAULT_LOOPBACK FALSE 235#define DEFAULT_RX_TIME_STAMP_EN FALSE 236#define DEFAULT_TX_TIME_STAMP_EN FALSE 237#define DEFAULT_RX_FLOW TRUE 238#define DEFAULT_TX_FLOW TRUE 239#define DEFAULT_RX_GROUP_HASH_EXD FALSE 240#define DEFAULT_TX_PAUSE_TIME_EXTD 0 241#define DEFAULT_RX_PROMISC FALSE 242#define DEFAULT_NON_BACK_TO_BACK_IPG1 0x40 243#define DEFAULT_NON_BACK_TO_BACK_IPG2 0x60 244#define DEFAULT_MIN_IFG_ENFORCEMENT 0x50 245#define DEFAULT_BACK_TO_BACK_IPG 0x60 246#define DEFAULT_MAXIMUM_FRAME 0x600 247#define DEFAULT_TBI_PHY_ADDR 5 248#define DEFAULT_WAKE_ON_LAN FALSE 249 250/* register related defines (bits, field offsets..) */ 251#define DTSEC_ID1_ID 0xffff0000 252#define DTSEC_ID1_REV_MJ 0x0000FF00 253#define DTSEC_ID1_REV_MN 0x000000ff 254 255#define DTSEC_ID2_INT_REDUCED_OFF 0x00010000 256#define DTSEC_ID2_INT_NORMAL_OFF 0x00020000 257 258#define DTSEC_ECNTRL_CLRCNT 0x00004000 259#define DTSEC_ECNTRL_AUTOZ 0x00002000 260#define DTSEC_ECNTRL_STEN 0x00001000 261#define DTSEC_ECNTRL_CFG_RO 0x80000000 262#define DTSEC_ECNTRL_GMIIM 0x00000040 263#define DTSEC_ECNTRL_TBIM 0x00000020 264#define DTSEC_ECNTRL_SGMIIM 0x00000002 265#define DTSEC_ECNTRL_RPM 0x00000010 266#define DTSEC_ECNTRL_R100M 0x00000008 267#define DTSEC_ECNTRL_RMM 0x00000004 268#define DTSEC_ECNTRL_QSGMIIM 0x00000001 269 270#define DTSEC_TCTRL_THDF 0x00000800 271#define DTSEC_TCTRL_TTSE 0x00000040 272#define DTSEC_TCTRL_GTS 0x00000020 273#define DTSEC_TCTRL_TFC_PAUSE 0x00000010 274 275/* PTV offsets */ 276#define PTV_PTE_OFST 16 277 278#define RCTRL_CFA 0x00008000 279#define RCTRL_GHTX 0x00000400 280#define RCTRL_RTSE 0x00000040 281#define RCTRL_GRS 0x00000020 282#define RCTRL_BC_REJ 0x00000010 283#define RCTRL_MPROM 0x00000008 284#define RCTRL_RSF 0x00000004 285#define RCTRL_UPROM 0x00000001 286#define RCTRL_PROM (RCTRL_UPROM | RCTRL_MPROM) 287 288#define TMR_CTL_ESFDP 0x00000800 289#define TMR_CTL_ESFDE 0x00000400 290 291#define MACCFG1_SOFT_RESET 0x80000000 292#define MACCFG1_LOOPBACK 0x00000100 293#define MACCFG1_RX_FLOW 0x00000020 294#define MACCFG1_TX_FLOW 0x00000010 295#define MACCFG1_TX_EN 0x00000001 296#define MACCFG1_RX_EN 0x00000004 297#define MACCFG1_RESET_RxMC 0x00080000 298#define MACCFG1_RESET_TxMC 0x00040000 299#define MACCFG1_RESET_RxFUN 0x00020000 300#define MACCFG1_RESET_TxFUN 0x00010000 301 302#define MACCFG2_NIBBLE_MODE 0x00000100 303#define MACCFG2_BYTE_MODE 0x00000200 304#define MACCFG2_PRE_AM_Rx_EN 0x00000080 305#define MACCFG2_PRE_AM_Tx_EN 0x00000040 306#define MACCFG2_LENGTH_CHECK 0x00000010 307#define MACCFG2_MAGIC_PACKET_EN 0x00000008 308#define MACCFG2_PAD_CRC_EN 0x00000004 309#define MACCFG2_CRC_EN 0x00000002 310#define MACCFG2_FULL_DUPLEX 0x00000001 311 312#define PREAMBLE_LENGTH_SHIFT 12 313 314#define IPGIFG_NON_BACK_TO_BACK_IPG_1_SHIFT 24 315#define IPGIFG_NON_BACK_TO_BACK_IPG_2_SHIFT 16 316#define IPGIFG_MIN_IFG_ENFORCEMENT_SHIFT 8 317 318#define IPGIFG_NON_BACK_TO_BACK_IPG_1 0x7F000000 319#define IPGIFG_NON_BACK_TO_BACK_IPG_2 0x007F0000 320#define IPGIFG_MIN_IFG_ENFORCEMENT 0x0000FF00 321#define IPGIFG_BACK_TO_BACK_IPG 0x0000007F 322 323#define HAFDUP_ALT_BEB 0x00080000 324#define HAFDUP_BP_NO_BACKOFF 0x00040000 325#define HAFDUP_NO_BACKOFF 0x00020000 326#define HAFDUP_EXCESS_DEFER 0x00010000 327#define HAFDUP_COLLISION_WINDOW 0x000003ff 328 329#define HAFDUP_ALTERNATE_BEB_TRUNCATION_SHIFT 20 330#define HAFDUP_RETRANSMISSION_MAX_SHIFT 12 331#define HAFDUP_RETRANSMISSION_MAX 0x0000f000 332 333#define NUM_OF_HASH_REGS 8 /* Number of hash table registers */ 334 335/* CAR1/2 bits */ 336#define DTSEC_CAR1_TR64 0x80000000 337#define DTSEC_CAR1_TR127 0x40000000 338#define DTSEC_CAR1_TR255 0x20000000 339#define DTSEC_CAR1_TR511 0x10000000 340#define DTSEC_CAR1_TRK1 0x08000000 341#define DTSEC_CAR1_TRMAX 0x04000000 342#define DTSEC_CAR1_TRMGV 0x02000000 343 344#define DTSEC_CAR1_RBYT 0x00010000 345#define DTSEC_CAR1_RPKT 0x00008000 346#define DTSEC_CAR1_RFCS 0x00004000 347#define DTSEC_CAR1_RMCA 0x00002000 348#define DTSEC_CAR1_RBCA 0x00001000 349#define DTSEC_CAR1_RXCF 0x00000800 350#define DTSEC_CAR1_RXPF 0x00000400 351#define DTSEC_CAR1_RXUO 0x00000200 352#define DTSEC_CAR1_RALN 0x00000100 353#define DTSEC_CAR1_RFLR 0x00000080 354#define DTSEC_CAR1_RCDE 0x00000040 355#define DTSEC_CAR1_RCSE 0x00000020 356#define DTSEC_CAR1_RUND 0x00000010 357#define DTSEC_CAR1_ROVR 0x00000008 358#define DTSEC_CAR1_RFRG 0x00000004 359#define DTSEC_CAR1_RJBR 0x00000002 360#define DTSEC_CAR1_RDRP 0x00000001 361 362#define DTSEC_CAR2_TJBR 0x00080000 363#define DTSEC_CAR2_TFCS 0x00040000 364#define DTSEC_CAR2_TXCF 0x00020000 365#define DTSEC_CAR2_TOVR 0x00010000 366#define DTSEC_CAR2_TUND 0x00008000 367#define DTSEC_CAR2_TFRG 0x00004000 368#define DTSEC_CAR2_TBYT 0x00002000 369#define DTSEC_CAR2_TPKT 0x00001000 370#define DTSEC_CAR2_TMCA 0x00000800 371#define DTSEC_CAR2_TBCA 0x00000400 372#define DTSEC_CAR2_TXPF 0x00000200 373#define DTSEC_CAR2_TDFR 0x00000100 374#define DTSEC_CAR2_TEDF 0x00000080 375#define DTSEC_CAR2_TSCL 0x00000040 376#define DTSEC_CAR2_TMCL 0x00000020 377#define DTSEC_CAR2_TLCL 0x00000010 378#define DTSEC_CAR2_TXCL 0x00000008 379#define DTSEC_CAR2_TNCL 0x00000004 380#define DTSEC_CAR2_TDRP 0x00000001 381 382#define CAM1_ERRORS_ONLY \ 383 (DTSEC_CAR1_RXPF | DTSEC_CAR1_RALN | DTSEC_CAR1_RFLR \ 384 | DTSEC_CAR1_RCDE | DTSEC_CAR1_RCSE | DTSEC_CAR1_RUND \ 385 | DTSEC_CAR1_ROVR | DTSEC_CAR1_RFRG | DTSEC_CAR1_RJBR \ 386 | DTSEC_CAR1_RDRP) 387 388#define CAM2_ERRORS_ONLY (DTSEC_CAR2_TFCS | DTSEC_CAR2_TXPF | DTSEC_CAR2_TDRP) 389 390/* 391 * Group of dTSEC specific counters relating to the standard RMON MIB Group 1 392 * (or Ethernet) statistics. 393 */ 394#define CAM1_MIB_GRP_1 \ 395 (DTSEC_CAR1_RDRP | DTSEC_CAR1_RBYT | DTSEC_CAR1_RPKT | DTSEC_CAR1_RMCA\ 396 | DTSEC_CAR1_RBCA | DTSEC_CAR1_RALN | DTSEC_CAR1_RUND | DTSEC_CAR1_ROVR\ 397 | DTSEC_CAR1_RFRG | DTSEC_CAR1_RJBR \ 398 | DTSEC_CAR1_TR64 | DTSEC_CAR1_TR127 | DTSEC_CAR1_TR255 \ 399 | DTSEC_CAR1_TR511 | DTSEC_CAR1_TRMAX) 400 401#define CAM2_MIB_GRP_1 (DTSEC_CAR2_TNCL | DTSEC_CAR2_TDRP) 402 403/* memory map */ 404 405struct dtsec_regs { 406 /* dTSEC General Control and Status Registers */ 407 uint32_t tsec_id; /* 0x000 ETSEC_ID register */ 408 uint32_t tsec_id2; /* 0x004 ETSEC_ID2 register */ 409 uint32_t ievent; /* 0x008 Interrupt event register */ 410 uint32_t imask; /* 0x00C Interrupt mask register */ 411 uint32_t reserved0010[1]; 412 uint32_t ecntrl; /* 0x014 E control register */ 413 uint32_t ptv; /* 0x018 Pause time value register */ 414 uint32_t tbipa; /* 0x01C TBI PHY address register */ 415 uint32_t tmr_ctrl; /* 0x020 Time-stamp Control register */ 416 uint32_t tmr_pevent; /* 0x024 Time-stamp event register */ 417 uint32_t tmr_pemask; /* 0x028 Timer event mask register */ 418 uint32_t reserved002c[5]; 419 uint32_t tctrl; /* 0x040 Transmit control register */ 420 uint32_t reserved0044[3]; 421 uint32_t rctrl; /* 0x050 Receive control register */ 422 uint32_t reserved0054[11]; 423 uint32_t igaddr[8]; /* 0x080-0x09C Individual/group address */ 424 uint32_t gaddr[8]; /* 0x0A0-0x0BC Group address registers 0-7 */ 425 uint32_t reserved00c0[16]; 426 uint32_t maccfg1; /* 0x100 MAC configuration #1 */ 427 uint32_t maccfg2; /* 0x104 MAC configuration #2 */ 428 uint32_t ipgifg; /* 0x108 IPG/IFG */ 429 uint32_t hafdup; /* 0x10C Half-duplex */ 430 uint32_t maxfrm; /* 0x110 Maximum frame */ 431 uint32_t reserved0114[10]; 432 uint32_t ifstat; /* 0x13C Interface status */ 433 uint32_t macstnaddr1; /* 0x140 Station Address,part 1 */ 434 uint32_t macstnaddr2; /* 0x144 Station Address,part 2 */ 435 struct { 436 uint32_t exact_match1; /* octets 1-4 */ 437 uint32_t exact_match2; /* octets 5-6 */ 438 } macaddr[15]; /* 0x148-0x1BC mac exact match addresses 1-15 */ 439 uint32_t reserved01c0[16]; 440 uint32_t tr64; /* 0x200 transmit and receive 64 byte frame counter */ 441 uint32_t tr127; /* 0x204 transmit and receive 65 to 127 byte frame 442 * counter */ 443 uint32_t tr255; /* 0x208 transmit and receive 128 to 255 byte frame 444 * counter */ 445 uint32_t tr511; /* 0x20C transmit and receive 256 to 511 byte frame 446 * counter */ 447 uint32_t tr1k; /* 0x210 transmit and receive 512 to 1023 byte frame 448 * counter */ 449 uint32_t trmax; /* 0x214 transmit and receive 1024 to 1518 byte frame 450 * counter */ 451 uint32_t trmgv; /* 0x218 transmit and receive 1519 to 1522 byte good 452 * VLAN frame count */ 453 uint32_t rbyt; /* 0x21C receive byte counter */ 454 uint32_t rpkt; /* 0x220 receive packet counter */ 455 uint32_t rfcs; /* 0x224 receive FCS error counter */ 456 uint32_t rmca; /* 0x228 RMCA receive multicast packet counter */ 457 uint32_t rbca; /* 0x22C receive broadcast packet counter */ 458 uint32_t rxcf; /* 0x230 receive control frame packet counter */ 459 uint32_t rxpf; /* 0x234 receive pause frame packet counter */ 460 uint32_t rxuo; /* 0x238 receive unknown OP code counter */ 461 uint32_t raln; /* 0x23C receive alignment error counter */ 462 uint32_t rflr; /* 0x240 receive frame length error counter */ 463 uint32_t rcde; /* 0x244 receive code error counter */ 464 uint32_t rcse; /* 0x248 receive carrier sense error counter */ 465 uint32_t rund; /* 0x24C receive undersize packet counter */ 466 uint32_t rovr; /* 0x250 receive oversize packet counter */ 467 uint32_t rfrg; /* 0x254 receive fragments counter */ 468 uint32_t rjbr; /* 0x258 receive jabber counter */ 469 uint32_t rdrp; /* 0x25C receive drop */ 470 uint32_t tbyt; /* 0x260 transmit byte counter */ 471 uint32_t tpkt; /* 0x264 transmit packet counter */ 472 uint32_t tmca; /* 0x268 transmit multicast packet counter */ 473 uint32_t tbca; /* 0x26C transmit broadcast packet counter */ 474 uint32_t txpf; /* 0x270 transmit pause control frame counter */ 475 uint32_t tdfr; /* 0x274 transmit deferral packet counter */ 476 uint32_t tedf; /* 0x278 transmit excessive deferral packet counter */ 477 uint32_t tscl; /* 0x27C transmit single collision packet counter */ 478 uint32_t tmcl; /* 0x280 transmit multiple collision packet counter */ 479 uint32_t tlcl; /* 0x284 transmit late collision packet counter */ 480 uint32_t txcl; /* 0x288 transmit excessive collision packet counter */ 481 uint32_t tncl; /* 0x28C transmit total collision counter */ 482 uint32_t reserved0290[1]; 483 uint32_t tdrp; /* 0x294 transmit drop frame counter */ 484 uint32_t tjbr; /* 0x298 transmit jabber frame counter */ 485 uint32_t tfcs; /* 0x29C transmit FCS error counter */ 486 uint32_t txcf; /* 0x2A0 transmit control frame counter */ 487 uint32_t tovr; /* 0x2A4 transmit oversize frame counter */ 488 uint32_t tund; /* 0x2A8 transmit undersize frame counter */ 489 uint32_t tfrg; /* 0x2AC transmit fragments frame counter */ 490 uint32_t car1; /* 0x2B0 carry register one register* */ 491 uint32_t car2; /* 0x2B4 carry register two register* */ 492 uint32_t cam1; /* 0x2B8 carry register one mask register */ 493 uint32_t cam2; /* 0x2BC carry register two mask register */ 494 uint32_t reserved02c0[848]; 495}; 496 497/** 498 * struct dtsec_mib_grp_1_counters - MIB counter overflows 499 * 500 * @tr64: Transmit and Receive 64 byte frame count. Increment for each 501 * good or bad frame, of any type, transmitted or received, which 502 * is 64 bytes in length. 503 * @tr127: Transmit and Receive 65 to 127 byte frame count. Increments for 504 * each good or bad frame of any type, transmitted or received, 505 * which is 65-127 bytes in length. 506 * @tr255: Transmit and Receive 128 to 255 byte frame count. Increments 507 * for each good or bad frame, of any type, transmitted or 508 * received, which is 128-255 bytes in length. 509 * @tr511: Transmit and Receive 256 to 511 byte frame count. Increments 510 * for each good or bad frame, of any type, transmitted or 511 * received, which is 256-511 bytes in length. 512 * @tr1k: Transmit and Receive 512 to 1023 byte frame count. Increments 513 * for each good or bad frame, of any type, transmitted or 514 * received, which is 512-1023 bytes in length. 515 * @trmax: Transmit and Receive 1024 to 1518 byte frame count. Increments 516 * for each good or bad frame, of any type, transmitted or 517 * received, which is 1024-1518 bytes in length. 518 * @rfrg: Receive fragments count. Increments for each received frame 519 * which is less than 64 bytes in length and contains an invalid 520 * FCS. This includes integral and non-integral lengths. 521 * @rjbr: Receive jabber count. Increments for received frames which 522 * exceed 1518 (non VLAN) or 1522 (VLAN) bytes and contain an 523 * invalid FCS. This includes alignment errors. 524 * @rdrp: Receive dropped packets count. Increments for received frames 525 * which are streamed to system but are later dropped due to lack 526 * of system resources. Does not increment for frames rejected due 527 * to address filtering. 528 * @raln: Receive alignment error count. Increments for each received 529 * frame from 64 to 1518 (non VLAN) or 1522 (VLAN) which contains 530 * an invalid FCS and is not an integral number of bytes. 531 * @rund: Receive undersize packet count. Increments each time a frame is 532 * received which is less than 64 bytes in length and contains a 533 * valid FCS and is otherwise well formed. This count does not 534 * include range length errors. 535 * @rovr: Receive oversize packet count. Increments each time a frame is 536 * received which exceeded 1518 (non VLAN) or 1522 (VLAN) and 537 * contains a valid FCS and is otherwise well formed. 538 * @rbyt: Receive byte count. Increments by the byte count of frames 539 * received, including those in bad packets, excluding preamble and 540 * SFD but including FCS bytes. 541 * @rpkt: Receive packet count. Increments for each received frame 542 * (including bad packets, all unicast, broadcast, and multicast 543 * packets). 544 * @rmca: Receive multicast packet count. Increments for each multicast 545 * frame with valid CRC and of lengths 64 to 1518 (non VLAN) or 546 * 1522 (VLAN), excluding broadcast frames. This count does not 547 * include range/length errors. 548 * @rbca: Receive broadcast packet count. Increments for each broadcast 549 * frame with valid CRC and of lengths 64 to 1518 (non VLAN) or 550 * 1522 (VLAN), excluding multicast frames. Does not include 551 * range/length errors. 552 * @tdrp: Transmit drop frame count. Increments each time a memory error 553 * or an underrun has occurred. 554 * @tncl: Transmit total collision counter. Increments by the number of 555 * collisions experienced during the transmission of a frame. Does 556 * not increment for aborted frames. 557 * 558 * The structure contains a group of dTSEC HW specific counters relating to the 559 * standard RMON MIB Group 1 (or Ethernet statistics) counters. This structure 560 * is counting only the carry events of the corresponding HW counters. 561 * 562 * tr64 to trmax notes: Frame sizes specified are considered excluding preamble 563 * and SFD but including FCS bytes. 564 */ 565struct dtsec_mib_grp_1_counters { 566 uint64_t rdrp; 567 uint64_t tdrp; 568 uint64_t rbyt; 569 uint64_t rpkt; 570 uint64_t rbca; 571 uint64_t rmca; 572 uint64_t raln; 573 uint64_t rund; 574 uint64_t rovr; 575 uint64_t rfrg; 576 uint64_t rjbr; 577 uint64_t tncl; 578 uint64_t tr64; 579 uint64_t tr127; 580 uint64_t tr255; 581 uint64_t tr511; 582 uint64_t tr1k; 583 uint64_t trmax; 584}; 585 586enum dtsec_stat_counters { 587 E_DTSEC_STAT_TR64, 588 E_DTSEC_STAT_TR127, 589 E_DTSEC_STAT_TR255, 590 E_DTSEC_STAT_TR511, 591 E_DTSEC_STAT_TR1K, 592 E_DTSEC_STAT_TRMAX, 593 E_DTSEC_STAT_TRMGV, 594 E_DTSEC_STAT_RBYT, 595 E_DTSEC_STAT_RPKT, 596 E_DTSEC_STAT_RMCA, 597 E_DTSEC_STAT_RBCA, 598 E_DTSEC_STAT_RXPF, 599 E_DTSEC_STAT_RALN, 600 E_DTSEC_STAT_RFLR, 601 E_DTSEC_STAT_RCDE, 602 E_DTSEC_STAT_RCSE, 603 E_DTSEC_STAT_RUND, 604 E_DTSEC_STAT_ROVR, 605 E_DTSEC_STAT_RFRG, 606 E_DTSEC_STAT_RJBR, 607 E_DTSEC_STAT_RDRP, 608 E_DTSEC_STAT_TFCS, 609 E_DTSEC_STAT_TBYT, 610 E_DTSEC_STAT_TPKT, 611 E_DTSEC_STAT_TMCA, 612 E_DTSEC_STAT_TBCA, 613 E_DTSEC_STAT_TXPF, 614 E_DTSEC_STAT_TNCL, 615 E_DTSEC_STAT_TDRP 616}; 617 618enum dtsec_stat_level { 619 /* No statistics */ 620 E_MAC_STAT_NONE = 0, 621 /* Only RMON MIB group 1 (ether stats). Optimized for performance */ 622 E_MAC_STAT_MIB_GRP1, 623 /* Only error counters are available. Optimized for performance */ 624 E_MAC_STAT_PARTIAL, 625 /* All counters available. Not optimized for performance */ 626 E_MAC_STAT_FULL 627}; 628 629 630/** 631 * struct dtsec_cfg - dTSEC configuration 632 * 633 * @halfdup_on: Transmit half-duplex flow control, under software 634 * control for 10/100-Mbps half-duplex media. If set, 635 * back pressure is applied to media by raising carrier. 636 * @halfdup_retransmit: Number of retransmission attempts following a collision. 637 * If this is exceeded dTSEC aborts transmission due to 638 * excessive collisions. The standard specifies the 639 * attempt limit to be 15. 640 * @halfdup_coll_window:The number of bytes of the frame during which 641 * collisions may occur. The default value of 55 642 * corresponds to the frame byte at the end of the 643 * standard 512-bit slot time window. If collisions are 644 * detected after this byte, the late collision event is 645 * asserted and transmission of current frame is aborted. 646 * @rx_drop_bcast: Discard broadcast frames. If set, all broadcast frames 647 * will be discarded by dTSEC. 648 * @rx_short_frm: Accept short frames. If set, dTSEC will accept frames 649 * of length 14..63 bytes. 650 * @rx_len_check: Length check for received frames. If set, the MAC 651 * checks the frame's length field on receive to ensure it 652 * matches the actual data field length. This only works 653 * for received frames with length field less than 1500. 654 * No check is performed for larger frames. 655 * @tx_pad_crc: Pad and append CRC. If set, the MAC pads all 656 * transmitted short frames and appends a CRC to every 657 * frame regardless of padding requirement. 658 * @tx_crc: Transmission CRC enable. If set, the MAC appends a CRC 659 * to all frames. If frames presented to the MAC have a 660 * valid length and contain a valid CRC, @tx_crc should be 661 * reset. 662 * This field is ignored if @tx_pad_crc is set. 663 * @rx_ctrl_acc: Control frame accept. If set, this overrides 802.3 664 * standard control frame behavior, and all Ethernet frames 665 * that have an ethertype of 0x8808 are treated as normal 666 * Ethernet frames and passed up to the packet interface on 667 * a DA match. Received pause control frames are passed to 668 * the packet interface only if Rx flow control is also 669 * disabled. See fman_dtsec_handle_rx_pause() function. 670 * @tx_pause_time: Transmit pause time value. This pause value is used as 671 * part of the pause frame to be sent when a transmit pause 672 * frame is initiated. If set to 0 this disables 673 * transmission of pause frames. 674 * @rx_preamble: Receive preamble enable. If set, the MAC recovers the 675 * received Ethernet 7-byte preamble and passes it to the 676 * packet interface at the start of each received frame. 677 * This field should be reset for internal MAC loop-back 678 * mode. 679 * @tx_preamble: User defined preamble enable for transmitted frames. 680 * If set, a user-defined preamble must passed to the MAC 681 * and it is transmitted instead of the standard preamble. 682 * @preamble_len: Length, in bytes, of the preamble field preceding each 683 * Ethernet start-of-frame delimiter byte. The default 684 * value of 0x7 should be used in order to guarantee 685 * reliable operation with IEEE 802.3 compliant hardware. 686 * @rx_prepend: Packet alignment padding length. The specified number 687 * of bytes (1-31) of zero padding are inserted before the 688 * start of each received frame. For Ethernet, where 689 * optional preamble extraction is enabled, the padding 690 * appears before the preamble, otherwise the padding 691 * precedes the layer 2 header. 692 * 693 * This structure contains basic dTSEC configuration and must be passed to 694 * fman_dtsec_init() function. A default set of configuration values can be 695 * obtained by calling fman_dtsec_defconfig(). 696 */ 697struct dtsec_cfg { 698 bool halfdup_on; 699 bool halfdup_alt_backoff_en; 700 bool halfdup_excess_defer; 701 bool halfdup_no_backoff; 702 bool halfdup_bp_no_backoff; 703 uint8_t halfdup_alt_backoff_val; 704 uint16_t halfdup_retransmit; 705 uint16_t halfdup_coll_window; 706 bool rx_drop_bcast; 707 bool rx_short_frm; 708 bool rx_len_check; 709 bool tx_pad_crc; 710 bool tx_crc; 711 bool rx_ctrl_acc; 712 unsigned short tx_pause_time; 713 unsigned short tbipa; 714 bool ptp_tsu_en; 715 bool ptp_exception_en; 716 bool rx_preamble; 717 bool tx_preamble; 718 unsigned char preamble_len; 719 unsigned char rx_prepend; 720 bool loopback; 721 bool rx_time_stamp_en; 722 bool tx_time_stamp_en; 723 bool rx_flow; 724 bool tx_flow; 725 bool rx_group_hash_exd; 726 bool rx_promisc; 727 uint8_t tbi_phy_addr; 728 uint16_t tx_pause_time_extd; 729 uint16_t maximum_frame; 730 uint32_t non_back_to_back_ipg1; 731 uint32_t non_back_to_back_ipg2; 732 uint32_t min_ifg_enforcement; 733 uint32_t back_to_back_ipg; 734 bool wake_on_lan; 735}; 736 737 738/** 739 * fman_dtsec_defconfig() - Get default dTSEC configuration 740 * @cfg: pointer to configuration structure. 741 * 742 * Call this function to obtain a default set of configuration values for 743 * initializing dTSEC. The user can overwrite any of the values before calling 744 * fman_dtsec_init(), if specific configuration needs to be applied. 745 */ 746void fman_dtsec_defconfig(struct dtsec_cfg *cfg); 747 748/** 749 * fman_dtsec_init() - Init dTSEC hardware block 750 * @regs: Pointer to dTSEC register block 751 * @cfg: dTSEC configuration data 752 * @iface_mode: dTSEC interface mode, the type of MAC - PHY interface. 753 * @iface_speed: 1G or 10G 754 * @macaddr: MAC station address to be assigned to the device 755 * @fm_rev_maj: major rev number 756 * @fm_rev_min: minor rev number 757 * @exceptions_mask: initial exceptions mask 758 * 759 * This function initializes dTSEC and applies basic configuration. 760 * 761 * dTSEC initialization sequence: 762 * Before enabling Rx/Tx call dtsec_set_address() to set MAC address, 763 * fman_dtsec_adjust_link() to configure interface speed and duplex and finally 764 * dtsec_enable_tx()/dtsec_enable_rx() to start transmission and reception. 765 * 766 * Returns: 0 if successful, an error code otherwise. 767 */ 768int fman_dtsec_init(struct dtsec_regs *regs, struct dtsec_cfg *cfg, 769 enum enet_interface iface_mode, 770 enum enet_speed iface_speed, 771 uint8_t *macaddr, uint8_t fm_rev_maj, 772 uint8_t fm_rev_min, 773 uint32_t exception_mask); 774 775/** 776 * fman_dtsec_enable() - Enable dTSEC Tx and Tx 777 * @regs: Pointer to dTSEC register block 778 * @apply_rx: enable rx side 779 * @apply_tx: enable tx side 780 * 781 * This function resets Tx and Rx graceful stop bit and enables dTSEC Tx and Rx. 782 */ 783void fman_dtsec_enable(struct dtsec_regs *regs, bool apply_rx, bool apply_tx); 784 785/** 786 * fman_dtsec_disable() - Disable dTSEC Tx and Rx 787 * @regs: Pointer to dTSEC register block 788 * @apply_rx: disable rx side 789 * @apply_tx: disable tx side 790 * 791 * This function disables Tx and Rx in dTSEC. 792 */ 793void fman_dtsec_disable(struct dtsec_regs *regs, bool apply_rx, bool apply_tx); 794 795/** 796 * fman_dtsec_get_revision() - Get dTSEC hardware revision 797 * @regs: Pointer to dTSEC register block 798 * 799 * Returns dtsec_id content 800 * 801 * Call this function to obtain the dTSEC hardware version. 802 */ 803uint32_t fman_dtsec_get_revision(struct dtsec_regs *regs); 804 805/** 806 * fman_dtsec_set_mac_address() - Set MAC station address 807 * @regs: Pointer to dTSEC register block 808 * @macaddr: MAC address array 809 * 810 * This function sets MAC station address. To enable unicast reception call 811 * this after fman_dtsec_init(). While promiscuous mode is disabled dTSEC will 812 * match the destination address of received unicast frames against this 813 * address. 814 */ 815void fman_dtsec_set_mac_address(struct dtsec_regs *regs, uint8_t *macaddr); 816 817/** 818 * fman_dtsec_get_mac_address() - Query MAC station address 819 * @regs: Pointer to dTSEC register block 820 * @macaddr: MAC address array 821 */ 822void fman_dtsec_get_mac_address(struct dtsec_regs *regs, uint8_t *macaddr); 823 824/** 825 * fman_dtsec_set_uc_promisc() - Sets unicast promiscuous mode 826 * @regs: Pointer to dTSEC register block 827 * @enable: Enable unicast promiscuous mode 828 * 829 * Use this function to enable/disable dTSEC L2 address filtering. If the 830 * address filtering is disabled all unicast packets are accepted. 831 * To set dTSEC in promiscuous mode call both fman_dtsec_set_uc_promisc() and 832 * fman_dtsec_set_mc_promisc() to disable filtering for both unicast and 833 * multicast addresses. 834 */ 835void fman_dtsec_set_uc_promisc(struct dtsec_regs *regs, bool enable); 836 837/** 838 * fman_dtsec_set_wol() - Enable/Disable wake on lan 839 * (magic packet support) 840 * @regs: Pointer to dTSEC register block 841 * @en: Enable Wake On Lan support in dTSEC 842 * 843 */ 844void fman_dtsec_set_wol(struct dtsec_regs *regs, bool en); 845 846/** 847 * fman_dtsec_adjust_link() - Adjust dTSEC speed/duplex settings 848 * @regs: Pointer to dTSEC register block 849 * @iface_mode: dTSEC interface mode 850 * @speed: Link speed 851 * @full_dx: True for full-duplex, false for half-duplex. 852 * 853 * This function configures the MAC to function and the desired rates. Use it 854 * to configure dTSEC after fman_dtsec_init() and whenever the link speed 855 * changes (for instance following PHY auto-negociation). 856 * 857 * Returns: 0 if successful, an error code otherwise. 858 */ 859int fman_dtsec_adjust_link(struct dtsec_regs *regs, 860 enum enet_interface iface_mode, 861 enum enet_speed speed, bool full_dx); 862 863/** 864 * fman_dtsec_set_tbi_phy_addr() - Updates TBI address field 865 * @regs: Pointer to dTSEC register block 866 * @address: Valid PHY address in the range of 1 to 31. 0 is reserved. 867 * 868 * In SGMII mode, the dTSEC's TBIPA field must contain a valid TBI PHY address 869 * so that the associated TBI PHY (i.e. the link) may be initialized. 870 * 871 * Returns: 0 if successful, an error code otherwise. 872 */ 873int fman_dtsec_set_tbi_phy_addr(struct dtsec_regs *regs, 874 uint8_t addr); 875 876/** 877 * fman_dtsec_set_max_frame_len() - Set max frame length 878 * @regs: Pointer to dTSEC register block 879 * @length: Max frame length. 880 * 881 * Sets maximum frame length for received and transmitted frames. Frames that 882 * exceeds this length are truncated. 883 */ 884void fman_dtsec_set_max_frame_len(struct dtsec_regs *regs, uint16_t length); 885 886/** 887 * fman_dtsec_get_max_frame_len() - Query max frame length 888 * @regs: Pointer to dTSEC register block 889 * 890 * Returns: the current value of the maximum frame length. 891 */ 892uint16_t fman_dtsec_get_max_frame_len(struct dtsec_regs *regs); 893 894/** 895 * fman_dtsec_handle_rx_pause() - Configure pause frame handling 896 * @regs: Pointer to dTSEC register block 897 * @en: Enable pause frame handling in dTSEC 898 * 899 * If enabled, dTSEC will handle pause frames internally. This must be disabled 900 * if dTSEC is set in half-duplex mode. 901 * If pause frame handling is disabled and &dtsec_cfg.rx_ctrl_acc is set, pause 902 * frames will be transferred to the packet interface just like regular Ethernet 903 * frames. 904 */ 905void fman_dtsec_handle_rx_pause(struct dtsec_regs *regs, bool en); 906 907/** 908 * fman_dtsec_set_tx_pause_frames() - Configure Tx pause time 909 * @regs: Pointer to dTSEC register block 910 * @time: Time value included in pause frames 911 * 912 * Call this function to set the time value used in transmitted pause frames. 913 * If time is 0, transmission of pause frames is disabled 914 */ 915void fman_dtsec_set_tx_pause_frames(struct dtsec_regs *regs, uint16_t time); 916 917/** 918 * fman_dtsec_ack_event() - Acknowledge handled events 919 * @regs: Pointer to dTSEC register block 920 * @ev_mask: Events to acknowledge 921 * 922 * After handling events signaled by dTSEC in either polling or interrupt mode, 923 * call this function to reset the associated status bits in dTSEC event 924 * register. 925 */ 926void fman_dtsec_ack_event(struct dtsec_regs *regs, uint32_t ev_mask); 927 928/** 929 * fman_dtsec_get_event() - Returns currently asserted events 930 * @regs: Pointer to dTSEC register block 931 * @ev_mask: Mask of relevant events 932 * 933 * Call this function to obtain a bit-mask of events that are currently asserted 934 * in dTSEC, taken from IEVENT register. 935 * 936 * Returns: a bit-mask of events asserted in dTSEC. 937 */ 938uint32_t fman_dtsec_get_event(struct dtsec_regs *regs, uint32_t ev_mask); 939 940/** 941 * fman_dtsec_get_interrupt_mask() - Returns a bit-mask of enabled interrupts 942 * @regs: Pointer to dTSEC register block 943 * 944 * Call this function to obtain a bit-mask of enabled interrupts 945 * in dTSEC, taken from IMASK register. 946 * 947 * Returns: a bit-mask of enabled interrupts in dTSEC. 948 */ 949uint32_t fman_dtsec_get_interrupt_mask(struct dtsec_regs *regs); 950 951void fman_dtsec_clear_addr_in_paddr(struct dtsec_regs *regs, 952 uint8_t paddr_num); 953 954void fman_dtsec_add_addr_in_paddr(struct dtsec_regs *regs, 955 uint64_t addr, 956 uint8_t paddr_num); 957 958void fman_dtsec_enable_tmr_interrupt (struct dtsec_regs *regs); 959 960void fman_dtsec_disable_tmr_interrupt(struct dtsec_regs *regs); 961 962/** 963 * fman_dtsec_disable_interrupt() - Disables interrupts for the specified events 964 * @regs: Pointer to dTSEC register block 965 * @ev_mask: Mask of relevant events 966 * 967 * Call this function to disable interrupts in dTSEC for the specified events. 968 * To enable interrupts use fman_dtsec_enable_interrupt(). 969 */ 970void fman_dtsec_disable_interrupt(struct dtsec_regs *regs, uint32_t ev_mask); 971 972/** 973 * fman_dtsec_enable_interrupt() - Enable interrupts for the specified events 974 * @regs: Pointer to dTSEC register block 975 * @ev_mask: Mask of relevant events 976 * 977 * Call this function to enable interrupts in dTSEC for the specified events. 978 * To disable interrupts use fman_dtsec_disable_interrupt(). 979 */ 980void fman_dtsec_enable_interrupt(struct dtsec_regs *regs, uint32_t ev_mask); 981 982/** 983 * fman_dtsec_set_ts() - Enables dTSEC timestamps 984 * @regs: Pointer to dTSEC register block 985 * @en: true to enable timestamps, false to disable them 986 * 987 * Call this function to enable/disable dTSEC timestamps. This affects both 988 * Tx and Rx. 989 */ 990void fman_dtsec_set_ts(struct dtsec_regs *regs, bool en); 991 992/** 993 * fman_dtsec_set_bucket() - Enables/disables a filter bucket 994 * @regs: Pointer to dTSEC register block 995 * @bucket: Bucket index 996 * @enable: true/false to enable/disable this bucket 997 * 998 * This function enables or disables the specified bucket. Enabling a bucket 999 * associated with an address configures dTSEC to accept received packets 1000 * with that destination address. 1001 * Multiple addresses may be associated with the same bucket. Disabling a 1002 * bucket will affect all addresses associated with that bucket. A bucket that 1003 * is enabled requires further filtering and verification in the upper layers 1004 * 1005 */ 1006void fman_dtsec_set_bucket(struct dtsec_regs *regs, int bucket, bool enable); 1007 1008/** 1009 * dtsec_set_hash_table() - insert a crc code into thr filter table 1010 * @regs: Pointer to dTSEC register block 1011 * @crc: crc to insert 1012 * @mcast: true is this is a multicast address 1013 * @ghtx: true if we are in ghtx mode 1014 * 1015 * This function inserts a crc code into the filter table. 1016 */ 1017void fman_dtsec_set_hash_table(struct dtsec_regs *regs, uint32_t crc, 1018 bool mcast, bool ghtx); 1019 1020/** 1021 * fman_dtsec_reset_filter_table() - Resets the address filtering table 1022 * @regs: Pointer to dTSEC register block 1023 * @mcast: Reset multicast entries 1024 * @ucast: Reset unicast entries 1025 * 1026 * Resets all entries in L2 address filter table. After calling this function 1027 * all buckets enabled using fman_dtsec_set_bucket() will be disabled. 1028 * If dtsec_init_filter_table() was called with @unicast_hash set to false, 1029 * @ucast argument is ignored. 1030 * This does not affect the primary nor the 15 additional addresses configured 1031 * using dtsec_set_address() or dtsec_set_match_address(). 1032 */ 1033void fman_dtsec_reset_filter_table(struct dtsec_regs *regs, bool mcast, 1034 bool ucast); 1035 1036/** 1037 * fman_dtsec_set_mc_promisc() - Set multicast promiscuous mode 1038 * @regs: Pointer to dTSEC register block 1039 * @enable: Enable multicast promiscuous mode 1040 * 1041 * Call this to enable/disable L2 address filtering for multicast packets. 1042 */ 1043void fman_dtsec_set_mc_promisc(struct dtsec_regs *regs, bool enable); 1044 1045/* statistics APIs */ 1046 1047/** 1048 * fman_dtsec_set_stat_level() - Enable a group of MIB statistics counters 1049 * @regs: Pointer to dTSEC register block 1050 * @level: Specifies a certain group of dTSEC MIB HW counters or _all_, 1051 * to specify all the existing counters. 1052 * If set to _none_, it disables all the counters. 1053 * 1054 * Enables the MIB statistics hw counters and sets up the carry interrupt 1055 * masks for the counters corresponding to the @level input parameter. 1056 * 1057 * Returns: error if invalid @level value given. 1058 */ 1059int fman_dtsec_set_stat_level(struct dtsec_regs *regs, 1060 enum dtsec_stat_level level); 1061 1062/** 1063 * fman_dtsec_reset_stat() - Completely resets all dTSEC HW counters 1064 * @regs: Pointer to dTSEC register block 1065 */ 1066void fman_dtsec_reset_stat(struct dtsec_regs *regs); 1067 1068/** 1069 * fman_dtsec_get_clear_carry_regs() - Read and clear carry bits (CAR1-2 registers) 1070 * @regs: Pointer to dTSEC register block 1071 * @car1: car1 register value 1072 * @car2: car2 register value 1073 * 1074 * When set, the carry bits signal that an overflow occurred on the 1075 * corresponding counters. 1076 * Note that the carry bits (CAR1-2 registers) will assert the 1077 * %DTSEC_IEVENT_MSRO interrupt if unmasked (via CAM1-2 regs). 1078 * 1079 * Returns: true if overflow occurred, otherwise - false 1080 */ 1081bool fman_dtsec_get_clear_carry_regs(struct dtsec_regs *regs, 1082 uint32_t *car1, uint32_t *car2); 1083 1084uint32_t fman_dtsec_check_and_clear_tmr_event(struct dtsec_regs *regs); 1085 1086uint32_t fman_dtsec_get_stat_counter(struct dtsec_regs *regs, 1087 enum dtsec_stat_counters reg_name); 1088 1089void fman_dtsec_start_tx(struct dtsec_regs *regs); 1090void fman_dtsec_start_rx(struct dtsec_regs *regs); 1091void fman_dtsec_stop_tx(struct dtsec_regs *regs); 1092void fman_dtsec_stop_rx(struct dtsec_regs *regs); 1093uint32_t fman_dtsec_get_rctrl(struct dtsec_regs *regs); 1094 1095 1096#endif /* __FSL_FMAN_DTSEC_H */ 1097