1/*
2 * Copyright 2008-2012 Freescale Semiconductor Inc.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *     * Redistributions of source code must retain the above copyright
7 *       notice, this list of conditions and the following disclaimer.
8 *     * Redistributions in binary form must reproduce the above copyright
9 *       notice, this list of conditions and the following disclaimer in the
10 *       documentation and/or other materials provided with the distribution.
11 *     * Neither the name of Freescale Semiconductor nor the
12 *       names of its contributors may be used to endorse or promote products
13 *       derived from this software without specific prior written permission.
14 *
15 *
16 * ALTERNATIVELY, this software may be distributed under the terms of the
17 * GNU General Public License ("GPL") as published by the Free Software
18 * Foundation, either version 2 of that License or (at your option) any
19 * later version.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33
34/******************************************************************************
35 @File          memac.h
36
37 @Description   FM Multirate Ethernet MAC (mEMAC)
38*//***************************************************************************/
39#ifndef __MEMAC_H
40#define __MEMAC_H
41
42#include "std_ext.h"
43#include "error_ext.h"
44#include "list_ext.h"
45
46#include "fsl_fman_memac_mii_acc.h"
47#include "fm_mac.h"
48#include "fsl_fman_memac.h"
49
50
51#define MEMAC_default_exceptions    \
52        ((uint32_t)(MEMAC_IMASK_TSECC_ER | MEMAC_IMASK_TECC_ER | MEMAC_IMASK_RECC_ER | MEMAC_IMASK_MGI))
53
54#define GET_EXCEPTION_FLAG(bitMask, exception)       switch (exception){    \
55    case e_FM_MAC_EX_10G_1TX_ECC_ER:                                        \
56        bitMask = MEMAC_IMASK_TECC_ER; break;                               \
57    case e_FM_MAC_EX_10G_RX_ECC_ER:                                         \
58        bitMask = MEMAC_IMASK_RECC_ER; break;                               \
59    case e_FM_MAC_EX_TS_FIFO_ECC_ERR:                                       \
60        bitMask = MEMAC_IMASK_TSECC_ER; break;                              \
61    case e_FM_MAC_EX_MAGIC_PACKET_INDICATION:                               \
62        bitMask = MEMAC_IMASK_MGI; break;                                   \
63    default: bitMask = 0;break;}
64
65
66typedef struct
67{
68    t_FmMacControllerDriver     fmMacControllerDriver;               /**< Upper Mac control block */
69    t_Handle                    h_App;                               /**< Handle to the upper layer application  */
70    struct memac_regs           *p_MemMap;                           /**< Pointer to MAC memory mapped registers */
71    struct memac_mii_access_mem_map *p_MiiMemMap;                        /**< Pointer to MII memory mapped registers */
72    uint64_t                    addr;                                /**< MAC address of device */
73    e_EnetMode                  enetMode;                            /**< Ethernet physical interface  */
74    t_FmMacExceptionCallback    *f_Exception;
75    int                         mdioIrq;
76    t_FmMacExceptionCallback    *f_Event;
77    bool                        indAddrRegUsed[MEMAC_NUM_OF_PADDRS]; /**< Whether a particular individual address recognition register is being used */
78    uint64_t                    paddr[MEMAC_NUM_OF_PADDRS];          /**< MAC address for particular individual address recognition register */
79    uint8_t                     numOfIndAddrInRegs;                  /**< Number of individual addresses in registers for this station. */
80    t_EthHash                   *p_MulticastAddrHash;                /**< Pointer to driver's global address hash table  */
81    t_EthHash                   *p_UnicastAddrHash;                  /**< Pointer to driver's individual address hash table  */
82    bool                        debugMode;
83    uint8_t                     macId;
84    uint32_t                    exceptions;
85    struct memac_cfg            *p_MemacDriverParam;
86} t_Memac;
87
88
89/* Internal PHY access */
90#define PHY_MDIO_ADDR               0
91
92/* Internal PHY Registers - SGMII */
93#define PHY_SGMII_CR_PHY_RESET          0x8000
94#define PHY_SGMII_CR_RESET_AN           0x0200
95#define PHY_SGMII_CR_DEF_VAL            0x1140
96#define PHY_SGMII_DEV_ABILITY_SGMII     0x4001
97#define PHY_SGMII_DEV_ABILITY_1000X     0x01A0
98#define PHY_SGMII_IF_SPEED_GIGABIT	0x0008
99#define PHY_SGMII_IF_MODE_AN            0x0002
100#define PHY_SGMII_IF_MODE_SGMII         0x0001
101#define PHY_SGMII_IF_MODE_1000X         0x0000
102
103
104#define MEMAC_TO_MII_OFFSET         0x030       /* Offset from the MEM map to the MDIO mem map */
105
106t_Error MEMAC_MII_WritePhyReg(t_Handle h_Memac, uint8_t phyAddr, uint8_t reg, uint16_t data);
107t_Error MEMAC_MII_ReadPhyReg(t_Handle h_Memac,  uint8_t phyAddr, uint8_t reg, uint16_t *p_Data);
108
109
110#endif /* __MEMAC_H */
111