1/* SPDX-License-Identifier: GPL-2.0 */ 2 3#ifndef _DT_BINDINGS_CLK_MT6765_H 4#define _DT_BINDINGS_CLK_MT6765_H 5 6/* FIX Clks */ 7#define CLK_TOP_CLK26M 0 8 9/* APMIXEDSYS */ 10#define CLK_APMIXED_ARMPLL_L 0 11#define CLK_APMIXED_ARMPLL 1 12#define CLK_APMIXED_CCIPLL 2 13#define CLK_APMIXED_MAINPLL 3 14#define CLK_APMIXED_MFGPLL 4 15#define CLK_APMIXED_MMPLL 5 16#define CLK_APMIXED_UNIV2PLL 6 17#define CLK_APMIXED_MSDCPLL 7 18#define CLK_APMIXED_APLL1 8 19#define CLK_APMIXED_MPLL 9 20#define CLK_APMIXED_ULPOSC1 10 21#define CLK_APMIXED_ULPOSC2 11 22#define CLK_APMIXED_SSUSB26M 12 23#define CLK_APMIXED_APPLL26M 13 24#define CLK_APMIXED_MIPIC0_26M 14 25#define CLK_APMIXED_MDPLLGP26M 15 26#define CLK_APMIXED_MMSYS_F26M 16 27#define CLK_APMIXED_UFS26M 17 28#define CLK_APMIXED_MIPIC1_26M 18 29#define CLK_APMIXED_MEMPLL26M 19 30#define CLK_APMIXED_CLKSQ_LVPLL_26M 20 31#define CLK_APMIXED_MIPID0_26M 21 32#define CLK_APMIXED_NR_CLK 22 33 34/* TOPCKGEN */ 35#define CLK_TOP_SYSPLL 0 36#define CLK_TOP_SYSPLL_D2 1 37#define CLK_TOP_SYSPLL1_D2 2 38#define CLK_TOP_SYSPLL1_D4 3 39#define CLK_TOP_SYSPLL1_D8 4 40#define CLK_TOP_SYSPLL1_D16 5 41#define CLK_TOP_SYSPLL_D3 6 42#define CLK_TOP_SYSPLL2_D2 7 43#define CLK_TOP_SYSPLL2_D4 8 44#define CLK_TOP_SYSPLL2_D8 9 45#define CLK_TOP_SYSPLL_D5 10 46#define CLK_TOP_SYSPLL3_D2 11 47#define CLK_TOP_SYSPLL3_D4 12 48#define CLK_TOP_SYSPLL_D7 13 49#define CLK_TOP_SYSPLL4_D2 14 50#define CLK_TOP_SYSPLL4_D4 15 51#define CLK_TOP_USB20_192M 16 52#define CLK_TOP_USB20_192M_D4 17 53#define CLK_TOP_USB20_192M_D8 18 54#define CLK_TOP_USB20_192M_D16 19 55#define CLK_TOP_USB20_192M_D32 20 56#define CLK_TOP_UNIVPLL 21 57#define CLK_TOP_UNIVPLL_D2 22 58#define CLK_TOP_UNIVPLL1_D2 23 59#define CLK_TOP_UNIVPLL1_D4 24 60#define CLK_TOP_UNIVPLL_D3 25 61#define CLK_TOP_UNIVPLL2_D2 26 62#define CLK_TOP_UNIVPLL2_D4 27 63#define CLK_TOP_UNIVPLL2_D8 28 64#define CLK_TOP_UNIVPLL2_D32 29 65#define CLK_TOP_UNIVPLL_D5 30 66#define CLK_TOP_UNIVPLL3_D2 31 67#define CLK_TOP_UNIVPLL3_D4 32 68#define CLK_TOP_MMPLL 33 69#define CLK_TOP_MMPLL_D2 34 70#define CLK_TOP_MPLL 35 71#define CLK_TOP_DA_MPLL_104M_DIV 36 72#define CLK_TOP_DA_MPLL_52M_DIV 37 73#define CLK_TOP_MFGPLL 38 74#define CLK_TOP_MSDCPLL 39 75#define CLK_TOP_MSDCPLL_D2 40 76#define CLK_TOP_APLL1 41 77#define CLK_TOP_APLL1_D2 42 78#define CLK_TOP_APLL1_D4 43 79#define CLK_TOP_APLL1_D8 44 80#define CLK_TOP_ULPOSC1 45 81#define CLK_TOP_ULPOSC1_D2 46 82#define CLK_TOP_ULPOSC1_D4 47 83#define CLK_TOP_ULPOSC1_D8 48 84#define CLK_TOP_ULPOSC1_D16 49 85#define CLK_TOP_ULPOSC1_D32 50 86#define CLK_TOP_DMPLL 51 87#define CLK_TOP_F_FRTC 52 88#define CLK_TOP_F_F26M 53 89#define CLK_TOP_AXI 54 90#define CLK_TOP_MM 55 91#define CLK_TOP_SCP 56 92#define CLK_TOP_MFG 57 93#define CLK_TOP_F_FUART 58 94#define CLK_TOP_SPI 59 95#define CLK_TOP_MSDC50_0 60 96#define CLK_TOP_MSDC30_1 61 97#define CLK_TOP_AUDIO 62 98#define CLK_TOP_AUD_1 63 99#define CLK_TOP_AUD_ENGEN1 64 100#define CLK_TOP_F_FDISP_PWM 65 101#define CLK_TOP_SSPM 66 102#define CLK_TOP_DXCC 67 103#define CLK_TOP_I2C 68 104#define CLK_TOP_F_FPWM 69 105#define CLK_TOP_F_FSENINF 70 106#define CLK_TOP_AES_FDE 71 107#define CLK_TOP_F_BIST2FPC 72 108#define CLK_TOP_ARMPLL_DIVIDER_PLL0 73 109#define CLK_TOP_ARMPLL_DIVIDER_PLL1 74 110#define CLK_TOP_ARMPLL_DIVIDER_PLL2 75 111#define CLK_TOP_DA_USB20_48M_DIV 76 112#define CLK_TOP_DA_UNIV_48M_DIV 77 113#define CLK_TOP_APLL12_DIV0 78 114#define CLK_TOP_APLL12_DIV1 79 115#define CLK_TOP_APLL12_DIV2 80 116#define CLK_TOP_APLL12_DIV3 81 117#define CLK_TOP_ARMPLL_DIVIDER_PLL0_EN 82 118#define CLK_TOP_ARMPLL_DIVIDER_PLL1_EN 83 119#define CLK_TOP_ARMPLL_DIVIDER_PLL2_EN 84 120#define CLK_TOP_FMEM_OCC_DRC_EN 85 121#define CLK_TOP_USB20_48M_EN 86 122#define CLK_TOP_UNIVPLL_48M_EN 87 123#define CLK_TOP_MPLL_104M_EN 88 124#define CLK_TOP_MPLL_52M_EN 89 125#define CLK_TOP_F_UFS_MP_SAP_CFG_EN 90 126#define CLK_TOP_F_BIST2FPC_EN 91 127#define CLK_TOP_MD_32K 92 128#define CLK_TOP_MD_26M 93 129#define CLK_TOP_MD2_32K 94 130#define CLK_TOP_MD2_26M 95 131#define CLK_TOP_AXI_SEL 96 132#define CLK_TOP_MEM_SEL 97 133#define CLK_TOP_MM_SEL 98 134#define CLK_TOP_SCP_SEL 99 135#define CLK_TOP_MFG_SEL 100 136#define CLK_TOP_ATB_SEL 101 137#define CLK_TOP_CAMTG_SEL 102 138#define CLK_TOP_CAMTG1_SEL 103 139#define CLK_TOP_CAMTG2_SEL 104 140#define CLK_TOP_CAMTG3_SEL 105 141#define CLK_TOP_UART_SEL 106 142#define CLK_TOP_SPI_SEL 107 143#define CLK_TOP_MSDC50_0_HCLK_SEL 108 144#define CLK_TOP_MSDC50_0_SEL 109 145#define CLK_TOP_MSDC30_1_SEL 110 146#define CLK_TOP_AUDIO_SEL 111 147#define CLK_TOP_AUD_INTBUS_SEL 112 148#define CLK_TOP_AUD_1_SEL 113 149#define CLK_TOP_AUD_ENGEN1_SEL 114 150#define CLK_TOP_DISP_PWM_SEL 115 151#define CLK_TOP_SSPM_SEL 116 152#define CLK_TOP_DXCC_SEL 117 153#define CLK_TOP_USB_TOP_SEL 118 154#define CLK_TOP_SPM_SEL 119 155#define CLK_TOP_I2C_SEL 120 156#define CLK_TOP_PWM_SEL 121 157#define CLK_TOP_SENINF_SEL 122 158#define CLK_TOP_AES_FDE_SEL 123 159#define CLK_TOP_PWRAP_ULPOSC_SEL 124 160#define CLK_TOP_CAMTM_SEL 125 161#define CLK_TOP_NR_CLK 126 162 163/* INFRACFG */ 164#define CLK_IFR_ICUSB 0 165#define CLK_IFR_GCE 1 166#define CLK_IFR_THERM 2 167#define CLK_IFR_I2C_AP 3 168#define CLK_IFR_I2C_CCU 4 169#define CLK_IFR_I2C_SSPM 5 170#define CLK_IFR_I2C_RSV 6 171#define CLK_IFR_PWM_HCLK 7 172#define CLK_IFR_PWM1 8 173#define CLK_IFR_PWM2 9 174#define CLK_IFR_PWM3 10 175#define CLK_IFR_PWM4 11 176#define CLK_IFR_PWM5 12 177#define CLK_IFR_PWM 13 178#define CLK_IFR_UART0 14 179#define CLK_IFR_UART1 15 180#define CLK_IFR_GCE_26M 16 181#define CLK_IFR_CQ_DMA_FPC 17 182#define CLK_IFR_BTIF 18 183#define CLK_IFR_SPI0 19 184#define CLK_IFR_MSDC0 20 185#define CLK_IFR_MSDC1 21 186#define CLK_IFR_TRNG 22 187#define CLK_IFR_AUXADC 23 188#define CLK_IFR_CCIF1_AP 24 189#define CLK_IFR_CCIF1_MD 25 190#define CLK_IFR_AUXADC_MD 26 191#define CLK_IFR_AP_DMA 27 192#define CLK_IFR_DEVICE_APC 28 193#define CLK_IFR_CCIF_AP 29 194#define CLK_IFR_AUDIO 30 195#define CLK_IFR_CCIF_MD 31 196#define CLK_IFR_RG_PWM_FBCLK6 32 197#define CLK_IFR_DISP_PWM 33 198#define CLK_IFR_CLDMA_BCLK 34 199#define CLK_IFR_AUDIO_26M_BCLK 35 200#define CLK_IFR_SPI1 36 201#define CLK_IFR_I2C4 37 202#define CLK_IFR_SPI2 38 203#define CLK_IFR_SPI3 39 204#define CLK_IFR_I2C5 40 205#define CLK_IFR_I2C5_ARBITER 41 206#define CLK_IFR_I2C5_IMM 42 207#define CLK_IFR_I2C1_ARBITER 43 208#define CLK_IFR_I2C1_IMM 44 209#define CLK_IFR_I2C2_ARBITER 45 210#define CLK_IFR_I2C2_IMM 46 211#define CLK_IFR_SPI4 47 212#define CLK_IFR_SPI5 48 213#define CLK_IFR_CQ_DMA 49 214#define CLK_IFR_FAES_FDE 50 215#define CLK_IFR_MSDC0_SELF 51 216#define CLK_IFR_MSDC1_SELF 52 217#define CLK_IFR_I2C6 53 218#define CLK_IFR_AP_MSDC0 54 219#define CLK_IFR_MD_MSDC0 55 220#define CLK_IFR_MSDC0_SRC 56 221#define CLK_IFR_MSDC1_SRC 57 222#define CLK_IFR_AES_TOP0_BCLK 58 223#define CLK_IFR_MCU_PM_BCLK 59 224#define CLK_IFR_CCIF2_AP 60 225#define CLK_IFR_CCIF2_MD 61 226#define CLK_IFR_CCIF3_AP 62 227#define CLK_IFR_CCIF3_MD 63 228#define CLK_IFR_NR_CLK 64 229 230/* AUDIO */ 231#define CLK_AUDIO_AFE 0 232#define CLK_AUDIO_22M 1 233#define CLK_AUDIO_APLL_TUNER 2 234#define CLK_AUDIO_ADC 3 235#define CLK_AUDIO_DAC 4 236#define CLK_AUDIO_DAC_PREDIS 5 237#define CLK_AUDIO_TML 6 238#define CLK_AUDIO_I2S1_BCLK 7 239#define CLK_AUDIO_I2S2_BCLK 8 240#define CLK_AUDIO_I2S3_BCLK 9 241#define CLK_AUDIO_I2S4_BCLK 10 242#define CLK_AUDIO_NR_CLK 11 243 244/* MIPI_RX_ANA_CSI0A */ 245 246#define CLK_MIPI0A_CSR_CSI_EN_0A 0 247#define CLK_MIPI0A_NR_CLK 1 248 249/* MMSYS_CONFIG */ 250 251#define CLK_MM_MDP_RDMA0 0 252#define CLK_MM_MDP_CCORR0 1 253#define CLK_MM_MDP_RSZ0 2 254#define CLK_MM_MDP_RSZ1 3 255#define CLK_MM_MDP_TDSHP0 4 256#define CLK_MM_MDP_WROT0 5 257#define CLK_MM_MDP_WDMA0 6 258#define CLK_MM_DISP_OVL0 7 259#define CLK_MM_DISP_OVL0_2L 8 260#define CLK_MM_DISP_RSZ0 9 261#define CLK_MM_DISP_RDMA0 10 262#define CLK_MM_DISP_WDMA0 11 263#define CLK_MM_DISP_COLOR0 12 264#define CLK_MM_DISP_CCORR0 13 265#define CLK_MM_DISP_AAL0 14 266#define CLK_MM_DISP_GAMMA0 15 267#define CLK_MM_DISP_DITHER0 16 268#define CLK_MM_DSI0 17 269#define CLK_MM_FAKE_ENG 18 270#define CLK_MM_SMI_COMMON 19 271#define CLK_MM_SMI_LARB0 20 272#define CLK_MM_SMI_COMM0 21 273#define CLK_MM_SMI_COMM1 22 274#define CLK_MM_CAM_MDP 23 275#define CLK_MM_SMI_IMG 24 276#define CLK_MM_SMI_CAM 25 277#define CLK_MM_IMG_DL_RELAY 26 278#define CLK_MM_IMG_DL_ASYNC_TOP 27 279#define CLK_MM_DIG_DSI 28 280#define CLK_MM_F26M_HRTWT 29 281#define CLK_MM_NR_CLK 30 282 283/* IMGSYS */ 284 285#define CLK_IMG_LARB2 0 286#define CLK_IMG_DIP 1 287#define CLK_IMG_FDVT 2 288#define CLK_IMG_DPE 3 289#define CLK_IMG_RSC 4 290#define CLK_IMG_NR_CLK 5 291 292/* VENCSYS */ 293 294#define CLK_VENC_SET0_LARB 0 295#define CLK_VENC_SET1_VENC 1 296#define CLK_VENC_SET2_JPGENC 2 297#define CLK_VENC_SET3_VDEC 3 298#define CLK_VENC_NR_CLK 4 299 300/* CAMSYS */ 301 302#define CLK_CAM_LARB3 0 303#define CLK_CAM_DFP_VAD 1 304#define CLK_CAM 2 305#define CLK_CAMTG 3 306#define CLK_CAM_SENINF 4 307#define CLK_CAMSV0 5 308#define CLK_CAMSV1 6 309#define CLK_CAMSV2 7 310#define CLK_CAM_CCU 8 311#define CLK_CAM_NR_CLK 9 312 313#endif /* _DT_BINDINGS_CLK_MT6765_H */ 314