1/* SPDX-License-Identifier: ISC */ 2/* Copyright (C) 2020 MediaTek Inc. */ 3 4#ifndef __MT7915_REGS_H 5#define __MT7915_REGS_H 6 7/* used to differentiate between generations */ 8struct mt7915_reg_desc { 9 const u32 *reg_rev; 10 const u32 *offs_rev; 11 const struct mt76_connac_reg_map *map; 12 u32 map_size; 13}; 14 15enum reg_rev { 16 INT_SOURCE_CSR, 17 INT_MASK_CSR, 18 INT1_SOURCE_CSR, 19 INT1_MASK_CSR, 20 INT_MCU_CMD_SOURCE, 21 INT_MCU_CMD_EVENT, 22 WFDMA0_ADDR, 23 WFDMA0_PCIE1_ADDR, 24 WFDMA_EXT_CSR_ADDR, 25 CBTOP1_PHY_END, 26 INFRA_MCU_ADDR_END, 27 FW_ASSERT_STAT_ADDR, 28 FW_EXCEPT_TYPE_ADDR, 29 FW_EXCEPT_COUNT_ADDR, 30 FW_CIRQ_COUNT_ADDR, 31 FW_CIRQ_IDX_ADDR, 32 FW_CIRQ_LISR_ADDR, 33 FW_TASK_ID_ADDR, 34 FW_TASK_IDX_ADDR, 35 FW_TASK_QID1_ADDR, 36 FW_TASK_QID2_ADDR, 37 FW_TASK_START_ADDR, 38 FW_TASK_END_ADDR, 39 FW_TASK_SIZE_ADDR, 40 FW_LAST_MSG_ID_ADDR, 41 FW_EINT_INFO_ADDR, 42 FW_SCHED_INFO_ADDR, 43 SWDEF_BASE_ADDR, 44 TXQ_WED_RING_BASE, 45 RXQ_WED_RING_BASE, 46 RXQ_WED_DATA_RING_BASE, 47 __MT_REG_MAX, 48}; 49 50enum offs_rev { 51 TMAC_CDTR, 52 TMAC_ODTR, 53 TMAC_ATCR, 54 TMAC_TRCR0, 55 TMAC_ICR0, 56 TMAC_ICR1, 57 TMAC_CTCR0, 58 TMAC_TFCR0, 59 MDP_BNRCFR0, 60 MDP_BNRCFR1, 61 ARB_DRNGR0, 62 ARB_SCR, 63 RMAC_MIB_AIRTIME14, 64 AGG_AWSCR0, 65 AGG_PCR0, 66 AGG_ACR0, 67 AGG_ACR4, 68 AGG_MRCR, 69 AGG_ATCR1, 70 AGG_ATCR3, 71 LPON_UTTR0, 72 LPON_UTTR1, 73 LPON_FRCR, 74 MIB_SDR3, 75 MIB_SDR4, 76 MIB_SDR5, 77 MIB_SDR7, 78 MIB_SDR8, 79 MIB_SDR9, 80 MIB_SDR10, 81 MIB_SDR11, 82 MIB_SDR12, 83 MIB_SDR13, 84 MIB_SDR14, 85 MIB_SDR15, 86 MIB_SDR16, 87 MIB_SDR17, 88 MIB_SDR18, 89 MIB_SDR19, 90 MIB_SDR20, 91 MIB_SDR21, 92 MIB_SDR22, 93 MIB_SDR23, 94 MIB_SDR24, 95 MIB_SDR25, 96 MIB_SDR27, 97 MIB_SDR28, 98 MIB_SDR29, 99 MIB_SDRVEC, 100 MIB_SDR31, 101 MIB_SDR32, 102 MIB_SDRMUBF, 103 MIB_DR8, 104 MIB_DR9, 105 MIB_DR11, 106 MIB_MB_SDR0, 107 MIB_MB_SDR1, 108 TX_AGG_CNT, 109 TX_AGG_CNT2, 110 MIB_ARNG, 111 WTBLON_TOP_WDUCR, 112 WTBL_UPDATE, 113 PLE_FL_Q_EMPTY, 114 PLE_FL_Q_CTRL, 115 PLE_AC_QEMPTY, 116 PLE_FREEPG_CNT, 117 PLE_FREEPG_HEAD_TAIL, 118 PLE_PG_HIF_GROUP, 119 PLE_HIF_PG_INFO, 120 AC_OFFSET, 121 ETBF_PAR_RPT0, 122 __MT_OFFS_MAX, 123}; 124 125#define __REG(id) (dev->reg.reg_rev[(id)]) 126#define __OFFS(id) (dev->reg.offs_rev[(id)]) 127 128/* MCU WFDMA0 */ 129#define MT_MCU_WFDMA0_BASE 0x2000 130#define MT_MCU_WFDMA0(ofs) (MT_MCU_WFDMA0_BASE + (ofs)) 131 132#define MT_MCU_WFDMA0_DUMMY_CR MT_MCU_WFDMA0(0x120) 133 134/* MCU WFDMA1 */ 135#define MT_MCU_WFDMA1_BASE 0x3000 136#define MT_MCU_WFDMA1(ofs) (MT_MCU_WFDMA1_BASE + (ofs)) 137 138#define MT_MCU_INT_EVENT __REG(INT_MCU_CMD_EVENT) 139#define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0) 140#define MT_MCU_INT_EVENT_DMA_INIT BIT(1) 141#define MT_MCU_INT_EVENT_SER_TRIGGER BIT(2) 142#define MT_MCU_INT_EVENT_RESET_DONE BIT(3) 143 144/* PLE */ 145#define MT_PLE_BASE 0x820c0000 146#define MT_PLE(ofs) (MT_PLE_BASE + (ofs)) 147 148#define MT_PLE_HOST_RPT0 MT_PLE(0x030) 149#define MT_PLE_HOST_RPT0_TX_LATENCY BIT(3) 150 151#define MT_FL_Q_EMPTY MT_PLE(__OFFS(PLE_FL_Q_EMPTY)) 152#define MT_FL_Q0_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL)) 153#define MT_FL_Q2_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0x8) 154#define MT_FL_Q3_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0xc) 155 156#define MT_PLE_FREEPG_CNT MT_PLE(__OFFS(PLE_FREEPG_CNT)) 157#define MT_PLE_FREEPG_HEAD_TAIL MT_PLE(__OFFS(PLE_FREEPG_HEAD_TAIL)) 158#define MT_PLE_PG_HIF_GROUP MT_PLE(__OFFS(PLE_PG_HIF_GROUP)) 159#define MT_PLE_HIF_PG_INFO MT_PLE(__OFFS(PLE_HIF_PG_INFO)) 160 161#define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(__OFFS(PLE_AC_QEMPTY) + \ 162 __OFFS(AC_OFFSET) * \ 163 (ac) + ((n) << 2)) 164#define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2)) 165 166#define MT_PSE_BASE 0x820c8000 167#define MT_PSE(ofs) (MT_PSE_BASE + (ofs)) 168 169/* WF MDP TOP */ 170#define MT_MDP_BASE 0x820cd000 171#define MT_MDP(ofs) (MT_MDP_BASE + (ofs)) 172 173#define MT_MDP_DCR0 MT_MDP(0x000) 174#define MT_MDP_DCR0_DAMSDU_EN BIT(15) 175 176#define MT_MDP_DCR1 MT_MDP(0x004) 177#define MT_MDP_DCR1_MAX_RX_LEN GENMASK(15, 3) 178 179#define MT_MDP_DCR2 MT_MDP(0x0e8) 180#define MT_MDP_DCR2_RX_TRANS_SHORT BIT(2) 181 182#define MT_MDP_BNRCFR0(_band) MT_MDP(__OFFS(MDP_BNRCFR0) + \ 183 ((_band) << 8)) 184#define MT_MDP_RCFR0_MCU_RX_MGMT GENMASK(5, 4) 185#define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR GENMASK(7, 6) 186#define MT_MDP_RCFR0_MCU_RX_CTL_BAR GENMASK(9, 8) 187 188#define MT_MDP_BNRCFR1(_band) MT_MDP(__OFFS(MDP_BNRCFR1) + \ 189 ((_band) << 8)) 190#define MT_MDP_RCFR1_MCU_RX_BYPASS GENMASK(23, 22) 191#define MT_MDP_RCFR1_RX_DROPPED_UCAST GENMASK(28, 27) 192#define MT_MDP_RCFR1_RX_DROPPED_MCAST GENMASK(30, 29) 193#define MT_MDP_TO_HIF 0 194#define MT_MDP_TO_WM 1 195 196/* TRB: band 0(0x820e1000), band 1(0x820f1000) */ 197#define MT_WF_TRB_BASE(_band) ((_band) ? 0x820f1000 : 0x820e1000) 198#define MT_WF_TRB(_band, ofs) (MT_WF_TRB_BASE(_band) + (ofs)) 199 200#define MT_TRB_RXPSR0(_band) MT_WF_TRB(_band, 0x03c) 201#define MT_TRB_RXPSR0_RX_WTBL_PTR GENMASK(25, 16) 202#define MT_TRB_RXPSR0_RX_RMAC_PTR GENMASK(9, 0) 203 204/* TMAC: band 0(0x820e4000), band 1(0x820f4000) */ 205#define MT_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000) 206#define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs)) 207 208#define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0) 209#define MT_TMAC_TCR0_TX_BLINK GENMASK(7, 6) 210#define MT_TMAC_TCR0_TBTT_STOP_CTRL BIT(25) 211 212#define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_CDTR)) 213 #define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ODTR)) 214#define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0) 215#define MT_TIMEOUT_VAL_CCA GENMASK(31, 16) 216 217#define MT_TMAC_ATCR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ATCR)) 218#define MT_TMAC_ATCR_TXV_TOUT GENMASK(7, 0) 219 220#define MT_TMAC_TRCR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_TRCR0)) 221#define MT_TMAC_TRCR0_TR2T_CHK GENMASK(8, 0) 222#define MT_TMAC_TRCR0_I2T_CHK GENMASK(24, 16) 223 224#define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ICR0)) 225#define MT_IFS_EIFS_OFDM GENMASK(8, 0) 226#define MT_IFS_RIFS GENMASK(14, 10) 227#define MT_IFS_SIFS GENMASK(22, 16) 228#define MT_IFS_SLOT GENMASK(30, 24) 229 230#define MT_TMAC_ICR1(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ICR1)) 231#define MT_IFS_EIFS_CCK GENMASK(8, 0) 232 233#define MT_TMAC_CTCR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_CTCR0)) 234#define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0) 235#define MT_TMAC_CTCR0_INS_DDLMT_EN BIT(17) 236#define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN BIT(18) 237 238#define MT_TMAC_TFCR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_TFCR0)) 239 240/* WF DMA TOP: band 0(0x820e7000),band 1(0x820f7000) */ 241#define MT_WF_DMA_BASE(_band) ((_band) ? 0x820f7000 : 0x820e7000) 242#define MT_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs)) 243 244#define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000) 245#define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3) 246#define MT_DMA_DCR0_RXD_G5_EN BIT(23) 247 248/* WTBLOFF TOP: band 0(0x820e9000),band 1(0x820f9000) */ 249#define MT_WTBLOFF_TOP_BASE(_band) ((_band) ? 0x820f9000 : 0x820e9000) 250#define MT_WTBLOFF_TOP(_band, ofs) (MT_WTBLOFF_TOP_BASE(_band) + (ofs)) 251 252#define MT_WTBLOFF_TOP_RSCR(_band) MT_WTBLOFF_TOP(_band, 0x008) 253#define MT_WTBLOFF_TOP_RSCR_RCPI_MODE GENMASK(31, 30) 254#define MT_WTBLOFF_TOP_RSCR_RCPI_PARAM GENMASK(25, 24) 255 256/* ETBF: band 0(0x820ea000), band 1(0x820fa000) */ 257#define MT_WF_ETBF_BASE(_band) ((_band) ? 0x820fa000 : 0x820ea000) 258#define MT_WF_ETBF(_band, ofs) (MT_WF_ETBF_BASE(_band) + (ofs)) 259 260#define MT_ETBF_TX_NDP_BFRP(_band) MT_WF_ETBF(_band, 0x040) 261#define MT_ETBF_TX_FB_CPL GENMASK(31, 16) 262#define MT_ETBF_TX_FB_TRI GENMASK(15, 0) 263 264#define MT_ETBF_PAR_RPT0(_band) MT_WF_ETBF(_band, __OFFS(ETBF_PAR_RPT0)) 265#define MT_ETBF_PAR_RPT0_FB_BW GENMASK(7, 6) 266#define MT_ETBF_PAR_RPT0_FB_NC GENMASK(5, 3) 267#define MT_ETBF_PAR_RPT0_FB_NR GENMASK(2, 0) 268 269#define MT_ETBF_TX_APP_CNT(_band) MT_WF_ETBF(_band, 0x0f0) 270#define MT_ETBF_TX_IBF_CNT GENMASK(31, 16) 271#define MT_ETBF_TX_EBF_CNT GENMASK(15, 0) 272 273#define MT_ETBF_RX_FB_CNT(_band) MT_WF_ETBF(_band, 0x0f8) 274#define MT_ETBF_RX_FB_ALL GENMASK(31, 24) 275#define MT_ETBF_RX_FB_HE GENMASK(23, 16) 276#define MT_ETBF_RX_FB_VHT GENMASK(15, 8) 277#define MT_ETBF_RX_FB_HT GENMASK(7, 0) 278 279/* LPON: band 0(0x820eb000), band 1(0x820fb000) */ 280#define MT_WF_LPON_BASE(_band) ((_band) ? 0x820fb000 : 0x820eb000) 281#define MT_WF_LPON(_band, ofs) (MT_WF_LPON_BASE(_band) + (ofs)) 282 283#define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, __OFFS(LPON_UTTR0)) 284#define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, __OFFS(LPON_UTTR1)) 285#define MT_LPON_FRCR(_band) MT_WF_LPON(_band, __OFFS(LPON_FRCR)) 286 287#define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + \ 288 (((n) * 4) << 1)) 289#define MT_LPON_TCR_MT7916(_band, n) MT_WF_LPON(_band, 0x0a8 + \ 290 (((n) * 4) << 4)) 291#define MT_LPON_TCR_SW_MODE GENMASK(1, 0) 292#define MT_LPON_TCR_SW_WRITE BIT(0) 293#define MT_LPON_TCR_SW_ADJUST BIT(1) 294#define MT_LPON_TCR_SW_READ GENMASK(1, 0) 295 296/* MIB: band 0(0x820ed000), band 1(0x820fd000) */ 297/* These counters are (mostly?) clear-on-read. So, some should not 298 * be read at all in case firmware is already reading them. These 299 * are commented with 'DNR' below. The DNR stats will be read by querying 300 * the firmware API for the appropriate message. For counters the driver 301 * does read, the driver should accumulate the counters. 302 */ 303#define MT_WF_MIB_BASE(_band) ((_band) ? 0x820fd000 : 0x820ed000) 304#define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE(_band) + (ofs)) 305 306#define MT_MIB_SDR0(_band) MT_WF_MIB(_band, 0x010) 307#define MT_MIB_SDR0_BERACON_TX_CNT_MASK GENMASK(15, 0) 308 309#define MT_MIB_SDR3(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR3)) 310#define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(15, 0) 311#define MT_MIB_SDR3_FCS_ERR_MASK_MT7916 GENMASK(31, 16) 312 313#define MT_MIB_SDR4(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR4)) 314#define MT_MIB_SDR4_RX_FIFO_FULL_MASK GENMASK(15, 0) 315 316/* rx mpdu counter, full 32 bits */ 317#define MT_MIB_SDR5(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR5)) 318 319#define MT_MIB_SDR6(_band) MT_WF_MIB(_band, 0x020) 320#define MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK GENMASK(15, 0) 321 322#define MT_MIB_SDR7(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR7)) 323#define MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK GENMASK(15, 0) 324 325#define MT_MIB_SDR8(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR8)) 326#define MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK GENMASK(15, 0) 327 328/* aka CCA_NAV_TX_TIME */ 329#define MT_MIB_SDR9_DNR(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR9)) 330#define MT_MIB_SDR9_CCA_BUSY_TIME_MASK GENMASK(23, 0) 331 332#define MT_MIB_SDR10(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR10)) 333#define MT_MIB_SDR10_MRDY_COUNT_MASK GENMASK(25, 0) 334#define MT_MIB_SDR10_MRDY_COUNT_MASK_MT7916 GENMASK(31, 0) 335 336#define MT_MIB_SDR11(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR11)) 337#define MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK GENMASK(15, 0) 338 339/* tx ampdu cnt, full 32 bits */ 340#define MT_MIB_SDR12(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR12)) 341 342#define MT_MIB_SDR13(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR13)) 343#define MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK GENMASK(15, 0) 344 345/* counts all mpdus in ampdu, regardless of success */ 346#define MT_MIB_SDR14(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR14)) 347#define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK GENMASK(23, 0) 348#define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK_MT7916 GENMASK(31, 0) 349 350/* counts all successfully tx'd mpdus in ampdu */ 351#define MT_MIB_SDR15(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR15)) 352#define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK GENMASK(23, 0) 353#define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK_MT7916 GENMASK(31, 0) 354 355/* in units of 'us' */ 356#define MT_MIB_SDR16(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR16)) 357#define MT_MIB_SDR16_PRIMARY_CCA_BUSY_TIME_MASK GENMASK(23, 0) 358 359#define MT_MIB_SDR17(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR17)) 360#define MT_MIB_SDR17_SECONDARY_CCA_BUSY_TIME_MASK GENMASK(23, 0) 361 362#define MT_MIB_SDR18(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR18)) 363#define MT_MIB_SDR18_PRIMARY_ENERGY_DETECT_TIME_MASK GENMASK(23, 0) 364 365/* units are us */ 366#define MT_MIB_SDR19(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR19)) 367#define MT_MIB_SDR19_CCK_MDRDY_TIME_MASK GENMASK(23, 0) 368 369#define MT_MIB_SDR20(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR20)) 370#define MT_MIB_SDR20_OFDM_VHT_MDRDY_TIME_MASK GENMASK(23, 0) 371 372#define MT_MIB_SDR21(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR21)) 373#define MT_MIB_SDR21_GREEN_MDRDY_TIME_MASK GENMASK(23, 0) 374 375/* rx ampdu count, 32-bit */ 376#define MT_MIB_SDR22(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR22)) 377 378/* rx ampdu bytes count, 32-bit */ 379#define MT_MIB_SDR23(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR23)) 380 381/* rx ampdu valid subframe count */ 382#define MT_MIB_SDR24(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR24)) 383#define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK GENMASK(23, 0) 384#define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK_MT7916 GENMASK(31, 0) 385 386/* rx ampdu valid subframe bytes count, 32bits */ 387#define MT_MIB_SDR25(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR25)) 388 389/* remaining windows protected stats */ 390#define MT_MIB_SDR27(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR27)) 391#define MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK GENMASK(15, 0) 392 393#define MT_MIB_SDR28(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR28)) 394#define MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK GENMASK(15, 0) 395 396#define MT_MIB_SDR29(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR29)) 397#define MT_MIB_SDR29_RX_PFDROP_CNT_MASK GENMASK(7, 0) 398#define MT_MIB_SDR29_RX_PFDROP_CNT_MASK_MT7916 GENMASK(15, 0) 399 400#define MT_MIB_SDRVEC(_band) MT_WF_MIB(_band, __OFFS(MIB_SDRVEC)) 401#define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK GENMASK(15, 0) 402#define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK_MT7916 GENMASK(31, 16) 403 404/* rx blockack count, 32 bits */ 405#define MT_MIB_SDR31(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR31)) 406 407#define MT_MIB_SDR32(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR32)) 408#define MT_MIB_SDR32_TX_PKT_EBF_CNT GENMASK(15, 0) 409#define MT_MIB_SDR32_TX_PKT_IBF_CNT GENMASK(31, 16) 410 411#define MT_MIB_SDR33(_band) MT_WF_MIB(_band, 0x088) 412#define MT_MIB_SDR33_TX_PKT_IBF_CNT GENMASK(15, 0) 413 414#define MT_MIB_SDRMUBF(_band) MT_WF_MIB(_band, __OFFS(MIB_SDRMUBF)) 415#define MT_MIB_MU_BF_TX_CNT GENMASK(15, 0) 416 417/* 36, 37 both DNR */ 418 419#define MT_MIB_DR8(_band) MT_WF_MIB(_band, __OFFS(MIB_DR8)) 420#define MT_MIB_DR9(_band) MT_WF_MIB(_band, __OFFS(MIB_DR9)) 421#define MT_MIB_DR11(_band) MT_WF_MIB(_band, __OFFS(MIB_DR11)) 422 423#define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(_band, __OFFS(MIB_MB_SDR0) + (n)) 424#define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16) 425#define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0) 426 427#define MT_MIB_MB_SDR1(_band, n) MT_WF_MIB(_band, __OFFS(MIB_MB_SDR1) + (n)) 428#define MT_MIB_BA_MISS_COUNT_MASK GENMASK(15, 0) 429#define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(31, 16) 430 431#define MT_MIB_MB_SDR2(_band, n) MT_WF_MIB(_band, 0x518 + (n)) 432#define MT_MIB_MB_BFTF(_band, n) MT_WF_MIB(_band, 0x510 + (n)) 433 434#define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, __OFFS(TX_AGG_CNT) + \ 435 ((n) << 2)) 436#define MT_TX_AGG_CNT2(_band, n) MT_WF_MIB(_band, __OFFS(TX_AGG_CNT2) + \ 437 ((n) << 2)) 438#define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, __OFFS(MIB_ARNG) + \ 439 ((n) << 2)) 440#define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(7, 0)) 441 442#define MT_MIB_BFCR0(_band) MT_WF_MIB(_band, 0x7b0) 443#define MT_MIB_BFCR0_RX_FB_HT GENMASK(15, 0) 444#define MT_MIB_BFCR0_RX_FB_VHT GENMASK(31, 16) 445 446#define MT_MIB_BFCR1(_band) MT_WF_MIB(_band, 0x7b4) 447#define MT_MIB_BFCR1_RX_FB_HE GENMASK(15, 0) 448 449#define MT_MIB_BFCR2(_band) MT_WF_MIB(_band, 0x7b8) 450#define MT_MIB_BFCR2_BFEE_TX_FB_TRIG GENMASK(15, 0) 451 452#define MT_MIB_BFCR7(_band) MT_WF_MIB(_band, 0x7cc) 453#define MT_MIB_BFCR7_BFEE_TX_FB_CPL GENMASK(15, 0) 454 455/* WTBLON TOP */ 456#define MT_WTBLON_TOP_BASE 0x820d4000 457#define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs)) 458#define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(__OFFS(WTBLON_TOP_WDUCR)) 459#define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0) 460 461#define MT_WTBL_UPDATE MT_WTBLON_TOP(__OFFS(WTBL_UPDATE)) 462#define MT_WTBL_UPDATE_WLAN_IDX GENMASK(9, 0) 463#define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12) 464#define MT_WTBL_UPDATE_BUSY BIT(31) 465 466/* WTBL */ 467#define MT_WTBL_BASE 0x820d8000 468#define MT_WTBL_LMAC_ID GENMASK(14, 8) 469#define MT_WTBL_LMAC_DW GENMASK(7, 2) 470#define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \ 471 FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \ 472 FIELD_PREP(MT_WTBL_LMAC_DW, _dw)) 473 474/* AGG: band 0(0x820e2000), band 1(0x820f2000) */ 475#define MT_WF_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000) 476#define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs)) 477 478#define MT_AGG_AWSCR0(_band, _n) MT_WF_AGG(_band, (__OFFS(AGG_AWSCR0) + \ 479 (_n) * 4)) 480#define MT_AGG_PCR0(_band, _n) MT_WF_AGG(_band, (__OFFS(AGG_PCR0) + \ 481 (_n) * 4)) 482#define MT_AGG_PCR0_MM_PROT BIT(0) 483#define MT_AGG_PCR0_GF_PROT BIT(1) 484#define MT_AGG_PCR0_BW20_PROT BIT(2) 485#define MT_AGG_PCR0_BW40_PROT BIT(4) 486#define MT_AGG_PCR0_BW80_PROT BIT(6) 487#define MT_AGG_PCR0_ERP_PROT GENMASK(12, 8) 488#define MT_AGG_PCR0_VHT_PROT BIT(13) 489#define MT_AGG_PCR0_PTA_WIN_DIS BIT(15) 490 491#define MT_AGG_PCR1_RTS0_NUM_THRES GENMASK(31, 23) 492#define MT_AGG_PCR1_RTS0_LEN_THRES GENMASK(19, 0) 493 494#define MT_AGG_ACR0(_band) MT_WF_AGG(_band, __OFFS(AGG_ACR0)) 495#define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0) 496#define MT_AGG_ACR_BAR_RATE GENMASK(29, 16) 497 498#define MT_AGG_ACR4(_band) MT_WF_AGG(_band, __OFFS(AGG_ACR4)) 499#define MT_AGG_ACR_PPDU_TXS2H BIT(1) 500 501#define MT_AGG_MRCR(_band) MT_WF_AGG(_band, __OFFS(AGG_MRCR)) 502#define MT_AGG_MRCR_BAR_CNT_LIMIT GENMASK(15, 12) 503#define MT_AGG_MRCR_LAST_RTS_CTS_RN BIT(6) 504#define MT_AGG_MRCR_RTS_FAIL_LIMIT GENMASK(11, 7) 505#define MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT GENMASK(28, 24) 506 507#define MT_AGG_ATCR1(_band) MT_WF_AGG(_band, __OFFS(AGG_ATCR1)) 508#define MT_AGG_ATCR3(_band) MT_WF_AGG(_band, __OFFS(AGG_ATCR3)) 509 510/* ARB: band 0(0x820e3000), band 1(0x820f3000) */ 511#define MT_WF_ARB_BASE(_band) ((_band) ? 0x820f3000 : 0x820e3000) 512#define MT_WF_ARB(_band, ofs) (MT_WF_ARB_BASE(_band) + (ofs)) 513 514#define MT_ARB_SCR(_band) MT_WF_ARB(_band, __OFFS(ARB_SCR)) 515#define MT_ARB_SCR_TX_DISABLE BIT(8) 516#define MT_ARB_SCR_RX_DISABLE BIT(9) 517 518#define MT_ARB_DRNGR0(_band, _n) MT_WF_ARB(_band, (__OFFS(ARB_DRNGR0) + \ 519 (_n) * 4)) 520 521/* RMAC: band 0(0x820e5000), band 1(0x820f5000) */ 522#define MT_WF_RMAC_BASE(_band) ((_band) ? 0x820f5000 : 0x820e5000) 523#define MT_WF_RMAC(_band, ofs) (MT_WF_RMAC_BASE(_band) + (ofs)) 524 525#define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000) 526#define MT_WF_RFCR_DROP_STBC_MULTI BIT(0) 527#define MT_WF_RFCR_DROP_FCSFAIL BIT(1) 528#define MT_WF_RFCR_DROP_VERSION BIT(3) 529#define MT_WF_RFCR_DROP_PROBEREQ BIT(4) 530#define MT_WF_RFCR_DROP_MCAST BIT(5) 531#define MT_WF_RFCR_DROP_BCAST BIT(6) 532#define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7) 533#define MT_WF_RFCR_DROP_A3_MAC BIT(8) 534#define MT_WF_RFCR_DROP_A3_BSSID BIT(9) 535#define MT_WF_RFCR_DROP_A2_BSSID BIT(10) 536#define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11) 537#define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12) 538#define MT_WF_RFCR_DROP_CTL_RSV BIT(13) 539#define MT_WF_RFCR_DROP_CTS BIT(14) 540#define MT_WF_RFCR_DROP_RTS BIT(15) 541#define MT_WF_RFCR_DROP_DUPLICATE BIT(16) 542#define MT_WF_RFCR_DROP_OTHER_BSS BIT(17) 543#define MT_WF_RFCR_DROP_OTHER_UC BIT(18) 544#define MT_WF_RFCR_DROP_OTHER_TIM BIT(19) 545#define MT_WF_RFCR_DROP_NDPA BIT(20) 546#define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21) 547 548#define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004) 549#define MT_WF_RFCR1_DROP_ACK BIT(4) 550#define MT_WF_RFCR1_DROP_BF_POLL BIT(5) 551#define MT_WF_RFCR1_DROP_BA BIT(6) 552#define MT_WF_RFCR1_DROP_CFEND BIT(7) 553#define MT_WF_RFCR1_DROP_CFACK BIT(8) 554 555#define MT_WF_RMAC_RSVD0(_band) MT_WF_RMAC(_band, 0x02e0) 556#define MT_WF_RMAC_RSVD0_EIFS_CLR BIT(21) 557 558#define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380) 559#define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31) 560#define MT_WF_RMAC_MIB_OBSS_BACKOFF GENMASK(15, 0) 561#define MT_WF_RMAC_MIB_ED_OFFSET GENMASK(20, 16) 562 563#define MT_WF_RMAC_MIB_AIRTIME1(_band) MT_WF_RMAC(_band, 0x0384) 564#define MT_WF_RMAC_MIB_NONQOSD_BACKOFF GENMASK(31, 16) 565 566#define MT_WF_RMAC_MIB_AIRTIME3(_band) MT_WF_RMAC(_band, 0x038c) 567#define MT_WF_RMAC_MIB_QOS01_BACKOFF GENMASK(31, 0) 568 569#define MT_WF_RMAC_MIB_AIRTIME4(_band) MT_WF_RMAC(_band, 0x0390) 570#define MT_WF_RMAC_MIB_QOS23_BACKOFF GENMASK(31, 0) 571 572/* WFDMA0 */ 573#define MT_WFDMA0_BASE __REG(WFDMA0_ADDR) 574#define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs)) 575 576#define MT_WFDMA0_RST MT_WFDMA0(0x100) 577#define MT_WFDMA0_RST_LOGIC_RST BIT(4) 578#define MT_WFDMA0_RST_DMASHDL_ALL_RST BIT(5) 579 580#define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c) 581#define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0) 582#define MT_WFDMA0_BUSY_ENA_TX_FIFO1 BIT(1) 583#define MT_WFDMA0_BUSY_ENA_RX_FIFO BIT(2) 584 585#define MT_WFDMA0_MCU_HOST_INT_ENA MT_WFDMA0(0x1f4) 586 587#define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208) 588#define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0) 589#define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2) 590#define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28) 591#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27) 592#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21) 593 594#define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c) 595 596#define MT_WFDMA0_EXT0_CFG MT_WFDMA0(0x2b0) 597#define MT_WFDMA0_EXT0_RXWB_KEEP BIT(10) 598 599#define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0) 600#define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4) 601#define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8) 602#define MT_WPDMA_GLO_CFG MT_WFDMA0(0x208) 603 604/* WFDMA1 */ 605#define MT_WFDMA1_BASE 0xd5000 606#define MT_WFDMA1(ofs) (MT_WFDMA1_BASE + (ofs)) 607 608#define MT_WFDMA1_RST MT_WFDMA1(0x100) 609#define MT_WFDMA1_RST_LOGIC_RST BIT(4) 610#define MT_WFDMA1_RST_DMASHDL_ALL_RST BIT(5) 611 612#define MT_WFDMA1_BUSY_ENA MT_WFDMA1(0x13c) 613#define MT_WFDMA1_BUSY_ENA_TX_FIFO0 BIT(0) 614#define MT_WFDMA1_BUSY_ENA_TX_FIFO1 BIT(1) 615#define MT_WFDMA1_BUSY_ENA_RX_FIFO BIT(2) 616 617#define MT_WFDMA1_GLO_CFG MT_WFDMA1(0x208) 618#define MT_WFDMA1_GLO_CFG_TX_DMA_EN BIT(0) 619#define MT_WFDMA1_GLO_CFG_RX_DMA_EN BIT(2) 620#define MT_WFDMA1_GLO_CFG_OMIT_TX_INFO BIT(28) 621#define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO BIT(27) 622#define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21) 623 624#define MT_WFDMA1_RST_DTX_PTR MT_WFDMA1(0x20c) 625#define MT_WFDMA1_PRI_DLY_INT_CFG0 MT_WFDMA1(0x2f0) 626 627/* WFDMA CSR */ 628#define MT_WFDMA_EXT_CSR_BASE __REG(WFDMA_EXT_CSR_ADDR) 629#define MT_WFDMA_EXT_CSR_PHYS_BASE 0x18027000 630#define MT_WFDMA_EXT_CSR(ofs) (MT_WFDMA_EXT_CSR_BASE + (ofs)) 631#define MT_WFDMA_EXT_CSR_PHYS(ofs) (MT_WFDMA_EXT_CSR_PHYS_BASE + (ofs)) 632 633#define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR_PHYS(0x30) 634#define MT_WFDMA_HOST_CONFIG_PDMA_BAND BIT(0) 635#define MT_WFDMA_HOST_CONFIG_WED BIT(1) 636 637#define MT_WFDMA_WED_RING_CONTROL MT_WFDMA_EXT_CSR_PHYS(0x34) 638#define MT_WFDMA_WED_RING_CONTROL_TX0 GENMASK(4, 0) 639#define MT_WFDMA_WED_RING_CONTROL_TX1 GENMASK(12, 8) 640#define MT_WFDMA_WED_RING_CONTROL_RX1 GENMASK(20, 16) 641 642#define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR_PHYS(0x44) 643#define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0) 644 645#define MT_PCIE_RECOG_ID 0xd7090 646#define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0) 647#define MT_PCIE_RECOG_ID_SEM BIT(31) 648 649#define MT_INT_WED_SOURCE_CSR MT_WFDMA_EXT_CSR(0x200) 650#define MT_INT_WED_MASK_CSR MT_WFDMA_EXT_CSR(0x204) 651 652#define MT_WED_TX_RING_BASE MT_WFDMA_EXT_CSR(0x300) 653#define MT_WED_RX_RING_BASE MT_WFDMA_EXT_CSR(0x400) 654 655/* WFDMA0 PCIE1 */ 656#define MT_WFDMA0_PCIE1_BASE __REG(WFDMA0_PCIE1_ADDR) 657#define MT_WFDMA0_PCIE1(ofs) (MT_WFDMA0_PCIE1_BASE + (ofs)) 658 659#define MT_WFDMA0_PCIE1_BUSY_ENA MT_WFDMA0_PCIE1(0x13c) 660#define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0) 661#define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1) 662#define MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO BIT(2) 663 664/* WFDMA1 PCIE1 */ 665#define MT_WFDMA1_PCIE1_BASE 0xd9000 666#define MT_WFDMA1_PCIE1(ofs) (MT_WFDMA1_PCIE1_BASE + (ofs)) 667 668#define MT_WFDMA1_PCIE1_BUSY_ENA MT_WFDMA1_PCIE1(0x13c) 669#define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0) 670#define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1) 671#define MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO BIT(2) 672 673/* WFDMA COMMON */ 674#define __RXQ(q) ((q) + __MT_MCUQ_MAX) 675#define __TXQ(q) (__RXQ(q) + MT_RXQ_BAND2) 676 677#define MT_Q_ID(q) (dev->q_id[(q)]) 678#define MT_Q_BASE(q) ((dev->wfdma_mask >> (q)) & 0x1 ? \ 679 MT_WFDMA1_BASE : MT_WFDMA0_BASE) 680 681#define MT_MCUQ_ID(q) MT_Q_ID(q) 682#define MT_TXQ_ID(q) MT_Q_ID(__TXQ(q)) 683#define MT_RXQ_ID(q) MT_Q_ID(__RXQ(q)) 684 685#define MT_MCUQ_RING_BASE(q) (MT_Q_BASE(q) + 0x300) 686#define MT_TXQ_RING_BASE(q) (MT_Q_BASE(__TXQ(q)) + 0x300) 687#define MT_RXQ_RING_BASE(q) (MT_Q_BASE(__RXQ(q)) + 0x500) 688 689#define MT_MCUQ_EXT_CTRL(q) (MT_Q_BASE(q) + 0x600 + \ 690 MT_MCUQ_ID(q)* 0x4) 691#define MT_RXQ_BAND1_CTRL(q) (MT_Q_BASE(__RXQ(q)) + 0x680 + \ 692 MT_RXQ_ID(q)* 0x4) 693#define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \ 694 MT_TXQ_ID(q)* 0x4) 695 696#define MT_TXQ_WED_RING_BASE __REG(TXQ_WED_RING_BASE) 697#define MT_RXQ_WED_RING_BASE __REG(RXQ_WED_RING_BASE) 698#define MT_RXQ_WED_DATA_RING_BASE __REG(RXQ_WED_DATA_RING_BASE) 699 700#define MT_INT_SOURCE_CSR __REG(INT_SOURCE_CSR) 701#define MT_INT_MASK_CSR __REG(INT_MASK_CSR) 702 703#define MT_INT1_SOURCE_CSR __REG(INT1_SOURCE_CSR) 704#define MT_INT1_MASK_CSR __REG(INT1_MASK_CSR) 705 706#define MT_INT_RX_DONE_BAND0 BIT(16) 707#define MT_INT_RX_DONE_BAND1 BIT(17) 708#define MT_INT_RX_DONE_WM BIT(0) 709#define MT_INT_RX_DONE_WA BIT(1) 710#define MT_INT_RX_DONE_WA_MAIN BIT(1) 711#define MT_INT_RX_DONE_WA_EXT BIT(2) 712#define MT_INT_MCU_CMD BIT(29) 713#define MT_INT_RX_DONE_BAND0_MT7916 BIT(22) 714#define MT_INT_RX_DONE_BAND1_MT7916 BIT(23) 715#define MT_INT_RX_DONE_WA_MAIN_MT7916 BIT(2) 716#define MT_INT_RX_DONE_WA_EXT_MT7916 BIT(3) 717 718#define MT_INT_WED_RX_DONE_BAND0_MT7916 BIT(18) 719#define MT_INT_WED_RX_DONE_BAND1_MT7916 BIT(19) 720#define MT_INT_WED_RX_DONE_WA_MAIN_MT7916 BIT(1) 721#define MT_INT_WED_RX_DONE_WA_MT7916 BIT(17) 722 723#define MT_INT_RX(q) (dev->q_int_mask[__RXQ(q)]) 724#define MT_INT_TX_MCU(q) (dev->q_int_mask[(q)]) 725 726#define MT_INT_RX_DONE_MCU (MT_INT_RX(MT_RXQ_MCU) | \ 727 MT_INT_RX(MT_RXQ_MCU_WA)) 728 729#define MT_INT_BAND0_RX_DONE (MT_INT_RX(MT_RXQ_MAIN) | \ 730 MT_INT_RX(MT_RXQ_MAIN_WA)) 731 732#define MT_INT_BAND1_RX_DONE (MT_INT_RX(MT_RXQ_BAND1) | \ 733 MT_INT_RX(MT_RXQ_BAND1_WA) | \ 734 MT_INT_RX(MT_RXQ_MAIN_WA)) 735 736#define MT_INT_RX_DONE_ALL (MT_INT_RX_DONE_MCU | \ 737 MT_INT_BAND0_RX_DONE | \ 738 MT_INT_BAND1_RX_DONE) 739 740#define MT_INT_TX_DONE_FWDL BIT(26) 741#define MT_INT_TX_DONE_MCU_WM BIT(27) 742#define MT_INT_TX_DONE_MCU_WA BIT(15) 743#define MT_INT_TX_DONE_BAND0 BIT(30) 744#define MT_INT_TX_DONE_BAND1 BIT(31) 745#define MT_INT_TX_DONE_MCU_WA_MT7916 BIT(25) 746#define MT_INT_WED_TX_DONE_BAND0 BIT(4) 747#define MT_INT_WED_TX_DONE_BAND1 BIT(5) 748 749#define MT_INT_TX_DONE_MCU (MT_INT_TX_MCU(MT_MCUQ_WA) | \ 750 MT_INT_TX_MCU(MT_MCUQ_WM) | \ 751 MT_INT_TX_MCU(MT_MCUQ_FWDL)) 752 753#define MT_MCU_CMD __REG(INT_MCU_CMD_SOURCE) 754#define MT_MCU_CMD_STOP_DMA_FW_RELOAD BIT(1) 755#define MT_MCU_CMD_STOP_DMA BIT(2) 756#define MT_MCU_CMD_RESET_DONE BIT(3) 757#define MT_MCU_CMD_RECOVERY_DONE BIT(4) 758#define MT_MCU_CMD_NORMAL_STATE BIT(5) 759#define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1) 760 761#define MT_MCU_CMD_WA_WDT BIT(31) 762#define MT_MCU_CMD_WM_WDT BIT(30) 763#define MT_MCU_CMD_WDT_MASK GENMASK(31, 30) 764 765/* TOP RGU */ 766#define MT_TOP_RGU_BASE 0x18000000 767#define MT_TOP_PWR_CTRL (MT_TOP_RGU_BASE + (0x0)) 768#define MT_TOP_PWR_KEY (0x5746 << 16) 769#define MT_TOP_PWR_SW_RST BIT(0) 770#define MT_TOP_PWR_SW_PWR_ON GENMASK(3, 2) 771#define MT_TOP_PWR_HW_CTRL BIT(4) 772#define MT_TOP_PWR_PWR_ON BIT(7) 773 774#define MT_TOP_RGU_SYSRAM_PDN (MT_TOP_RGU_BASE + 0x050) 775#define MT_TOP_RGU_SYSRAM_SLP (MT_TOP_RGU_BASE + 0x054) 776#define MT_TOP_WFSYS_PWR (MT_TOP_RGU_BASE + 0x010) 777#define MT_TOP_PWR_EN_MASK BIT(7) 778#define MT_TOP_PWR_ACK_MASK BIT(6) 779#define MT_TOP_PWR_KEY_MASK GENMASK(31, 16) 780 781#define MT7986_TOP_WM_RESET (MT_TOP_RGU_BASE + 0x120) 782#define MT7986_TOP_WM_RESET_MASK BIT(0) 783 784/* l1/l2 remap */ 785#define MT_HIF_REMAP_L1 0xf11ac 786#define MT_HIF_REMAP_L1_MT7916 0xfe260 787#define MT_HIF_REMAP_L1_MASK GENMASK(15, 0) 788#define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0) 789#define MT_HIF_REMAP_L1_BASE GENMASK(31, 16) 790#define MT_HIF_REMAP_BASE_L1 0xe0000 791 792#define MT_HIF_REMAP_L2 0xf11b0 793#define MT_HIF_REMAP_L2_MASK GENMASK(19, 0) 794#define MT_HIF_REMAP_L2_OFFSET GENMASK(11, 0) 795#define MT_HIF_REMAP_L2_BASE GENMASK(31, 12) 796#define MT_HIF_REMAP_L2_MT7916 0x1b8 797#define MT_HIF_REMAP_L2_MASK_MT7916 GENMASK(31, 16) 798#define MT_HIF_REMAP_L2_OFFSET_MT7916 GENMASK(15, 0) 799#define MT_HIF_REMAP_L2_BASE_MT7916 GENMASK(31, 16) 800#define MT_HIF_REMAP_BASE_L2_MT7916 0x40000 801 802#define MT_INFRA_BASE 0x18000000 803#define MT_WFSYS0_PHY_START 0x18400000 804#define MT_WFSYS1_PHY_START 0x18800000 805#define MT_WFSYS1_PHY_END 0x18bfffff 806#define MT_CBTOP1_PHY_START 0x70000000 807#define MT_CBTOP1_PHY_END __REG(CBTOP1_PHY_END) 808#define MT_CBTOP2_PHY_START 0xf0000000 809#define MT_INFRA_MCU_START 0x7c000000 810#define MT_INFRA_MCU_END __REG(INFRA_MCU_ADDR_END) 811#define MT_CONN_INFRA_OFFSET(p) ((p) - MT_INFRA_BASE) 812 813/* CONN INFRA CFG */ 814#define MT_CONN_INFRA_BASE 0x18001000 815#define MT_CONN_INFRA(ofs) (MT_CONN_INFRA_BASE + (ofs)) 816 817#define MT_CONN_INFRA_EFUSE MT_CONN_INFRA(0x020) 818 819#define MT_CONN_INFRA_ADIE_RESET MT_CONN_INFRA(0x030) 820#define MT_CONN_INFRA_ADIE1_RESET_MASK BIT(0) 821#define MT_CONN_INFRA_ADIE2_RESET_MASK BIT(2) 822 823#define MT_CONN_INFRA_OSC_RC_EN MT_CONN_INFRA(0x380) 824 825#define MT_CONN_INFRA_OSC_CTRL MT_CONN_INFRA(0x300) 826#define MT_CONN_INFRA_OSC_RC_EN_MASK BIT(7) 827#define MT_CONN_INFRA_OSC_STB_TIME_MASK GENMASK(23, 0) 828 829#define MT_CONN_INFRA_HW_CTRL MT_CONN_INFRA(0x200) 830#define MT_CONN_INFRA_HW_CTRL_MASK BIT(0) 831 832#define MT_CONN_INFRA_WF_SLP_PROT MT_CONN_INFRA(0x540) 833#define MT_CONN_INFRA_WF_SLP_PROT_MASK BIT(0) 834 835#define MT_CONN_INFRA_WF_SLP_PROT_RDY MT_CONN_INFRA(0x544) 836#define MT_CONN_INFRA_CONN_WF_MASK (BIT(29) | BIT(31)) 837#define MT_CONN_INFRA_CONN (BIT(25) | BIT(29) | BIT(31)) 838 839#define MT_CONN_INFRA_EMI_REQ MT_CONN_INFRA(0x414) 840#define MT_CONN_INFRA_EMI_REQ_MASK BIT(0) 841#define MT_CONN_INFRA_INFRA_REQ_MASK BIT(5) 842 843/* AFE */ 844#define MT_AFE_CTRL_BASE(_band) (0x18003000 + ((_band) << 19)) 845#define MT_AFE_CTRL(_band, ofs) (MT_AFE_CTRL_BASE(_band) + (ofs)) 846 847#define MT_AFE_DIG_EN_01(_band) MT_AFE_CTRL(_band, 0x00) 848#define MT_AFE_DIG_EN_02(_band) MT_AFE_CTRL(_band, 0x04) 849#define MT_AFE_DIG_EN_03(_band) MT_AFE_CTRL(_band, 0x08) 850#define MT_AFE_DIG_TOP_01(_band) MT_AFE_CTRL(_band, 0x0c) 851 852#define MT_AFE_PLL_STB_TIME(_band) MT_AFE_CTRL(_band, 0xf4) 853#define MT_AFE_PLL_STB_TIME_MASK (GENMASK(30, 16) | GENMASK(14, 0)) 854#define MT_AFE_PLL_STB_TIME_VAL (FIELD_PREP(GENMASK(30, 16), 0x4bc) | \ 855 FIELD_PREP(GENMASK(14, 0), 0x7e4)) 856#define MT_AFE_BPLL_CFG_MASK GENMASK(7, 6) 857#define MT_AFE_WPLL_CFG_MASK GENMASK(1, 0) 858#define MT_AFE_MCU_WPLL_CFG_MASK GENMASK(3, 2) 859#define MT_AFE_MCU_BPLL_CFG_MASK GENMASK(17, 16) 860#define MT_AFE_PLL_CFG_MASK (MT_AFE_BPLL_CFG_MASK | \ 861 MT_AFE_WPLL_CFG_MASK | \ 862 MT_AFE_MCU_WPLL_CFG_MASK | \ 863 MT_AFE_MCU_BPLL_CFG_MASK) 864#define MT_AFE_PLL_CFG_VAL (FIELD_PREP(MT_AFE_BPLL_CFG_MASK, 0x1) | \ 865 FIELD_PREP(MT_AFE_WPLL_CFG_MASK, 0x2) | \ 866 FIELD_PREP(MT_AFE_MCU_WPLL_CFG_MASK, 0x1) | \ 867 FIELD_PREP(MT_AFE_MCU_BPLL_CFG_MASK, 0x2)) 868 869#define MT_AFE_DIG_TOP_01_MASK GENMASK(18, 15) 870#define MT_AFE_DIG_TOP_01_VAL FIELD_PREP(MT_AFE_DIG_TOP_01_MASK, 0x9) 871 872#define MT_AFE_RG_WBG_EN_RCK_MASK BIT(0) 873#define MT_AFE_RG_WBG_EN_BPLL_UP_MASK BIT(21) 874#define MT_AFE_RG_WBG_EN_WPLL_UP_MASK BIT(20) 875#define MT_AFE_RG_WBG_EN_PLL_UP_MASK (MT_AFE_RG_WBG_EN_BPLL_UP_MASK | \ 876 MT_AFE_RG_WBG_EN_WPLL_UP_MASK) 877#define MT_AFE_RG_WBG_EN_TXCAL_WF4 BIT(29) 878#define MT_AFE_RG_WBG_EN_TXCAL_BT BIT(21) 879#define MT_AFE_RG_WBG_EN_TXCAL_WF3 BIT(20) 880#define MT_AFE_RG_WBG_EN_TXCAL_WF2 BIT(19) 881#define MT_AFE_RG_WBG_EN_TXCAL_WF1 BIT(18) 882#define MT_AFE_RG_WBG_EN_TXCAL_WF0 BIT(17) 883 884#define MT_ADIE_SLP_CTRL_BASE(_band) (0x18005000 + ((_band) << 19)) 885#define MT_ADIE_SLP_CTRL(_band, ofs) (MT_ADIE_SLP_CTRL_BASE(_band) + (ofs)) 886 887#define MT_ADIE_SLP_CTRL_CK0(_band) MT_ADIE_SLP_CTRL(_band, 0x120) 888 889/* ADIE */ 890#define MT_ADIE_CHIP_ID 0x02c 891#define MT_ADIE_VERSION_MASK GENMASK(15, 0) 892#define MT_ADIE_CHIP_ID_MASK GENMASK(31, 16) 893#define MT_ADIE_IDX0 GENMASK(15, 0) 894#define MT_ADIE_IDX1 GENMASK(31, 16) 895 896#define MT_ADIE_RG_TOP_THADC_BG 0x034 897#define MT_ADIE_VRPI_SEL_CR_MASK GENMASK(15, 12) 898#define MT_ADIE_VRPI_SEL_EFUSE_MASK GENMASK(6, 3) 899 900#define MT_ADIE_RG_TOP_THADC 0x038 901#define MT_ADIE_PGA_GAIN_MASK GENMASK(25, 23) 902#define MT_ADIE_PGA_GAIN_EFUSE_MASK GENMASK(2, 0) 903#define MT_ADIE_LDO_CTRL_MASK GENMASK(27, 26) 904#define MT_ADIE_LDO_CTRL_EFUSE_MASK GENMASK(6, 5) 905 906#define MT_AFE_RG_ENCAL_WBTAC_IF_SW 0x070 907#define MT_ADIE_EFUSE_RDATA0 0x130 908 909#define MT_ADIE_EFUSE2_CTRL 0x148 910#define MT_ADIE_EFUSE_CTRL_MASK BIT(1) 911 912#define MT_ADIE_EFUSE_CFG 0x144 913#define MT_ADIE_EFUSE_MODE_MASK GENMASK(7, 6) 914#define MT_ADIE_EFUSE_ADDR_MASK GENMASK(25, 16) 915#define MT_ADIE_EFUSE_VALID_MASK BIT(29) 916#define MT_ADIE_EFUSE_KICK_MASK BIT(30) 917 918#define MT_ADIE_THADC_ANALOG 0x3a6 919 920#define MT_ADIE_THADC_SLOP 0x3a7 921#define MT_ADIE_ANA_EN_MASK BIT(7) 922 923#define MT_ADIE_7975_XTAL_CAL 0x3a1 924#define MT_ADIE_TRIM_MASK GENMASK(6, 0) 925#define MT_ADIE_EFUSE_TRIM_MASK GENMASK(5, 0) 926#define MT_ADIE_XO_TRIM_EN_MASK BIT(7) 927#define MT_ADIE_XTAL_DECREASE_MASK BIT(6) 928 929#define MT_ADIE_7975_XO_TRIM2 0x3a2 930#define MT_ADIE_7975_XO_TRIM3 0x3a3 931#define MT_ADIE_7975_XO_TRIM4 0x3a4 932#define MT_ADIE_7975_XTAL_EN 0x3a5 933 934#define MT_ADIE_XO_TRIM_FLOW 0x3ac 935#define MT_ADIE_XTAL_AXM_80M_OSC 0x390 936#define MT_ADIE_XTAL_AXM_40M_OSC 0x391 937#define MT_ADIE_XTAL_TRIM1_80M_OSC 0x398 938#define MT_ADIE_XTAL_TRIM1_40M_OSC 0x399 939#define MT_ADIE_WRI_CK_SEL 0x4ac 940#define MT_ADIE_RG_STRAP_PIN_IN 0x4fc 941#define MT_ADIE_XTAL_C1 0x654 942#define MT_ADIE_XTAL_C2 0x658 943#define MT_ADIE_RG_XO_01 0x65c 944#define MT_ADIE_RG_XO_03 0x664 945 946#define MT_ADIE_CLK_EN 0xa00 947 948#define MT_ADIE_7975_XTAL 0xa18 949#define MT_ADIE_7975_XTAL_EN_MASK BIT(29) 950 951#define MT_ADIE_7975_COCLK 0xa1c 952#define MT_ADIE_7975_XO_2 0xa84 953#define MT_ADIE_7975_XO_2_FIX_EN BIT(31) 954 955#define MT_ADIE_7975_XO_CTRL2 0xa94 956#define MT_ADIE_7975_XO_CTRL2_C1_MASK GENMASK(26, 20) 957#define MT_ADIE_7975_XO_CTRL2_C2_MASK GENMASK(18, 12) 958#define MT_ADIE_7975_XO_CTRL2_MASK (MT_ADIE_7975_XO_CTRL2_C1_MASK | \ 959 MT_ADIE_7975_XO_CTRL2_C2_MASK) 960 961#define MT_ADIE_7975_XO_CTRL6 0xaa4 962#define MT_ADIE_7975_XO_CTRL6_MASK BIT(16) 963 964/* TOP SPI */ 965#define MT_TOP_SPI_ADIE_BASE(_band) (0x18004000 + ((_band) << 19)) 966#define MT_TOP_SPI_ADIE(_band, ofs) (MT_TOP_SPI_ADIE_BASE(_band) + (ofs)) 967 968#define MT_TOP_SPI_BUSY_CR(_band) MT_TOP_SPI_ADIE(_band, 0) 969#define MT_TOP_SPI_POLLING_BIT BIT(5) 970 971#define MT_TOP_SPI_ADDR_CR(_band) MT_TOP_SPI_ADIE(_band, 0x50) 972#define MT_TOP_SPI_READ_ADDR_FORMAT (BIT(12) | BIT(13) | BIT(15)) 973#define MT_TOP_SPI_WRITE_ADDR_FORMAT (BIT(13) | BIT(15)) 974 975#define MT_TOP_SPI_WRITE_DATA_CR(_band) MT_TOP_SPI_ADIE(_band, 0x54) 976#define MT_TOP_SPI_READ_DATA_CR(_band) MT_TOP_SPI_ADIE(_band, 0x58) 977 978/* CONN INFRA CKGEN */ 979#define MT_INFRA_CKGEN_BASE 0x18009000 980#define MT_INFRA_CKGEN(ofs) (MT_INFRA_CKGEN_BASE + (ofs)) 981 982#define MT_INFRA_CKGEN_BUS MT_INFRA_CKGEN(0xa00) 983#define MT_INFRA_CKGEN_BUS_CLK_SEL_MASK BIT(23) 984#define MT_INFRA_CKGEN_BUS_RDY_SEL_MASK BIT(29) 985 986#define MT_INFRA_CKGEN_BUS_WPLL_DIV_1 MT_INFRA_CKGEN(0x008) 987#define MT_INFRA_CKGEN_BUS_WPLL_DIV_2 MT_INFRA_CKGEN(0x00c) 988 989#define MT_INFRA_CKGEN_RFSPI_WPLL_DIV MT_INFRA_CKGEN(0x040) 990#define MT_INFRA_CKGEN_DIV_SEL_MASK GENMASK(7, 2) 991#define MT_INFRA_CKGEN_DIV_EN_MASK BIT(0) 992 993/* CONN INFRA BUS */ 994#define MT_INFRA_BUS_BASE 0x1800e000 995#define MT_INFRA_BUS(ofs) (MT_INFRA_BUS_BASE + (ofs)) 996 997#define MT_INFRA_BUS_OFF_TIMEOUT MT_INFRA_BUS(0x300) 998#define MT_INFRA_BUS_TIMEOUT_LIMIT_MASK GENMASK(14, 7) 999#define MT_INFRA_BUS_TIMEOUT_EN_MASK GENMASK(3, 0) 1000 1001#define MT_INFRA_BUS_ON_TIMEOUT MT_INFRA_BUS(0x31c) 1002#define MT_INFRA_BUS_EMI_START MT_INFRA_BUS(0x360) 1003#define MT_INFRA_BUS_EMI_END MT_INFRA_BUS(0x364) 1004 1005/* CONN_INFRA_SKU */ 1006#define MT_CONNINFRA_SKU_DEC_ADDR 0x18050000 1007#define MT_CONNINFRA_SKU_MASK GENMASK(15, 0) 1008#define MT_ADIE_TYPE_MASK BIT(1) 1009 1010/* FW MODE SYNC */ 1011#define MT_FW_ASSERT_STAT __REG(FW_ASSERT_STAT_ADDR) 1012#define MT_FW_EXCEPT_TYPE __REG(FW_EXCEPT_TYPE_ADDR) 1013#define MT_FW_EXCEPT_COUNT __REG(FW_EXCEPT_COUNT_ADDR) 1014#define MT_FW_CIRQ_COUNT __REG(FW_CIRQ_COUNT_ADDR) 1015#define MT_FW_CIRQ_IDX __REG(FW_CIRQ_IDX_ADDR) 1016#define MT_FW_CIRQ_LISR __REG(FW_CIRQ_LISR_ADDR) 1017#define MT_FW_TASK_ID __REG(FW_TASK_ID_ADDR) 1018#define MT_FW_TASK_IDX __REG(FW_TASK_IDX_ADDR) 1019#define MT_FW_TASK_QID1 __REG(FW_TASK_QID1_ADDR) 1020#define MT_FW_TASK_QID2 __REG(FW_TASK_QID2_ADDR) 1021#define MT_FW_TASK_START __REG(FW_TASK_START_ADDR) 1022#define MT_FW_TASK_END __REG(FW_TASK_END_ADDR) 1023#define MT_FW_TASK_SIZE __REG(FW_TASK_SIZE_ADDR) 1024#define MT_FW_LAST_MSG_ID __REG(FW_LAST_MSG_ID_ADDR) 1025#define MT_FW_EINT_INFO __REG(FW_EINT_INFO_ADDR) 1026#define MT_FW_SCHED_INFO __REG(FW_SCHED_INFO_ADDR) 1027 1028#define MT_SWDEF_BASE __REG(SWDEF_BASE_ADDR) 1029 1030#define MT_SWDEF(ofs) (MT_SWDEF_BASE + (ofs)) 1031#define MT_SWDEF_MODE MT_SWDEF(0x3c) 1032#define MT_SWDEF_NORMAL_MODE 0 1033#define MT_SWDEF_ICAP_MODE 1 1034#define MT_SWDEF_SPECTRUM_MODE 2 1035 1036#define MT_SWDEF_SER_STATS MT_SWDEF(0x040) 1037#define MT_SWDEF_PLE_STATS MT_SWDEF(0x044) 1038#define MT_SWDEF_PLE1_STATS MT_SWDEF(0x048) 1039#define MT_SWDEF_PLE_AMSDU_STATS MT_SWDEF(0x04C) 1040#define MT_SWDEF_PSE_STATS MT_SWDEF(0x050) 1041#define MT_SWDEF_PSE1_STATS MT_SWDEF(0x054) 1042#define MT_SWDEF_LAMC_WISR6_BN0_STATS MT_SWDEF(0x058) 1043#define MT_SWDEF_LAMC_WISR6_BN1_STATS MT_SWDEF(0x05C) 1044#define MT_SWDEF_LAMC_WISR7_BN0_STATS MT_SWDEF(0x060) 1045#define MT_SWDEF_LAMC_WISR7_BN1_STATS MT_SWDEF(0x064) 1046 1047#define MT_DIC_CMD_REG_BASE 0x41f000 1048#define MT_DIC_CMD_REG(ofs) (MT_DIC_CMD_REG_BASE + (ofs)) 1049#define MT_DIC_CMD_REG_CMD MT_DIC_CMD_REG(0x10) 1050 1051#define MT_CPU_UTIL_BASE 0x41f030 1052#define MT_CPU_UTIL(ofs) (MT_CPU_UTIL_BASE + (ofs)) 1053#define MT_CPU_UTIL_BUSY_PCT MT_CPU_UTIL(0x00) 1054#define MT_CPU_UTIL_PEAK_BUSY_PCT MT_CPU_UTIL(0x04) 1055#define MT_CPU_UTIL_IDLE_CNT MT_CPU_UTIL(0x08) 1056#define MT_CPU_UTIL_PEAK_IDLE_CNT MT_CPU_UTIL(0x0c) 1057#define MT_CPU_UTIL_CTRL MT_CPU_UTIL(0x1c) 1058 1059/* LED */ 1060#define MT_LED_TOP_BASE 0x18013000 1061#define MT_LED_PHYS(_n) (MT_LED_TOP_BASE + (_n)) 1062 1063#define MT_LED_CTRL(_n) MT_LED_PHYS(0x00 + ((_n) * 4)) 1064#define MT_LED_CTRL_KICK BIT(7) 1065#define MT_LED_CTRL_BAND BIT(4) 1066#define MT_LED_CTRL_BLINK_MODE BIT(2) 1067#define MT_LED_CTRL_POLARITY BIT(1) 1068 1069#define MT_LED_TX_BLINK(_n) MT_LED_PHYS(0x10 + ((_n) * 4)) 1070#define MT_LED_TX_BLINK_ON_MASK GENMASK(7, 0) 1071#define MT_LED_TX_BLINK_OFF_MASK GENMASK(15, 8) 1072 1073#define MT_LED_STATUS_0(_n) MT_LED_PHYS(0x20 + ((_n) * 8)) 1074#define MT_LED_STATUS_1(_n) MT_LED_PHYS(0x24 + ((_n) * 8)) 1075#define MT_LED_STATUS_OFF GENMASK(31, 24) 1076#define MT_LED_STATUS_ON GENMASK(23, 16) 1077#define MT_LED_STATUS_DURATION GENMASK(15, 0) 1078 1079#define MT_LED_EN(_n) MT_LED_PHYS(0x40 + ((_n) * 4)) 1080 1081#define MT_LED_GPIO_MUX0 0x70005050 /* GPIO 1 and GPIO 2 */ 1082#define MT_LED_GPIO_MUX1 0x70005054 /* GPIO 14 and 15 */ 1083#define MT_LED_GPIO_MUX2 0x70005058 /* GPIO 18 */ 1084#define MT_LED_GPIO_MUX3 0x7000505c /* GPIO 26 */ 1085 1086/* MT TOP */ 1087#define MT_TOP_BASE 0x18060000 1088#define MT_TOP(ofs) (MT_TOP_BASE + (ofs)) 1089 1090#define MT_TOP_LPCR_HOST_BAND(_band) MT_TOP(0x10 + ((_band) * 0x10)) 1091#define MT_TOP_LPCR_HOST_FW_OWN BIT(0) 1092#define MT_TOP_LPCR_HOST_DRV_OWN BIT(1) 1093#define MT_TOP_LPCR_HOST_FW_OWN_STAT BIT(2) 1094 1095#define MT_TOP_LPCR_HOST_BAND_IRQ_STAT(_band) MT_TOP(0x14 + ((_band) * 0x10)) 1096#define MT_TOP_LPCR_HOST_BAND_STAT BIT(0) 1097 1098#define MT_TOP_MISC MT_TOP(0xf0) 1099#define MT_TOP_MISC_FW_STATE GENMASK(2, 0) 1100 1101#define MT_TOP_WFSYS_WAKEUP MT_TOP(0x1a4) 1102#define MT_TOP_WFSYS_WAKEUP_MASK BIT(0) 1103 1104#define MT_TOP_MCU_EMI_BASE MT_TOP(0x1c4) 1105#define MT_TOP_MCU_EMI_BASE_MASK GENMASK(19, 0) 1106 1107#define MT_TOP_WF_AP_PERI_BASE MT_TOP(0x1c8) 1108#define MT_TOP_WF_AP_PERI_BASE_MASK GENMASK(19, 0) 1109 1110#define MT_TOP_EFUSE_BASE MT_TOP(0x1cc) 1111#define MT_TOP_EFUSE_BASE_MASK GENMASK(19, 0) 1112 1113#define MT_TOP_CONN_INFRA_WAKEUP MT_TOP(0x1a0) 1114#define MT_TOP_CONN_INFRA_WAKEUP_MASK BIT(0) 1115 1116#define MT_TOP_WFSYS_RESET_STATUS MT_TOP(0x2cc) 1117#define MT_TOP_WFSYS_RESET_STATUS_MASK BIT(30) 1118 1119/* SEMA */ 1120#define MT_SEMA_BASE 0x18070000 1121#define MT_SEMA(ofs) (MT_SEMA_BASE + (ofs)) 1122 1123#define MT_SEMA_RFSPI_STATUS (MT_SEMA(0x2000) + (11 * 4)) 1124#define MT_SEMA_RFSPI_RELEASE (MT_SEMA(0x2200) + (11 * 4)) 1125#define MT_SEMA_RFSPI_STATUS_MASK BIT(1) 1126 1127/* MCU BUS */ 1128#define MT_MCU_BUS_BASE 0x18400000 1129#define MT_MCU_BUS(ofs) (MT_MCU_BUS_BASE + (ofs)) 1130 1131#define MT_MCU_BUS_TIMEOUT MT_MCU_BUS(0xf0440) 1132#define MT_MCU_BUS_TIMEOUT_SET_MASK GENMASK(7, 0) 1133#define MT_MCU_BUS_TIMEOUT_CG_EN_MASK BIT(28) 1134#define MT_MCU_BUS_TIMEOUT_EN_MASK BIT(31) 1135 1136#define MT_MCU_BUS_REMAP MT_MCU_BUS(0x120) 1137 1138/* TOP CFG */ 1139#define MT_TOP_CFG_BASE 0x184b0000 1140#define MT_TOP_CFG(ofs) (MT_TOP_CFG_BASE + (ofs)) 1141 1142#define MT_TOP_CFG_IP_VERSION_ADDR MT_TOP_CFG(0x010) 1143 1144/* TOP CFG ON */ 1145#define MT_TOP_CFG_ON_BASE 0x184c1000 1146#define MT_TOP_CFG_ON(ofs) (MT_TOP_CFG_ON_BASE + (ofs)) 1147 1148#define MT_TOP_CFG_ON_ROM_IDX MT_TOP_CFG_ON(0x604) 1149 1150/* SLP CTRL */ 1151#define MT_SLP_BASE 0x184c3000 1152#define MT_SLP(ofs) (MT_SLP_BASE + (ofs)) 1153 1154#define MT_SLP_STATUS MT_SLP(0x00c) 1155#define MT_SLP_WFDMA2CONN_MASK (BIT(21) | BIT(23)) 1156#define MT_SLP_CTRL_EN_MASK BIT(0) 1157#define MT_SLP_CTRL_BSY_MASK BIT(1) 1158 1159/* MCU BUS DBG */ 1160#define MT_MCU_BUS_DBG_BASE 0x18500000 1161#define MT_MCU_BUS_DBG(ofs) (MT_MCU_BUS_DBG_BASE + (ofs)) 1162 1163#define MT_MCU_BUS_DBG_TIMEOUT MT_MCU_BUS_DBG(0x0) 1164#define MT_MCU_BUS_DBG_TIMEOUT_SET_MASK GENMASK(31, 16) 1165#define MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK BIT(3) 1166#define MT_MCU_BUS_DBG_TIMEOUT_EN_MASK BIT(2) 1167 1168#define MT_HW_BOUND 0x70010020 1169#define MT_HW_REV 0x70010204 1170#define MT_WF_SUBSYS_RST 0x70002600 1171 1172/* PCIE MAC */ 1173#define MT_PCIE_MAC_BASE 0x74030000 1174#define MT_PCIE_MAC(ofs) (MT_PCIE_MAC_BASE + (ofs)) 1175#define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188) 1176 1177#define MT_PCIE1_MAC_INT_ENABLE 0x74020188 1178#define MT_PCIE1_MAC_INT_ENABLE_MT7916 0x74090188 1179 1180#define MT_WM_MCU_PC 0x7c060204 1181#define MT_WA_MCU_PC 0x7c06020c 1182 1183/* PP TOP */ 1184#define MT_WF_PP_TOP_BASE 0x820cc000 1185#define MT_WF_PP_TOP(ofs) (MT_WF_PP_TOP_BASE + (ofs)) 1186 1187#define MT_WF_PP_TOP_RXQ_WFDMA_CF_5 MT_WF_PP_TOP(0x0e8) 1188#define MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK BIT(6) 1189 1190#define MT_WF_IRPI_BASE 0x83000000 1191#define MT_WF_IRPI(ofs) (MT_WF_IRPI_BASE + (ofs)) 1192 1193#define MT_WF_IRPI_NSS(phy, nss) MT_WF_IRPI(0x6000 + ((phy) << 20) + ((nss) << 16)) 1194#define MT_WF_IRPI_NSS_MT7916(phy, nss) MT_WF_IRPI(0x1000 + ((phy) << 20) + ((nss) << 16)) 1195 1196/* PHY */ 1197#define MT_WF_PHY_BASE 0x83080000 1198#define MT_WF_PHY(ofs) (MT_WF_PHY_BASE + (ofs)) 1199 1200#define MT_WF_PHY_RX_CTRL1(_phy) MT_WF_PHY(0x2004 + ((_phy) << 16)) 1201#define MT_WF_PHY_RX_CTRL1_MT7916(_phy) MT_WF_PHY(0x2004 + ((_phy) << 20)) 1202#define MT_WF_PHY_RX_CTRL1_IPI_EN GENMASK(2, 0) 1203#define MT_WF_PHY_RX_CTRL1_STSCNT_EN GENMASK(11, 9) 1204 1205#define MT_WF_PHY_RXTD12(_phy) MT_WF_PHY(0x8230 + ((_phy) << 16)) 1206#define MT_WF_PHY_RXTD12_MT7916(_phy) MT_WF_PHY(0x8230 + ((_phy) << 20)) 1207#define MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY BIT(18) 1208#define MT_WF_PHY_RXTD12_IRPI_SW_CLR BIT(29) 1209 1210#define MT_WF_PHY_TPC_CTRL_STAT(_phy) MT_WF_PHY(0xe7a0 + ((_phy) << 16)) 1211#define MT_WF_PHY_TPC_CTRL_STAT_MT7916(_phy) MT_WF_PHY(0xe7a0 + ((_phy) << 20)) 1212#define MT_WF_PHY_TPC_POWER GENMASK(15, 8) 1213 1214#define MT_MCU_WM_CIRQ_BASE 0x89010000 1215#define MT_MCU_WM_CIRQ(ofs) (MT_MCU_WM_CIRQ_BASE + (ofs)) 1216#define MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR MT_MCU_WM_CIRQ(0x80) 1217#define MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR MT_MCU_WM_CIRQ(0xc0) 1218#define MT_MCU_WM_CIRQ_EINT_MASK_CLR_ADDR MT_MCU_WM_CIRQ(0x108) 1219#define MT_MCU_WM_CIRQ_EINT_SOFT_ADDR MT_MCU_WM_CIRQ(0x118) 1220 1221#endif 1222