1/* SPDX-License-Identifier: ISC */
2/* Copyright (C) 2020 MediaTek Inc. */
3
4#ifndef __MT76_CONNAC_H
5#define __MT76_CONNAC_H
6
7#include "mt76.h"
8
9enum rx_pkt_type {
10	PKT_TYPE_TXS,
11	PKT_TYPE_TXRXV,
12	PKT_TYPE_NORMAL,
13	PKT_TYPE_RX_DUP_RFB,
14	PKT_TYPE_RX_TMR,
15	PKT_TYPE_RETRIEVE,
16	PKT_TYPE_TXRX_NOTIFY,
17	PKT_TYPE_RX_EVENT,
18	PKT_TYPE_NORMAL_MCU,
19	PKT_TYPE_RX_FW_MONITOR	= 0x0c,
20	PKT_TYPE_TXRX_NOTIFY_V0	= 0x18,
21};
22
23#define MT76_CONNAC_SCAN_IE_LEN			600
24#define MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL	 10
25#define MT76_CONNAC_MAX_TIME_SCHED_SCAN_INTERVAL U16_MAX
26#define MT76_CONNAC_MAX_SCHED_SCAN_SSID		10
27#define MT76_CONNAC_MAX_SCAN_MATCH		16
28
29#define MT76_CONNAC_MAX_WMM_SETS		4
30
31#define MT76_CONNAC_COREDUMP_TIMEOUT		(HZ / 20)
32#define MT76_CONNAC_COREDUMP_SZ			(1300 * 1024)
33
34#define MT_TXD_SIZE				(8 * 4)
35
36#define MT_USB_TXD_SIZE				(MT_TXD_SIZE + 8 * 4)
37#define MT_USB_HDR_SIZE				4
38#define MT_USB_TAIL_SIZE			4
39
40#define MT_SDIO_TXD_SIZE			(MT_TXD_SIZE + 8 * 4)
41#define MT_SDIO_TAIL_SIZE			8
42#define MT_SDIO_HDR_SIZE			4
43
44#define MT_MSDU_ID_VALID		BIT(15)
45
46#define MT_TXD_LEN_LAST			BIT(15)
47#define MT_TXD_LEN_MASK			GENMASK(11, 0)
48#define MT_TXD_LEN_MSDU_LAST		BIT(14)
49#define MT_TXD_LEN_AMSDU_LAST		BIT(15)
50
51enum {
52	CMD_CBW_20MHZ = IEEE80211_STA_RX_BW_20,
53	CMD_CBW_40MHZ = IEEE80211_STA_RX_BW_40,
54	CMD_CBW_80MHZ = IEEE80211_STA_RX_BW_80,
55	CMD_CBW_160MHZ = IEEE80211_STA_RX_BW_160,
56	CMD_CBW_10MHZ,
57	CMD_CBW_5MHZ,
58	CMD_CBW_8080MHZ,
59	CMD_CBW_320MHZ,
60
61	CMD_HE_MCS_BW80 = 0,
62	CMD_HE_MCS_BW160,
63	CMD_HE_MCS_BW8080,
64	CMD_HE_MCS_BW_NUM
65};
66
67enum {
68	HW_BSSID_0 = 0x0,
69	HW_BSSID_1,
70	HW_BSSID_2,
71	HW_BSSID_3,
72	HW_BSSID_MAX = HW_BSSID_3,
73	EXT_BSSID_START = 0x10,
74	EXT_BSSID_1,
75	EXT_BSSID_15 = 0x1f,
76	EXT_BSSID_MAX = EXT_BSSID_15,
77	REPEATER_BSSID_START = 0x20,
78	REPEATER_BSSID_MAX = 0x3f,
79};
80
81struct mt76_connac_reg_map {
82	u32 phys;
83	u32 maps;
84	u32 size;
85};
86
87struct mt76_connac_pm {
88	bool enable:1;
89	bool enable_user:1;
90	bool ds_enable:1;
91	bool ds_enable_user:1;
92	bool suspended:1;
93
94	spinlock_t txq_lock;
95	struct {
96		struct mt76_wcid *wcid;
97		struct sk_buff *skb;
98	} tx_q[IEEE80211_NUM_ACS];
99
100	struct work_struct wake_work;
101	wait_queue_head_t wait;
102
103	struct {
104		spinlock_t lock;
105		u32 count;
106	} wake;
107	struct mutex mutex;
108
109	struct delayed_work ps_work;
110	unsigned long last_activity;
111	unsigned long idle_timeout;
112
113	struct {
114		unsigned long last_wake_event;
115		unsigned long awake_time;
116		unsigned long last_doze_event;
117		unsigned long doze_time;
118		unsigned int lp_wake;
119	} stats;
120};
121
122struct mt76_connac_coredump {
123	struct sk_buff_head msg_list;
124	struct delayed_work work;
125	unsigned long last_activity;
126};
127
128struct mt76_connac_sta_key_conf {
129	s8 keyidx;
130	u8 key[16];
131};
132
133#define MT_TXP_MAX_BUF_NUM		6
134
135struct mt76_connac_fw_txp {
136	__le16 flags;
137	__le16 token;
138	u8 bss_idx;
139	__le16 rept_wds_wcid;
140	u8 nbuf;
141	__le32 buf[MT_TXP_MAX_BUF_NUM];
142	__le16 len[MT_TXP_MAX_BUF_NUM];
143} __packed __aligned(4);
144
145#define MT_HW_TXP_MAX_MSDU_NUM		4
146#define MT_HW_TXP_MAX_BUF_NUM		4
147
148struct mt76_connac_txp_ptr {
149	__le32 buf0;
150	__le16 len0;
151	__le16 len1;
152	__le32 buf1;
153} __packed __aligned(4);
154
155struct mt76_connac_hw_txp {
156	__le16 msdu_id[MT_HW_TXP_MAX_MSDU_NUM];
157	struct mt76_connac_txp_ptr ptr[MT_HW_TXP_MAX_BUF_NUM / 2];
158} __packed __aligned(4);
159
160struct mt76_connac_txp_common {
161	union {
162		struct mt76_connac_fw_txp fw;
163		struct mt76_connac_hw_txp hw;
164	};
165};
166
167struct mt76_connac_tx_free {
168	__le16 rx_byte_cnt;
169	__le16 ctrl;
170	__le32 txd;
171} __packed __aligned(4);
172
173extern const struct wiphy_wowlan_support mt76_connac_wowlan_support;
174
175static inline bool is_mt7922(struct mt76_dev *dev)
176{
177	return mt76_chip(dev) == 0x7922;
178}
179
180static inline bool is_mt7921(struct mt76_dev *dev)
181{
182	return mt76_chip(dev) == 0x7961 || is_mt7922(dev);
183}
184
185static inline bool is_mt7663(struct mt76_dev *dev)
186{
187	return mt76_chip(dev) == 0x7663;
188}
189
190static inline bool is_mt7915(struct mt76_dev *dev)
191{
192	return mt76_chip(dev) == 0x7915;
193}
194
195static inline bool is_mt7916(struct mt76_dev *dev)
196{
197	return mt76_chip(dev) == 0x7906;
198}
199
200static inline bool is_mt7981(struct mt76_dev *dev)
201{
202	return mt76_chip(dev) == 0x7981;
203}
204
205static inline bool is_mt7986(struct mt76_dev *dev)
206{
207	return mt76_chip(dev) == 0x7986;
208}
209
210static inline bool is_mt798x(struct mt76_dev *dev)
211{
212	return is_mt7981(dev) || is_mt7986(dev);
213}
214
215static inline bool is_mt7996(struct mt76_dev *dev)
216{
217	return mt76_chip(dev) == 0x7990;
218}
219
220static inline bool is_mt7622(struct mt76_dev *dev)
221{
222	if (!IS_ENABLED(CONFIG_MT7622_WMAC))
223		return false;
224
225	return mt76_chip(dev) == 0x7622;
226}
227
228static inline bool is_mt7615(struct mt76_dev *dev)
229{
230	return mt76_chip(dev) == 0x7615 || mt76_chip(dev) == 0x7611;
231}
232
233static inline bool is_mt7611(struct mt76_dev *dev)
234{
235	return mt76_chip(dev) == 0x7611;
236}
237
238static inline bool is_connac_v1(struct mt76_dev *dev)
239{
240	return is_mt7615(dev) || is_mt7663(dev) || is_mt7622(dev);
241}
242
243static inline bool is_mt76_fw_txp(struct mt76_dev *dev)
244{
245	switch (mt76_chip(dev)) {
246	case 0x7961:
247	case 0x7922:
248	case 0x7663:
249	case 0x7622:
250		return false;
251	default:
252		return true;
253	}
254}
255
256static inline u8 mt76_connac_chan_bw(struct cfg80211_chan_def *chandef)
257{
258	static const u8 width_to_bw[] = {
259		[NL80211_CHAN_WIDTH_40] = CMD_CBW_40MHZ,
260		[NL80211_CHAN_WIDTH_80] = CMD_CBW_80MHZ,
261		[NL80211_CHAN_WIDTH_80P80] = CMD_CBW_8080MHZ,
262		[NL80211_CHAN_WIDTH_160] = CMD_CBW_160MHZ,
263		[NL80211_CHAN_WIDTH_5] = CMD_CBW_5MHZ,
264		[NL80211_CHAN_WIDTH_10] = CMD_CBW_10MHZ,
265		[NL80211_CHAN_WIDTH_20] = CMD_CBW_20MHZ,
266		[NL80211_CHAN_WIDTH_20_NOHT] = CMD_CBW_20MHZ,
267		[NL80211_CHAN_WIDTH_320] = CMD_CBW_320MHZ,
268	};
269
270	if (chandef->width >= ARRAY_SIZE(width_to_bw))
271		return 0;
272
273	return width_to_bw[chandef->width];
274}
275
276static inline u8 mt76_connac_lmac_mapping(u8 ac)
277{
278	/* LMAC uses the reverse order of mac80211 AC indexes */
279	return 3 - ac;
280}
281
282static inline void *
283mt76_connac_txwi_to_txp(struct mt76_dev *dev, struct mt76_txwi_cache *t)
284{
285	u8 *txwi;
286
287	if (!t)
288		return NULL;
289
290	txwi = mt76_get_txwi_ptr(dev, t);
291
292	return (void *)(txwi + MT_TXD_SIZE);
293}
294
295static inline u8 mt76_connac_spe_idx(u8 antenna_mask)
296{
297	static const u8 ant_to_spe[] = {0, 0, 1, 0, 3, 2, 4, 0,
298					9, 8, 6, 10, 16, 12, 18, 0};
299
300	if (antenna_mask >= sizeof(ant_to_spe))
301		return 0;
302
303	return ant_to_spe[antenna_mask];
304}
305
306static inline void mt76_connac_irq_enable(struct mt76_dev *dev, u32 mask)
307{
308	mt76_set_irq_mask(dev, 0, 0, mask);
309	tasklet_schedule(&dev->irq_tasklet);
310}
311
312int mt76_connac_pm_wake(struct mt76_phy *phy, struct mt76_connac_pm *pm);
313void mt76_connac_power_save_sched(struct mt76_phy *phy,
314				  struct mt76_connac_pm *pm);
315void mt76_connac_free_pending_tx_skbs(struct mt76_connac_pm *pm,
316				      struct mt76_wcid *wcid);
317
318static inline void mt76_connac_tx_cleanup(struct mt76_dev *dev)
319{
320	dev->queue_ops->tx_cleanup(dev, dev->q_mcu[MT_MCUQ_WM], false);
321	dev->queue_ops->tx_cleanup(dev, dev->q_mcu[MT_MCUQ_WA], false);
322}
323
324static inline bool
325mt76_connac_pm_ref(struct mt76_phy *phy, struct mt76_connac_pm *pm)
326{
327	bool ret = false;
328
329	spin_lock_bh(&pm->wake.lock);
330	if (test_bit(MT76_STATE_PM, &phy->state))
331		goto out;
332
333	pm->wake.count++;
334	ret = true;
335out:
336	spin_unlock_bh(&pm->wake.lock);
337
338	return ret;
339}
340
341static inline void
342mt76_connac_pm_unref(struct mt76_phy *phy, struct mt76_connac_pm *pm)
343{
344	spin_lock_bh(&pm->wake.lock);
345
346	pm->last_activity = jiffies;
347	if (--pm->wake.count == 0 &&
348	    test_bit(MT76_STATE_MCU_RUNNING, &phy->state))
349		mt76_connac_power_save_sched(phy, pm);
350
351	spin_unlock_bh(&pm->wake.lock);
352}
353
354static inline bool
355mt76_connac_skip_fw_pmctrl(struct mt76_phy *phy, struct mt76_connac_pm *pm)
356{
357	struct mt76_dev *dev = phy->dev;
358	bool ret;
359
360	if (dev->token_count)
361		return true;
362
363	spin_lock_bh(&pm->wake.lock);
364	ret = pm->wake.count || test_and_set_bit(MT76_STATE_PM, &phy->state);
365	spin_unlock_bh(&pm->wake.lock);
366
367	return ret;
368}
369
370static inline void
371mt76_connac_mutex_acquire(struct mt76_dev *dev, struct mt76_connac_pm *pm)
372	__acquires(&dev->mutex)
373{
374	mutex_lock(&dev->mutex);
375	mt76_connac_pm_wake(&dev->phy, pm);
376}
377
378static inline void
379mt76_connac_mutex_release(struct mt76_dev *dev, struct mt76_connac_pm *pm)
380	__releases(&dev->mutex)
381{
382	mt76_connac_power_save_sched(&dev->phy, pm);
383	mutex_unlock(&dev->mutex);
384}
385
386void mt76_connac_gen_ppe_thresh(u8 *he_ppet, int nss);
387int mt76_connac_init_tx_queues(struct mt76_phy *phy, int idx, int n_desc,
388			       int ring_base, u32 flags);
389void mt76_connac_write_hw_txp(struct mt76_dev *dev,
390			      struct mt76_tx_info *tx_info,
391			      void *txp_ptr, u32 id);
392void mt76_connac_txp_skb_unmap(struct mt76_dev *dev,
393			       struct mt76_txwi_cache *txwi);
394void mt76_connac_tx_complete_skb(struct mt76_dev *mdev,
395				 struct mt76_queue_entry *e);
396void mt76_connac_pm_queue_skb(struct ieee80211_hw *hw,
397			      struct mt76_connac_pm *pm,
398			      struct mt76_wcid *wcid,
399			      struct sk_buff *skb);
400void mt76_connac_pm_dequeue_skbs(struct mt76_phy *phy,
401				 struct mt76_connac_pm *pm);
402void mt76_connac2_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi,
403				 struct sk_buff *skb, struct mt76_wcid *wcid,
404				 struct ieee80211_key_conf *key, int pid,
405				 enum mt76_txq_id qid, u32 changed);
406u16 mt76_connac2_mac_tx_rate_val(struct mt76_phy *mphy,
407				 struct ieee80211_vif *vif,
408				 bool beacon, bool mcast);
409bool mt76_connac2_mac_fill_txs(struct mt76_dev *dev, struct mt76_wcid *wcid,
410			       __le32 *txs_data);
411bool mt76_connac2_mac_add_txs_skb(struct mt76_dev *dev, struct mt76_wcid *wcid,
412				  int pid, __le32 *txs_data);
413void mt76_connac2_mac_decode_he_radiotap(struct mt76_dev *dev,
414					 struct sk_buff *skb,
415					 __le32 *rxv, u32 mode);
416int mt76_connac2_reverse_frag0_hdr_trans(struct ieee80211_vif *vif,
417					 struct sk_buff *skb, u16 hdr_offset);
418int mt76_connac2_mac_fill_rx_rate(struct mt76_dev *dev,
419				  struct mt76_rx_status *status,
420				  struct ieee80211_supported_band *sband,
421				  __le32 *rxv, u8 *mode);
422void mt76_connac2_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi);
423void mt76_connac2_txwi_free(struct mt76_dev *dev, struct mt76_txwi_cache *t,
424			    struct ieee80211_sta *sta,
425			    struct list_head *free_list);
426void mt76_connac2_tx_token_put(struct mt76_dev *dev);
427
428/* connac3 */
429void mt76_connac3_mac_decode_he_radiotap(struct sk_buff *skb, __le32 *rxv,
430					 u8 mode);
431#endif /* __MT76_CONNAC_H */
432